CN116774016B - Chip testing method, device, equipment and storage medium - Google Patents
Chip testing method, device, equipment and storage medium Download PDFInfo
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- CN116774016B CN116774016B CN202311054782.2A CN202311054782A CN116774016B CN 116774016 B CN116774016 B CN 116774016B CN 202311054782 A CN202311054782 A CN 202311054782A CN 116774016 B CN116774016 B CN 116774016B
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- 238000012360 testing method Methods 0.000 title claims abstract description 380
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- 238000013101 initial test Methods 0.000 claims description 78
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The disclosure provides a chip testing method, device, equipment and storage medium. The chip testing method comprises the following steps: collecting test result information generated by running test cases in the test process; the test result information comprises running state information and positioning information generated by executing each test code in the test case; obtaining test results of each test code according to the running state information; and determining the position of each test code in the test case according to the positioning information. The method comprises the steps of determining whether a problem exists in the running process of each test code by collecting running state information generated by the test code of the test case; and then the position of the test code in the test case is determined according to the positioning information generated by executing each test code of the test case, so that the abnormal accurate positioning is realized, the problem positioning of the code level is realized, and the test time is greatly saved.
Description
Technical Field
The disclosure relates to the technical field of chip testing, and in particular relates to a chip testing method, device, equipment and storage medium.
Background
ATE (Automatic Test Equipment, automated test equipment) is used to detect the functional integrity of chips, and to ensure the quality of chips during the manufacturing process. The ATE test platform has the following basic flow: the method comprises the steps of providing a chip testing environment through an ATE machine, filling a test pattern (excitation) into a chip, observing the output response of the chip, comparing the output response with expected test data, obtaining the test result of the chip, and screening and grading the chip through the test result.
However, the existing scheme obtains a test result by judging whether the test case passes or not, belongs to a black box test, and cannot quickly locate a test problem point because it is unclear where the test case specifically goes wrong.
Disclosure of Invention
The disclosure aims to provide a chip testing method, device, equipment and storage medium, so as to realize abnormal accurate positioning and quickly find out a testing problem point.
According to one aspect of the present disclosure, there is provided a chip testing method including:
collecting test result information generated by running test cases in the test process; the test result information comprises running state information and positioning information generated by executing each test code in the test case;
obtaining test results of each test code according to the running state information;
and determining the position of each test code in the test case according to the positioning information.
Further, the step of collecting test result information generated by running the test case in the test process includes:
acquiring effective information meeting preset conditions, and recording a first periodic sequence corresponding to the effective information;
and carrying out completion operation on the effective information according to the first periodic sequence to obtain test result information.
Further, the step of collecting effective information meeting preset conditions includes:
matching initial test result information generated by running the test cases in the test process with preset test information to obtain a matching result;
and determining whether the initial test result information is effective information or not based on the matching result, and acquiring the effective information if the initial test result information is the effective information.
Further, the step of performing a completion operation on the effective information according to the first periodic sequence to obtain test result information includes:
obtaining a second periodic sequence according to the first periodic sequence and the time sequence;
setting non-collected test information based on the second periodic sequence; the non-collected test information is initial test result information which is not determined to be the effective information;
and combining the effective information and the non-collected test information according to the size sequence of the first periodic sequence and the second periodic sequence to obtain test result information.
Further, collecting effective information meeting preset conditions includes:
and collecting effective information according to a preset sampling rate.
Further, the preset sampling rate is at least 2 times the output rate of the chip.
Further, after the completion operation is performed on the effective information according to the first period sequence, the method further includes:
restoring the completed test result information into initial test result information according to the relation between the preset sampling rate and the output rate of the chip;
and carrying out format conversion on the initial test result information to obtain the test result information.
Further, the testing process is a pre-lighting test of the chip implemented in the wafer testing stage.
Further, the positioning information includes address information, time information, and a module name.
Further, the chip testing method further comprises:
receiving an initial test case provided by a system test platform;
protocol conversion is carried out on the initial test case, and a waveform file is obtained;
converting the format of the waveform file to obtain a text file;
converting the format of the text file to obtain a test case;
and sending the test cases to the chip so that the chip runs the test cases.
According to another aspect of the present disclosure, there is provided a chip testing apparatus including:
the acquisition module is used for acquiring test result information generated by running the test cases in the test process; the test result information comprises running state information and positioning information generated by executing each test code in the test case;
the test result acquisition module is used for acquiring test results of each test code according to the running state information;
and the positioning module is used for determining the position of each test code in the test case according to the positioning information.
Further, the acquisition module includes:
the acquisition subunit is used for acquiring effective information meeting preset conditions and recording a first periodic sequence corresponding to the effective information;
and the complementing unit is used for complementing the effective information according to the first periodic sequence to obtain the test result information.
Further, the acquisition subunit is used for matching initial test result information generated by running the test case in the test process with preset test information to obtain a matching result;
the acquisition subunit is further configured to determine whether the initial test result information is valid information based on the matching result, and if so, acquire the valid information.
Further, a complementing unit, configured to obtain a second periodic sequence according to the first periodic sequence;
the complement unit is also used for setting non-collected test information based on the second periodic sequence; the non-collected test information is initial test result information which is not determined to be the effective information;
and the complementing unit is also used for merging the effective information and the non-collected test information according to the size sequence of the first periodic sequence and the second periodic sequence to obtain the test result information.
According to another aspect of the present disclosure, there is provided a test apparatus comprising a memory for storing one or more programs, and one or more processors; the method of any of the embodiments described above is implemented when one or more programs are executed by one or more processors.
According to another aspect of the present disclosure, there is provided a computer storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any of the above embodiments.
Drawings
Fig. 1 is a schematic flow chart of a chip testing method according to an embodiment of the disclosure;
FIG. 2 is a schematic flow chart of a chip testing method according to another embodiment of the disclosure;
fig. 3 is a schematic diagram of generating test result information of a chip test method according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a graphics processing system according to one embodiment of the present disclosure;
fig. 5 is a schematic diagram of a graphics processing system according to another embodiment of the present disclosure.
Detailed Description
Before describing embodiments of the present disclosure, it should be noted that:
some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.
The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.
It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
The purpose of the present disclosure is to provide a chip test method, which determines whether there is a problem in the running process of each test code by collecting the running state information generated by executing the test code of the test case; and determining the position of the test code in the test case according to the positioning information generated by executing each test code of the test case, so as to realize the abnormal accurate positioning and achieve the accurate code level.
One embodiment of the present disclosure provides a chip testing method that is applied to a testing device, which may be an ATE. As shown in fig. 1, the chip testing method includes the following steps:
step 101, collecting test result information generated by running test cases in a test process; the test result information comprises running state information and positioning information generated by executing each test code in the test case.
Step 102, obtaining the test result of each test code according to the running state information.
And step 103, determining the position of each test code in the test case according to the positioning information.
It should be understood that each test code is a test code involved in single-step execution of the test case, and may be a row of test codes or a section of test codes corresponding to a certain function.
The running state information disclosed by the disclosure is used for representing whether the corresponding test code is abnormal in the running process, and the content of the running state information can comprise a conclusion that the corresponding test code runs successfully or fails, and can also comprise a description of a specific value or a specific function of the corresponding test code. For example, a test code is executed for accessing a target file on the memory module, and then the running state information corresponding to the test code may be success or failure of accessing the target file, or may be that the content corresponding to the target address on the memory module is accessed.
The test results of each test code obtained according to the operation state information can be understood as: if the running state information is that the corresponding test code is successful to run, the obtained test result is normal; if the running state information is that the corresponding test code fails to run, the obtained test result is abnormal. When the running state information is a specific value or specific function description of the running corresponding test code, if the specific value of the running corresponding test code is the same as a preset value, the obtained test result is normal, and if the specific value is different from the preset value, the obtained test result is abnormal; or if the specific function description of the running corresponding test code accords with the expected description, the obtained test result is normal, and if the specific function description does not accord with the expected description, the obtained test result is abnormal.
And when the test result is abnormal, judging the test code corresponding to the test result as a problem point.
Because only according to the running state information, whether the test code has a problem or not can be obtained, and the specific problem is where, namely, where the corresponding test code is in the test case, the position of the test code in the test case can be obtained according to the positioning information. After the test result is determined to be abnormal according to the running state information, the specific position of the abnormal test code can be determined according to the corresponding positioning information, so that the problem point can be positioned, the problem positioning of the code level can be realized, and compared with the existing problem positioning, the method is more specific, and the test time is greatly saved.
The location information of the present disclosure includes address information, time information, and a module name. The address information is used for representing the position of the test code in the test case, the time information is used for representing the time when the test code is executed, and the module name is used for representing the name of the test object corresponding to the test code.
The present disclosure obtains a location of each test code in a test case based on address information corresponding to each test code. In order to further ensure the position accuracy of the test codes, the position of each test code in the retest case can be further confirmed through time information; because the test case is composed of a plurality of test codes, each test code is executed step by step according to a preset sequence in the test process, namely the time for executing each test code is different, and the position of the test code in the test case can be determined according to the preset sequence and the time information of each test code.
Since the position of the test code in the test case can only be determined according to the address information and the time information, it is not clear which module in the test chip the test code is used for testing, so that the test code can be determined by the module name which module in the test chip, and further, which module in the test chip is tested to have a problem can be determined according to the abnormal test code. That is, the present disclosure can locate not only which test code the problem is present in, but also which module the problem is present in.
In the present disclosure, in order to further save test time and reduce occupation of test resources, a problem of a dead halt caused by insufficient cache of test equipment is prevented. As shown in fig. 2, the steps of collecting test result information generated by running a test case in a test process according to the present disclosure include:
in step 1011, effective information meeting preset conditions is collected, and a first periodic sequence corresponding to the effective information is recorded.
And step 1012, carrying out completion operation on the effective information according to the first periodic sequence to obtain test result information.
It should be understood that when collecting test result information, the present disclosure collects only valid information meeting preset conditions, and not all test result information will be collected. In other words, the method and the device for testing the data volume of the data storage device improve testing efficiency, reduce occupation of testing resources and prevent the problem of dead halt caused by insufficient cache of the testing equipment by acquiring the minimum data volume.
The realization principle of collecting effective information meeting preset conditions is as follows:
matching initial test result information generated by running the test cases in the test process with preset test information to obtain a matching result; and determining whether the initial test result information is effective information or not based on the matching result, and acquiring the effective information if the initial test result information is the effective information.
It should be understood that the initial test result information is generated by the chip running test case, and the initial test result information generated by the chip running test case is sent to the test equipment through a serial port pin of the chip, where the serial port pin may be a uart_tx pin; the test equipment can be in communication connection with the serial port pin of the chip through the probe, and the test equipment receives initial test result information provided by the chip through the serial port pin through the probe.
After receiving the initial test result information, the test equipment matches the initial test result information with preset test information. It can be understood that the initial test result information is level shift information, i.e., information composed of a high level and a low level; when the test code is operated by the chip, the chip outputs level conversion information consisting of high level and low level through the serial port pin under the condition of information output; when the test code is not operated by the chip, the chip outputs continuous high level through the serial port pin under the condition of no information output; that is, when there is an information output, the chip outputs information with a level change, and when there is no information output, the chip output is kept at a high level.
In the present disclosure, preset test information is set to a high level.
Matching the initial test result information with preset test information, namely comparing the high level and the low level in the initial test result information with the high level of the preset test information, wherein the high level in the initial test result information is the same as the high level of the preset test information, the obtained matching result is the matching, and the high level information in the initial test result information is discarded under the condition that the matching result is the matching; and if the low level in the initial test result information is different from the high level of the preset test information, the obtained matching result is unmatched, and if the matching result is unmatched, the low level information in the initial test result information is determined to be effective information, and the low level information in the initial test result information is acquired.
Of course, in another embodiment provided in the present disclosure, the preset test information may also be set to a low level, and determining whether the initial test result information is valid information based on the matching result may also be: matching the high level and the low level in the initial test result information with the low level of the preset test information, wherein the high level in the initial test result information is different from the low level of the preset test information, so that a matching result is not matched, and discarding the high level information in the initial test result information under the condition that the matching result is not matched; and if the low level in the initial test result information is the same as the low level of the preset test information, obtaining a matching result, determining the low level information in the initial test result information as effective information under the condition that the matching result is the matching, and collecting the low level information in the initial test result information. The setting of the preset test information and the adjustment of the processing mode according to different matching results can be performed by a person skilled in the art according to actual situations, and the method is not limited herein.
It can be appreciated that the present disclosure discards high level information in the initial test result information by comparing the initial test result information with the preset test information, and only collects low level information in the initial test result information. Because the initial test result information output by the chip only generates low-level information when the test code is operated, and high-level information is generated when the test code is not operated, the low-level information in the initial test result information is less than the high-level information in general cases, and only the low-level information in the initial test result information is acquired, so that the acquisition of minimum data can be realized, and the occupation of test resources is reduced to the greatest extent.
And in order to ensure the accuracy of the test result, the effective information is complemented to obtain the complete test result information. Performing completion operation on the effective information according to the first periodic sequence to obtain the test information, wherein the implementation principle is as follows:
obtaining a second periodic sequence according to the first periodic sequence; setting non-collected test information based on the second periodic sequence; the non-collected test information is initial test result information which is not determined to be effective information; and combining the effective information and the non-collected test information according to the size sequence of the first periodic sequence and the second periodic sequence to obtain test result information.
It should be understood that when the test device receives the low level information and the high level information in the initial test result information, the information is collected by taking a periodic sequence as a period, and each periodic sequence collects one high level information or one low level information, that is, each periodic sequence collects 1 bit (bit) of data. Since the low level information is effective information, the high level information is initial test result information which is not determined to be effective information, that is, discarded initial test result information, that is, non-collected test information. The periodic sequence corresponding to the effective information is a first periodic sequence, the periodic sequence corresponding to the non-collected test information is a second periodic sequence, so the periodic sequence corresponding to the low-level information is the first periodic sequence, and the periodic sequence corresponding to the high-level information is the second periodic sequence.
In the present disclosure, a periodic sequence may be understood as a time period, each of which collects one high level information or one low level information, i.e., each of which collects 1 bit (bit) of data. Similarly, the chip also outputs one high level information or low level information in the initial test result information by taking the periodic sequence as a time period. For example, if the periodic sequence is 1ns, the chip continuously outputs the low level information or the high level information during the period of 1ns, and similarly, the test device continuously receives the low level information or the high level information during the period of 1 ns. Since the periodic sequence is 1ns, that means that a level information is generated every 1ns, if the 1 st ns, the 2 nd ns, the 5 th ns and the 10 th ns are all low level information, the 1 st ns, the 2 nd ns, the 5 th ns and the 10 th ns are the first periodic sequence, and the 3 rd ns, the 4 th ns, the 6 th ns, the 7 th ns, the 8 th ns and the 9 th ns are the second periodic sequence after the first periodic sequence is complemented. Correspondingly, the information generated at 3ns, 4ns, 6ns, 7ns, 8ns, and 9ns is high level information.
And combining the effective information and the non-collected test information according to the size sequence of the first periodic sequence and the second periodic sequence to obtain test result information, namely obtaining initial test result information output by the chip. For example, if the 1 st ns, the 2 nd ns, the 5 th ns and the 10 th ns are the first periodic sequence, and the 3 rd ns, the 4 th ns, the 6 th ns, the 7 th ns, the 8 th ns and the 9 th ns are the second periodic sequence, the effective information and the non-collected test information are combined according to the order of the first periodic sequence and the second periodic sequence, and the obtained test result information is: 1ns is low level information, 2ns is low level information, 3ns is high level information, 4ns is high level information, 5ns is low level information, 6ns is high level information, 7ns is high level information, 8ns is high level information, 9ns is high level information, and 10ns is low level information, and the test result information is expressed as follows in binary format: 0011011110.
in order to ensure the stability of the sampled data, the present disclosure may collect valid information at a preset sampling rate.
It should be appreciated that the preset sampling rate is at least 2 times the output rate of the chip. The sampling rate of the test equipment for collecting the effective information is at least 2 times of the output rate of the serial port pin of the chip for outputting the effective information. The preset sampling rate is set to be at least 2 times of the output rate of the chip, the sampling rate is set according to the principle of the sampling theorem, and the sampled information can be recovered generally more than twice, so that the stability of the sampled data can be ensured. For example, if the output rate of the serial pin of the chip is 576KHz, the preset sampling rate of the test equipment may be set to 1152KHz.
Because multiple sampling rates are adopted during collection, after the effective information is complemented, the test result information collected by the test equipment needs to be restored to the initial test result information output by the chip in the following mode. The specific implementation mode is as follows:
and recovering the completed test result information into initial test result information according to the relation between the preset sampling rate and the output rate of the chip.
If the relation between the preset sampling rate and the output rate is 5 times, combining 5 level information of the completed test result information into one level information, and combining the combined level information into initial test result information. For example, if the completed test result information is 0000011111000001111111111 and the preset relationship between the sampling rate and the output rate is 5 times, the recovered initial test result information is 01011.
Because the initial test result information output by the chip is in a binary format, in order to increase the readability, format conversion can be performed on the initial test result information to obtain final test result information.
It should be appreciated that the binary format of the initial test result information may be converted to an ASCII (American Standard Codefor Information Interchange ) format.
To facilitate an understanding of the principles of implementation of the solution of the present disclosure, reference will now be made to fig. 3. The testing equipment collects effective information meeting preset conditions according to a preset sampling rate, and records a first periodic sequence corresponding to the effective information, namely low-level information in initial test result information is collected according to the preset sampling rate, the preset sampling rate is 5 times of the output rate of the chip, and the first periodic sequence recorded by the testing equipment is 11, 12, 13, 14, 15, 21, 22, 23, 24 and 25 as shown in figure 3; obtaining a second periodic sequence according to the first periodic sequence, wherein the obtained second periodic sequence is shown as 16, 17, 18, 19 and 20 in fig. 3, and arranging the first periodic sequence and the second periodic sequence according to the size sequence of the first periodic sequence and the second periodic sequence, namely 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 and 25 in fig. 3; according to the mapping relation between the first periodic sequence and the second periodic sequence and the level information, namely the time corresponding to the low level information (namely the effective information) of the first periodic sequence, the time corresponding to the high level information (namely the non-collected test information) of the second periodic sequence, the low level information and the high level information are arranged according to the size sequence of the first periodic sequence and the second periodic sequence, and the completed test result information is obtained, namely 000001111100000 shown in fig. 3; combining five level information in the completed test result signals into one level information according to a 5-frequency multiplication relation between a preset sampling rate and the output rate of the chip, namely combining five 0 in 000001111100000 into one 0 and combining five 1 into one 1 to obtain initial test result information 010; and converting the format of the initial test result information from binary system to ASCII code to obtain final test result information, namely STRING in figure 3.
The test procedure of the present disclosure may be a pre-light test that is performed by the chip during the wafer test phase.
It should be understood that the test contents of the pre-ignition test include the on-current-path test of the chip, the access function test of the module and the interface. The modules may be fuse modules, SRAM (static random access memory) modules, low power consumption modules, etc., and the interfaces may be DDR (double data rate) interfaces, PCIE (PCI express, PCI standard protocol) interfaces, etc.
In general, the pre-lighting test of the chip is performed in a system verification stage, and the produced wafer needs to be cut and packaged into individual chips, and then soldered on an EVB (evaluation board) board, and then subjected to the system verification test. The compiled test case file is downloaded to the appointed position of the chip SRAM through the serial port, the chip runs the test case, and the power-on flow, the module and the interface access of the chip are obtained through log (system log) output by the serial port, so that whether the abnormality exists or not.
The pre-lighting test of the chip is advanced to the wafer test stage, the chip with problems can be screened out in the wafer test stage, the whole time can be advanced by about 2-5 weeks, the follow-up verification pressure of the chip is greatly relieved, and a foundation is provided for normal or advanced release of the chip. And the pre-lighting test of the chip is advanced to the wafer test stage, the chip is pre-lighting tested in the wafer test stage, packaging is not needed, and test hardware is not needed, namely, the wafer bare chip is tested through the test equipment, so that risks of chip packaging and delay of the test hardware (such as an EVB board card) can be eliminated, and the packaging cost of the failed chip can be saved.
The test cases of the pre-lighting test are carried into the SRAM of the chip for execution through JTAG (Joint Test Action Group, joint test working group) links, and the test cases of the normal wafer test are not different from the test cases of the normal wafer test, and special circuits, registers, multiplexing keys and the like are not required to be designed for the chip, and hardware of test equipment is not required to be modified.
The test cases of the present disclosure may be generated based on the following:
receiving an initial test case provided by a system test platform; protocol conversion is carried out on the initial test case, and a waveform file is obtained; converting the format of the waveform file to obtain a text file; converting the format of the text file to obtain a test case; and sending the test cases to the chip so that the chip runs the test cases.
It should be understood that the simulation and verification of the test cases of the pre-lighting test can be performed by the system test platform in the system level simulation environment, after the verification is passed, the initial test cases which can be downloaded into the chip SRAM are compiled, and the initial test cases are sent to the test equipment.
After receiving the initial test case, the test equipment carries out protocol conversion on the initial test case, namely converts the initial test case into a VCD (Value Change Dump) waveform file according to a required interface protocol format; the VCD file format is a universal waveform file format, is an ASCII file defined in IEEE1364 standard (Verilog HDL hardware description language standard, p 325), and is a universal chip design simulation file; the VCD waveform file includes complete data of the JTAG protocol handling BootLoader, pin control information required for chip start-up, a boot post-start download data interface select GPIO pin state, and frequencies required for chip pin excitation.
After the test equipment obtains the VCD waveform file, format conversion is performed to obtain a text file, and the VCD waveform file can be converted into a STIL (Standard Test Interface Language ) file. When the STIL file conversion is carried out, the test equipment groups chip pins according to the information such as the excitation execution frequency, the function, the input/output state and the like according to the test case requirement, cuts the VCD waveform file according to the excitation execution frequency, extracts the time sequence information of the VCD waveform file, optimizes and adjusts the time sequence information, so that the VCD waveform file is concise and universal, the test requirement of the test equipment can be met, and the VCD waveform file is converted into the STIL file through the extracted time sequence information and the waveform quantity.
After the test equipment obtains the STIL file, the STIL file is converted into a test case which can be identified by the test equipment according to the requirements of the test equipment. If the test equipment can identify a binary special test case, the STIL file is converted into the test case in a binary format.
After the test equipment obtains the test cases, the test cases are carried into the SRAM space appointed in the chip through JTAG, so that the chip runs the test cases to realize the pre-lighting test.
Because the operating frequency and the operating voltage of each module or interface of the chip can be different, test cases can be grouped according to the operating frequency and the operating voltage of each module or interface of the chip, and the test cases of different groups are used for realizing the test of the corresponding module or interface of different operating frequencies or operating voltages.
Based on the same inventive concept, the embodiments of the present disclosure also provide a chip testing apparatus, which is shown in fig. 4. The chip testing apparatus 200 includes: the system comprises an acquisition module 210, a test result acquisition module 220 and a positioning module 230.
The collection module 210 is configured to collect test result information generated by running a test case in a test process; the test result information comprises running state information and positioning information generated by executing each test code in the test case.
It should be understood that the acquisition module 210 is configured to perform the content corresponding to the step 101.
The test result obtaining module 220 is configured to obtain a test result of each test code according to the running state information.
It should be understood that the test result obtaining module 220 is configured to execute the content corresponding to the step 102.
The positioning module 230 is configured to determine a position of each test code in the test case according to the positioning information.
It should be understood that the positioning module 230 is configured to perform the content corresponding to step 103 described above.
In the present disclosure, as shown in fig. 5, the acquisition module 210 includes: an acquisition subunit 211 and a completion unit 212.
The acquisition subunit 211 is configured to acquire valid information meeting a preset condition, and record a first periodic sequence corresponding to the valid information.
It should be understood that, the collecting subunit 211 is configured to match initial test result information generated by running a test case in the test process with preset test information, so as to obtain a matching result; and determining whether the initial test result information is effective information or not based on the matching result, and acquiring the effective information if the initial test result information is the effective information.
In the present disclosure, the acquisition subunit 211 is configured to perform the content of step 1011 described above.
And the complementing unit 212 is configured to perform complementing operation on the effective information according to the first periodic sequence, so as to obtain test result information.
It should be appreciated that the complementing unit 212 is configured to obtain a second periodic sequence from the first periodic sequence; setting non-collected test information based on the second periodic sequence; the non-collected test information is initial test result information which is not determined to be effective information; and combining the effective information and the non-collected test information according to the size sequence of the first periodic sequence and the second periodic sequence to obtain test result information.
In this disclosure, the completion unit 212 is configured to perform the content of step 1012 described above.
Based on the same inventive concept, embodiments of the present disclosure also provide a test apparatus including a memory for storing one or more programs, and one or more processors; the one or more programs, when executed by the one or more processors, implement the chip testing methods as described above.
Based on the same inventive concept, the embodiments of the present disclosure also provide a computer storage medium having a computer program stored thereon, which when executed by a processor, implements the steps of the aforementioned chip test method.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (12)
1. A method of testing a chip, comprising:
collecting effective information which is generated by running a test case and meets preset conditions in the test process, discarding non-collected test information which does not meet the preset conditions, and recording a first periodic sequence corresponding to the effective information; the non-collected test information is initial test result information which is not determined to be the effective information;
obtaining a second periodic sequence according to the first periodic sequence, setting the non-collected test information based on the second periodic sequence, and combining the effective information and the non-collected test information according to the size sequence of the first periodic sequence and the second periodic sequence to obtain test result information; the test result information comprises running state information and positioning information generated by executing each test code in the test case;
obtaining test results of each test code according to the running state information;
and determining the position of each test code in the test case according to the positioning information.
2. The method according to claim 1, wherein the step of collecting the valid information meeting a preset condition comprises:
matching initial test result information generated by running the test cases in the test process with preset test information to obtain a matching result;
and determining whether the initial test result information is the effective information or not based on the matching result, and acquiring the effective information if the initial test result information is the effective information.
3. The method according to claim 1, wherein collecting the valid information meeting the preset condition comprises:
and collecting the effective information according to a preset sampling rate.
4. A method according to claim 3, wherein the predetermined sampling rate is at least 2 times the output rate of the chip.
5. The method of claim 3, wherein the obtaining a second periodic sequence according to the first periodic sequence, setting the non-collected test information based on the second periodic sequence, merging the valid information and the non-collected test information according to the order of sizes of the first periodic sequence and the second periodic sequence, and obtaining test result information further comprises:
restoring the completed test result information into initial test result information according to the relation between the preset sampling rate and the output rate of the chip;
and carrying out format conversion on the initial test result information to obtain the test result information.
6. The method of claim 1, wherein the test procedure is a pre-light test performed by the die during a wafer test phase.
7. The method of claim 1, wherein the location information comprises address information, time information, and a module name.
8. The method according to claim 1, wherein the method further comprises:
receiving an initial test case provided by a system test platform;
performing protocol conversion on the initial test case to obtain a waveform file;
converting the format of the waveform file to obtain a text file;
converting the format of the text file to obtain the test case;
and sending the test case to the chip so that the chip runs the test case.
9. A chip testing apparatus, comprising:
the acquisition module is used for acquiring test result information generated by running the test cases in the test process; the test result information comprises running state information and positioning information generated by executing each test code in the test case;
the acquisition module comprises an acquisition subunit and a complementation unit, wherein the acquisition subunit is used for acquiring effective information which is generated by running a test case in the test process and accords with preset conditions, discarding non-acquired test information which does not accord with the preset conditions, and recording a first periodic sequence corresponding to the effective information; the non-collected test information is initial test result information which is not determined to be the effective information; the completion unit is configured to obtain a second periodic sequence according to the first periodic sequence, set the non-collected test information based on the second periodic sequence, and combine the effective information and the non-collected test information according to the size sequence of the first periodic sequence and the second periodic sequence to obtain the test result information;
the test result acquisition module is used for acquiring test results of each test code according to the running state information;
and the positioning module is used for determining the position of each test code in the test case according to the positioning information.
10. The apparatus of claim 9, wherein the collecting subunit is configured to match initial test result information generated by running a test case in a test process with preset test information to obtain a matching result;
the acquisition subunit is further configured to determine whether the initial test result information is the valid information based on the matching result, and if so, acquire the valid information.
11. A test apparatus comprising a memory for storing one or more programs, and one or more processors; the one or more programs, when executed by the one or more processors, implement the method of any of claims 1-8.
12. A computer storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the method according to any of claims 1 to 8.
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