CN117076337B - Data transmission method and device, electronic equipment and readable storage medium - Google Patents
Data transmission method and device, electronic equipment and readable storage medium Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3652—Software debugging using additional hardware in-circuit-emulation [ICE] arrangements
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
- G06F11/3656—Software debugging using additional hardware using a specific debug interface
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- G—PHYSICS
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- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention provides a data transmission method, a data transmission device, electronic equipment and a readable storage medium, and relates to the technical field of computers. The method comprises the following steps: under the condition that the data acquisition condition is met, acquiring target data in the mass storage unit by utilizing a logic reading module; packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage addresses one by one; and sending the target file to target equipment for the target equipment to analyze and use the target file. The embodiment of the invention provides a feasible implementation way for reading the configuration data from the mass storage unit of the programmable logic chip to the target device, and improves the efficiency of reading the configuration data from the programmable logic chip to the target device.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a data transmission method, a data transmission device, an electronic device, and a readable storage medium.
Background
The Readback technology plays a key role in the design and verification of Field programmable gate arrays (Field-Programmable Gate Array, FPGAs). Configuration data in the FPGA chip can be read into simulation software through a Readback technology to perform operations such as verification, debugging and backup.
Currently, FPGA vendors typically offer FPGA development tools and command line options that allow users to perform Readback operations. These operations typically allow a user to read configuration data from the FPGA into an external storage device for subsequent processing.
However, in addition to the conventional logic configuration, some mass storage units may be present in the FPGA chip, such as super ram (URAM) of xilinx (xilinx). Current Readback technology cannot read data from a mass storage unit.
Disclosure of Invention
The embodiment of the invention provides a data transmission method, a data transmission device, electronic equipment and a readable storage medium, which can solve the problem that data cannot be read from a mass storage unit of a programmable logic chip in the related technology.
In order to solve the problems, the embodiment of the invention discloses a data transmission method which is applied to a programmable logic chip, wherein the programmable logic chip comprises a design to be tested, a logic reading module and a large-capacity storage unit, the large-capacity storage unit is used for storing configuration data of the design to be tested, and the logic reading module and the large-capacity storage unit are parallel and commonly connected to a data output port of the design to be tested; the method comprises the following steps:
Under the condition that the data acquisition condition is met, acquiring target data in the mass storage unit by utilizing the logic reading module;
packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage addresses one by one;
and sending the target file to target equipment for the target equipment to analyze and use the target file.
On the other hand, the embodiment of the invention discloses a data transmission device which is applied to a programmable logic chip, wherein the programmable logic chip comprises a design to be tested, a logic reading module and a large-capacity storage unit, the large-capacity storage unit is used for storing configuration data of the design to be tested, and the logic reading module and the large-capacity storage unit are parallel and commonly connected to a data output port of the design to be tested; the device comprises:
the acquisition module is used for acquiring target data in the large-capacity storage unit by utilizing the logic reading module under the condition that the data acquisition condition is met;
the packaging module is used for packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage addresses one by one;
And the sending module is used for sending the target file to target equipment so as to be used for analyzing the target file by the target equipment.
In still another aspect, the embodiment of the invention also discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used for storing executable instructions which enable the processor to execute the data transmission method.
The embodiment of the invention also discloses a readable storage medium, which enables the electronic equipment to execute the data transmission method when the instructions in the readable storage medium are executed by the processor of the electronic equipment.
The embodiment of the invention has the following advantages:
the embodiment of the invention provides a data transmission method, which is characterized in that a logic reading module is additionally arranged in a programmable logic chip, so that the programmable logic chip can acquire target data from a large-capacity storage unit of the programmable logic chip by utilizing the logic reading module under the condition that the data acquisition condition is met, the target data are packed into a target file according to the storage address of the target data in the large-capacity storage unit, the configuration data in the large-capacity storage unit are read to target equipment in the form of the target file, a feasible implementation mode is provided for reading the configuration data from the large-capacity storage unit of the programmable logic chip to the target equipment, and the efficiency of reading the configuration data from the programmable logic chip to the target equipment is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of an embodiment of a data transmission method of the present invention;
FIG. 2 is a schematic diagram of a data transmission system according to the present invention;
FIG. 3 is a schematic diagram of another data transmission system according to the present invention;
fig. 4 is a block diagram of a data transmission apparatus of the present invention;
fig. 5 is a block diagram of an electronic device for data transmission according to an example of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
Method embodiment
Referring to fig. 1, a flowchart illustrating steps of an embodiment of a data transmission method according to the present invention may specifically include the steps of:
And step 101, acquiring target data in the mass storage unit by utilizing the logic reading module under the condition that the data acquisition condition is met.
102, packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage addresses one by one.
And step 103, sending the target file to target equipment for the target equipment to analyze and use the target file.
The data transmission method provided by the embodiment of the invention can be applied to a programmable logic chip, wherein the programmable logic chip comprises a design to be tested, a logic reading module and a large-capacity storage unit; the large-capacity storage unit is used for storing configuration data of the design to be tested, and the logic reading module is parallel to the large-capacity storage unit and is commonly connected to a data output port of the design to be tested. The programmable logic chip can be an FPGA chip, the design to be tested (Design Under Test, DUT) is a hardware design running on the FPGA chip, and the design to be tested in prototype verification is a circuit design or implementation. The mass storage unit may be a URAM, or may be other mass storage units provided by other FPGA manufacturers, which is not particularly limited in the embodiments of the present invention.
The logic reading module is a module for reading configuration data in the large-capacity storage unit, is parallel to the large-capacity storage unit and is commonly connected to a data output port of the design to be tested, and is used for acquiring target data stored in the large-capacity storage unit of the design to be tested under the condition that data acquisition conditions are met, packaging the target data according to a storage address of the target data in the large-capacity storage unit, obtaining a target file, and sending the target file to target equipment.
In an embodiment of the present invention, the Logic Read module may include, but is not limited to, an integrated Logic analyzer (Integrated Logic Analyzer, ILA), signalTap, virtual Input/Output (VIO) port, a Logic Read Logic device, and the like. The virtual input/output port is matched with the logic reading device, and is often used for testing, debugging and verifying circuits in the programmable logic chip. It allows a designer to simulate and manipulate the input and output of a circuit in a software manner, without actually connecting physical signals, providing a more flexible and efficient way of testing and debugging. SignalTap is a hardware-based logic analysis tool that allows designers to monitor and analyze signals inside programmable logic chips in real-time.
The target device may be a personal computer (personal computer, PC) device with simulation software installed, or an external storage device other than a programmable logic chip, which is not particularly limited in the embodiment of the present invention.
It should be noted that the programmable logic chip may establish a connection with the target device through any one of a universal serial bus (Universal Serial Bus, USB) interface, ethernet, and an optical fiber interface.
Referring to fig. 2, there is shown a schematic architecture of a data transmission system of the present invention. The data transmission system comprises a programmable logic chip 20 and a target device 30, wherein the programmable logic chip 20 establishes a connection with the target device 30 for transmitting a target file to the target device 30.
The programmable logic chip 20 includes a design 201 to be tested, a mass storage unit 202 and a logic reading module 203, and the logic reading module 203 is parallel to the mass storage unit 202 and commonly connected to a data output port of the design 201 to be tested.
In the embodiment of the invention, the logic reading module can be utilized to acquire the target data from the mass storage unit under the condition that the programmable logic chip meets the data acquisition condition in the operation process. The target data are part or all of the data stored in the mass storage unit, and the data stored in the mass storage unit are configuration data of the design to be tested.
Wherein, a preset buffer area corresponding to the logic reading module can be set, after the programmable logic chip obtains the target data in the execution step 101, the target data can be temporarily stored in the preset buffer area, and under the condition that the data transmission condition is met, the execution step 102 obtains the target file, and the execution step 103 transmits the target file to the target device; of course, the programmable logic chip may not set the preset buffer area, and after executing step 101 to obtain the target data, step 102 and step 103 may be directly executed to send the target file corresponding to the target data to the target device.
It should be noted that, in the case of setting the preset cache area, the logic reading module may be any one of an integrated logic analyzer and a SignalTap, and the preset cache area is a storage space opened up in the logic reading module. Under the condition that the preset buffer area is not set, the logic reading module can be a virtual input/output port and a logic reading device which are cooperatively set, wherein the virtual input/output port is connected with the large-capacity storage unit through the logic reading device.
The conditions under which the programmable logic chip performs steps 102 and 103, i.e., the data acquisition conditions, may include, but are not limited to: the programmable logic chip captures the read back signal for the mass storage unit, the programmable logic chip runs to a preset breakpoint, etc.
In the embodiment of the invention, the programmable logic chip can firstly determine the storage address of the target data in the large-capacity storage unit in the process of packaging the target data according to the storage address of the target data in the large-capacity storage unit, and then package the target data and the storage address into the target file according to a one-to-one correspondence relationship.
The programmable logic chip can determine the storage address of the target data in the mass storage unit based on the write signal when the configuration data is written into the mass storage unit by the design to be tested, and can also determine the storage address of the target data in the mass storage unit by traversing the mass storage unit.
In the embodiment of the invention, the programmable logic chip can package the target data into a file in csv format according to the storage address, or package the target data into a file in txt format or excel format, and the specific file format of the target file can be determined based on the packaging logic provided by the programmable logic chip manufacturer, which is not particularly limited in the embodiment of the invention.
After receiving the target file, the target device may parse the target file based on parsing logic corresponding to a file format of the target file, and use target data in the parsed target file.
In the case where the target device is a personal computer device in which emulation software is installed, the target device may include a parsing module, the emulation software and a cache area (e.g., sys_tb.v file) to which the emulation software corresponds. The analysis module is used for analyzing the target file, and storing target data and a storage address in the analyzed target file into the cache area so as to enable simulation software to perform operations such as verification, debugging and backup on the design to be tested based on the target data. Specifically, under the condition that the target device receives the target file sent by the programmable logic chip, firstly determining the file format of the target file, and analyzing the target file into a target format supported by simulation software based on analysis logic corresponding to the file format; and writing the target data and the storage address in the analyzed target file into a cache area corresponding to the simulation software.
As an example, the simulation software installed in the target device is ModelSim and the mass storage unit is URAM. Under the condition that the target device receives the target file sent by the programmable logic chip, firstly determining that the file format of the target file is a csv format (for example, ila _uram-state.csv), and analyzing the target file into a target format supported by ModelSim (for example, uram_rb_dump.py) based on analysis logic corresponding to the csv format; and writing the target data and the storage address in the analyzed target file into a cache area corresponding to the simulation software, wherein the cache area can be, for example, a sys_tb.v file or other forms of cache areas, and the storage format of the target data and the storage address in the cache area can be a load_en, rb_addr and rb_wdata. Referring to table 1, a correspondence relationship between target data and a storage address in a cache area corresponding to simulation software in the present invention is shown.
TABLE 1
It should be noted that, the correspondence relationship between the target data and the storage address shown in table 1 is only an example, and in the actual application scenario, the data content and the storage address of different target data are different.
In the embodiment of the invention, when the target device is an external storage device, the target device may include an analysis module and a storage area, where the analysis module is configured to analyze the target file and store the target data and the storage address in the analyzed target file into the storage area.
According to the data transmission method provided by the embodiment of the invention, the logic reading module is additionally arranged in the programmable logic chip, so that the programmable logic chip can acquire target data from the large-capacity storage unit of the programmable logic chip under the condition that the data acquisition condition is met, the target data is packaged into the target file according to the storage address of the target data in the large-capacity storage unit, the configuration data in the large-capacity storage unit is read to the target device in the form of the target file, a practical realization mode is provided for reading the configuration data from the large-capacity storage unit of the programmable logic chip to the target device, and the efficiency of reading the configuration data from the programmable logic chip to the target device is improved.
Optionally, the data acquisition condition includes at least one of:
capturing a write signal corresponding to the mass storage unit, wherein the write signal is effective;
a readback signal is captured for the mass storage unit.
In the embodiment of the invention, under the condition that the write signal corresponding to the large-capacity storage unit is effective, the configuration data indicating the design to be tested is written into the large-capacity storage unit, and the programmable logic chip can acquire the target data stored in the large-capacity storage unit and the storage address of the target data in the large-capacity storage unit by utilizing the logic reading module based on the write signal. At this time, the target data is configuration data corresponding to the write signal.
The Readback signal may be a Readback signal generated based on a Readback technique. Specifically, the readback signal may be a signal generated by the target device and sent to the programmable logic chip when the target data readback condition is satisfied; the read-back signal may also be a signal generated by the programmable chip if the target data read-back condition is met. At this time, the target data is configuration data corresponding to the readback signal.
Among other things, data write-back conditions include, but are not limited to: errors in running the design under test, the running time of the design under test reaching a preset time period, etc.
It will be appreciated that the programmable logic chip may utilize the logic read module to obtain target data in the mass storage unit each time there is a data write to the mass storage unit or a data write back to the target device is required in the mass storage unit.
Specifically, the programmable logic chip may acquire target data in the mass storage unit by using the logic reading module when a write signal corresponding to the mass storage unit is captured each time and the write signal is valid. The programmable logic chip may also acquire target data in the mass storage unit with the logic read module each time a readback signal for the mass storage unit is captured.
The programmable logic chip can capture a write signal or a read-back signal corresponding to the mass storage unit through the logic reading module; the programmable logic chip may capture a write signal or a read-back signal corresponding to the mass storage unit through a functional module other than the logic reading module, which is not particularly limited in the embodiment of the present invention.
Optionally, in step 101, in a case that the data acquisition condition is met, acquiring, by using the logic reading module, the target data in the mass storage unit includes:
And step 1011, recording a write address carried by the write signal and data to be written by using the logic reading module under the condition that the data acquisition condition is that the write signal corresponding to the mass storage unit is captured and the write signal is effective.
Step 1012, determining the data to be written as target data.
Step 1013, determining the write address as a storage address of the target data in the mass storage unit.
In the embodiment of the invention, the write signal carries the data to be written and the write address of the data to be written in the mass storage unit. The write-in data and the write-in address are in one-to-one correspondence, and one write-in signal can carry at least one group of data to be written in and the write-in address corresponding to the data to be written in.
It can be understood that, under the condition that the data acquisition condition is that the write signal corresponding to the mass storage unit is captured and the write signal is effective, the logic reading module can directly determine the target data and the storage address according to the data to be written and the write address carried in the write signal, without acquiring the target data and the storage address by accessing the mass storage unit, thereby improving the efficiency of acquiring the target data in the mass storage unit by using the logic reading module.
Specifically, when the write signal corresponding to the mass storage unit is captured and the write signal is valid, the logic reading module may record the data to be written and the write address in the write signal according to a one-to-one correspondence relationship between the data to be written and the write address, determine the data to be written as target data, and determine the write address corresponding to the data to be written as a storage address of the target data in the mass storage unit.
Optionally, in step 101, in a case that the data acquisition condition is met, acquiring, by using the logic reading module, the target data in the mass storage unit includes:
step 1014, in the case that the data acquisition condition is that a read-back signal for the mass storage unit is captured, traversing the mass storage unit by using the logic reading module, and reading target data stored in the mass storage unit.
In embodiments of the present invention, the read-back signal may be used to instruct the logic read module to read some or all of the data stored in the mass storage unit.
Specifically, in the case where a readback signal for the mass storage unit is captured and the readback signal is used to instruct the logic reading module to read all the data stored in the mass storage unit, the programmable logic chip may traverse the mass storage unit with the logic reading module, read all the data stored in the mass storage unit, and take the read all the data as target data.
When the readback signal for the mass storage unit is captured and the readback signal is used for indicating the logic reading module to read part of the data stored in the mass storage unit, the readback signal can carry a storage address corresponding to the target data to be read, and the programmable logic chip can traverse the mass storage unit by utilizing the logic reading module based on the storage address carried by the readback signal and read the target data from the storage address.
Optionally, the logic reading module is configured with a preset storage space; before packaging the target data according to the storage address of the target data in the mass storage unit in step 102 to obtain a target file, the method further includes:
and step S11, storing the target data into the preset storage space according to the storage address of the target data in the mass storage unit.
In the embodiment of the invention, in the case that the logic reading module is configured with the preset storage space, the programmable logic chip can store the target data into the preset storage space after acquiring the target data in the mass storage unit by using the logic reading module. After that, in the case where the conditions for performing steps 102 and 103 are satisfied, the programmable logic chip re-uses the logic reading module to read out the target data from the preset storage space, and performs steps 102 and 103.
Wherein the depth of use of the target storage space is the same as the depth of use of the mass storage unit. For example, in the case where the use depth of the mass storage unit is 4096, a preset storage space having the use depth of 4096 may be configured for the logic reading module accordingly.
It should be noted that in step 101, the programmable logic chip may record the storage addresses corresponding to each group of target data while acquiring the target data in the mass storage unit by using the logic reading module, and store the target data and the storage addresses in a one-to-one correspondence to the preset storage space.
In the embodiment of the invention, when the logic reading module is an integrated logic analyzer or a SignalTap, a preset storage space can be configured in the integrated logic analyzer or the SignalTap; under the condition that the logic reading module is a virtual input/output port and a logic reading device which are cooperatively arranged, a preset storage space can be configured in the logic reading device.
Optionally, the logic reading module comprises a virtual input-output interface and a logic reading device; in step 101, in the case that the data acquisition condition is met, acquiring, by using the logic reading module, the target data in the mass storage unit includes:
Step 1015, in the case that the data acquisition condition is satisfied, acquiring the target data in the mass storage unit by using the logic read device.
Step 1016, obtaining the target data from the logic read device according to a preset period by using the virtual input/output interface.
Step 102, packaging the target data according to the storage address of the target data in the mass storage unit to obtain a target file, including:
and 1021, packaging the target data and the storage address of the target data in the mass storage unit by using the virtual input/output interface to obtain a target file.
Step 103, sending the target file to a target device, including:
and step 1031, transmitting the target file to target equipment by utilizing the virtual input/output interface.
Referring to fig. 3, a schematic diagram of the architecture of another data transmission system of the invention is shown. The system includes a programmable logic chip 20 and a target device 30; the programmable logic chip 20 includes a design under test 201, a mass storage unit 202, and a logic read module 203, and the logic read module 203 includes a logic read device 2031 and an analog input output port 2032.
Specifically, the logic reading device is connected with the large-capacity storage unit, and is used for acquiring target data in the large-capacity storage unit under the condition that the data acquisition condition is met, so that the virtual input/output interface can acquire the target data from the logic reading device according to a preset period.
The programmable logic chip can store target data into the preset storage space after the target data in the large-capacity storage unit are acquired by the logic read device; then, the programmable logic chip can acquire target data from a preset storage space of the logic reading device according to a preset period by utilizing the virtual input/output interface.
It should be noted that the preset period may be a clock period in which the programmable logic chip operates, or may be a period formed by a plurality of clock periods. In the embodiment of the invention, the preset break point can be set at the preset period, and when the programmable logic chip runs to the preset break point, the running process of the programmable logic chip is interrupted, and the programmable logic chip traverses the logic reading device by utilizing the virtual input/output interface to acquire the target data from the logic reading device.
In the embodiment of the invention, when the logic reading module is an integrated logic analyzer or a SignalTap, the logic reading module needs to occupy a larger circuit area due to the configuration of a preset storage space, and meanwhile, the logic reading module can package target data according to the storage address of the target data in a large-capacity storage unit in the normal operation process of a programmable logic chip due to the existence of the preset storage space, so as to obtain a target file, and the target file is sent to target equipment. Therefore, no extra data read-back time is needed, and the data read-back efficiency is high.
In the case that the logic reading module includes a virtual input/output port and a logic reading device, a preset storage space is not required to be configured for the virtual input/output port, so that the virtual input/output port occupies a smaller circuit area, however, when the virtual input/output port is utilized to obtain target data from the logic reading device, the operation of the programmable logic chip needs to be interrupted, and the data reading time is longer.
In the actual application process, the logic reading module can be flexibly determined based on the circuit area of the programmable logic chip and the efficiency requirement of reading back to the target device, and the embodiment of the invention is not particularly limited.
As an example, after the design to be tested is NutShell, nutShell is comprehensively implemented, 4 integrated logic analyzers are shared, and all the integrated logic analyzers are from an array_3_ext module in the topain.v, and when a write signal corresponding to a mass storage unit is captured and the write signal is valid (write_enable), a logic reading module is utilized to obtain target data in the mass storage unit and a storage address (addr+data) corresponding to the target data, and the implementation process is as follows:
module array_3_ext(
input RW0_clk,
input [11:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask, //<---4*wr_en
input [255:0] RW0_wdata,
output [255:0] RW0_rdata
);
reg reg_RW0_ren;
reg [11:0] reg_RW0_addr;
reg [255:0] ram [4095:0]; //<---4*URAM
...
...
...
as shown in the code, the target data and the storage address of the target data sent to the URAM by the design under test can be easily intercepted by the reg [255:0] ram [4095:0 ].
In summary, the embodiment of the invention provides a data transmission method, by adding a logic reading module in a programmable logic chip, the programmable logic chip can acquire target data from a large-capacity storage unit of the programmable logic chip by utilizing the logic reading module under the condition that the data acquisition condition is met, package the target data into a target file according to a storage address of the target data in the large-capacity storage unit, and read configuration data in the large-capacity storage unit to target equipment in the form of the target file, thereby providing a feasible implementation mode for reading the configuration data from the large-capacity storage unit of the programmable logic chip to the target equipment, and improving the efficiency of reading the configuration data from the programmable logic chip to the target equipment.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Device embodiment
Referring to fig. 4, a block diagram of a data transmission device of the present invention is shown, and the block diagram is applied to a programmable logic chip, where the programmable logic chip includes a design to be tested, a logic reading module, and a large-capacity storage unit, where the large-capacity storage unit is used to store configuration data of the design to be tested, and the logic reading module is parallel to the large-capacity storage unit and connected together to a data output port of the design to be tested; the device may specifically include:
an acquisition module 401, configured to acquire target data in the mass storage unit by using the logic reading module when a data acquisition condition is satisfied;
A packaging module 402, configured to package the target data according to a storage address of the target data in the mass storage unit, to obtain a target file; in the target file, the target data corresponds to the storage addresses one by one;
and the sending module 403 is configured to send the target file to a target device, so that the target device can parse the target file.
Optionally, the data acquisition condition includes at least one of:
capturing a write signal corresponding to the mass storage unit, wherein the write signal is effective;
a readback signal is captured for the mass storage unit.
Optionally, the acquiring module includes:
the recording sub-module is used for recording a write address carried by the write signal and data to be written by utilizing the logic reading module under the condition that the data acquisition condition is that the write signal corresponding to the large-capacity storage unit is captured and the write signal is effective;
the first determining submodule is used for determining the data to be written as target data;
and a second determining sub-module for determining the write address as a storage address of the target data in the mass storage unit.
Optionally, the acquiring module includes:
and the reading sub-module is used for traversing the mass storage unit by utilizing the logic reading module and reading target data stored in the mass storage unit under the condition that the data acquisition condition is that a readback signal aiming at the mass storage unit is captured.
Optionally, the logic reading module is configured with a preset storage space; the apparatus further comprises:
and the storage module is used for storing the target data into the preset storage space according to the storage address of the target data in the large-capacity storage unit.
Optionally, the logic reading module comprises a virtual input-output interface and a logic reading device; the acquisition module comprises:
a first obtaining sub-module, configured to obtain, with the logic read device, target data in the mass storage unit if a data obtaining condition is satisfied;
the second obtaining submodule is used for obtaining the target data from the logic reading device according to a preset period by utilizing the virtual input/output interface;
the packaging module comprises:
the packing sub-module is used for packing the target data and the storage address of the target data in the mass storage unit by utilizing the virtual input/output interface to obtain a target file;
The sending module comprises:
and the sending sub-module is used for sending the target file to target equipment by utilizing the virtual input/output interface.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The specific manner in which the various modules perform the operations in relation to the processor of the above-described embodiments have been described in detail in relation to the embodiments of the method and will not be described in detail herein.
Referring to fig. 5, a block diagram of an electronic device for data transmission according to an embodiment of the present invention is provided. As shown in fig. 5, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions that cause the processor to perform the data transmission method of the foregoing embodiment.
The processor may be a CPU (Central Processing Unit ), general purpose processor, DSP (Digital Signal Processor ), ASIC (Application Specific Integrated Circuit, application specific integrated circuit), FPGA (Field Programmble Gate Array, field programmable gate array) or other editable device, transistor logic device, hardware components, or any combination thereof. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.
The communication bus may include a path to transfer information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus, or the like. The communication bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 5, but not only one bus or one type of bus.
The memory may be a ROM (Read Only memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only, electrically erasable programmable Read Only memory), a CD-ROM (Compact Disa Read Only, compact disc Read Only), a magnetic tape, a floppy disk, an optical data storage device, and the like.
Embodiments of the present invention also provide a non-transitory computer-readable storage medium, which when executed by a processor of an electronic device (server or terminal), enables the processor to perform the data transmission method shown in fig. 1.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has described in detail the method, apparatus, electronic device and readable storage medium for data transmission provided by the present invention, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the above description of the examples is only for helping to understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (8)
1. The data transmission method is characterized by being applied to a programmable logic chip, wherein the programmable logic chip comprises a design to be tested, a logic reading module and a large-capacity storage unit, the large-capacity storage unit is used for storing configuration data of the design to be tested, and the logic reading module and the large-capacity storage unit are parallel and commonly connected to a data output port of the design to be tested; the method comprises the following steps:
under the condition that the data acquisition condition is met, acquiring target data in the mass storage unit by utilizing the logic reading module;
packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage addresses one by one;
the target file is sent to target equipment so as to be used for analyzing the target file by the target equipment;
wherein, when the data acquisition condition is satisfied, acquiring the target data in the mass storage unit by using the logic reading module includes:
when the data acquisition condition is that a write signal corresponding to the large-capacity storage unit is captured and the write signal is effective, recording a write address carried by the write signal and data to be written by utilizing the logic reading module;
Determining the data to be written as target data;
determining the write address as a storage address of the target data in the mass storage unit; and/or the number of the groups of groups,
and under the condition that the data acquisition condition is that a readback signal aiming at the large-capacity storage unit is captured, traversing the large-capacity storage unit by utilizing the logic reading module, and reading target data stored in the large-capacity storage unit.
2. The method of claim 1, wherein the logic reading module is configured with a preset memory space;
before the target data is packed according to the storage address of the target data in the mass storage unit to obtain a target file, the method further comprises:
and storing the target data into the preset storage space according to the storage address of the target data in the mass storage unit.
3. The method of claim 1, wherein the logic read module comprises a virtual input-output interface and a logic read device;
the obtaining, by the logic reading module, the target data in the mass storage unit when the data obtaining condition is satisfied, includes:
Acquiring target data in the mass storage unit by using the logic reading device under the condition that the data acquisition condition is met;
acquiring the target data from the logic reading device according to a preset period by utilizing the virtual input/output interface;
packaging the target data according to the storage address of the target data in the mass storage unit to obtain a target file, wherein the method comprises the following steps:
packaging the target data and the storage address of the target data in the mass storage unit by utilizing the virtual input/output interface to obtain a target file;
the sending the target file to target equipment comprises the following steps:
and sending the target file to target equipment by utilizing the virtual input/output interface.
4. The data transmission device is characterized by being applied to a programmable logic chip, wherein the programmable logic chip comprises a design to be tested, a logic reading module and a large-capacity storage unit, the large-capacity storage unit is used for storing configuration data of the design to be tested, and the logic reading module and the large-capacity storage unit are parallel and commonly connected to a data output port of the design to be tested; the device comprises:
The acquisition module is used for acquiring target data in the large-capacity storage unit by utilizing the logic reading module under the condition that the data acquisition condition is met;
the packaging module is used for packaging the target data according to the storage address of the target data in the large-capacity storage unit to obtain a target file; in the target file, the target data corresponds to the storage addresses one by one;
the sending module is used for sending the target file to target equipment so as to be used for analyzing the target file by the target equipment;
wherein, the acquisition module includes:
the recording sub-module is used for recording a write address carried by the write signal and data to be written by utilizing the logic reading module under the condition that the data acquisition condition is that the write signal corresponding to the large-capacity storage unit is captured and the write signal is effective;
the first determining submodule is used for determining the data to be written as target data;
a second determining sub-module for determining the write address as a storage address of the target data in the mass storage unit; and/or the number of the groups of groups,
and the reading sub-module is used for traversing the mass storage unit by utilizing the logic reading module and reading target data stored in the mass storage unit under the condition that the data acquisition condition is that a readback signal aiming at the mass storage unit is captured.
5. The apparatus of claim 4, wherein the logic reading module is configured with a preset memory space; the apparatus further comprises:
and the storage module is used for storing the target data into the preset storage space according to the storage address of the target data in the large-capacity storage unit.
6. The apparatus of claim 4, wherein the logic read module comprises a virtual input-output interface and a logic read device; the acquisition module comprises:
a first obtaining sub-module, configured to obtain, with the logic read device, target data in the mass storage unit if a data obtaining condition is satisfied;
the second obtaining submodule is used for obtaining the target data from the logic reading device according to a preset period by utilizing the virtual input/output interface;
the packaging module comprises:
the packing sub-module is used for packing the target data and the storage address of the target data in the mass storage unit by utilizing the virtual input/output interface to obtain a target file;
the sending module comprises:
and the sending sub-module is used for sending the target file to target equipment by utilizing the virtual input/output interface.
7. An electronic device, comprising a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is configured to store executable instructions that cause the processor to perform the data transmission method according to any one of claims 1 to 3.
8. A readable storage medium, characterized in that instructions in the readable storage medium, when executed by a processor of an electronic device, enable the processor to perform the data transmission method of any one of claims 1 to 3.
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