CN115656791A

CN115656791A - Test method and test platform for chip testability design

Info

Publication number: CN115656791A
Application number: CN202211701297.5A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-01-31
Anticipated expiration: 2042-12-29
Also published as: CN115656791B

Abstract

The present disclosure relates to the technical field of new generation information, and provides a test method and a test platform for chip testability design, wherein the method is applied to the test platform, and comprises the following steps: receiving a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, wherein different test vector segments are used for realizing or testing independent chip functions of a tested chip; testing the tested chip, wherein the testing chip comprises a code for controlling the excitation signal corresponding to the testing vector segment to be output to the tested chip based on the auxiliary information; acquiring an actual vector value of the code output of the tested chip; determining a test result according to a comparison result of an expected vector value and an actual vector value included in the test vector segment; and the test result is displayed through the use case execution log. When the test method for chip testability design in the embodiment of the disclosure is applied to the test platform in the embodiment of the disclosure, the test of the testability design DFT can be completed before the chip is put into a chip aiming at a large-scale chip, so that the test platform has an enhanced function.

Description

Test method and test platform for chip testability design

Technical Field

The present disclosure relates to the field of new generation information technologies, and in particular, to a test method and a test platform for chip testability design.

Background

Design for Test (DFT) refers to inserting various hardware logics for improving the chip testability (including controllability and observability) in the original chip Design stage, and the Test vector engine software can generate Test vectors based on the logics, and the Test vectors are tested on an automatic Test machine, so as to achieve the purpose of testing large-scale chips. If some functional problems exist in the design for testability DFT itself, which causes errors in the generated Test vectors, the time for debugging the Test vectors on an Automatic Test Equipment (ATE) is greatly increased when the Test vector Test chip is used, which may affect the reliability of the Test result of the chip, increase the cost of chip testing, even affect the chip function, and cause the tape-out failure. Therefore, the testing of the DFT is a very important step after the chip production and manufacturing, and needs to be completed before the chip is put into production.

The currently mainstream known technology is to perform the testing of the chip design for testability DFT through a software Simulation platform (e.g. Simulation). However, with the development of integrated circuits, the scale of chips is getting larger and larger, and as the software simulation platform is not good at large-scale chips, the software simulation platform catches the trouble in the scale and test time of the chips, thereby forming an obvious bottleneck and providing great challenges for the chips to complete the test of design for testability DFT before the chips are put into service.

Therefore, how to complete the testing of design for testability DFT before chip-putting becomes a research focus in the field for larger-scale chips.

Disclosure of Invention

In view of this, the present disclosure provides a test method and a test platform for chip testability design, and when the test method for chip testability design according to the embodiments of the present disclosure is applied to the test platform according to the embodiments of the present disclosure, a test of design for testability DFT can be completed before a chip is put into a test for a large scale chip, so that the test platform has an enhanced function.

According to an aspect of the present disclosure, a method for testing a chip design for testability is provided, the method is applied to a test platform, and the method includes: receiving a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, wherein the test vector segments are segments which can be identified by the test platform, different test vector segments are used for realizing or testing independent chip functions of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip; testing the chip under test, comprising: code for controlling an excitation signal corresponding to the test vector segment to be output to the chip under test based on the auxiliary information; acquiring an actual vector value of the code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value which are included in the test vector segment; and the test results corresponding to the test vector segments indicate whether the chip functions corresponding to the test vector segments are normal or not, and the test results are displayed through the case execution log.

In a possible implementation manner, the code for controlling, based on the auxiliary information, an excitation signal corresponding to the test vector segment to be output to the chip under test includes: and at the time point indicated by the test cycle driving parameters in the auxiliary information, outputting the excitation signal to an input interface of the code of the chip to be tested, and outputting the actual vector value by an output interface of the code of the chip to be tested.

In a possible implementation manner, the determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment includes: when the expected vector values included in the test vector segments indicate comparison, comparing whether the expected vector values in the test vector segments are matched with the actual vector values output by the chip pins at the time points indicated by the test period comparison parameters; when the comparison result is that the actual vector value and the expected vector value at the time point are not matched, recording error information, wherein the error information comprises a test period corresponding to the time point, the actual vector value and the expected vector value at the time point; and determining a test result according to the error information.

In one possible implementation, the test platform is adapted to a software simulation platform and a hardware simulation platform.

According to another aspect of the present disclosure, a method for generating a test platform is provided, the method including: analyzing a plurality of original vector fragments to obtain test vector analysis data corresponding to each original vector fragment, wherein the plurality of original vector fragments are obtained by splitting a plurality of second test vectors, different original vector fragments are used for realizing or testing independent chip functions of a tested chip, and the second test vectors are original test vectors; analyzing test vector analysis data corresponding to each original vector segment, and identifying to obtain public information of the plurality of second test vectors; and generating a test platform according to the public information, wherein the size of the storage space of the test platform is related to the original vector segment with the largest length.

In one possible implementation manner, the common information includes one or more of chip pin parameters, time parameters, and test cycle time definitions of the tested chip.

In one possible implementation, the method further includes: and generating test vector segments corresponding to the original vector segments according to the test vector analysis data corresponding to each original vector segment, wherein the test vector segments are segments which can be identified by the test platform and are used when the test platform tests the independent chip function of the chip to be tested.

In one possible implementation manner, the chip under test includes at least one subsystem, each subsystem includes at least one module, and the splitting condition of the plurality of second test vectors includes: aiming at the part, related to the initialization function of the tested chip, of the second test vectors, obtaining a first original vector segment, wherein the first original vector segment corresponds to each subsystem and each module; aiming at a part of a plurality of second test vectors related to the initialization function of at least one subsystem of the tested chip, obtaining at least one second original vector segment, wherein each second original vector segment corresponds to one subsystem; and aiming at the part of each second test vector, which is related to the function of at least one module of the tested chip, at least one third original vector segment is obtained, wherein each third original vector segment corresponds to at least one module or function belonging to the same subsystem, and the correlation degree among a plurality of modules corresponding to the same third original vector segment is greater than a first threshold value.

In one possible implementation, the method further includes: and generating at least one execution file according to the plurality of test vector segments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test cases are executed, the plurality of test vector segments and auxiliary information corresponding to the execution files of the test cases are sequentially input to the test platform.

In one possible implementation, the test vector segments of the single execution file are generated, including the test vector segments corresponding to the first original vector segment, the second original vector segment, and the third original vector segment, and the combination condition includes at least one of: generating test vector segments of a single execution file to be combined according to a preset sequence; generating a test vector segment of a single execution file corresponding to a preset subsystem; and generating a single execution file, wherein the total number of the test vector segments corresponding to the third original vector segment is greater than or equal to the second threshold and less than or equal to the third threshold.

In a possible implementation manner, the auxiliary information includes guidance information for controlling the test platform to test the chip under test and difference information of each second test vector.

In one possible implementation, the test vector segment includes an expected vector value and a stimulus vector value of the unidirectional pin and an expected/stimulus vector value of the bidirectional pin of the chip under test in each test cycle under the test vector segment.

In one possible implementation, the plurality of second test vectors include test vectors written in different languages, including at least one of a standard test interface language stll, a waveform generation language WGL, and a test description language TDL.

According to another aspect of the present disclosure, there is provided a test platform comprising: the device comprises a receiving module, a judging module and a judging module, wherein the receiving module is used for receiving a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, the test vector segments are segments which can be identified by a test platform, different test vector segments are used for realizing or testing independent chip functions of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip; the test module is used for testing the tested chip and comprises: code for controlling an excitation signal corresponding to the test vector segment to be output to the chip under test based on the auxiliary information; acquiring an actual vector value output by the code of the chip to be tested; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the test vector segments indicate whether the chip functions corresponding to the test vector segments are normal or not, and the test results are displayed through the case execution log.

In a possible implementation manner, the code that controls, based on the auxiliary information, an excitation signal corresponding to the test vector segment to be output to the chip under test includes: and at the time point indicated by the test cycle driving parameters in the auxiliary information, outputting the excitation signal to an input interface of the code of the chip to be tested, and outputting the actual vector value by an output interface of the code of the chip to be tested.

According to another aspect of the present disclosure, there is provided a generation apparatus of a test platform, including: the first analysis module is used for analyzing a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, the plurality of original vector segments are obtained by splitting a plurality of second test vectors, different original vector segments are used for realizing or testing independent chip functions of a chip to be tested, and the second test vectors are original test vectors; the second analysis module is used for analyzing the test vector analysis data corresponding to each original vector segment and identifying to obtain the public information of the plurality of second test vectors; and the first generation module is used for generating a test platform according to the public information, and the size of the storage space of the test platform is related to the original vector segment with the largest length.

In a possible implementation manner, the common information includes one or more of chip pin parameters, time parameters and test cycle time definitions of the tested chip.

In one possible implementation, the apparatus further includes: and the second generation module is used for generating test vector segments corresponding to the original vector segments according to the test vector analysis data corresponding to each original vector segment, wherein the test vector segments are segments which can be identified by the test platform, and the test vector segments are used when the test platform tests the independent chip functions of the chip to be tested.

In one possible implementation, the apparatus further includes: and the third generation module is used for generating at least one execution file according to the plurality of test vector fragments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test cases are executed, the plurality of test vector fragments and the auxiliary information corresponding to the execution files of the test cases are sequentially input to the test platform.

In one possible implementation, generating test vector segments of a single execution file, including test vector segments corresponding to a first original vector segment, a second original vector segment, and a third original vector segment, the combining condition including at least one of: generating test vector segments of a single execution file to be combined according to a preset sequence; generating a test vector segment of a single execution file corresponding to a preset subsystem; and generating a single execution file, wherein the total number of the test vector segments corresponding to the third original vector segment is greater than or equal to the second threshold and less than or equal to the third threshold.

According to another aspect of the present disclosure, there is provided a test platform comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described chip design-for-test testing methodology when executing the instructions stored by the memory.

According to another aspect of the present disclosure, there is provided a generation apparatus of a test platform, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described test platform generation method when executing the instructions stored in the memory.

According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions, when executed by a processor, implement the above test method for chip testability design or implement the above generation method for a test platform.

According to another aspect of the present disclosure, there is provided a computer program product comprising computer readable code or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, the processor in the electronic device performs the above-mentioned method for testing chip testability design or performs the above-mentioned method for generating a test platform.

According to the test method for chip testability design, the test platform can acquire necessary information for chip testability design test by receiving a plurality of test vector segments and auxiliary information corresponding to the execution file of the test case, wherein the test vector segments are segments which can be identified by the test platform, and the auxiliary information comprises guidance information for controlling the test platform to test the chip to be tested; controlling an excitation signal corresponding to the test vector segment to be output to a code of the tested chip based on the auxiliary information, obtaining an actual vector value output by the code of the tested chip, and determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment, so that tests corresponding to a plurality of test vector segments can be completed; different test vector segments are used for realizing or testing the independent chip functions of the tested chip, so that the functions of the tested chip which can be tested by the test vector segments corresponding to the execution files can be random, and the test has randomness. Based on the test platform of the embodiment of the disclosure, the test method of the chip testability design of the embodiment of the disclosure provides a set of comprehensive test architecture, and can realize accurate positioning to the test vector segment where the test exception is located and the corresponding test cycle number. The test results corresponding to the test vector segments indicate whether the chip functions corresponding to the test vector segments are normal or not, the test results can be displayed through the case execution logs, and the automation of the test process of the chip testable design is realized. In the testing process, any non-universal self-research device, equipment and chip peripheral circuit are not needed, so that the unpredictable problem caused by other hardware is avoided, and the testing method of the chip testability design in the embodiment of the disclosure is more accurate in testing result. The length of the test vector segment can be far smaller than that of the complete test vector, so that the size of the storage space of the test platform can be set to be smaller, and the data storage pressure of the test platform is reduced.

According to the test platform generation method disclosed by the embodiment of the disclosure, test vector analysis data corresponding to each original vector fragment is obtained by analyzing a plurality of original vector fragments, the plurality of original vector fragments are obtained by splitting a plurality of second test vectors, and the test vector analysis data corresponding to each original vector fragment is analyzed, so that public information of the plurality of second test vectors can be identified; a test platform may be generated from the common information. The size of the storage space of the test platform is related to the original vector segment with the largest length, and compared with the storage of complete test vector data, the storage cost of the test platform is greatly reduced; different original vector segments are used for realizing or testing the independent chip functions of the tested chip, so that the independent chip functions of the tested chip can be respectively tested, and the mode of testing the tested chip by the test platform is more flexible. The process of analyzing the second test vector to generate the test platform can be automated, and the energy of a user for building a test environment is released; the second test vector is an original test vector, and the analysis of the second test vector does not involve converting the second test vector into a specific format, so that the distortion degree of the analysis data of the test vector and the common information compared with the second test vector can be reduced; the test platform generated by the test platform generation method provided by the embodiment of the disclosure can be used for testing chip testability design, and the completeness of the test of the chip testability design can be ensured. The test platform does not need a specific self-research hardware device and a chip peripheral circuit, and has little limitation on data storage of test vectors, logic scale of a test chip, the number of pins, pin driving capability and debugging capability after errors, so the test platform has strong universality; and the test before the chip is put into use can be realized, the problem can be found in the early stage of the chip project, the testability design risk of the chip is released to a greater extent at a lower cost, the test vector problem is eliminated, and the test vector debugging time consumed by the test vector problem on the Automatic Test Equipment (ATE) is saved, so that the test expense of the ATE is saved, and the test cost of the chip is reduced.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows a method flow diagram of a method of generating a test platform according to an embodiment of the present disclosure.

Fig. 2 shows a method flowchart of a method of generating a test platform according to an embodiment of the present disclosure.

FIG. 3 illustrates an example of test speed of a test platform on different simulation platforms in different usage modes according to an embodiment of the disclosure.

Fig. 4 illustrates an example of a plurality of test vector segments resulting from splitting one second test vector according to a splitting condition of an embodiment of the present disclosure.

FIG. 5 illustrates an example of obtaining an execution file according to an embodiment of the present disclosure.

Fig. 6 illustrates an example of combining conditions to get an execution file according to an embodiment of the present disclosure.

FIG. 7 illustrates a method flow diagram of a method for testing a design for chip testability according to an embodiment of the disclosure.

FIG. 8 illustrates a method flow diagram of a method for testing a design for chip testability according to an embodiment of the disclosure.

FIG. 9 illustrates a method flow diagram of a method for testing a design for chip testability according to an embodiment of the disclosure.

FIG. 10 shows a block diagram of a test platform according to an embodiment of the disclosure.

Fig. 11 shows a block diagram of a generation apparatus of a test platform according to an embodiment of the present disclosure.

Fig. 12 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

Several prior art methods for testing the design for testability of a chip are described below.

In a scheme in the prior art, a test system for DFT (Field-Programmable Gate Array) design based on a chip testability of a PFGA (Field-Programmable Gate Array) is provided. The system comprises a file processing device and an automatic test platform, wherein the automatic test platform comprises a hardware bottom plate and a field programmable gate array (PFGA) daughter board: the file processing device can only process test vectors in a Waveform Generation Language (WGL) format, the script converts the test vectors in the WGL format into a comprehensive code file, and the comprehensive code file is subjected to comprehensive processing and the like and then is written on a Field Programmable Gate Array (FPGA) daughter board; after the field programmable gate array FPGA daughter board is started through power-on reset, input/output (IO) excitation information is sent to a tested chip of a hardware bottom board through a slot, an actual return value output by the tested chip is obtained, and then the actual return value is compared with a preset ideal return value so as to verify the correctness of a test vector in a waveform generation language WGL format.

The method has the following defects: the chip to be tested is required to be arranged on the hardware bottom plate, so that the test before the chip is put into operation cannot be realized; test vectors in a WGL format are generated only for waveforms, and the test vectors written in other languages are not suitable; the system requires custom chip peripheral circuitry that introduces unexpected problems; the method can not be adapted to other hardware simulation platforms or software simulation platforms except for the field programmable gate array (PFGA); the model selection of the field programmable gate array FPGA can limit the data storage of the test vector, the logic scale of the chip to be tested and the quantity of pins; the test based on the field programmable gate array FPGA has very limited debugging capability on the test vector.

The second prior art proposes a testing method for designing DFT based on chip testability of general hardware devices or self-developed hardware devices. The method respectively provides corresponding test vector analysis modes aiming at test vectors of various formats, and analyzes the test vectors into data which can be processed by general hardware equipment or a self-developed hardware device; the testing environment of an automatic test machine ATE is simulated by matching with a control flow, a server or a self-developed hardware device, so that the testing of the chip testability design DFT is realized.

The scheme has the following defects: the test before the sheet casting can not be realized; the self-research hardware device is strongly related to the hardware simulation platform and cannot be adapted to the software simulation platform; customizing a chip peripheral circuit after the tape-out is finished; the hardware simulation platform is required to achieve the equivalent performance of the ATE, such as real clock frequency, signal integrity, etc., for large-scale and multi-input/output chips.

In the third scheme of the prior art, a method is provided for converting a test vector in a format unrecognizable by ATE of an Automatic Test Equipment (ATE) into a format recognizable by a self-developed hardware device and then testing the test vector by using the self-developed hardware device. The correctness of the format conversion of the test vectors is tested on a self-developed hardware device.

The scheme has the following defects: the test before the sheet casting can not be realized; the method cannot directly support various test vector formats, and the converted test vectors have certain distortion, so that the accuracy of the test result can be reduced.

In summary, the test method for chip testability design in the prior art has the following problems:

1. the test before the sheet casting can not be realized; after the test is carried out after the film is cut back, the problem is found too late, and the ATE test of an automatic test machine cannot be completely replaced;

2. the platform has poor portability and cannot be flexibly switched between a software Simulation platform (such as Simulation) and a hardware Simulation platform (such as Emulation and Field Programmable Gate Array (FPGA);

3. the hardware device can limit the data storage of test vectors, the logic scale of a test chip, the number of pins, the driving capability of the pins and the debugging capability after errors, particularly, the self-developed hardware device can bring extra hardware problems to the chip test, and the universality in the industry is poor;

4. customizing a chip peripheral circuit after tape-out is finished, wherein the peripheral circuit introduces unexpected problems;

5. the existing technology only supports the input of a single test vector format, and is too single; the prior art supports a plurality of test vector formats to be converted into one format, but cannot directly support a plurality of test vector formats and cannot extract data from an original input test vector without distortion.

In view of this, the present disclosure provides a test method and a test platform for chip design for testability, which, when applied to the test platform of the present disclosure, can complete a test of design for testability DFT before a chip is dropped on a chip with a larger scale, so that the test platform has an enhanced function.

Fig. 1 and 2 show a method flowchart of a method of generating a test platform according to an embodiment of the present disclosure. As shown in fig. 1, the test platform generation method includes steps S11 to S13:

step S11, analyzing a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, wherein the plurality of original vector segments are obtained by splitting a plurality of second test vectors, different original vector segments are used for realizing or testing independent chip functions of a tested chip, and the second test vectors are original test vectors;

step S12, analyzing the test vector analysis data corresponding to each original vector segment, and identifying to obtain the public information of a plurality of second test vectors;

and S13, generating a test platform according to the public information, wherein the size of the storage space of the test platform is related to the original vector segment with the largest length.

For example, as shown in fig. 2, a "test vector parsing engine" may be provided for executing the test platform generation method of the embodiment of the present disclosure. A user may specify a set of test vector files (not shown) that include second test vectors in multiple formats, where the second test vectors are original test vectors, i.e., test vectors that have not been format converted, may be test vectors in different formats written or generated using different tools (programming languages), and may be tested for the same piece of chip. A complete second test vector is typically used to test various functions of the chip under test, such as power-up and initialization functions of the chip, functions of each module of the chip, and so on. Therefore, the second test vectors can be decomposed according to functions, for example, a user can specify a splitting condition, each second test vector is split into a plurality of independent original vector segments, so that different original vector segments are used for testing independent chip functions of the chip under test, including a chip common initialization function, a subsystem initialization function, a test function of the whole chip or subsystem or module, and the like. Examples of the splitting conditions can be found in the related description below. Alternatively, the user is also enabled to specify a set of segments (not shown) comprising multiple formats of original vector segments, which may be segments that can form a complete plurality of second test vectors. In step S11, by analyzing a plurality of original vector segments and identifying the format of each original vector segment, valid information of each original vector segment can be extracted and stored in a local database in the form of test vector parsing data corresponding to each original vector segment for use in subsequent steps. The extracted information may be data common to test vectors in various formats, such as pins, test cycles, and the like.

Alternatively, as shown in fig. 2, a "test vector parser" (software module) may be provided in the "test vector parsing engine", and the "test vector parser" may perform the splitting step and the step S11 of the second test vector when the second test vector is used as the input of the "test vector parser"; taking the original vector fragment as input to the "test vector parser", the "test vector parser" may perform step S11. Examples of formats of the second test vector and the original vector fragment can be found in the related description below.

In step S12, by analyzing the test vector analysis data corresponding to the original vector segments of different second test vectors, a non-different portion of the analysis data of different second test vectors can be identified, and common information of a plurality of second test vectors is obtained. Optionally, as shown in fig. 2, the above-mentioned "test vector parser" may also perform step S12. The difference part of each second test vector from other second test vectors can be used as auxiliary information of the second test vector. The test vector parsed data corresponding to each original vector segment may be stored in correspondence with its corresponding auxiliary information. The auxiliary information is used when testing the chip under test. The second test vector corresponding to the test vector analysis data analyzed in this step may be all or part of the test vector file set, which is not limited in this disclosure. Examples of common information and auxiliary information may be found in the related description below.

After identifying the common information, a Testbench (TB) may be generated from the common information in step S13. Optionally, as shown in fig. 2, a "test platform generator" (software module) may be provided, the public information is used as an input of the "test platform generator", the "test platform generator" performs secondary comprehensive analysis on the public information, and summarizes functions that the test platform may have in an analysis test manner to form each module in the test platform, and the size of the storage space of the test platform may be determined according to the original vector segment with the largest length, so as to automatically generate the test platform. Alternatively, each module in the test platform may be in a form of software that is not comprehensive, or may be in a form of hardware that is comprehensive into hardware. The testing platform can complete the testing of the chips under test associated with all the original vector segments analyzed in step S13. Examples of the modules of the test platform can be found in the description of the test method section below, where the test platform performs chip design for testability.

The test platform of the embodiment of the disclosure can have the following functions: excitation driving, vector value comparison, error Information (Error Information) recording (storage) and/or outputting (printing and reporting). Examples of each function can be found in the description of the test methodology section below where the test platform performs chip design for testability.

According to the test platform generation method disclosed by the embodiment of the disclosure, test vector analysis data corresponding to each original vector fragment is obtained by analyzing a plurality of original vector fragments, the plurality of original vector fragments are obtained by splitting a plurality of second test vectors, and the test vector analysis data corresponding to each original vector fragment is analyzed, so that public information of the plurality of second test vectors can be identified; a test platform may be generated from the common information. The size of the storage space of the test platform is related to the original vector segment with the largest length, and compared with the storage of complete test vector data, the storage cost of the test platform is greatly reduced; different original vector segments are used for realizing or testing the independent chip functions of the tested chip, so that the independent chip functions of the tested chip can be respectively tested, and the mode of testing the tested chip by the test platform is more flexible. The process of analyzing the second test vector to generate the test platform can be automated, and the energy of a user for building a test environment is released; the second test vector is an original test vector, and the analysis of the second test vector does not involve converting the second test vector into a specific format, so that the distortion degree of the analysis data of the test vector and the common information compared with the second test vector can be reduced; the test platform generated by the test platform generation method provided by the embodiment of the disclosure can be used for testing chip testability design, and the completeness of the test of the chip testability design can be ensured. The test platform does not need a specific self-research hardware device and a chip peripheral circuit, and has little limitation on data storage of test vectors, logic scale of a test chip, the number of pins, pin driving capability and debugging capability after errors, so the test platform has strong universality; and the test before the chip is put into operation can be realized, the problem can be found in the early stage of a chip project, the chip testability design risk is released to a greater extent at lower cost, the test vector problem is eliminated, and the test vector debugging time consumed by the test vector problem on the Automatic Test Equipment (ATE) is saved, so that the test expense of the ATE is saved, and the test cost of the chip is reduced.

In one possible implementation manner, the plurality of second Test vectors include Test vectors written in different languages, including at least one of a Standard Test Interface Language (stll), a Waveform Generation Language (WGL), and a Test Description Language (TDL).

For example, referring to FIG. 2, the second test vector in the WGL format of the waveform generation language may be numbered A0-An, the second test vector in the STIL format of the Standard test interface language may be numbered B0-Bn, and the second test vector in the other format may be numbered C0-Cn. It should be noted that references to A0-An, B0-Bn, C0-Cn in this disclosure merely denote a number and do not denote the second test vector itself. In fig. 2, the number of the second test vectors in each format is the same and equal to n as an example, and it should be understood by those skilled in the art that the number of the second test vectors in each format may also be different, and the disclosure is not limited thereto.

Those skilled in the art should understand that the format of the second test vector can be further extended, as long as the programming language of the test vector capable of programming the chip testability design in the prior art is available, and the present disclosure does not limit the specific format of the second test vector.

In this way, diversification of the test vector format can be achieved.

Examples of common information and auxiliary information identified by analyzing test vector parsed data are described below.

In one possible implementation, the common information includes one or more of chip pin parameters, time parameters, and test cycle time definitions of the chip under test.

The chip pin parameter may indicate a chip pin used for a test and information about the chip pin such as an input attribute, an output attribute, an input and output bidirectional attribute, and the like. For example, for a second test vector In the standard test interface language stll format, the chip pins used for the test may be pins under the Signals keyword In the second test vector, and the input attribute, the output attribute, the input bidirectional attribute, and the output bidirectional attribute of each pin may be described by In, out, and intout of each pin under the Signals keyword In the second test vector respectively; for the second test vector in the waveform generation language WGL format, the chip pins used for the test may be pins under the signal keyword in the second test vector, and the input attribute, the output attribute, and the bidirectional input and output attribute of each pin may be described by each pin input, output, and bidi under the signal keyword in the second test vector. The chip pin parameter may also indicate grouping information of the chip pins, for example, for a second test vector in a standard test interface language STIL format, the grouping information of the chip pins may be described by a plurality of signal groups under a SignalGroups key in the second test vector.

The time parameter may indicate a test period, and the testing of the chip design for testability may correspond to a plurality of test periods. For example, for the second test vector in the standard test interface language stll format, the time parameter may be described by parameter values such as a test machine cycle (tester _ periods), an excitation driving time (t _ time), an excitation driving window length (t _ width), an output observation time (strobe _ t), and an output observation window length (strobe _ window _ tmp) under the Spec keyword in the second test vector; for a second test vector in the waveform generation language WGL format, the time parameter may be described by an equalitionsheet key in the second test vector.

The test cycle time definition can indicate the waveform of an excitation signal in a test cycle and the vector value time of observation chip output, wherein the excitation signal can be used for a code output to a chip to be tested, the code of the chip to be tested can generate and output a vector value according to the excitation signal, and the vector value output by the chip can be used for vector value comparison. For example, for a second test vector in the standard test interface language stll format, the waveform of the excitation signal may pass through the description of Waveforms under the Timing key in the second test vector, and in combination with the time parameter, define the time point of the waveform of the excitation signal and the vector value of the observation chip output in the test period; for the second test vector in the waveform generation language WGL format, the test cycle time definition can be described by the excitation and output observations input by each pin under the timeplate key in the second test vector.

For the second test vectors in formats other than the standard test interface language STIL and the waveform generation language WGL, the common information may be extracted based on the specific keywords included in the second test vectors, and details are not repeated here.

The chip pin parameter, the time parameter, and the test cycle time definition in the common information may be a common part defined by the chip pin parameter, the time parameter, and the test cycle time in the analysis data of each second test vector. In this way, the data processing cost of obtaining a test platform using common information can be reduced.

For example, the auxiliary information may be used to determine a control behavior of the test platform during the testability design of the chip under test performed by the test platform, for example, the test platform is controlled to execute a test method of the testability design of the chip as described below, so that the auxiliary information may include guidance information for controlling the test platform to perform the test on the chip under test, which is obtained by analyzing the test vector analysis data. The guide information may include a test period driving parameter for controlling the excitation driving manner and a test period observation alignment parameter for controlling the alignment manner, and an exemplary use manner of the guide information may be as described in the following section of the test method for chip testability design.

Next, the second test vectors are different, and the difference information between each second test vector and the other second test vectors may be stored as part of the auxiliary information along with the common information. For example, when the test cycle time definition of a second test vector is inconsistent with other second test vectors, the auxiliary information of the second test vector may include the excitation driving and output observation time definition part of the chip input in the second test vector.

In this way, the common information and the auxiliary information are combined to describe each second test vector without distortion, the amount of data needing to be stored is less, and the data storage cost is reduced.

The test platform of the embodiment of the present disclosure may be implemented by a very comprehensive hardware description language verilog. In this case, the test platform may be adapted to a hardware simulation platform, such as a hardware accelerator (Emulation), so that the test platform performs the test method of chip design for testability described below at a faster speed. The test platform of the embodiment of the disclosure can also be realized by a synthesizable hardware description language verilog and a non-synthesizable statement, and the non-synthesizable statement can be used for adding functions such as debugging and positioning to the test platform so as to improve the capability of the test platform. The test platform can also be adapted to a software Simulation platform, such as a software Simulation server (Simulation), so that the test platform can be switched between the software Simulation platform and a hardware Simulation platform, and the flexibility of the application mode of the test platform is improved. Fig. 3 and table 1 show examples of test speeds of a test platform on different simulation platforms, in different usage modes, according to an embodiment of the disclosure.

TABLE 1

Referring to fig. 3 and table 1, when the test platform of the embodiment of the present disclosure is applied to a software simulation server, the usage mode may include a simulation mode, in which the test platform may be applied in a Simulator (Simulator) scenario, and the test speed (simulation speed) is about 10Hz; when the test platform is applied to a hardware accelerator, the use mode may include a Transaction Based Acceleration (TBA) mode and an internal Circuit simulation (ICE) mode, wherein the test platform In the Transaction Based Acceleration (TBA) mode may be applied to an EMU-simulation Acceleration scenario of the hardware accelerator, the test speed (simulation speed) may reach 10khz to 100khz, the test platform In the internal Circuit simulation ICE mode may be applied to an EMU-prototype verification scenario of the hardware accelerator, and the test speed (simulation speed) may reach 100khz to 4mhz. It can be seen that the test speed (simulation speed) of the test platform when applied to the hardware accelerator is greater than the test speed (simulation speed) when applied to the software simulation server. When the method is applied to a hardware accelerator, the test speed (simulation speed) is fastest in an internal circuit simulation (ICE) mode. Moreover, the logic scale of the tested circuit supported by the test platform when the test platform is applied to the hardware accelerator is much larger than that when the test platform is applied to the software simulation server.

Alternatively, the test platform may also be applied to other hardware simulation platforms besides a hardware accelerator, such as a field programmable gate array FPGA, and other software simulation platforms besides a software simulation server, which is not limited by the present disclosure.

Through the mode, the test platform disclosed by the embodiment of the disclosure can realize the promotion of simulation speed, can be adapted to various platforms, promotes the flexibility of the application mode of the test platform, reduces the logic scale limitation degree of the tested chip, and promotes the capability of the test platform.

An example of a split condition of an embodiment of the present disclosure is described below.

In one possible implementation manner, the chip under test includes at least one subsystem, each subsystem includes at least one module, and the splitting condition of the plurality of second test vectors includes:

aiming at the part of the plurality of second test vectors related to the initialization function of the tested chip, obtaining a first original vector segment, wherein the first original vector segment corresponds to each subsystem and each module;

aiming at a part of a plurality of second test vectors related to the initialization function of at least one subsystem of the tested chip, obtaining at least one second original vector segment, wherein each second original vector segment corresponds to one subsystem;

and aiming at the part of each second test vector, which is related to the function of at least one module of the tested chip, at least one third original vector segment is obtained, wherein each third original vector segment corresponds to at least one module or function belonging to the same subsystem, and the correlation degree among a plurality of modules corresponding to the same third original vector segment is greater than a first threshold value.

For example, the chip under test may include at least one subsystem, and each subsystem may include at least one module. When writing the second test vector, corresponding parts for testing the functions of the modules and/or subsystems and/or the whole chip can be written respectively to jointly form the second test vector.

In this case, no matter which part of the chip is targeted when the second test vector is written, the test chip needs to be powered on for initialization and check whether the test chip is normal, so that the second test vector may have a part related to the initialization function of the chip under test (i.e., the above-mentioned chip common initialization function). For different second test vectors, the parts relevant for the test of the initialization function of the chips may be the same as long as the chips are the same. In this regard, a first original vector segment may be obtained for a portion of the second test vectors related to the initialization function of the chip under test, and when the second test vectors are used for testing the same chip under test, the first original vector segment may correspond to each subsystem and each module of the chip under test. In this case, the first original vector segment corresponds to the segment split from each second test vector for testing the initialization function of the chip.

When the second test vector is written for at least one subsystem and/or at least one module of the chip under test, it is necessary to test whether the power-on initialization and check functions of at least one subsystem are normal, so that the second test vector may have a portion related to the initialization function (i.e., the above-mentioned subsystem initialization function) of at least one subsystem of the chip under test. The parts relating to the testing of the initialization function of the subsystem may be the same for different second test vectors for the same subsystem. In this regard, at least one second original vector segment may be obtained for a portion of the plurality of second test vectors that is relevant to an initialization function of at least one subsystem of the chip under test, where each second original vector segment corresponds to a subsystem. In this case, the second original vector segment corresponding to a certain subsystem is equivalent to a segment split by each second test vector written for the subsystem for testing the initialization function of the subsystem.

When the second test vector is written for at least one module of the chip under test (i.e. the second test vector is used to implement or test the combined function of one module or multiple modules), it is necessary to test whether the function of at least one module is normal, so that the second test vector may have a part related to the function of at least one module of the chip under test (i.e. the above-mentioned test function of the whole chip or subsystem or module). For example, when the second test vector is written for only one module, for example, when the second test vector is written for a plurality of modules, when the degree of association between the modules is weak, the functions completed by each module can be considered to be independent, and the splitting according to the functions of each module does not have adverse effects on the function test of the modules of the chip. In order to ensure the independence and the integrity of functions, a plurality of coupled modules can be taken as a unit for splitting, and the functional test of the module group is realized.

In this regard, the embodiment of the present disclosure provides that a first threshold is set, and at least one third original vector segment is obtained for a portion of the plurality of second test vectors related to a function of at least one module of the chip under test, so that each third original vector segment corresponds to at least one module belonging to the same subsystem, and a degree of association between a plurality of modules corresponding to the same third original vector segment is greater than the first threshold, so that a portion corresponding to a module with a stronger degree of association is not split.

For different second test vectors, the parts relating to the testing of the functionality of the modules may be the same for the same module. In this case, the third original vector segment corresponding to a certain module (or certain modules) is equivalent to a segment split by each second test vector written for the certain module (or modules) for testing the function of the certain module (or modules).

As described above, the splitting step may be performed by a "test vector parser" comprised by the "test vector parsing engine". When splitting is performed based on the splitting condition, the splitting mode can be as follows:

1. when writing the second test vector, the keywords used by different functions of the module, subsystem and chip are different, so that a user can provide the keywords, and when the test vector parser determines that the second test vector has the keywords matched with the specified keywords, the fragments corresponding to the complete module or subsystem or chip function to which the determined keywords belong are split.

2. The second test Vector may include a Vector value (Tester Cycle Vector) of a pin of the chip under test in each test Cycle, the user may specify a Vector value (Tester group) of a specific pin group (pin group) of the chip in the second test Vector in the specific test Cycle, and the "test Vector parser" splits out a segment corresponding to a complete module or subsystem or chip function to which the Vector value of the specific pin group in the specific test Cycle belongs when the Vector value of the specific pin group in the second test Vector in the specific test Cycle matches the Vector value specified by the user.

3. The second test Vector may include a Vector value (Tester Cycle Vector) of the pins of the chip under test in each test Cycle, and the Vector values of the pins in each test Cycle may form a sequence. The user can specify a sequence of vector values in a specific period, and when the test vector resolver determines that the sequence of vector values in the specific test period in the second test vector matches the sequence of vector values specified by the user, the test vector resolver splits out a segment corresponding to a complete module or subsystem or chip function to which the determined sequence of vector values in the specific test period belongs.

4. The second test vector may include the timing of the pins of the chip under test. When the user can specify the time sequence of a specific pin, and the test vector resolver determines that the time sequence of the specific pin in the second test vector is matched with the time sequence specified by the user, the determined time sequence of the specific pin is divided into segments corresponding to complete modules or subsystems or chip functions.

It should be understood by those skilled in the art that the splitting manner should not be limited to the above examples, and for example, the combination of the above manners and the like can also be adopted, and the present disclosure is not limited thereto.

The "test vector parser" may store the relevant information (e.g. length, etc.) of the split original vector fragments in a database, where the length information of the original vector fragment with the largest length may be used by the "test platform generator" to calculate the storage space of the test platform, and other information may be used by the "test platform generator" to determine the control logic of the test platform, etc.

Furthermore, reasonable grouping management can be carried out on the split original vector fragments, so that the use of subsequent processes is facilitated. The original vector fragments may be stored as a set of fragments, for example. For example, the first original vector segment may be used as a segment set related to the initialization function of the chip under test, the second original vector segment corresponding to each subsystem may be used as a segment set related to the initialization function of the subsystem, and the third original vector segment corresponding to each subsystem may be used as a functional segment set of the subsystem.

After splitting a plurality of fragments based on the splitting condition specified by the user, the splitting condition satisfied by each fragment can be identified, or the fragment set to which each fragment belongs can be identified, so as to clarify the relationship between the fragments.

In one possible implementation, the method further includes:

and S14, generating test vector segments corresponding to the original vector segments according to the test vector analysis data corresponding to each original vector segment, wherein the test vector segments are segments which can be identified by the test platform and are used when the test platform tests the independent chip function of the chip to be tested.

For example, the original second test vector is a vector that is not recognizable by the test platform, so the original vector segment obtained by splitting the second test vector is also a segment that is not recognizable by the test platform, and cannot be used when the test platform tests the chip under test. In contrast, when analyzing the test Vector analysis data corresponding to the original Vector segment, in step S14, the Vector value (Tester Cycle Vector) of the original Vector segment in each test Cycle may also be obtained by extracting and converting based on the test Cycle (Tester Cycle), that is, the excitation Vector value input to each pin and the expected Vector value output from each pin in each test Cycle of the original Vector segment are stored in a data format recognizable by the test platform, so as to obtain the test Vector segment corresponding to each original Vector segment one to one. At this time, the test vector segment may be a segment that can be recognized by the test platform and can be used when the test platform tests the chip to be tested. Fig. 4 illustrates an example of a plurality of test vector segments resulting from splitting one second test vector according to a splitting condition of an embodiment of the present disclosure. In the example of fig. 4, for the second test vector of number A0, a segment for testing the initialization function of the chip, a segment for testing the initialization function of the subsystem D, and a segment for testing the functions of the modules of the subsystem D (numbers a00-A0 a) may be obtained correspondingly.

Alternatively, as shown in fig. 2, a "test vector segment generator" (software module) may be provided, and the test vector parsing data corresponding to each original vector segment is used as the input of the "test vector segment generator", and the "test vector segment generator" executes step S14. Wherein the test vector parsed data corresponding to each original vector segment may be serially input into a "test vector segment generator". Because the test vector analysis data corresponding to each second test vector also correspondingly obtains the auxiliary information of the second test vector, the auxiliary information corresponding to the same original vector segment and the test vector segment may also be corresponding, and may be output together by the "test vector segment generator". Wherein, the test vector segment obtained from the original vector segments in the same segment set can also be used as a segment set. In the example of FIG. 2, the "test vector fragment generator" output may be a set of fragments related to the initialization function of the chip under test (including fragments for testing the initialization function of the chip), a set of fragments related to the initialization function of the subsystem D (including fragments for testing the initialization function of the subsystem D), a set of fragments related to the initialization function of the subsystem E (including fragments for testing the initialization function of the subsystem E), a set of fragments related to the function of the module in the subsystem D (including fragments A00-A0a, … …, fragments Am 0-Amb), a set of fragments related to the function of the module in the subsystem E, and so on. Wherein fragments A00-A0a are derived from the second test vector numbered A0 and fragments Am0-Amb are derived from the second test vector numbered Am.

By the method, the test vector segment which can be identified by the test platform can be obtained, and the auxiliary information corresponding to the test vector segment is obtained, so that the test platform can be used for testing the tested chip.

In one possible implementation, the test vector segment includes expected vector and stimulus vector values for unidirectional pins and expected/stimulus vector values for bidirectional pins of the chip under test in each test cycle under the test vector segment.

For example, the length of a test vector segment is related to the number of cycles under the test vector segment, with longer lengths having a greater number of cycles and shorter lengths having a smaller number of cycles. The format of the test Vector segment recognizable by the test platform may be a two-dimensional array, where each row of the two-dimensional array may store Vector (Vector) data of a single test cycle, for example, when the array has m rows, the first row may store Vector data of a test cycle (test cycle) 0, and so on, the m-th row may store Vector data of a test cycle m-1, that is, the number of test cycles of the test Vector segment is equal to the depth (number of rows) of the two-dimensional array. The two-dimensional array may be a binary array such that test vector segments may be loaded directly into a storage area of the test platform. It will be understood by those skilled in the art that the two-dimensional array may be an array in other formats recognizable by the test platform memory space, and the disclosure is not limited thereto.

Based on this, the data is analyzed for the test vectors of the test vector segments, and the data of each test cycle can be analyzed first. For example, for the basic grammar, with the test period as a unit, a part corresponding to each test period in the test vector parsing data can be directly extracted, and for the test vector parsing data of the test vector segment in the standard test interface language STIL format, a part under the V keyword can be analyzed; for test vector segment test vector parse data in the waveform generation language WGL format, the portion under the vector key can be analyzed.

For Loop syntax, the Loop description for the test vector in the parse data may be expanded as data for each test period, for example, for the test vector parse data of the test vector segment in the standard test interface language stll format, the part under the Loop key may be expanded.

For scan chain syntax, it is possible to obtain scan chain definitions and some macro definitions at parsing time. The scan chain definition may be a statement for a scan unit in the scan chain, and a structural description, a state description, and the like of the scan chain, for example, for test vector analysis data of a test vector segment in a standard test interface language stll format, the structural description of the scan chain may be written under a ScanStructures keyword, including descriptions of a chain length, an inversion number, an input pin, an output pin, and a scan clock of each scan chain; for the test vector analysis data of the test vector segment in the WGL format, the structural description of the scan chain may be recorded under the scancell and scanchain keywords, and the state description of the scan chain may be recorded under the scanstate keywords. The macro definition may include a macro definition template of the test vector, e.g., the macro definition may be loaded under the MacroDefs keyword for test vector parse data for test vector fragments in the Standard test interface language, STIL, format. The data for each test cycle can be parsed by combining the scan chain definition and the macro definition.

It should be understood that, the example of analyzing the test vector analysis data to obtain the data of each test cycle should not be limited to the above manner, as long as the analysis manner can be implemented by the prior art, and the embodiment of the present disclosure does not limit this.

After the data of each test cycle is obtained, vector data (Vector) of one row in the test Vector segment can be correspondingly obtained based on the data of each test cycle. The vector data for each row may include the following: the excitation vector value and the expected vector value of the unidirectional pin of the tested chip, namely the input/output attribute of the pin is not changed in the whole testing process, and respectively occupy 2 bits; the expected/excitation vector value of the bidirectional pin of the tested chip, namely the input/output attribute of the pin changes in the whole test process, and occupies 3 bits. Optionally, a test cycle number, that is, a test cycle number of the vector data in the entire first test vector, may be further included, and the test cycle number may be used when debugging the first test vector and may occupy 32 bits. Optionally, other information can be further expanded and added to define the bit width by itself. Examples of excitation vector values for unidirectional pins and expected vector values for unidirectional pins can be seen in tables 2 and 3, respectively. An example of expected/excitation vector values for a bi-directional pin can be seen in table 4.

TABLE 2

Unidirectional base pin excitation vector value (2 bit)	Description of the invention
		2’b00	Chip pin input stimulus is 0
2’b01	Chip pin input stimulus is 1
		2’b10	-
2’b11	Chip pin input excitation is in high impedance state Z

TABLE 3

Unidirectional pin expected vector value (2 bit)	Description of the invention
		2’b00	Chip pin-out expected to be 0
2’b01	Chip pin out is expected to be 1
		2’b10	-
2’b11	Chip pin-out expected to be X, i.e. not expected

TABLE 4

Bidirectional pin excitation/expected vector value (3 bit)	Description of the preferred embodiment
		3’b000	Chip pin input stimulus is 0
3’b001	Chip pin input stimulus is 1
		3’b010	-
3’b011	Chip pin input excitation is in high impedance state Z
		3’b100	Chip pin out expected to be 0
3’b101	Chip pin out is expected to be 1
		3’b110	-
3’b111	Chip pin-out expected to be X, i.e. not expected

Referring to table 2, when it is determined that the unidirectional pin input excitation of the chip is 0 according to the test vector analysis data, an excitation vector value of 2' b00 of the unidirectional pin can be obtained; determining that the excitation input to the unidirectional pin of the chip is 1, and obtaining an excitation vector value of 2' b01 of the unidirectional pin; when the input excitation of the unidirectional pin of the chip is determined to be in a high-impedance state Z, an excitation vector value 11 of the unidirectional pin can be obtained. Wherein "2'b" is used to describe that the bit width occupied by the stimulus vector value of the unidirectional pin is 2, and the value is binary.

Referring to table 3, when it is determined that the unidirectional pin output of the chip is expected to be 0 according to the test vector analysis data, an expected vector value of 2' b00 of the unidirectional pin can be obtained; when the unidirectional pin output expectation of the chip is 1, the expected vector value of the unidirectional pin is 2' b01; when it is determined that the chip unidirectional pin output is expected to be X, i.e., unexpected, the expected vector value 11 of the unidirectional pin can be obtained.

Referring to table 4, when it is determined that the input excitation of the bidirectional pin of the chip is 0 according to the test vector analysis data, an excitation vector value of 3' b000 of the bidirectional pin can be obtained; determining that when the input excitation of the chip pin is 1, obtaining an excitation vector value of a bidirectional pin of 3' b001; when the input excitation of the chip pin is determined to be in a high-impedance state Z, an excitation vector value of 3' b011 of the bidirectional pin can be obtained; when the output expectation of the bidirectional pin of the chip is 0, the expectation vector value of the bidirectional pin is 3' b100; when the output of the bidirectional pin of the chip is determined to be 1, an expected vector value of 3' b101 of the bidirectional pin can be obtained; determining that the chip bidirectional pin output is expected to be X, i.e., unexpected, an expected vector value of 3' b111 for the bidirectional pin can be obtained. Where "3'b" is used to describe the expected/excitation vector value for the bi-directional pin occupies a bit width of 3 and the value is binary.

After determining each row of vector data of the test vector segment, determining the position of each row of vector data in the two-dimensional array according to the sequence of the test cycle sequence numbers from small to large, and thus obtaining the test vector segment in the two-dimensional array format. Table 5 shows an example of a format of a test vector segment according to an embodiment of the present disclosure.

TABLE 5

Chip pin a (unidirectional excitation)

…

Chip pin b (unidirectional expectation)

…

Chip base pin c (bidirectional)

…

Test cycle number

2’b00

…

2’b11

…

3’b000

…

32’h0000_0000

2’b01

…

2’b11

…

3’b001

…

32’h0000_0001

2’b00

…

2’b11

…

3’b111

…

32’h0000_0002

…

As shown in Table 5, each pin may have a different stimulus/expected vector value per test cycle. In the example of table 5, the chip under test may include 3 or more test cycles (test cycle numbers 32' h0000_0000, 32' h0000_0001, 32' h0000_0002, … …) and 2 or more unidirectional pins (chip pin a, chip pin b, … …), 1 or more bidirectional pins (chip pin c, … …). Taking a test cycle with a test cycle number of 32'h0000_0000 as an example, in the test cycle, the input stimulus of chip pin a can be 0 (stimulus vector value 2' b00), the output stimulus of chip pin b can be expected to be 1 (expected vector value 2 'b11), and the input stimulus of chip pin c can be 0 (stimulus/expected vector value 3' b000). "32" h "indicates that the bit width occupied by the test cycle number is 32, and the value is hexadecimal.

It is understood that the correspondence relationship between the excitation/expected vector values in binary form and the input excitation/output expectation of the pin shown in tables 2 to 4 is only an example, for example, the correspondence relationship between the excitation/expected vector values and the input excitation/output expectation of the pin may also be that when the excitation vector values are 2'b 10', the input excitation of the corresponding unidirectional pin is in a high impedance state, etc., as long as the one-to-one correspondence between the excitation/expected vector values and the input/output states of the pin is satisfied, and the excitation/expected vector values corresponding to different states of the pin are different, which is not limited by the present disclosure. Optionally, the bit width of the excitation/expected vector values, etc. may also be varied, and the disclosure is not limited thereto. The format of the first test vector shown in table 5 is merely an example, and the first test vector may further include more information, such as control information for the chip, debugging information, and the like, besides the expected/excitation vector value of the pin, which is not limited by the present disclosure.

It should be understood by those skilled in the art that the "test vector parser" may also obtain a complete vector and auxiliary information recognizable by the test platform according to the parsed data of the complete second test vector without using a splitting condition, and the complete vector and auxiliary information are used when the test platform tests the chip to be tested, which is not limited by the present disclosure.

In one possible implementation, the method further includes:

and S15, generating at least one execution file according to the plurality of test vector segments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test cases are executed, the plurality of test vector segments and auxiliary information corresponding to the execution files of the test cases are sequentially input to the test platform.

The number of the executed files can be different according to different requirements of users. FIG. 5 illustrates an example of obtaining an execution file according to an embodiment of the present disclosure.

For example, as shown in fig. 5, when the user needs to be a single-use case simulation, based on the test vector segment, a use case execution file for single-use case execution (single-random use case execution file) may be generated; when the user requirement is multi-case regression, a plurality of case execution files (random case R0 execution file-random case Rn execution file) and regression execution files for multi-case regression can be generated based on the test vector segments. Alternatively, as shown in fig. 2 and fig. 5, an "execution file generator" (software module) may be provided, the set of test vector fragments and the combination condition are used as the input of the "execution file generator", and the "execution file generator" executes step S15, and may generate a compilation/synthesis execution file, a use case execution file, and a regression execution file.

The combination condition may indicate a combination manner of the segments in the segment set of the test vector segments. Examples of combining conditions and generating at least one execution file from the plurality of test vector segments and the combining conditions may be found in the related description below.

Executing a test case corresponding to an execution file may be to run a corresponding command line in the execution file, so that a plurality of test vector segments corresponding to the execution file are sequentially input to the test platform, and a case execution log is generated by the test platform. Then aiming at the case execution file, the case execution log can also be a log corresponding to a single test case; for the regression execution file, the use case execution log may be a log corresponding to a plurality of test cases. The purpose of the various execution files can be seen in the description of the test methods section of chip testability design below.

By the method, the execution file can be automatically generated and can correspond to at least one test case, so that the test case corresponding to the execution file can be subjected to single-case simulation and multi-case regression during execution, and the convenience of executing the test case is improved.

In one possible implementation, the test vector segments of the single execution file are generated, including the test vector segments corresponding to the first original vector segment, the second original vector segment, and the third original vector segment, and the combination condition includes at least one of:

generating test vector segments of a single execution file to be combined according to a preset sequence;

generating a test vector segment of a single execution file corresponding to a preset subsystem;

and generating a test vector segment of the single execution file, wherein the total number of the test vector segments corresponding to the third original vector segment is greater than or equal to the second threshold value and less than or equal to the third threshold value.

For example, in the prior art, one test case generally covers all subsystems of the whole chip, and in this case, the result obtained by executing the test case each time is generally the same and lacks randomness. In this regard, in the embodiment of the present disclosure, it is proposed that a random combination condition is specified by a user, and based on all the test vector segments obtained in the above steps, the segments are combined to obtain an execution file of one or more random test cases (hereinafter also referred to as random cases), so that the test platform can execute the one or more random cases.

Any random case may be a complete case, that is, may be used to test the initialization function of the chip under test, the initialization function of one or more subsystems of the chip under test, and the functions of some or all modules included in the one or more subsystems, so, first, a test vector segment of a single execution file is generated, which may include test vector segments corresponding to the first original vector segment, the second original vector segment, and the third original vector segment. On this basis, the combination condition may include at least one of:

1. and defining a combination condition of the vector segment sequence when combining so that the test vector segments generating the single execution file are combined in a preset sequence. For example: the test vector segment corresponding to the first original vector segment is at the top, followed by the second original vector segment, and finally followed by the test vector segment corresponding to the third original vector segment.

2. The range of the set of segments to which the vector segments belong when combined is defined such that the test vector segments that generate a single execution file correspond to preset subsystems, for example: if the user wants to test the function of the subsystem D of the chip under test, it can be defined that the second original vector segment in combination belongs to the segment set related to the initialization function of the subsystem D, and the third original vector segment belongs to the segment set related to the module function in the subsystem D.

3. The number of test vector segments in combination is limited, so that the total number of test vector segments corresponding to the third original vector segment in the test vector segments for generating a single execution file is greater than or equal to the second threshold and less than or equal to the third threshold, for example, the second threshold may be set to 1, and the third threshold may be set to 6, and then the total number of test vector segments corresponding to the third original vector segment may be limited to a random integer between [1:6 ].

As shown in fig. 6, the user requirement may be an execution file, such as a random case R0 execution file, to obtain the functions of 1~6 arbitrary modules for testing subsystem D. The combination conditions may be: generating a test vector segment of a single execution file, and combining the test vector segments according to a preset sequence, wherein the preset sequence is that the test vector segment corresponding to the first original vector segment is at the top, the second original vector segment is next, and the test vector segment corresponding to the third original vector segment is finally; generating a test vector segment of a single execution file corresponding to subsystem D; and generating a total number of test vector segments of the single execution file corresponding to the third origin vector segment that is greater than or equal to 1 and less than or equal to 6. According to the combination condition, the first test vector segment of the test vector segment sequence may be an index of a segment for testing the initialization function of the chip, and the second test vector segment may be an index of a segment for testing the initialization function of the subsystem D, and then sequentially indexes of 1~6 test vector segments, for example, indexes of test vector segments R00-R0n, related to the functions of 1~6 random modules in the subsystem D. When the random case R0 is executed according to the generated execution file, the test of the initialization function of the tested chip is completed firstly, then the test of the initialization function of the subsystem D is completed, and finally the test of the functions of 1~6 modules in the subsystem D corresponding to the test vector segment is completed in sequence.

Alternatively, in the execution file, only the index of the test vector segment may be recorded, and specific information of the test vector segment does not need to be recorded.

It should be understood by those skilled in the art that the combination conditions supportable by the embodiments of the present disclosure should not be limited to the above examples, as long as the test vector segments can be combined with a certain randomness, for example, a user can also be supported to specify a case random seed, that is, the random results are consistent for the same seed in the same verification environment; supporting the regression times of the specified use cases; the method supports the specification of multiple sets of random constraints, the specification of the regression times of the use cases under each set of constraints, and the like, and the method is not limited by the disclosure.

According to the test requirements of users, for single case simulation, an "execution file generator" can obtain a case execution file corresponding to a random case, and for multi-use case regression, an "execution file generator" can obtain a plurality of case execution files corresponding to a plurality of random cases (R0-Rn) and regression execution files. Further, the "test vector parsing engine" may automatically execute a single random use case or multiple random use cases. Optionally, the embodiment of the present disclosure also supports a user to manually execute a single random use case or multiple random use cases. The following describes a method for implementing random case execution in the embodiments of the present disclosure, that is, a test method for chip testability design in the embodiments of the present disclosure.

7-9 illustrate method flow diagrams of a method of testing a design for chip testability according to an embodiment of the present disclosure. As shown in fig. 7, the method is applied to a test platform, and the method includes:

step S21, receiving a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, wherein the test vector segments are segments which can be identified by a test platform, different test vector segments are used for realizing or testing independent chip functions of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip;

step S22, testing the tested chip, comprising: based on the auxiliary information, controlling the excitation signal corresponding to the test vector segment to be output to the tested chip; acquiring an actual vector value of the code output of the tested chip; and determining a test result according to a comparison result of the expected vector value and the actual vector value included by the test vector segments, wherein the test results corresponding to the test vector segments indicate whether the chip functions of the tested chip corresponding to the test vector segments are normal, and the test results are displayed through a case execution log.

For example, the size of the whole chip is usually very large, and the code of the chip is generally compiled/synthesized and then tested. As shown in fig. 8, based on the test platform, a "compile/synthesize file" can be generated by using the prior art, and a series of command operations are packaged into a compact command, which is convenient for the user to operate. In this case, when executing the test case, the user only needs to input the file of the test platform and the code of the chip to be tested. The user modifies a small amount of necessary information (such as a test data storage path, which test case or test cases are executed, and the like), the execution of the test cases can be completed by running the command, and the executed results (i.e. test results, case logs, and the like) can be stored in a database (database).

According to the combination condition given by the user, the test case to be executed (i.e. the random case, which may be a single random case or a multi-use case as described above) can be determined, and the test case is executed. As shown in fig. 9, the test platform may include the following modules: memory space, excitation driver, control logic, vector value comparator. When executing the test cases, under the control of a processor (not shown), the test vector segments and auxiliary information corresponding to the execution files of the test cases (a single test case corresponds to the case execution file described above, and a plurality of test cases may correspond to the case execution file and the regression execution file described above) stored in the test vector segment set may be sequentially loaded into the storage space of the test platform; the method comprises the steps of receiving a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, wherein the counting of a counter is increased by 1 when one test vector segment is received, and when the counting of the counter reaches the total number of the test vector segments corresponding to the execution file, the fact that the receiving of the plurality of test vector segments is completed is determined, a new test vector segment is not received any more, and otherwise, the next test vector segment is continuously received. For example, the test vector segment and the obtaining manner may refer to the relevant descriptions in tables 2 to 5 above, for example, the obtaining manner of the auxiliary information may refer to step S12 above, and for example, the obtaining manner of the test vector segment may refer to step S14 above.

In step S22, when testing the chip under test, the test of the test vector segment can be completed each time one test vector segment and the auxiliary information are received. Based on the auxiliary information, controlling an excitation signal corresponding to the test vector segment to be output to a code of the chip to be tested, obtaining an actual vector value output by the code of the chip to be tested, and determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment, wherein the test result can be obtained by a test platform reading data in a storage space first and distinguishing the test vector segment and the auxiliary information, the auxiliary information includes guidance information for controlling the test platform to test the chip to be tested, when the case is executed, the auxiliary information is loaded into a 'control logic' according to a flow indicated by an execution file, and the 'control logic' can control the execution of the step S22 to complete the following functions: and controlling the sending time sequence of the excitation signal, the comparison of vector values, the storage of comparison results and the like based on the auxiliary information. All test platform behavior control related processing can be generalized to this module. For example, the "control logic" may drive the "excitation driver" to output an excitation signal to a code of the chip according to the auxiliary information, and control the "vector value comparator" to obtain an expected vector value included in the test vector segment from the "storage space", and control the "vector value comparator" to obtain an actual vector value from the code of the chip according to the expected vector value, and control the "vector value comparator" to compare the expected vector value included in the test vector segment with the actual vector value, so as to obtain a comparison result corresponding to the test vector segment. The specific implementation manner thereof can be seen in the further description of step S22 below. After the test platform finishes the comparison between the expected vector value and the actual vector value included in the current test vector segment, the current test vector segment can be considered to have finished the test, the next test vector segment can be continuously received, and the chip is continuously tested by using the next test vector segment until the last test vector segment corresponding to the execution file finishes the test. When the test of all the test vector segments is determined to be completed, the test result can be determined according to the comparison result of the expected vector values and the actual vector values included in the plurality of test vector segments, and the test result can be displayed through the case execution log.

The current test vector segment can be cleared after completing the test and the next test vector segment is received to continue the test, so that the memory space only needs to store one test vector segment.

As shown in fig. 8, assuming that each second test vector corresponds to a test case, for example, the second test with the number A0 corresponds to the test case with the number A0, for the test case of single-case simulation (for example, the test case with the number A0/the number An/the number Cn), a case execution log (for example, the case execution log with the number A0/the number An/the number Cn) may be obtained, and then, the log may be further analyzed by the execution case call log analysis function to determine whether the current test case passes or fails.

For a plurality of test cases (for example, test cases with the numbers A0, an, cn) of the multi-use case regression, a plurality of case execution logs (for example, case execution logs with the numbers A0, an, cn) corresponding to a plurality of test cases can be obtained for each case execution file corresponding to the test case or regression execution files corresponding to all cases, and then the regression analysis report of the chip testability test can be obtained by analyzing the plurality of case execution logs in a unified manner.

Where A0, an, cn represent numbers and do not represent test cases themselves.

According to the test method for chip testability design, the test platform can acquire necessary information for chip testability design test by receiving a plurality of test vector segments and auxiliary information corresponding to the execution file of the test case, wherein the test vector segments are segments which can be identified by the test platform, and the auxiliary information comprises guide information for controlling the test platform to test the chip to be tested; controlling an excitation signal corresponding to the test vector segment to be output to a code of the tested chip based on the auxiliary information, obtaining an actual vector value output by the code of the tested chip, and determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment, so that tests corresponding to a plurality of test vector segments can be completed; different test vector segments are used for realizing or testing the independent chip functions of the tested chip, so that the functions of the tested chip which can be tested by the test vector segments corresponding to the execution files can be random, and the test has randomness. Based on the test platform of the embodiment of the disclosure, the test method of the chip testability design of the embodiment of the disclosure provides a set of comprehensive test architecture, and can realize accurate positioning to the test vector segment where the test exception is located and the corresponding test cycle number. The test results corresponding to the test vector segments indicate whether the chip functions corresponding to the test vector segments are normal or not, the test results can be displayed through the case execution logs, and the automation of the test process of the chip testable design is realized. In the testing process, any non-universal self-research device, equipment and chip peripheral circuit are not needed, so that the unpredictable problem caused by other hardware is avoided, and the testing method for the chip testability design in the embodiment of the disclosure is more accurate in testing result. The length of the test vector segment can be far smaller than that of the complete test vector, so that the size of the storage space of the test platform can be set to be smaller, and the data storage pressure of the test platform is reduced.

In a possible implementation manner, in step S22, the code for controlling the excitation signal corresponding to the test vector segment to be output to the chip under test based on the auxiliary information includes:

and at the time point indicated by the test period driving parameters in the auxiliary information, outputting an excitation signal to an input interface of the code of the tested chip, and outputting an actual vector value by an output interface of the code of the tested chip.

For example, as described above, the auxiliary information may comprise test period driving parameters for indicating at which points in time the output stimulus signal starts a test period, etc. In this regard, as shown in fig. 8, each test case may have a corresponding stimulus signal (i.e., a case Waveform with the number A0/the number An/the number Cn in fig. 8, etc.), the "control logic" may control the "stimulus driver" to output the stimulus signal to the input interface of the code of the chip under test at a correct time point to complete driving based on the test period driving parameters in the auxiliary information, and the Waveform of the stimulus signal may be set based on a plurality of Waveform templates (Waveform tables), which is not limited by the present disclosure. And simulating the signal processing process of the actual chip by the code of the tested chip according to the excitation signal to obtain the actual vector value of each pin of the tested chip, wherein if no error occurs in the testability design of the chip, the actual vector value of each pin and the expected vector value (embodied in the test vector segment) of the pin can be the same. The actual vector values may be output by an output interface of the code of the chip under test.

In this way, the excitation driving of the tested chip can be completed. The excitation signal used for driving supports various waveforms, and the flexibility of an excitation driving mode can be improved.

In one possible implementation manner, in step S22, determining a test result according to a comparison result between an expected vector value and an actual vector value included in the test vector segment includes:

when the expected vector values included in the test vector segments indicate comparison, comparing whether the expected vector values in the test vector segments are matched with the actual vector values output by the chip pins at the time points indicated by the comparison parameters of the test period;

when the comparison result is that the actual vector value and the expected vector value at the time point are not matched, recording error information, wherein the error information comprises a test period corresponding to the time point, the actual vector value and the expected vector value at the time point;

and determining a test result corresponding to the current test vector segment according to the error information.

For example, as shown in fig. 9, the "control logic" may control the "vector value comparator" to read an expected vector value from the "memory space", which may determine whether the vector values of the pins in the test cycle need to be compared. For example, if the expected vector value is "2'b01" or "3' b101", indicating that the comparison is performed, it is expected that the interface pin of the chip code in the test period outputs 1, if the interface pin of the chip code actually outputs 1, matching is performed, otherwise, the comparison fails; similarly, if the expected vector value is '2' b00 'or' 3 'b100', indicating that comparison is performed, and expecting that the interface pin of the chip code in the test period outputs 0, if the interface pin of the chip code actually outputs 0, matching is performed, otherwise, comparison fails; similarly, an expected vector value of "2'b11" or "3' b111" indicates no comparison, and no care is taken about the actual output vector value of the interface pins of the chip code within this test period. And the test period comparison parameter in the auxiliary information is used for indicating a time point of the pin output actual vector value for acquiring the tested chip code in the test period. When the expected vector value of the pin in the test period indicates the comparison, the actual vector value output at the time point indicated by the comparison parameter of the test period can be obtained through the output interface of the code of the tested chip, and whether the actual vector value and the expected vector value at the time point are matched or not is compared. If the comparison result is that the actual vector value and the expected vector value at the time point do not match, the comparison may be considered as failed, and error information may be recorded, where the error information may include the test period corresponding to the time point, the actual vector value and the expected vector value at the time point, and the like. The storage depth of the error information may be specified by a user.

When the test platform is completely realized by the very integrated hardware description language verilog, the storage space can support the storage of the earliest error information and the refreshing of the latest error information. For example, in the internal circuit emulation ICE mode described above, the "control logic" may trigger a test pause when error information is generated, and notify the user to perform debugging work of the vector. The error information can be printed into a use case execution log according to the requirements of the user or stored by using a storage space, so that the user can analyze the test condition.

When the test platform is realized by the very comprehensive hardware description language verilog and comprises the non-comprehensive sentences, the non-comprehensive sentences can be used for directly displaying the error information through the printing grammar corresponding to the non-comprehensive sentences when the error information is generated, so that the debugging of a user is more convenient. For example, a hardware accelerator EMU platform using cadence, in the ICE mode described above, the test platform uses an "$ display" statement to enable an Acceleration (ATB) characteristic of the test platform, and performs simulation test in a Logic Analyzer (LA) mode; or a direct acceleration COMpiler (IXCOM) may be used directly.

In this way, the test method of the chip testability design supports the comparison of chip pin output and expectation; when the comparison is wrong, the error information can be recorded and printed, and the positioning is efficient.

Examples of software emulation platforms and hardware emulation platforms have been described above and are not described in detail herein.

The embodiment of the disclosure further provides a test platform, and fig. 10 shows a structure diagram of the test platform according to the embodiment of the disclosure.

As shown in fig. 10, the test platform includes:

a receiving module 101, configured to receive multiple test vector segments and auxiliary information corresponding to an execution file of a test case, where the test vector segments are segments that can be recognized by the test platform, different test vector segments are used to implement or test an independent chip function of a chip to be tested, and the auxiliary information includes guidance information for controlling the test platform to test the chip to be tested;

the test module 102 is configured to test the chip under test, and includes: code for controlling an excitation signal corresponding to the test vector segment to be output to the chip under test based on the auxiliary information; acquiring an actual vector value output by the code of the chip to be tested; determining a test result according to a comparison result of an expected vector value and the actual vector value which are included in the test vector segment; and the test results corresponding to the test vector segments indicate whether the chip functions corresponding to the test vector segments are normal or not, and the test results are displayed through the case execution log.

The function of the receiving module can be implemented by the storage space shown in fig. 9 and above, and the function of the testing module can be implemented by the excitation driver, the control logic, and the vector value comparator shown in fig. 9 and above.

The embodiment of the present disclosure further provides a device for generating a test platform, and fig. 11 shows a structure diagram of the device for generating a test platform according to the embodiment of the present disclosure.

As shown in fig. 11, the generation apparatus of the test platform includes: a first analysis module 111, configured to analyze a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, where the plurality of original vector segments are obtained by splitting a plurality of second test vectors, different original vector segments are used to implement or test an independent chip function of a chip under test, and the second test vector is an original test vector; the second analysis module 112 is configured to analyze the test vector analysis data corresponding to each original vector segment, and identify to obtain common information of the plurality of second test vectors; a first generating module 113, configured to generate a testing platform according to the common information, where a size of a storage space of the testing platform is related to the original vector segment with the largest length.

The functions of the first analysis module and the second analysis module may be implemented by the test vector parser described above and shown in fig. 2, and the functions of the first generation module may be implemented by the test platform generator described above and shown in fig. 2.

The function of the second generation module may be implemented by the test vector segment generator described above and shown in fig. 2.

In one possible implementation, the apparatus further includes: and the third generation module is used for generating at least one execution file according to the plurality of test vector segments and the combination condition, wherein each execution file corresponds to at least one test case, and the plurality of test vector segments and the auxiliary information corresponding to the execution file of the test case are sequentially input to the test platform during the test case execution.

The function of the third generation module can be implemented by the execution file generator described above and shown in fig. 2.

In some embodiments, functions of or modules included in the apparatus provided in the embodiments of the present disclosure may be used to execute the method described in the above method embodiments, and for specific implementation, reference may be made to the description of the above method embodiments, and for brevity, details are not described here again.

The embodiment of the present disclosure further provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the test method for chip testability design described above is implemented, or the generation method for the test platform described above is implemented. The computer readable storage medium may be a volatile or non-volatile computer readable storage medium.

The embodiment of the present disclosure further provides a test platform, which includes: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above-described chip design-for-test testing methodology when executing the instructions stored by the memory.

The embodiment of the present disclosure further provides a device for generating a test platform, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the generation method of the test platform when executing the instructions stored in the memory.

The disclosed embodiments also provide a computer program product comprising computer readable code or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, the processor in the electronic device performs the above method.

Fig. 12 shows a block diagram of an apparatus 1900 according to an embodiment of the disclosure. The apparatus 1900 may be the test platform or a generation apparatus of the test platform, and the apparatus 1900 may be provided as a server or a terminal device. Referring to fig. 12, the device 1900 includes a processing component 1922 further including one or more processors and memory resources, represented by memory 1932, for storing instructions, e.g., applications, executable by the processing component 1922. The application programs stored in memory 1932 may include one or more modules that each correspond to a set of instructions. Further, the processing component 1922 is configured to execute instructions to perform the above-described method for testing design-for-testability of a chip or method for generating a test platform.

The device 1900 may also include a power component 1926 configured to perform power management of the device 1900, a wired or wireless network interface 1950 configured to connect the device 1900 to a network, and an input/output interface 1958 (I/O interface). The device 1900 may operate based on an operating system, such as Windows Server, stored in memory 1932 ^TM ，Mac OS X ^TM ，Unix ^TM , Linux ^TM ，FreeBSD ^TM Or the like.

In an exemplary embodiment, a non-transitory computer readable storage medium, such as a memory 1932, is also provided that includes computer program instructions executable by the processing component 1922 of the apparatus 1900 to perform the above-described method for testing a design of chip testability or method for generating a test platform.

The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for testing chip design for testability, the method is applied to a test platform, and the method comprises the following steps:

receiving a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, wherein the test vector segments are segments which can be identified by the test platform, different test vector segments are used for realizing or testing independent chip functions of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip;

testing the chip under test, comprising: based on the auxiliary information, controlling the excitation signal corresponding to the test vector segment to be output to the tested chip; acquiring an actual vector value of the code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the test vector segments indicate whether the chip functions corresponding to the test vector segments are normal or not, and the test results are displayed through the case execution log.

2. The method of claim 1, wherein the code that controls the excitation signals corresponding to the test vector segments to be output to the chip under test based on the auxiliary information comprises:

and at the time point indicated by the test cycle driving parameters in the auxiliary information, outputting the excitation signal to an input interface of the code of the chip to be tested, and outputting the actual vector value by an output interface of the code of the chip to be tested.

3. The method of claim 2, wherein determining a test result according to the comparison of the expected vector value and the actual vector value included in the test vector segment comprises:

when the expected vector values included in the test vector segments indicate comparison, comparing whether the expected vector values in the test vector segments are matched with the actual vector values output by the chip pins at the time points indicated by the test period comparison parameters;

and determining a test result according to the error information.

4. A method according to any of claims 1-3, characterized in that the test platform is adapted to a software simulation platform and a hardware simulation platform.

5. A method for generating a test platform, the method comprising:

analyzing a plurality of original vector segments to obtain test vector analysis data corresponding to each original vector segment, wherein the plurality of original vector segments are obtained by splitting a plurality of second test vectors, different original vector segments are used for realizing or testing independent chip functions of a chip to be tested, and the second test vectors are original test vectors;

analyzing test vector analysis data corresponding to each original vector segment, and identifying to obtain public information of the plurality of second test vectors;

and generating a test platform according to the public information, wherein the size of the storage space of the test platform is related to the original vector segment with the largest length.

6. The method of claim 5, wherein the common information comprises one or more of chip pin parameters, time parameters, and test cycle time definitions of the chip under test.

7. The method of claim 6, further comprising:

and generating test vector segments corresponding to the original vector segments according to the test vector analysis data corresponding to each original vector segment, wherein the test vector segments are segments which can be identified by the test platform and are used when the test platform tests the independent chip function of the chip to be tested.

8. The method of claim 7, wherein the chip under test comprises at least one subsystem, each subsystem comprises at least one module, and the splitting condition of the plurality of second test vectors comprises:

aiming at the part, related to the initialization function of the tested chip, of the second test vectors, obtaining a first original vector segment, wherein the first original vector segment corresponds to each subsystem and each module;

obtaining at least one second original vector segment aiming at the part of the plurality of second test vectors, wherein the part of the plurality of second test vectors is related to the initialization function of at least one subsystem of the tested chip, and each second original vector segment corresponds to one subsystem;

9. The method of claim 8, further comprising:

and generating at least one execution file according to the plurality of test vector segments and the combination condition, wherein each execution file corresponds to at least one test case, and when the test cases are executed, the plurality of test vector segments and auxiliary information corresponding to the execution files of the test cases are sequentially input to the test platform.

10. The method of claim 9, wherein generating test vector segments for a single execution file comprises generating test vector segments corresponding to a first original vector segment, a second original vector segment, and a third original vector segment, wherein the combining condition comprises at least one of:

11. The method according to claim 9 or 10, wherein the auxiliary information includes guide information for controlling the test platform to test the chip under test and difference information of each second test vector.

12. The method of claim 11, wherein the test vector segment comprises expected vector and stimulus vector values for unidirectional pins and expected/stimulus vector values for bidirectional pins of the chip under test in each test cycle under the test vector segment.

13. The method of claim 12, wherein the plurality of second test vectors comprise test vectors written in different languages, including at least one of Standard Test Interface Language (STIL), waveform Generation Language (WGL), and Test Description Language (TDL).

14. The method of claim 13, wherein the test platform is adapted to a software simulation platform and a hardware simulation platform.

15. A test platform, comprising:

the device comprises a first receiving module, a second receiving module and a third receiving module, wherein the first receiving module is used for receiving a plurality of test vector segments and auxiliary information corresponding to an execution file of a test case, the test vector segments are segments which can be identified by the test platform, different test vector segments are used for realizing or testing independent chip functions of a tested chip, and the auxiliary information comprises guide information for controlling the test platform to test the tested chip;

the test module is used for testing the tested chip and comprises: code for controlling an excitation signal corresponding to the test vector segment to be output to the chip under test based on the auxiliary information; acquiring an actual vector value of the code output of the tested chip; determining a test result according to a comparison result of an expected vector value and the actual vector value included in the test vector segment; and the test results corresponding to the test vector segments indicate whether the chip functions corresponding to the test vector segments are normal or not, and the test results are displayed through the case execution log.

16. An apparatus for generating a test platform, comprising:

the device comprises a first analysis module, a second analysis module and a third analysis module, wherein the first analysis module is used for analyzing a plurality of original vector fragments to obtain test vector analysis data corresponding to each original vector fragment, the plurality of original vector fragments are obtained by splitting a plurality of second test vectors, different original vector fragments are used for realizing or testing independent chip functions of a chip to be tested, and the second test vectors are original test vectors;

the second analysis module is used for analyzing the test vector analysis data corresponding to each original vector segment and identifying to obtain the public information of the plurality of second test vectors;

and the first generation module is used for generating a test platform according to the public information, and the size of the storage space of the test platform is related to the original vector segment with the largest length.

17. A test platform, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 1 to 4 when executing the memory-stored instructions.

18. An apparatus for generating a test platform, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to implement the method of any one of claims 5 to 14 when executing the memory-stored instructions.

19. A non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the method of any one of claims 1 to 4 or implement the method of any one of claims 5 to 14.