CN113378502B - Test method, device, medium and equipment for verifying signal trend code matching - Google Patents
Test method, device, medium and equipment for verifying signal trend code matching Download PDFInfo
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- CN113378502B CN113378502B CN202110916195.4A CN202110916195A CN113378502B CN 113378502 B CN113378502 B CN 113378502B CN 202110916195 A CN202110916195 A CN 202110916195A CN 113378502 B CN113378502 B CN 113378502B
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- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
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Abstract
The invention provides a test method, a device, a medium and equipment for verifying signal trend code matching, which are used for obtaining wiring node information of all signals by analyzing a signal wiring trend file to be verified; generating a code matching command file and a code matching command list according to the wiring node information; setting the path address of the command file and the path address of the log file generated by executing the command file in a code matching execution file called when code matching is executed; and executing the code matching execution file, finding an actual code matching value according to the log file, comparing the actual code matching value with the code matching expected value in the command list, if the actual code matching value is consistent with the command list, matching the code correctly, if the actual code matching value is inconsistent with the command list, matching the code unsuccessfully, and writing the inconsistent circuit path address and the inconsistent code matching value into a result file and outputting the result file. By using the idea of software verification, batch automatic verification of the circuit is realized, verification time is greatly saved, test time and energy of testers are saved, and code matching verification speed and test coverage rate are improved.
Description
Technical Field
The invention belongs to the technical field of programmable logic devices, and particularly relates to a test method, a test device, a test medium and test equipment for verifying signal trend code matching.
Background
The main function of the FPGA (Field-Programmable Gate Array electronic Design Automation) tool is to convert a specific Circuit Design into a netlist file (the netlist file is a file describing a connection relationship of a Circuit, generally a text file, and simply translates a schematic diagram into the text file, and the file includes a label of a device, a package, and a connection relationship, and is introduced into a PCB (Printed Circuit Board) editor, and the editor takes out a corresponding package from a package library and gives the corresponding label and the connection relationship to the package library, and then performs subsequent processes of packaging, layout, wiring, code generation, and the like on the netlist file, where the process flow of the EDA tool on the Circuit is shown in fig. 1.
The wiring direction of each signal in each circuit needs to be matched with codes, code streams can be generated and corresponding work can be carried out after the code matching is successful, the wiring direction is invalid if the code matching fails, namely, the wiring direction does not play a corresponding role, but the wiring direction is configured at a position where each wiring direction needs to be configured, the number of values which need to be configured is large, testers need to compare the code matching configuration files one by one, and if the testers manually match the code for the wiring direction of each signal, a large amount of time and energy are consumed, and the comparison is likely to be wrong manually, even if simulation is carried out, whether each value is matched with codes correctly can be verified, but from the aspect of execution time, the time consumed by simulation is relatively large.
Disclosure of Invention
The invention aims to solve the technical problem of how to rapidly carry out code matching configuration on the signal wiring trend, and provides a test method, a device, a medium and equipment for verifying the code matching of the signal trend.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a test method for verifying signal trend code matching comprises the following steps:
step 1: analyzing a signal trend wiring file to be verified to obtain wiring node information of all signals;
step 2: generating a plurality of commands related to each signal according to the wiring node information of each signal, wherein the commands of all the signals form a code matching command file and a command list, the command list comprises each command in the command file and a code matching expected value when each command is executed, and the code matching expected value is a preset code matching value of each signal wiring node;
and step 3: setting the path address of the code matching command file and the path address of a log file generated when the code matching command file is executed in a code matching execution file called when the code matching is executed;
and 4, step 4: and executing the code matching execution file, finding the actual code matching value of each command in the log file generated during the execution of the code matching execution file according to the path address of the log file, comparing the actual code matching value with the expected code matching value in the code matching command list, if the actual code matching value is consistent with the expected code matching value in the code matching command list, matching the code correctly, and if the actual code matching value is inconsistent with the expected code matching value in the code matching command list, matching the code unsuccessfully, and writing the wrong circuit path address and code matching value into a result file and outputting the error circuit path address and code matching value.
Further, before step 1, the method further comprises:
step 1′: reading a CASE file storing the circuit path and the top entity name, and finding out a signal routing wiring file path address and a code matching file path address corresponding to the circuit path and the top entity according to the circuit path and the top entity name in the CASE file;
step 2′: judging whether a signal routing wiring file exists in a signal routing wiring file path address or not, judging whether a code matching file exists in a code matching file address or not, if both exist, executing the step 1, otherwise, returning to the step 1′And reading the information of the next circuit to be tested from the CASE file.
Further, the code allocation value of each signal wiring node preset In step 2 is to obtain, by analyzing the code allocation configuration file, a code allocation configuration dictionary corresponding to the code allocation configuration file, configure the code allocation configuration dictionary with a Module Name of KEY, including an Instance Name of each Module Name, an output Port Out Port and an input Port In Port, each In Port being a configuration item, the value of the In Port being a code allocation value, and the code allocation value of each Module node being a code allocation expected value of the wiring node corresponding to each Module node.
Further, when the commands of all the signals form a code matching command file in step 2, when the number of the commands exceeds 5 ten thousand, a plurality of command files are generated according to the principle that each code matching command file has at most 5 ten thousand, and the path addresses of the plurality of code matching command files are written into the code matching execution file.
Further, when a plurality of commands related to each signal are generated according to the wiring node information of the signal in step 2, when the information of the wiring node cannot find the corresponding module node in the code matching configuration dictionary, the information of the wiring node is recorded in a result file for a tester to check whether the wiring node is a BUG.
The invention also provides a testing device for verifying the signal trend matching code, which comprises the following modules: a signal wiring node information acquisition module: the system comprises a signal wiring trend file, a signal processing unit and a signal processing unit, wherein the signal wiring trend file is used for analyzing a signal wiring trend file to be verified to obtain wiring node information of all signals;
a command file generation module: the device comprises a wiring circuit, a code matching command file, a code matching command list, a code matching expected value and a code matching command processing unit, wherein the wiring circuit is used for generating a plurality of commands related to each signal according to the trend of the signal, the commands of all the signals form the code matching command file and the code matching command list, the code matching command list comprises each command in the code matching command file and the code matching expected value when each command is executed, and the code matching expected value is a preset code matching value of a wiring node of each signal;
the execution file updating module: the path address of the code matching command file and the path address of the log file generated by executing the code matching command file are arranged in a code matching execution file called when code matching is executed;
a verification module: the method is used for searching the actual code matching value of each command in the log file generated during the execution of the code matching execution file according to the path address of the log file when the code matching execution file is executed, comparing the actual code matching value with the expected code matching value in the code matching command list, if the actual code matching value is consistent with the expected code matching value in the code matching command list, matching the code correctly, and if the actual code matching value is inconsistent with the expected code matching value in the code matching command list, matching the code unsuccessfully, and writing the wrong circuit path address and code matching value into a result file and outputting the error circuit path address and code matching value.
Further, the method also comprises the following modules:
signal trend wiring file acquisition module: the CASE file is used for reading the circuit path and the top entity name, and finding out a signal routing wiring file address and a code matching file address corresponding to the top entity and the circuit path address according to the circuit path and the top entity name in the CASE file;
whether a code matching file exists in a module: the device is used for judging whether a signal routing wiring file exists in a signal routing wiring file path address or not, judging whether a code matching file exists in a code matching file address or not, if so, executing a signal wiring node information acquisition module, and if not, returning to the signal routing wiring file acquisition module to read the information of the next circuit to be tested in the CASE file.
The invention also provides a computer readable medium storing a computer program executable by a processor to implement the method for testing verification signal trend matching code.
The invention also provides computer equipment which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the test method for verifying the signal trend matching code when executing the computer program.
By adopting the technical scheme, the invention has the following beneficial effects:
the invention provides a test method, a device, a medium and equipment for verifying signal trend code matching, which are characterized in that wiring node information of all signals is obtained by analyzing a signal wiring trend file, then a plurality of commands are generated according to the wiring trend of each signal, further the commands of all the signals form a command file, a command log file is generated when the command file is executed, an actual code matching value generated in the command execution process is compared with a code matching expected value set in a code matching configuration file, if the actual code matching value is consistent with the code matching expected value, the code matching is correct, and if the actual code matching value is inconsistent with the code matching expected value, the code matching fails. By using the idea of software verification, the invention realizes batch automatic verification of the circuit, greatly saves verification time, saves test time and energy of testers, and improves code matching verification speed and test coverage rate.
Drawings
FIG. 1 is a flow of EDA tool processing a circuit;
FIG. 2 is a system flow diagram of the present invention;
FIG. 3 is a flowchart of determining whether a signal routing file and a code matching file exist.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following provides a specific embodiment of a test method for verifying signal trend code matching, which comprises the following steps:
step 1′: read and store circuit path and top layerThe CASE file of the entity name finds out the signal trend routing file path address and the code matching file path address corresponding to the top entity and the circuit path address according to the circuit path and the top entity name in the CASE file;
step 2′: judging whether a signal routing wiring file exists in a signal routing wiring file path address or not, judging whether a code matching file exists in a code matching file address or not, if both exist, executing the step 1, otherwise, returning to the step 1′And reading the information of the next circuit to be tested from the CASE file.
The CASE file is used for storing a circuit path and a top entity name, reading the file, splicing a circuit wiring file address and a code matching file address of the circuit, judging whether the circuit performs wiring and code matching successfully, if the code matching file exists, indicating that the steps of integrating, boxing, layout, wiring and the like before code matching are successful, performing code matching verification operation, if the code matching file does not exist, indicating that the circuit does not generate a corresponding code matching file, not performing verification, reading a record in the next CASE file, and continuing to judge, specifically as shown in fig. 3.
Figure 2 shows the key steps of the test method:
step 1: analyzing a signal trend wiring file to be verified to obtain wiring node information of all signals;
analyzing a signal trend wiring file In each circuit to form a signal wiring path dictionary, acquiring the wiring trend of each signal, taking the signal Name as a KEY, and storing a path through which the signal passes, wherein the path comprises a passing Module node Module Name, an Instance Name, an input Port In Port and an output Port Out Port; when the signal does not need to be wired, the value corresponding to the signal name is null.
The signal routing path dictionary is exemplified as follows:
{Signal1:{Module_Name1:{Instance_Name1:{Out_Port1:{In_Port1:value1, In_Port2:value2......}}, {Instance_Name2:{Out_Port2:{In_Port1:value1, In_Port2:value2......}}}}}, Signal2:{Module_Name1:{Instance_Name1:{Out_Port1:{In_Port1:value1, In_Port2:value2......}}, {Instance_Name2:{Out_Port2:{In_Port1:value1, In_Port2:value2......}}}}}}。
step 2: and generating a plurality of commands related to each signal according to the wiring node information of each signal, wherein the commands of all the signals form a code matching command file and a code matching command list, the code matching command list comprises each command in the code matching command file and a code matching expected value when each command is executed, and the code matching expected value is a preset code matching value of each signal wiring node.
In this embodiment, a code allocation value of each signal wiring node that is preset In this embodiment is obtained by parsing a code allocation configuration XML (Extensible Markup Language) file, where a Module Name is used as a KEY of the code allocation configuration dictionary, the code allocation configuration dictionary includes an Instance Name under each Module Name, an output Port Out Port and an input Port In Port, each In Port is a configuration item, a value of the In Port is a code allocation value, and the code allocation value of each Module node is a code allocation expected value of a wiring node corresponding to each Module node.
In addition, because the configuration XML (Extensible Markup Language) file of the configuration code is fixed, the configuration code dictionary obtained by analyzing the configuration code file can be directly used when each circuit is verified later, and the time consumed by analysis is saved.
In this embodiment, according to each wiring node through which each signal passes, the Module Name, the Instance Name, the In Port and the Out Port corresponding to each wiring node are used to match the code configuration dictionary to find the corresponding value of the Instance Name and the In Port layer by layer, generate a corresponding command, and store the command In a command file and a command list corresponding to the command file; and when the wiring node cannot find the corresponding module node in the code matching configuration dictionary, recording the information of the wiring node into a result file so as to enable a tester to check whether the wiring node is a BUG.
And step 3: and setting the path address of the code matching command file and the path address of the log file generated by executing the code matching command file in a code matching execution file called when the code matching is executed.
In this embodiment, the generated code matching command file is often very large, tens of thousands of lines or even hundreds of thousands of lines, and at this time, the result recorded in the generated log file may be incomplete after executing the command file, so that 5 ten thousand are set as a limit on this side, and when the number of commands does not exceed 5 ten thousand, the command file is placed in the same command file, and when the number of commands exceeds 5 ten thousand, a plurality of command files are generated according to the principle that at most 5 ten thousand of command files are allocated, and the addresses of the plurality of code matching command files are written into the code matching execution file.
And 4, step 4: and executing the code matching execution file, finding the actual code matching value of each command in the log file generated during the execution of the code matching execution file according to the path address of the log file, comparing the actual code matching value with the expected code matching value in the code matching command list, if the actual code matching value is consistent with the expected code matching value in the code matching command list, matching the code correctly, and if the actual code matching value is inconsistent with the expected code matching value in the code matching command list, matching the code unsuccessfully, and writing the wrong circuit path address and code matching value into a result file and outputting the error circuit path address and code matching value.
The invention also provides a testing device for verifying the signal trend matching code, which comprises the following modules:
signal trend wiring file acquisition module: the device comprises a CASE file, a log file and a code matching file, wherein the CASE file is used for reading a CASE file for storing a circuit path and a top entity name, and finding a signal trend wiring file address and a code matching file address corresponding to a top entity and a circuit path address in the log file according to the circuit path and the top entity name in the CASE file;
whether a code matching file exists in a module: and the signal wiring node information acquisition module is used for judging whether the code matching file exists in the code matching file address, if so, executing the signal wiring node information acquisition module, and otherwise, returning a signal to the wiring file acquisition module to read the information of the next circuit to be tested.
A signal wiring node information acquisition module: the system comprises a signal wiring trend file, a signal processing unit and a signal processing unit, wherein the signal wiring trend file is used for analyzing a signal wiring trend file to be verified to obtain wiring node information of all signals;
a command file generation module: the device comprises a wiring circuit, a code matching command file, a code matching command list, a code matching expected value and a code matching command processing unit, wherein the wiring circuit is used for generating a plurality of commands related to each signal according to the trend of the signal, the commands of all the signals form the code matching command file and the code matching command list, the code matching command list comprises each command in the code matching command file and the code matching expected value when each command is executed, and the code matching expected value is a preset code matching value of a wiring node of each signal;
the execution file updating module: the path address used for setting the code matching command file path address and the path address used for executing the code matching command file to generate the log file in the code matching execution file called when the code matching is executed;
a verification module: the system is used for executing the code matching execution file, finding the actual code matching value of each command in the log file generated during the execution of the execution file according to the path address of the log file, comparing the actual code matching value with the expected code matching value in the command list, if the actual code matching value is consistent with the expected code matching value in the command list, matching the code correctly, and if the actual code matching value is inconsistent with the expected code matching value in the command list, matching the code unsuccessfully, and writing the wrong circuit path address and code matching value into a result file and outputting the written result.
The invention also provides a computer readable medium storing a computer program executable by a processor to implement the method for testing verification signal trend matching code.
It will be understood by those skilled in the art that all or part of the steps in the method of the above embodiments may be implemented by hardware instructions related to a program, the program may be stored in a computer-readable storage medium, and when executed, the program includes the steps of the method of the above embodiments, and the storage medium may be: ROM/RAM, magnetic disks, optical disks, memory cards, and the like.
The invention also provides computer equipment which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the test method for verifying the signal trend matching code when executing the computer program.
The invention can effectively improve the testing efficiency of FPGA software, is more convenient for testers, reduces the complex processes of searching different configuration data in various files, executing code matching and finally comparing, has strong portability, is also suitable for testing different devices, and can directly call and execute other bottom layer scripts or interface automation scripts.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A test method for verifying signal trend code matching is characterized by comprising the following steps:
step 1: analyzing a signal trend wiring file to be verified to obtain wiring node information of all signals;
step 2: generating a plurality of commands related to each signal according to the wiring node information of each signal, wherein the commands of all the signals form a code matching command file and a code matching command list, the code matching command list comprises each command in the code matching command file and a code matching expected value when each command is executed, and the code matching expected value is a preset code matching value of each signal wiring node;
and step 3: setting the path address of the code matching command file and the path address of a log file generated by executing the code matching command file in a code matching execution file called when code matching is executed;
and 4, step 4: and executing the code matching execution file, finding the actual code matching value of each command in the log file generated during the execution of the code matching execution file according to the path address of the log file, comparing the actual code matching value with the expected code matching value in the code matching command list, if the actual code matching value is consistent with the expected code matching value in the code matching command list, matching the code correctly, and if the actual code matching value is inconsistent with the expected code matching value in the code matching command list, matching the code unsuccessfully, and writing the inconsistent circuit path address and code matching value into a result file and outputting the written result file.
2. The testing method of claim 1, further comprising, prior to step 1:
step 1′: reading a CASE file storing the circuit path and the top entity name, and finding out a signal routing wiring file path address and a code matching file path address corresponding to the circuit path and the top entity according to the circuit path and the top entity name in the CASE file;
step 2′: judging whether a signal routing wiring file exists in a signal routing wiring file path address or not, judging whether a code matching file exists in a code matching file address or not, if both exist, executing the step 1, otherwise, returning to the step 1′And reading the information of the next circuit to be tested from the CASE file.
3. The test method according to claim 2, wherein the code allocation value of each signal wiring node preset in step 2 is a code allocation configuration dictionary corresponding to the code allocation configuration file obtained by analyzing the code allocation configuration file, the code allocation configuration dictionary uses a module name as a keyword and includes an instance name under each module name, an output port and an input port, each input port is a configuration item, the value of the input port is a code allocation value, and the code allocation value of each module node is a code allocation expected value of the wiring node corresponding to each module node.
4. The test method according to claim 3, wherein in step 2, when the commands of all the signals form a code matching command file, when the number of the commands exceeds 5 ten thousand, a plurality of code matching command files are generated according to the principle that at most 5 ten thousand of the code matching command files are generated, and path addresses of the plurality of code matching command files are written into the code matching execution file.
5. The test method according to claim 3, wherein when the plurality of commands related to each signal are generated according to the wiring node information of the signal in step 2, when a wiring node cannot find a corresponding module node in the code matching configuration dictionary, the information of the wiring node is recorded in a result file for a tester to check whether the wiring node is a bug.
6. A test device for verifying signal trend code matching is characterized by comprising the following modules:
a signal wiring node information acquisition module: the system comprises a wiring file, a signal verification module and a signal verification module, wherein the wiring file is used for analyzing the trend of a signal to be verified to obtain wiring node information of all signals;
a command file generation module: the device comprises a code matching command file and a code matching command list, wherein the code matching command list comprises each command in the code matching command file and a code matching expected value when each command is executed, and the code matching expected value is a preset code matching value of a wiring node of each signal;
the execution file updating module: the path address of the code matching command file and the path address of the log file generated by executing the code matching command file are arranged in a code matching execution file called when code matching is executed;
a verification module: the method is used for searching the actual code matching value of each command in the log file generated during the execution of the code matching execution file according to the path address of the log file when the code matching execution file is executed, comparing the actual code matching value with the expected code matching value in the code matching command list, if the actual code matching value is consistent with the expected code matching value in the code matching command list, matching the code correctly, and if the actual code matching value is inconsistent with the expected code matching value in the code matching command list, matching the code unsuccessfully, and writing the wrong circuit path address and code matching value into a result file and outputting the error circuit path address and code matching value.
7. The testing device of claim 6, further comprising the following modules:
signal trend wiring file acquisition module: the CASE file is used for reading the circuit path and the top entity name, and finding out a signal routing wiring file address and a code matching file address corresponding to the top entity and the circuit path address according to the circuit path and the top entity name in the CASE file;
whether a code matching file exists in a module: the device is used for judging whether a signal routing wiring file exists in a signal routing wiring file path address or not, judging whether a code matching file exists in a code matching file address or not, if so, executing a signal wiring node information acquisition module, and if not, returning to the signal routing wiring file acquisition module to read the information of the next circuit to be tested in the CASE file.
8. A computer-readable medium storing a computer program, characterized in that the computer program is executable by a processor to implement the method of any one of claims 1 to 5.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the method of any one of claims 1 to 5 when executing the computer program.
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