CN112731117A - Automatic verification method and system for chip, and storage medium - Google Patents
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Abstract
The embodiment of the application discloses a method and a system for automatically verifying a chip and a storage medium, wherein the method comprises the following steps: reading test parameters and test scenes corresponding to a chip to be verified from a preset test case library, and generating a test case list according to the test parameters and the test scenes; generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to at least one test case; the second file list comprises at least one second file corresponding to at least one test case; obtaining at least one first test result corresponding to at least one first file based on the first preset test model and the first file list; meanwhile, at least one second test result corresponding to at least one second file is obtained based on a second preset test model and a second file list; and determining a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to an automatic chip verification method and system, and a storage medium.
Background
At present, in order to ensure the correctness of chip design and effectively improve the chip design quality, designers need to perform coverage test on a large number of cases for chip function design. The method mainly comprises the following steps: designing a test case, running a test program, comparing test results and the like.
However, as the integrated circuit rapidly develops and the chip scale increases, the verification work in the chip design becomes more difficult, which becomes the most expensive work in the process and occupies a larger and larger proportion of the whole design cycle. The traditional mode of manually executing the chip function verification based on manpower cannot meet the current large-scale chip verification requirement due to low verification speed, high time consumption and high verification error probability. Therefore, how to accurately and efficiently verify the chip functions becomes a technical problem to be solved urgently.
Disclosure of Invention
The embodiment of the application provides an automatic verification method and system of a chip and a storage medium, the verification speed of the chip is high, the accuracy is good, the chip verification efficiency is greatly improved, and the efficient verification of the chip is further realized.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides an automatic verification method for a chip, where the method includes:
reading test parameters and test scenes corresponding to the chip to be verified from a preset test case library, and generating a test case list according to the test parameters and the test scenes; the test case list comprises at least one test case;
generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to the at least one test case; the second file list comprises at least one second file corresponding to the at least one test case;
obtaining at least one first test result corresponding to the at least one first file based on a first preset test model and the first file list; meanwhile, obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list;
and determining a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
In a second aspect, an embodiment of the present application provides an automatic verification system, where the chip verification system includes a reading unit, a generating unit, an obtaining unit, and a determining unit,
the reading unit is used for reading the test parameters and the test scenes corresponding to the chip to be verified from a preset test case library;
the generating unit is used for generating a test case list according to the test parameters and the test scene; the test case list comprises at least one test case; generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to the at least one test case; the second file list comprises at least one second file corresponding to the at least one test case;
the obtaining unit is configured to obtain at least one first test result corresponding to the at least one first file based on a first preset test model and the first file list; meanwhile, obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list;
the determining unit is configured to determine a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
In a third aspect, an embodiment of the present application provides an automatic verification system, where the automatic verification system includes a processor and a memory storing instructions executable by the processor, and when the instructions are executed by the processor, the automatic verification method for a chip as described above is implemented.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, on which a program is stored, where the program, when executed by a processor, implements the automatic verification method for a chip as described above.
The embodiment of the application provides an automatic verification method and system of a chip and a storage medium, wherein the automatic verification system can read test parameters and test scenes corresponding to the chip to be verified from a preset test case library and generate a test case list according to the test parameters and the test scenes; the test case list comprises at least one test case; generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to at least one test case; the second file list comprises at least one second file corresponding to at least one test case; obtaining at least one first test result corresponding to at least one first file based on the first preset test model and the first file list; meanwhile, at least one second test result corresponding to at least one second file is obtained based on a second preset test model and a second file list; and determining a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
That is to say, in the embodiment of the present application, the automatic verification system may automatically analyze the test parameters and the test scenes corresponding to the chip to be verified in the preset test case library, and immediately automatically generate the test case list including the complete test cases; then, the automatic verification system can automatically convert each test case in the test case list into two executable files with different formats, such as a first file and a second file, according to different specific file formats, and respectively load and operate the two executable files through two different preset test models, so as to obtain two test results corresponding to each test case; furthermore, the chip verification system can automatically compare two test results corresponding to each test case, and automatically count all comparison results to determine the verification result of the chip to be verified. Therefore, the chip verification system realizes automation of generation of the test case, generation of the executable file, running of the test program and comparison of the test result, the verification speed of the chip is high, accuracy is good, chip verification efficiency and reliability of the verification result are greatly improved, and efficient verification of the chip is further realized.
Drawings
Fig. 1 is a first schematic flow chart illustrating an implementation of an automatic verification method for a chip according to an embodiment of the present application;
fig. 2 is a schematic diagram of an implementation flow of an automatic verification method for a chip according to an embodiment of the present application;
fig. 3 is a schematic flow chart illustrating an implementation of the automatic verification method for a chip according to the embodiment of the present application;
fig. 4 is a schematic flow chart illustrating an implementation of an automatic verification method for a chip according to an embodiment of the present application;
FIG. 5 is a block diagram of an automated verification system according to an embodiment of the present application;
fig. 6 is a first schematic structural diagram of the automatic verification system proposed in the present application;
fig. 7 is a schematic structural diagram of the automatic verification system according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are illustrative of the relevant application and are not limiting of the application. It should be noted that, for the convenience of description, only the parts related to the related applications are shown in the drawings.
Before further detailed description of the embodiments of the present invention, terms and expressions mentioned in the embodiments of the present invention are explained, and the terms and expressions mentioned in the embodiments of the present invention are applied to the following explanations.
1) Test Case (Test Case): refers to the description of testing tasks performed on a particular software product, embodying test schemes, methods, techniques and strategies. The contents of the test object, the test environment, the input data, the test steps, the expected results, the test scripts and the like are included, and finally, a document is formed. That is, a test case is a set of test inputs, execution conditions, and expected results tailored for a particular purpose to verify that a particular software requirement is met.
2) Design Under Verification (DUV) or (Design Under Test, DUT): in a modern Integrated Circuit (IC) design process, after a designer completes Register Transfer Level (RTL) codes according to a design specification, a verifier starts to verify the codes, which are generally called as a module to be tested, i.e., a DUT; that is, the design being verified may be a Register Transfer Level (RTL) design or may be a netlist.
3) High-performance application specific integrated circuit verification Systems (High-performance ASIC programming Systems): the HAPS family of products of synchronization is a high-performance, high-capacity, Field-Programmable Gate Array (FPGA) -based prototype verification board that is specifically provided for Application-specific integrated circuit (ASIC)/System On Chip (SOC) designers. The HAPS is a system composed of a motherboard and a daughter board, wherein one or more high-performance FPGA chips are configured on the motherboard, and different motherboards can be superposed to meet the verification requirement of a large-capacity ASIC/SOC. The daughter board may be selected from dozens of standard libraries provided by synchronization as needed, or may be customized by itself.
At present, in order to ensure the correctness of chip design and effectively improve the chip design quality, designers need to perform coverage test on a large number of cases for chip function design. The method mainly comprises the following steps: designing a test case, running a test program, comparing test results and the like.
Wherein, the work of verifying the above-mentioned chip is carried out by designer's manual work alone, specifically is:
(a) designing a test case aiming at each module function of the chip; wherein, coverage test may need to write hundreds or even thousands of cases;
(b) generating an algorithm model configuration file and a hardware simulation configuration file for each test case, namely compiling test programs corresponding to different test models, and operating an algorithm model executable program and a hardware simulation executable program;
(c) and comparing the algorithm model result and the hardware simulation result aiming at each test case, and forming a report.
However, as the integrated circuit rapidly develops and the chip scale increases, the verification work in the chip design becomes more difficult, which becomes the most expensive work in the process and occupies a larger and larger proportion of the whole design cycle. The traditional mode of manually executing the chip function verification based on manpower has the defects of low chip verification speed and large time consumption due to low automation degree; moreover, the verification process is manually participated, so that errors are easy to occur, and the verification error probability is high.
Therefore, the traditional manual chip verification mode cannot meet the current large-scale chip verification requirement. Therefore, how to accurately and efficiently verify the chip functions becomes a technical problem to be solved urgently.
In order to solve the problems of the existing chip verification mechanism, the embodiment of the application provides an automatic verification method and system of a chip and a storage medium. Specifically, in the automatic verification system provided by the application, the automatic verification system can automatically analyze test parameters and test scenes corresponding to chips to be verified in a preset test case library, and then automatically generate a test case list comprising complete test cases; then, the automatic verification system can automatically convert each test case in the test case list into two executable files with different formats, such as a first file and a second file, according to different specific file formats, and respectively load and operate the two executable files through two different preset test models, so as to obtain two test results corresponding to each test case; furthermore, the chip verification system can automatically compare two test results corresponding to each test case, and automatically count all comparison results to determine the verification result of the chip to be verified. Therefore, the chip verification system realizes automation of generation of the test case, generation of the executable file, running of the test program and comparison of the test result, the verification speed of the chip is high, accuracy is good, chip verification efficiency and reliability of the verification result are greatly improved, and efficient verification of the chip is further realized.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
An embodiment of the present application provides an automatic verification method for a chip, fig. 1 is a schematic implementation flow diagram of the automatic verification method for a chip provided in the embodiment of the present application, and as shown in fig. 1, in the embodiment of the present application, a method for an automatic verification system to perform automatic verification for a chip may include the following steps:
In the embodiment of the application, the chip verification system may first read information such as test parameters and test scenarios corresponding to the chip to be verified from a preset test case library, and then further generate a test case list corresponding to the chip to be verified according to the test parameters and the test scenarios.
It should be noted that, in the embodiment of the present application, the automatic verification system may be constituted by at least one device. Optionally, the at least one device may be a physical server, a virtual server (e.g., a cloud server), a tablet computer, a Personal Computer (PC), a notebook computer, or other devices having a computing function and a storage function, and the device of the automatic authentication method for an application chip in this embodiment of the present application is not particularly limited.
It should be understood that the test parameters and test scenarios refer to a large amount of test data used for generating test cases to verify the functions of the chip to be verified; a test case library is a database that stores a large amount of test data.
Specifically, before chip verification, a designer may design corresponding test parameters and test scenarios according to expected functional requirements of a chip to be verified, and store the test parameters and the test scenarios in a corresponding database, that is, a test case library.
Further, in the embodiment of the application, the automatic verification system can automatically read the test parameters and the test scenes from the test case library, and perform diversified combination and analysis on all the test scenes and the test parameters, so as to generate a complete test case of the chip to be verified, avoid the incompleteness when the test case is manually generated, and further realize the coverage test of the chip to be verified.
For example, assuming that the chip to be verified includes a login function, a designer designs a login scene for the login function of the chip to be verified, where the input situations of user names include n types and the input situations of passwords include m types, and stores the corresponding test data into the test case library. The automatic verification system can automatically combine and analyze the user name parameter and the password parameter to generate n multiplied by m test cases aiming at the login scene of the chip to be verified.
It should be noted that, in the embodiment of the present application, the automatic verification system stores the generated test case in an excel file form; that is to say, the chip verification system generates a test case list according to the generated complete test case of the chip to be verified, so as to further realize automatic switching of the test case based on the test case list.
Further, in the embodiment of the application, after the chip verification system reads the test parameters and the test scenario and generates the test case list corresponding to the chip to be verified according to the test parameters and the test scenario, the chip verification system may further generate the executable files, such as the first file and the second file, according to the test case list.
102, generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to at least one test case; the second file list comprises at least one second file corresponding to at least one test case.
In the embodiment of the application, after the automatic verification system generates the test case list including the complete test case of the chip to be verified according to the test parameters, the test scene and other information, the automatic verification system may further generate the first file list and the second file list according to the test case list.
It can be understood that, in the chip verification process, the corresponding test case generally needs to be converted into an executable file/configuration file capable of running on the machine, so as to implement the running of the corresponding test program. Therefore, in the embodiment of the application, the automatic verification system can perform format conversion on each test case in the test case list, so as to generate an executable file corresponding to each test case, and store the executable file in an excel file form, so as to generate a corresponding executable file list.
Specifically, in the embodiment of the application, the chip verification system may be configured with an assembler, a compiler, and a linker, the automatic verification system may determine a file format corresponding to an executable file according to actual verification needs, and when a test case is converted, the automatic verification system may automatically assemble, compile, and link each test case through the assembler, the compiler, and the linker according to a list order and a specified file format, thereby generating an executable file corresponding to each test case and storing the executable file in a list form.
It should be noted that, in the embodiment of the present application, the file format of the executable file is not limited to the binary format, such as the extension name being BIN or TSK; or a text format such as the extension TXT. That is, any file format that can be recognized by a corresponding test model after loading may be used as the file format of the executable file.
Specifically, in an embodiment of the present application, fig. 2 is a schematic view of an implementation flow of an automatic verification method for a chip provided in the embodiment of the present application, and as shown in fig. 2, a method for generating a first file list and a second file list by an automatic verification system according to a test case list includes:
102a, compiling at least one test case respectively according to a preset text format to obtain at least one text file, and generating a first file list according to the at least one text file.
And 102b, compiling at least one test case according to a preset binary format to obtain at least one secondary system file, and generating a second file list according to the at least one binary file.
Therefore, the automatic verification system can automatically compile each test case in the test case list according to a preset text format, and further generate an executable file, namely a first file, of the text format corresponding to each test case; meanwhile, the chip verification system can also automatically compile each test case in the test case list according to a preset binary format, and further generate an executable file, namely a second file, of the binary format corresponding to each test case. That is, the automatic verification system can automatically generate two executable files with different formats for the same test case.
In detail, in the embodiment of the present application, the automatic verification system may determine the file format parameter structure that can be identified according to different test models/platforms, and further determine the file format corresponding to the executable file, for example, the binary parameter structure that can be identified by the hardware environment and the text parameter structure that can be identified by the software simulation environment; the automatic verification system can generate the binary format executable/configuration file and the text format executable/configuration file corresponding to the same test case through compiling processing according to the binary parameter structure body or the text parameter structure body respectively.
Furthermore, the automatic verification system can store the first file corresponding to each test case according to the excel file form, so as to generate a first file list, and meanwhile, the automatic verification system can store the second file corresponding to each test case according to the excel file form, so as to generate a second file list.
It should be noted that, in the embodiment of the present application, the first file and the second file corresponding to the same test case may correspond to the same file name, but correspond to different extensions. In order to reflect the correspondence between the two executable files and the test cases, the file names of the first file and the second file can be named by the related information of the test cases.
It should be noted that, in the embodiment of the present application, the step 102a and the step 102b are independent processes, and the order is not limited. Step 102a may be before step 102b, or after step 102b, or may be performed simultaneously with step 102 b.
Further, in the embodiment of the application, after the automatic verification system generates the first file list and the second file list according to the test case list, the automatic verification system may execute the test program based on the preset test model, the first file list and the second file list, respectively, to obtain the test result.
103, obtaining at least one first test result corresponding to at least one first file based on a first preset test model and a first file list; and meanwhile, obtaining at least one second test result corresponding to at least one second file based on a second preset test model and the second file list.
In an embodiment of the application, after the automatic verification system respectively generates the corresponding first file list and the second file list according to the test case list, the automatic verification system may further obtain a first test result corresponding to the chip to be verified, that is, at least one first test result corresponding to at least one first file, based on the first preset test model and the first file list; meanwhile, the automatic verification system can further obtain a second test result corresponding to the chip to be verified based on the second preset test model and the second file list, namely, at least one second test result corresponding to at least one second file.
It should be noted that, in the embodiment of the present application, the first preset test model is a software algorithm verification model, and the executable file capable of running on the model is a configuration file in a text format, such as a TXT configuration file; the second predetermined test model is a hardware integrated circuit verification model, and the executable file capable of running on the hardware integrated circuit verification model is a configuration file in a binary format, such as a BIN configuration file.
It should be understood that in embodiments of the present application, a software algorithm verification model refers to a model written in an algorithmic language that does not require synthesis, e.g., an algorithmic model implemented using C or systemC. The software algorithm verification model is run on a Computer (PC). The hardware integrated circuit verification model refers to a hardware simulation environment, e.g., HAPS.
It should be noted that, in the embodiment of the present application, the automatic verification system may automatically load and run each executable file according to the file list through the preset test model, and further generate a first test result corresponding to each first file and a second test result corresponding to each second file; because the same test case respectively corresponds to a first file and a second file, two test results corresponding to each test case are generated.
Specifically, fig. 3 is a schematic view illustrating a third implementation flow of the automatic verification method for a chip according to the embodiment of the present application, as shown in fig. 3, in the embodiment of the present application,
on one hand, the method for obtaining at least one first test result corresponding to at least one first file by the automatic verification system based on the first preset test model and the first file list comprises the following steps:
In detail, in the embodiment of the present application, the automatic verification system may sequentially and automatically download each first file, such as a TXT configuration file, generated according to the test case to the software algorithm verification model according to the first file list, and then automatically run the TXT configuration file through the software algorithm model, so as to generate the first test result corresponding to each test case.
On the other hand, the method for obtaining at least one second test result corresponding to at least one second file by the automatic verification system based on the second preset test model and the second file list comprises the following steps:
and 103b, respectively loading and executing at least one second file through the hardware integrated circuit verification model to obtain at least one second test result.
In detail, in the embodiment of the present application, the automatic verification system may sequentially download each second file, such as a BIN configuration file, generated according to the test case to a hardware integrated circuit model, such as an HAPS, according to the second file list, and then automatically run the BIN configuration file through the HAPS, so as to generate a second test result corresponding to each test case.
It should be noted that, in the embodiment of the present application, running the first file through the software algorithm verification model and running the second file through the hardware integrated circuit verification model are two completely independent processes, which may be performed successively; the steps 103a and 103b may be performed simultaneously, and the execution sequence of the steps 103a and 103b is not limited in this application.
Further, in the embodiment of the application, after the automatic verification system generates two test results corresponding to each test case based on two different preset test models and two file lists, the verification result corresponding to the chip to be verified can be further determined based on the test results.
And step 104, determining a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
In the embodiment of the application, after the automatic verification system automatically generates the two test results corresponding to the test cases, the automatic verification system can further determine the verification result corresponding to the chip to be verified according to the first test result and the second test result corresponding to all the test cases.
It should be understood that the first test result is an output result generated after the software algorithm verification model is loaded and run in the first file (TXT configuration file); the second test result is an output result generated after the hardware integrated circuit verification model is loaded and runs a second file (BIN configuration file).
Optionally, in an embodiment of the present application, the test result may be stored in a preset file directory, or a test result list may be generated according to an output order of the test result.
Specifically, if the test result is stored in a file directory, the first test result and the second test result corresponding to the same test case may be two files stored in the same file directory and having the same file name but different file extensions; alternatively, two files having the same file name and extension are stored in different file directories.
Specifically, if the test results are stored in a table form, the test results are sequentially stored in an excel file form according to the output sequence of the test results. Obtaining a first test result list and a second test result list; and the first test result and the second test result corresponding to the same test case are positioned in the same row in different lists.
It should be noted that, in the embodiment of the present application, the first test result and the second test result corresponding to the same test case may be the same or different.
Specifically, in the embodiment of the application, after obtaining two test results corresponding to all test cases, the automatic verification system performs automatic comparison based on the two test results corresponding to each test case, records a comparison condition corresponding to each test case, counts all comparison conditions corresponding to all test cases, and determines a verification result corresponding to a chip to be verified based on all comparison conditions.
Further, if the verification result is determined to be that the chip function is correctly realized, the chip meets the expected function requirement, and the chip can be put into practical application in subsequent production; if the verification result is determined to be that the chip function is not correctly realized, the chip is indicated to not meet the expected function requirement, and designers can subsequently improve the chip until the chip is repeatedly verified to meet the expected function requirement, so that the chip can be produced and put into practical application.
The embodiment of the application provides an automatic verification method and system of a chip and a storage medium, wherein the automatic verification system can automatically analyze test parameters and test scenes corresponding to the chip to be verified in a preset test case library, and immediately and automatically generate a test case list comprising complete test cases; then, the automatic verification system can automatically convert each test case in the test case list into two executable files with different formats, such as a first file and a second file, according to different specific file formats, and respectively load and operate the two executable files through two different preset test models, so as to obtain two test results, such as a first test result and a second test result, corresponding to each test case; furthermore, the chip verification system can automatically compare two test results corresponding to each test case in the test case list, and automatically count all comparison results to determine the verification result of the chip to be verified. Therefore, the chip verification system realizes automation of test case generation, test program operation and test result comparison, the verification speed of the chip is high, accuracy is good, chip verification efficiency and reliability of verification results are greatly improved, and efficient verification of the chip is further realized.
Based on the foregoing embodiment, in another embodiment of the present application, fig. 4 is a schematic diagram of an implementation flow of an automatic verification method for a chip proposed in the embodiment of the present application, as shown in fig. 4, in an embodiment of the present application, a method for determining a verification result corresponding to a chip to be verified by an automatic verification system according to at least one first test result and at least one second test result may include the following steps:
104a, comparing at least one first test result with at least one second test result to obtain at least one comparison result corresponding to at least one test case; wherein, one comparison result corresponding to one test case is the same or different.
And step 104b, determining the ratio of the same comparison result in at least one comparison result.
Specifically, in the embodiment of the application, after the automatic verification system automatically generates the first test result and the second test result corresponding to each test case in the test case list, the chip verification system may automatically compare the test results to obtain a comparison result.
Optionally, the automatic verification system may automatically read the first test result and the second test result corresponding to the same test case from the same or different file directories based on the file name or the extension, and perform comparison processing.
Optionally, the automatic verification system may automatically and sequentially read two test results corresponding to the same test case and located in the same row according to the sequence of the test result list, and perform comparison processing.
It should be understood that, in the embodiment of the present application, if the first test result and the second test result corresponding to one test case are the same, it is determined that the comparison result corresponding to the test case is the same; if the first test result and the second test result corresponding to one test case are different, the comparison result corresponding to the test case can be determined to be different.
Furthermore, the chip verification system compares the first test result and the second test result corresponding to each test case in the test case list, that is, after the comparison processing of the output result of the software algorithm verification model and the output result of the hardware integrated circuit verification model is executed for each test case, the automatic verification system can count the comparison results corresponding to all test cases.
Specifically, in the embodiment of the present application, in the process of counting the comparison results, the automatic verification system may count the comparison results as the same number, and calculate the comparison value of the comparison results as the same number in all the comparison results.
For example, assuming that the chip to be verified corresponds to 100 test cases, the automatic verification system counts that the comparison results are 95% in the same number in all 100 comparison results, that is, the percentage occupied by the comparison results that are the same is 95%.
Further, in the embodiment of the application, after determining that the comparison results in all the comparison results corresponding to all the test cases are the same corresponding percentage value, the automatic verification system may further determine the verification result corresponding to the chip to be verified according to the percentage value.
And step 104c, determining a verification result corresponding to the chip to be verified according to the occupation ratio value.
In the embodiment of the application, after the automatic verification system determines that all comparison results corresponding to all test cases are the same corresponding percentage value, the automatic verification system can further determine the verification result corresponding to the chip to be verified according to the percentage value.
It should be noted that, in the embodiment of the present application, the automatic verification system may preset a ratio threshold for representing correct implementation of the chip function, and after determining that the comparison result is the same corresponding ratio value, the ratio value may be compared with the preset ratio threshold, so as to determine the verification result, corresponding to the chip to be verified, according to the comparison result,
Specifically, if the comparison result indicates that the same corresponding percentage value is greater than or equal to the preset percentage threshold, the automatic verification system may determine that the chip to be verified meets the preset design function requirement, that is, the verification result indicates that the chip function is correctly implemented.
Specifically, if the comparison result indicates that the same corresponding percentage value is smaller than the preset percentage threshold, the automatic verification system may determine that the chip to be verified cannot meet the preset design function requirement, that is, the verification result indicates that the chip function is not correctly implemented.
Furthermore, designers can determine whether the design is correct according to the chip verification result, continue to generate the chip and put into practical application, or make a design error, and modify the logic circuit.
The embodiment of the application provides an automatic verification method of a chip, wherein an automatic verification system can respectively load and operate corresponding configuration files generated by test cases through two different preset test models to obtain two test results corresponding to each test case; and automatically comparing the two test results corresponding to each test case, and automatically counting all comparison results to determine the verification result of the chip to be verified. Therefore, the chip verification system realizes automatic verification, the verification speed of the chip is high, the accuracy is good, the chip verification efficiency and the reliability of the verification result are greatly improved, and the efficient verification of the chip is further realized.
Based on the above embodiments, in another embodiment of the present application, fig. 5 is a schematic diagram of a framework of an automatic verification system proposed in the embodiment of the present application, and as shown in fig. 5, the automatic verification system 100 is mainly divided into three parts, including a front-end configuration part 10, a middle operation part 20, and a back-end analysis part 30.
The front-end configuration part 10 mainly includes a test case library 11, a test case analysis module 12, a software algorithm model configuration file generation module 13, and a hardware integrated circuit simulation configuration file generation module 14.
Specifically, the test case library 11 is used for storing a large number of test parameters and test scenes corresponding to the chips to be verified, which are used for generating the test cases;
the test case analysis module 12 is used for reading the test parameters and the test scenes from the test case library 11 and analyzing the test parameters and the test scenes to generate a test case list; the test case list comprises test cases with complete chips to be verified;
a software algorithm model configuration file generation module 13, configured to perform format conversion processing on the test case, and generate a configuration file in a text format, such as a TXT configuration file;
the hardware integrated circuit simulation configuration file generation module 14 is configured to perform format conversion processing on the test case, and generate a configuration file in a binary format, such as a BIN configuration file.
The intermediate operation part 20 mainly comprises a software algorithm model executable program 21, a hardware integrated circuit simulation program 22 and a program operation module 23; the program running module includes a software algorithm model running module 231, a hardware integrated circuit running module 232, and a JTAG debugging tool traue 24.
A software algorithm model executable 21, referred to as the software algorithm verification model, for loading a TXT configuration file into the software algorithm model executable;
a hardware integrated circuit simulation program 22, which refers to the hardware integrated circuit verification model, and is used for loading the BIN configuration file into the hardware integrated circuit simulation program;
a software algorithm model running module 231, configured to run the software algorithm model executable program after completing loading of the TXT configuration file, so as to obtain a first output result, that is, a first test result;
a hardware integrated circuit running module 232, configured to run the hardware integrated circuit simulation program after completing loading of the BIN configuration file, and obtain a second output result, that is, a second test result;
TRACE 3224 refers to an external debug interface, and is used for debugging a test program.
The back-end analysis part 30 mainly includes a comparison verification and result analysis module 31, which is divided into a result comparison module 311 and a report generation module 312.
The result comparison module 31 is used for comparing the output result of the executable program of the software algorithm model, namely the first test result, and the simulation operation result of the hardware integrated circuit, namely the second test result, aiming at each test case, and recording the comparison condition;
the report generating module 32 is configured to count comparison results of all test cases, generate an execution success rate and a correctness rate of the test cases, and determine a verification result corresponding to the chip to be verified.
Based on the above embodiments, in another embodiment of the present application, fig. 6 is a schematic structural diagram of the automatic verification system proposed in the present application, as shown in fig. 6, the automatic verification system 100 proposed in the embodiment of the present application may include a reading unit 41, a generating unit 42, an obtaining unit 43 and a determining unit 44,
the reading unit 41 is configured to read a test parameter and a test scene corresponding to the chip to be verified from a preset test case library;
the generating unit 42 is configured to generate a test case list according to the test parameters and the test scenario; the test case list comprises at least one test case; generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to the at least one test case; the second file list comprises at least one second file corresponding to the at least one test case;
the obtaining unit 43 is configured to obtain at least one first test result corresponding to the at least one first file based on a first preset test model and the first file list; meanwhile, obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list;
the determining unit 44 is configured to determine a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
Further, in an embodiment of the present application, the at least one first file is at least one text file, and the at least one second file is at least one binary file.
Further, in an embodiment of the present application, the first preset test model is a software algorithm verification model, and the second preset test model is a hardware integrated circuit verification model.
Further, in an embodiment of the present application, the generating unit 42 is specifically configured to compile the at least one test case according to a preset text format, so as to obtain the at least one text file; and simultaneously, compiling the at least one test case respectively according to a preset binary format to obtain the at least one secondary system file.
Further, in an embodiment of the present application, the obtaining unit 43 is specifically configured to load and run the at least one first file through the software algorithm verification model, respectively, to obtain the at least one first test result.
Further, in this embodiment of the application, the obtaining unit 43 is further specifically configured to load and run the at least one second file through the hardware integrated circuit verification model, respectively, to obtain the at least one second test result.
Further, in an embodiment of the present application, the determining unit 44 is specifically configured to compare the at least one first test result and the at least one second test result to obtain at least one comparison result corresponding to the at least one test case; wherein, one comparison result corresponding to one test case is the same or different; determining the ratio of the same comparison result in the at least one comparison result; and determining the verification result according to the ratio.
Further, in an embodiment of the present application, the determining unit 44 is further specifically configured to determine that the verification result is that the chip function is correctly implemented if the duty ratio is greater than or equal to a preset duty ratio threshold; and if the ratio value is smaller than the preset ratio threshold value, determining that the verification result is that the chip function is not correctly realized.
In the embodiment of the present application, further, fig. 7 is a schematic structural diagram of a composition of the automatic verification system provided in the embodiment of the present application, as shown in fig. 7, the automatic verification system 100 provided in the embodiment of the present application may further include a processor 45, a memory 46 storing executable instructions of the processor 45, and further, the automatic verification system 100 may further include a communication interface 47, and a bus 48 for connecting the processor 45, the memory 46, and the communication interface 47.
In an embodiment of the present Application, the Processor 45 may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a ProgRAMmable Logic Device (PLD), a Field ProgRAMmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It is understood that the electronic devices for implementing the above processor functions may be other devices, and the embodiments of the present application are not limited in particular. The automated verification system 100 may further include a memory 46, the memory 46 may be coupled to the processor 45, wherein the memory 46 is configured to store executable program code comprising computer operating instructions, and the memory 46 may comprise high speed RAM memory and may further comprise non-volatile memory, such as at least two disk memories.
In the embodiment of the present application, a bus 48 is used to connect the communication interface 47, the processor 45, and the memory 46 and the intercommunication among these devices.
In an embodiment of the present application, the memory 46 is used for storing instructions and data.
Further, in an embodiment of the present application, the processor 45 is configured to read a test parameter and a test scenario corresponding to the chip to be verified from a preset test scenario library, and generate a test scenario list according to the test parameter and the test scenario; the test case list comprises at least one test case; generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to the at least one test case; the second file list comprises at least one second file corresponding to the at least one test case; obtaining at least one first test result corresponding to the at least one first file based on a first preset test model and the first file list; meanwhile, obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list; and determining a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
In practical applications, the Memory 46 may be a volatile Memory (volatile Memory), such as a Random-Access Memory (RAM); or a non-volatile Memory (non-volatile Memory), such as a Read-Only Memory (ROM), a flash Memory (flash Memory), a Hard Disk (Hard Disk Drive, HDD) or a Solid-State Drive (SSD); or a combination of the above types of memories and provides instructions and data to the processor 45.
In addition, each functional module in this embodiment may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.
Based on the understanding that the technical solution of the present embodiment essentially or a part contributing to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The embodiment of the application provides an automatic verification system which can automatically analyze test parameters and test scenes corresponding to chips to be verified in a preset test case library and immediately and automatically generate a test case list comprising complete test cases; then, the automatic verification system can automatically convert each test case in the test case list into two executable files with different formats, such as a first file and a second file, according to different specific file formats, and respectively load and operate the two executable files through two different preset test models, so as to obtain two test results, such as a first test result and a second test result, corresponding to each test case; furthermore, the chip verification system can automatically compare two test results corresponding to each test case in the test case list, and automatically count all comparison results to determine the verification result of the chip to be verified. Therefore, the chip verification system realizes automation of test case generation, test program operation and test result comparison, the verification speed of the chip is high, the accuracy is good, the chip verification efficiency and the reliability of the verification result are greatly improved, and efficient verification of the chip is further realized
An embodiment of the present application provides a computer-readable storage medium, on which a program is stored, which when executed by a processor implements the automatic verification method of a chip as described above.
Specifically, the program instructions corresponding to an automatic chip verification method in the present embodiment may be stored in a storage medium such as an optical disc, a hard disc, or a usb disk, and when the program instructions corresponding to an automatic chip verification method in the storage medium are read or executed by an electronic device, the method includes the following steps:
reading test parameters and test scenes corresponding to the chip to be verified from a preset test case library, and generating a test case list according to the test parameters and the test scenes; the test case list comprises at least one test case;
generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to the at least one test case; the second file list comprises at least one second file corresponding to the at least one test case;
obtaining at least one first test result corresponding to the at least one first file based on a first preset test model and the first file list; meanwhile, obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list;
and determining a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of implementations of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks in the flowchart and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.
Claims (11)
1. A method for automatically verifying a chip, the method comprising:
reading test parameters and test scenes corresponding to the chip to be verified from a preset test case library, and generating a test case list according to the test parameters and the test scenes; the test case list comprises at least one test case;
generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to the at least one test case; the second file list comprises at least one second file corresponding to the at least one test case;
obtaining at least one first test result corresponding to the at least one first file based on a first preset test model and the first file list; meanwhile, obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list;
and determining a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
2. The method of claim 1, wherein the at least one first file is at least one text file and the at least one second file is at least one binary file.
3. The method of claim 1, wherein the first predetermined test model is a software algorithm verification model and the second predetermined test model is a hardware integrated circuit verification model.
4. The method of claim 2, wherein generating a first file list and a second file list according to the test case list comprises:
compiling the at least one test case respectively according to a preset text format to obtain at least one text file;
and simultaneously, compiling the at least one test case respectively according to a preset binary format to obtain the at least one secondary system file.
5. The method according to claim 3, wherein the obtaining at least one first test result corresponding to the at least one first file based on the first preset test model and the first file list comprises:
and respectively loading and operating the at least one first file through the software algorithm verification model to obtain the at least one first test result.
6. The method according to claim 3, wherein the obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list comprises:
and respectively loading and operating the at least one second file through the hardware integrated circuit verification model to obtain the at least one second test result.
7. The method according to claim 1, wherein the determining the verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result comprises:
comparing the at least one first test result with the at least one second test result to obtain at least one comparison result corresponding to the at least one test case; wherein, one comparison result corresponding to one test case is the same or different;
determining the ratio of the same comparison result in the at least one comparison result;
and determining the verification result according to the ratio.
8. The method of claim 7, wherein determining the verification result according to the fraction value comprises:
if the occupation ratio value is larger than or equal to a preset occupation ratio threshold value, determining that the verification result is that the chip function is correctly realized;
and if the occupation ratio value is smaller than the preset occupation ratio threshold value, determining that the verification result is that the chip function is not correctly realized.
9. An automatic authentication system characterized by comprising a reading unit, a generating unit, an acquiring unit, and a determining unit,
the reading unit is used for reading the test parameters and the test scenes corresponding to the chip to be verified from a preset test case library;
the generating unit is used for generating a test case list according to the test parameters and the test scene; the test case list comprises at least one test case; generating a first file list and a second file list according to the test case list; the first file list comprises at least one first file corresponding to the at least one test case; the second file list comprises at least one second file corresponding to the at least one test case;
the obtaining unit is configured to obtain at least one first test result corresponding to the at least one first file based on a first preset test model and the first file list; meanwhile, obtaining at least one second test result corresponding to the at least one second file based on a second preset test model and the second file list;
the determining unit is configured to determine a verification result corresponding to the chip to be verified according to the at least one first test result and the at least one second test result.
10. An automated verification system comprising a processor, a memory storing instructions executable by the processor, the instructions when executed by the processor implementing the method of any one of claims 1-8.
11. A computer-readable storage medium, on which a program is stored, for use in an automatic authentication system, wherein the program, when executed by a processor, implements the method of any one of claims 1-8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113485882A (en) * | 2021-07-21 | 2021-10-08 | 鹏城实验室 | Chip verification method and device and computer readable storage medium |
| WO2023060740A1 (en) * | 2021-10-15 | 2023-04-20 | 长鑫存储技术有限公司 | Data processing and test method and apparatus, device, and storage medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040181763A1 (en) * | 2003-03-14 | 2004-09-16 | Soltis Donald C. | Automatic manufacturing test case generation method and system |
| US20060064296A1 (en) * | 2005-12-09 | 2006-03-23 | Devins Robert J | Method and system of design verification |
| CN106708687A (en) * | 2015-11-12 | 2017-05-24 | 青岛海信电器股份有限公司 | Executable file-based chip verification method and apparatus |
| CN108804322A (en) * | 2018-06-05 | 2018-11-13 | 中国平安人寿保险股份有限公司 | Automated testing method, device, computer equipment and storage medium |
| CN110865971A (en) * | 2019-10-30 | 2020-03-06 | 南京南瑞微电子技术有限公司 | System and method for verifying SOC chip |
| CN111177007A (en) * | 2019-12-31 | 2020-05-19 | 中国银行股份有限公司 | Method and system for automatically generating BDD test case based on test data |
| CN111737134A (en) * | 2020-06-23 | 2020-10-02 | 湖南国科微电子股份有限公司 | Chip testing method and device, electronic equipment and storage medium |
| CN111859831A (en) * | 2020-07-16 | 2020-10-30 | Oppo广东移动通信有限公司 | Chip verification method and system, and storage medium |
| CN111881051A (en) * | 2020-08-03 | 2020-11-03 | Oppo广东移动通信有限公司 | Test case generation method and device, terminal and storage medium |
-
2021
- 2021-01-11 CN CN202110031434.8A patent/CN112731117A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040181763A1 (en) * | 2003-03-14 | 2004-09-16 | Soltis Donald C. | Automatic manufacturing test case generation method and system |
| US20060064296A1 (en) * | 2005-12-09 | 2006-03-23 | Devins Robert J | Method and system of design verification |
| CN106708687A (en) * | 2015-11-12 | 2017-05-24 | 青岛海信电器股份有限公司 | Executable file-based chip verification method and apparatus |
| CN108804322A (en) * | 2018-06-05 | 2018-11-13 | 中国平安人寿保险股份有限公司 | Automated testing method, device, computer equipment and storage medium |
| CN110865971A (en) * | 2019-10-30 | 2020-03-06 | 南京南瑞微电子技术有限公司 | System and method for verifying SOC chip |
| CN111177007A (en) * | 2019-12-31 | 2020-05-19 | 中国银行股份有限公司 | Method and system for automatically generating BDD test case based on test data |
| CN111737134A (en) * | 2020-06-23 | 2020-10-02 | 湖南国科微电子股份有限公司 | Chip testing method and device, electronic equipment and storage medium |
| CN111859831A (en) * | 2020-07-16 | 2020-10-30 | Oppo广东移动通信有限公司 | Chip verification method and system, and storage medium |
| CN111881051A (en) * | 2020-08-03 | 2020-11-03 | Oppo广东移动通信有限公司 | Test case generation method and device, terminal and storage medium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113485882A (en) * | 2021-07-21 | 2021-10-08 | 鹏城实验室 | Chip verification method and device and computer readable storage medium |
| WO2023060740A1 (en) * | 2021-10-15 | 2023-04-20 | 长鑫存储技术有限公司 | Data processing and test method and apparatus, device, and storage medium |
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