CN106546910A

CN106546910A - FPGA test platforms based on bit stream retaking of a year or grade

Info

Publication number: CN106546910A
Application number: CN201510589818.6A
Authority: CN
Inventors: 张洪
Original assignee: Individual
Current assignee: Individual
Priority date: 2015-09-17
Filing date: 2015-09-17
Publication date: 2017-03-29

Abstract

Boundary scan and bit stream retaking of a year or grade function of the present invention based on Xilinx companies FPGA, possess bit stream analysis ability.Whole test system is all completed in addition to jtag interface in a computer.The test system is not limited by FPGA exterior I OB number of pins, test and excitation is directly applied by boundary scan, the node for reclaiming test response is built into into d type flip flop and LUT, the occupancy and cost of labor of FPGA resource can be greatlyd save, while detection and the positioning of failure can be more accurately realized in bit stream retaking of a year or grade and bit stream parsing.

Description

FPGA test platforms based on bit stream retaking of a year or grade

Technical field

The present invention relates to bit stream retaking of a year or grade technology, the FPGA test platforms of the low cost of realization effectively can be transported Test for FPGA volume productions.

Background technology

Traditional FPGA method of testings are surveyed to design accordingly based on the logical resource and framework of FPGA itself Examination circuit, and produces test circuit pcb board, by manually through multiple testing process completing test. This method completes the configuration of FPGA internal circuits specifically by HDL code and generates bit stream file, then Bit stream file is downloaded in FPGA by eda software, then passes through peripheral circuit or external on pcb board Signal generator judges to survey finally by oscillograph or LED charactrons producing corresponding test and excitation Whether examination response is correct.Whole flow process is complicated and needs by manually to realize, and completes the test of FPGA Need through multiple above-mentioned flow process, in this way not only time-consuming for institute, and cost is also high.

It is, by writing test program, by computer controls, to have automated based on the FPGA method of testings of ATE Into the method [3] of cycle tests.Specially produced on ATE test equipment pins according to the test program write Corresponding test and excitation controlling FPGA internal states, then by other corresponding pin recovery FPGA The test response in portion, and processed and compared to judge to test the correctness of response.The method is relatively conventional FPGA method of testings for can accelerate testing process, but due to needing using ATE test equipments, and ATE test equipments are very expensive, so the increase of testing cost can be caused.And the storage of ATE test equipments is empty Between it is limited, the cycle tests that can store and the response reclaimed be it is conditional, can be to completing the complete of FPGA Test is impacted.

As traditional FPGA method of testings have disadvantage mentioned above, also been developed based on ATE in recent years (Automatic-Test-Equipment) method of testing, the method for testing and base based on boundary scan In the method for testing of BIST (Build-in Self Test).The appearance of these methods has promoted FPGA tests The fast development of technology, also overcomes the shortcoming of traditional FPGA method of testings to a certain extent.

It is that embedded BIST is electric on the basis of original FPGA test circuits based on the FPGA method of testings of BIST Road is tested to complete to correspond to.BIST circuit includes test vector generator TPG (Test Pattern Generator), circuit-under-test CUT (Circuit Under Test) and response analyzer ORA (Output Response Analyzer).TPG is for producing cycle tests inside FPGA, and is input to circuit-under-test In；Circuit-under-test is FPGA test circuits to be tested；Cycle tests is produced by TPG, then by ORA Test response is analyzed and is obtained final test result and is exported.This method is existed by hardware circuit The use that cycle tests avoids ATE equipment is produced inside FPGA, testing expense is reduced.And test sound The data processing answered is also to be completed by ORA circuits inside FPGA, improves data processing speed.But by In needing BIST circuit to be internally embedded in FPGA, not only occupy its internal resource, cause to need repeatedly survey Examination can just complete the covering to whole internal resource, and BIST circuit needs to take a significant amount of time to be designed, Versatility is not strong.But, although BIST circuit has a disadvantage mentioned above, but due to its test speed it is quick, Testing cost is low, is one of currently a popular method of testing.

The boundary scan module being internally integrated by FPGA based on the method for testing of boundary scan, i.e. JTAG (Joint Test Action Group) circuit come realize to FPGA excitation loading and respond recovery. Boundary scan module is mainly by test access port TAP (Test Access Port), TAP controller (TAP Controller), command register (Instruction Register) and data register (Data Register [4] are constituted).Data register is that the shift register concatenation in fpga chip I/O-unit is constituted, Can be used to move in and out data, so as to the loading and response of realizing FPGA excitations are reclaimed.Although the method Avoid based on embedded BIST circuit is needed in BIST approach so as to occupy the shortcoming of FPGA internal resources, but As moving in and out for boundary scan data is that serial is completed, so speed is slow.And due to FPGA cores Piece IO numbers are limited, and the test and excitation that also result in input and the test number of responses for reclaiming are limited, so as to increase The design difficulty of big FPGA test circuits and the number of times of test.

The content of the invention

The present invention is set up by the research to Xilinx companies FPGA product systems framework and test structure XDL language analysis databases, based on the automation vector design flow process of XDL, test vector automatic development software With test coverage statistical tool..Hardware components include JTAG cables and the JTAG modules in FPGA.It is soft Part part includes that bit stream is downloaded, and encourages a whole set of perfect test journey such as addition, bit stream retaking of a year or grade, retaking of a year or grade parsing Sequence.And test program automaticity is very high, manual intervention is not required in test process completely.

Description of the drawings

Fig. 1 is the FPGA test system Organization Charts of the present invention.

Output display when Fig. 2 is the opening cable success of the present invention.

Fig. 3 is the bit stream retaking of a year or grade key step of the present invention.

Fig. 4 is the bit stream parsing module workflow of the present invention.

Fig. 5 is the bit stream resolution file of the present invention.

Fig. 6 is the fault diagnosis and location module workflow of the present invention

Specific embodiment

Describe the present invention below in conjunction with the accompanying drawings.

Fig. 1 show FPGA test system Organization Charts.Software section is operated in PC, and the interaction of data is led to The JTAG download cables crossed between the jtag interface of the USB interface and FPGA that are connected to PC are completed.So For a JTAG download cable and a PC are only needed in the FPGA test system hardwares of PC versions, Hardware cost relative moderate.

Fig. 2 show output display when opening cable success.After test is started, main program module first will Connection between PC and FPGA device is checked, confirms whether JTAG cables are working properly.If JTAG Cable work is normal, and program will found a dialogue, at the same will show in display window open cable into The information alert of work(

Fig. 3 show FPGA bit stream retaking of a year or grade key steps.The first step is the initial frame address for arranging retaking of a year or grade (set Frame Address), bit stream read back operation will be from the beginning of the address.Second step is loading RCFG (Read Configuration Data) order, after retaking of a year or grade address is set, FPGA is set to into retaking of a year or grade state. 3rd step accesses FDRO (Frame Data Register Output) register command for loading.The deposit Device is connected with a flowing water path for being used for output, just can be obtained from configuration space by accessing the register In frame data.The total number of word of this retaking of a year or grade can be set while the order is loaded, for regulation from starting Frame address starts to read when retaking of a year or grade is completed the frame number for reading altogether.After above setting is completed, final step Just start to read data from FDRO registers.

Fig. 4 show the bit stream parsing module workflow of the present invention.After the completion of bit stream retaking of a year or grade, bit stream parsing Module is first loaded into corresponding bit stream parsing library file, will be recorded in physical bits different in FPGA therein Particular location of the trigger put in retaking of a year or grade bit stream character string is extracted, and is stored in corresponding file. Then extracted from the character string after analytical algorithm is parsed according to these more specific location informations corresponding State value.Finally by state value through respective handling be just obtained it is complete including concrete bitstream position information and The bit stream resolution file of physical location information and corresponding state value.

Fig. 5 show the bit stream resolution file example of the present invention.The second concrete bitstream position letter for being classified as register Breath, the 3rd and four are classified as its physical location information, so that " oras=is " as the 5th of the beginning state for being classified as recovery Value.Equally by taking the first row as an example, positioned at the register that output port in the Slice that numbering is X1Y79 is XQ The responses that different excitations twice are directed in test process are all 1.

Fig. 6 show the fault diagnosis and location module workflow of the present invention.Fault diagnosis and location module is born Blame last step in whole testing process：By bit stream parsing module produce bit stream resolution file and deposit It is that fault diagnosis list in test system is contrasted and obtained test result.Protect in bit stream resolution file What is deposited is the response in test process after addition excitation.What is preserved in fault diagnosis list is expected correct Response.By both are contrasted one by one, just can discover whether there is difference.If bit stream resolution file It is middle to there are the responses different from fault diagnosis list, then illustrate that FPGA occurs in that failure.Now, then search There is the concrete physical location information of the register of different responses, just the failure of FPGA can be positioned. Finally diagnosis and the specifying information for positioning are exported and be stored in test report.

Claims

1. the FPGA test systems of the present invention are divided into hardware components and software section：Hardware components include JTAG JTAG modules in cable and FPGA, software section include that bit stream is downloaded, excitation addition, bit stream retaking of a year or grade, A whole set of perfect test program such as retaking of a year or grade parsing, and test program automaticity is very high, is testing It is not required to manual intervention in journey completely.