CN114896922A - Chip IO multiplexing verification method based on formal verification - Google Patents
Chip IO multiplexing verification method based on formal verification Download PDFInfo
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- CN114896922A CN114896922A CN202210657892.7A CN202210657892A CN114896922A CN 114896922 A CN114896922 A CN 114896922A CN 202210657892 A CN202210657892 A CN 202210657892A CN 114896922 A CN114896922 A CN 114896922A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
Abstract
The invention discloses a chip IO multiplexing verification method based on formal verification, which comprises the following steps: s1, refining the chip IO multiplexing relation file according to the chip specified definition; s2, automatically forming an IO description file according to the chip IO multiplexing relation file; s3, performing open form verification, and importing a chip file and an IO description file to a verification tool; s4, starting formal verification and outputting a verification result; and S5, analyzing the result and judging whether the design BUG is adopted. Compared with the traditional Uvm verification, the IO multiplexing verification technology based on the formal verification is simple to use and concise in steps, and the workload is greatly reduced; the method does not need chip system-level simulation operation, so the operation time is short, and the verification efficiency is greatly improved.
Description
Technical Field
The invention relates to a chip IO multiplexing verification method based on formal verification.
Background
Verification is an important and indispensable link in modern chip development, and the mission of the verification is to ensure that the design function meets the design expectation and has no fault. Typically, in a chip development project, the time and human resources consumed for chip verification may account for 70%.
The mainstream traditional Verification method mainly uses a Verification methodology represented by uvm (universal Verification method) and systemveilog, and usually adopts a combination mode of random constraint and directional excitation to automatically generate excitation in circuit simulation, drive the circuit to operate, and complete the Verification function.
At present, formal verification is more and more concerned, and the main idea is to perform attribute description on design functions according to design rules and automatically perform mathematical analysis and verification based on mathematical expressions and models abstracted from chip design.
The traditional verification method has the defects that 1, UVM verification simulation time is long; 2. the workload is large, and the completeness is difficult to ensure. Due to the fact that UVM verification needs to drive a chip to run in a simulation mode, the scale of a modern chip is sharply increased, a large-scale server-level CPU chip can reach the scale of a billion gates at present, and under the condition of certain simulation computing resources, the time of system-level simulation running is greatly prolonged along with the increase of the scale of the chip. Due to the fact that verification is conducted in the UVM traditional mode, a verification scene needs to be set up for each function item, verification excitation is provided, an output result is analyzed and whether the result meets expectations or not is judged, the scale of a chip is rapidly improved at present, the integration level is higher and higher, the interconnection among internal components is more complicated, the function items to be verified are also increased explosively, the needed labor cost is extremely high, and the lack of the scene, the excitation or the result analysis easily causes the completeness of the function verification to be insufficient.
For a large-scale complex chip, multi-function multiplexing on an IO pin often exists, and different interface functions can be flexibly realized on the IO pin through different configurations of a register. For the verification of the multiplexing technology, if a traditional UVM verification method is adopted, a verification environment needs to be built, relevant configuration is carried out on each function of each pin, different excitation on the IO pin or in the chip is provided, observation is carried out in the chip or the IO pin, the result is judged, firstly, the operation time of a large-scale chip is long, only boot starting of a CPU core of the SoC chip has quite long time consumption, secondly, the workload is extremely large, and for a typical mcu chip, if 40 pins exist, and 5 functions are multiplexed on average on each pin, the verification process needs to be written 200 times.
Disclosure of Invention
The invention provides a chip IO multiplexing verification method based on formal verification, which can greatly improve the verification efficiency. According to the Formal verification method, simulation operation of a chip is not needed, only needs compiling, calls a Formal verification tool (such as VC Formal or Japer Gold) and combines the provided IO multiplexing relation table, automatic analysis and verification can be conducted, and finally a result is output.
The technical scheme is as follows:
a chip IO multiplexing verification method based on formal verification comprises the following steps:
s1, refining the chip IO multiplexing relation file according to the chip regulation definition;
s2, automatically forming an IO description file according to the chip IO multiplexing relation file;
s3, performing open form verification, and importing a chip file and an IO description file to a verification tool;
s4, starting formal verification and outputting a verification result;
and S5, analyzing the result, and judging whether the BUG is a design BUG.
Preferably, in S1, a chip IO multiplexing relationship file is written according to a chip design document, where the chip IO multiplexing relationship file includes a type and a signal name, and the type is input, output or both input and output, and the type is input; the signal name includes a signal name of the function multiplexing item and a signal name after each item multiplexing.
Preferably, in S2, the IO description file is a corresponding script configuration file written according to information in the chip IO multiplexing relationship file; and expanding the multiplexing function point of each input type and each output type into one table entry and expanding the multiplexing function point of each input type into two table entries for each pin in the IO description file.
Preferably, each table entry includes a hierarchical path of a pin in a chip code, a signal for driving the multiplexing function point or driven by the multiplexing function point inside the chip, an enabling condition and a test name.
Preferably, in S3, the verification tool is VC format.
Preferably, in S3, the formal verification tool is turned on, the related function configuration is performed, the chip source code file is imported, the compiling and synthesizing are performed to form a netlist, the IO multiplexing description file is imported, each entry to be tested is obtained, and the initialization state, the clock and the reset signal are set.
Preferably, in S4, verification is started, connectivity test is performed according to the input, output, and enable conditions of each entry of the IO description file, the IO multiplexing correctness is determined, and the result is output and analyzed.
Preferably, in the step S5, the IO multiplexing mode is not matched with the design document, and the error information is printed out for result analysis; when the printed information shows that a certain pin is in error, the multiplexing condition of the pin in the chip file is inconsistent with the script setting under the condition of the current script setting; when the inconsistency occurs, there may be two situations, one is that a chip file has an error, i.e., a BUG is designed, and the other is that a script is written with an error, even if the condition setting is inaccurate.
According to the optimization of the technical scheme, when the verification result is in problem, whether the design BUG for chip IO multiplexing or the enabling condition setting of the table entry is inaccurate is judged; if the latter, the entries of iteration S2 are modified, and S3 and S4 are restarted for the next round of testing until all design bugs are found.
Compared with the prior art, the invention has the beneficial effects that:
1. compared with the traditional Uvm verification, the verification method provided by the invention has the advantages that the IO multiplexing verification technology based on formal verification is simple to use and concise in steps, and the workload is greatly reduced.
2. According to the verification method, the simulation operation of a chip system level is not needed, so that the operation time is short, and the verification efficiency is greatly improved.
Drawings
FIG. 1 is a flow chart diagram of the verification method of the present invention.
Fig. 2 is a schematic diagram of an IO multiplexing relationship file according to this embodiment.
Detailed Description
The technical solution of the present invention is described in detail below, but the scope of the present invention is not limited to the embodiments.
In order to make the content of the present invention more comprehensible, the following description is further made in conjunction with the accompanying drawings 1 to 2 and the detailed description.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The chip IO multiplexing verification method based on formal verification comprises the following steps:
s1, refining the chip IO multiplexing relation file according to the chip specified definition;
s2, automatically forming an IO description file according to the chip IO multiplexing relation file;
s3, performing open form verification, and importing a chip file and an IO description file to a verification tool;
s4, starting formal verification and outputting a verification result;
and S5, analyzing the result and judging whether the design BUG is adopted.
In this embodiment, in S1, a chip IO multiplexing relationship file is written according to a chip design document, where the chip IO multiplexing relationship file includes a type and a signal name, and the type is input, output, or both input and output, inout; the signal name includes a signal name of the function multiplexing item and a signal name after each item multiplexing.
As shown in FIG. 2, for example, the first chip pin P0[6] can be multiplexed into the following 4 functions, I2S _ RX _ SDA type is input, SSP1_ SSEL input-output type, T2_ MAT0 output type and U1_ RTS output type.
In this embodiment, in S2, the IO description file is a corresponding script configuration file written according to information in the chip IO multiplexing relationship file; and expanding the multiplexing function point of each input type and each output type into one table entry and expanding the multiplexing function point of each input type into two table entries for each pin in the IO description file.
Each table entry comprises a hierarchical path of a pin in a chip code, a signal which drives the multiplexing function point or is driven by the multiplexing function point inside the chip, an enabling condition and a test name. The method specifically comprises the following steps: each entry covers the following parts:
a) the hierarchical path of the pin in the chip code is convenient for a formalization tool to analyze and position the pin in a network table in the chip;
b) the multiplexing function point is driven inside the chip or a signal driven by the multiplexing function point is driven by the multiplexing function point (module level output);
c) an enable condition (a general configuration pin is configured for a register of the multiplexing function, and an output enable signal needs to be added for an output signal);
d) test name, which is convenient to indicate which test was successful or failed.
In this embodiment, in S3, the verification tool is VC format or Japer Gold. Both of these validation tools are known in the art and known to those skilled in the art.
In this embodiment, in S3, a formal verification tool is turned on, a relevant function configuration is performed, a chip source code file is imported, compiling and synthesizing are performed to form a netlist, an IO multiplexing description file is imported, each entry to be tested is obtained, and signals such as an initialization state, a clock, and a reset are set.
In this embodiment, in S4, verification is started, a connectivity test is performed through the input, output, and enable conditions of each entry of the IO description file, the IO multiplexing correctness is determined, and the result is output and analyzed.
In S5, the IO multiplexing mode is not matched with the design document, and error information is printed out for result analysis; when the printed information shows that a certain pin is in error, the multiplexing condition of the pin in the chip file is inconsistent with the script setting under the condition of the current script setting; when the inconsistency occurs, there may be two situations, one is that a chip file has an error, i.e., a BUG is designed, and the other is that a script is written with an error, even if the condition setting is inaccurate.
When the verification result has a problem, judging whether the design BUG of the chip IO multiplexing or the enabling condition setting of the table entry is inaccurate; if the latter, the entries of iteration S2 are modified, S3 and S4 are restarted, and the next round of testing is performed until all design bugs are found.
The verification method of the embodiment is a verification method and thinking for IO multiplexing by adopting formal verification, the traditional UVM verification method needs to build a verification environment, construct a test scene, enable test excitation to obtain and compare test results, and conduct repeated testing on each function multiplexing item of all IO pins, the workload is huge, and because IO multiplexing belongs to system-level functions, the whole chip needs to be simulated and operated, the system operation time consumption of the whole chip is long, and the verification efficiency is low. The technology is based on formal verification, the steps are simple, the operation of a chip system level is not needed, only compiling is passed, and IO multiplexing related table items can be described by extracting and sorting according to the chip spec.
The specific embodiment is as follows:
as shown in FIG. 2, the IO mux register controlling P0[6] is P0_6_ IOCON, when this register is equal to 0, 1, 2, 3, 4, respectively corresponding to the four digital functions. If the enable condition in the IO description file is set to P0_6_ IOCON =3, then the signal t2_ mat inside the chip should be connected to the P0[6] port. In the chip description file, the signal t2_ mat is used as the source, and P0[6] is used as the target.
After the IO description file and the chip file are simultaneously imported, the tool can automatically compare whether the connection mode of the chip is consistent with that of the description file under the enabling condition in the chip file, and if the connection mode is not consistent with that of the description file, printing can be carried out to report errors.
After error report is found, engineers check whether writing of the IO description file is incorrect or a BUG exists in the chip design itself, and respectively process the BUG to eliminate the writing.
And repeating the debugging process until all IO descriptions can completely correspond to the chip file.
The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.
Claims (9)
1. A chip IO multiplexing verification method based on formal verification is characterized in that: the method comprises the following steps:
s1, refining the chip IO multiplexing relation file according to the chip specified definition;
s2, automatically forming an IO description file according to the chip IO multiplexing relation file;
s3, performing open form verification, and importing a chip file and an IO description file to a verification tool;
s4, starting formal verification and outputting a verification result;
and S5, analyzing the result and judging whether the design BUG is adopted.
2. The chip IO multiplexing verification method based on formal verification according to claim 1, wherein: in S1, writing a chip IO multiplexing relation file according to the chip design document, wherein the chip IO multiplexing relation file comprises a type and a signal name, and the type is input, output or both input and output; the signal name includes a signal name of the function multiplexing item and a signal name after each item multiplexing.
3. The chip IO multiplexing verification method based on formal verification according to claim 1 or 2, wherein: in S2, the IO description file is a corresponding script configuration file written according to the information in the chip IO multiplexing relation file; and expanding the multiplexing function point of each input type and each output type into one table entry and expanding the multiplexing function point of each input type into two table entries for each pin in the IO description file.
4. The chip IO multiplexing verification method based on formal verification according to claim 3, wherein: each table entry comprises a hierarchical path of a pin in a chip code, a signal which drives the multiplexing function point or is driven by the multiplexing function point inside the chip, an enabling condition and a test name.
5. The chip IO multiplexing verification method based on formal verification according to claim 1, wherein: in S3, the verification tool is VC Formal.
6. The chip IO multiplexing verification method based on formal verification according to claim 1 or 5, wherein: in S3, the formal verification tool is turned on, the relevant function configuration is performed, the chip source code file is imported, the compiling is performed to synthesize a netlist, the IO multiplexing description file is imported, each table entry to be tested is obtained, and the initialization state, the clock and the reset signal are set.
7. The chip IO multiplexing verification method based on formal verification according to claim 6, wherein: in S4, verification is started, a connectivity test is performed through the input, output, and enable conditions of each entry of the IO description file, the correctness of IO multiplexing is determined, and the result is output and analyzed.
8. The chip IO multiplexing verification method based on formal verification of claim 7, wherein: in S5, the IO multiplexing mode is not matched with the design document, and error information is printed out for result analysis; when the printed information shows that a certain pin is in error, the multiplexing condition of the pin in the chip file is inconsistent with the script setting under the condition of the current script setting; when the inconsistency occurs, there may be two situations, one is that a chip file has an error, i.e., a BUG is designed, and the other is that a script is written with an error, even if the condition setting is inaccurate.
9. The chip IO multiplexing verification method based on formal verification of claim 8, wherein: when the verification result has a problem, judging whether the design BUG of the chip IO multiplexing or the enabling condition setting of the table entry is inaccurate; if the latter, the entries of iteration S2 are modified, S3 and S4 are restarted, and the next round of testing is performed until all design bugs are found.
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| CN117271248A (en) * | 2023-11-23 | 2023-12-22 | 成都市楠菲微电子有限公司 | IO interface testing method and device and UVM verification environment |
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| CN117271248A (en) * | 2023-11-23 | 2023-12-22 | 成都市楠菲微电子有限公司 | IO interface testing method and device and UVM verification environment |
| CN117271248B (en) * | 2023-11-23 | 2024-02-09 | 成都市楠菲微电子有限公司 | IO interface testing method and device and UVM verification environment |
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