CN115757222A

CN115757222A - Data transmission method and device based on PL and PS

Info

Publication number: CN115757222A
Application number: CN202211189715.7A
Authority: CN
Inventors: 杨建旭; 金世超; 李晓晨; 高阳东; 吴成杰; 杨飞; 黄斐; 李明伟
Original assignee: Space Star Technology Co Ltd
Current assignee: Space Star Technology Co Ltd
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2023-03-07
Anticipated expiration: 2042-09-28
Also published as: CN115757222B

Abstract

The invention relates to a data transmission method and a device based on PL and PS, wherein AXI DMA IP core transmission is adopted in the direction from PL to PS, AXI CDMA IP core transmission is adopted in the direction from PS to PL, the method is suitable for video transmission, satellite communication, factory automation and other scenes, the application is wide, a double-ring cache mechanism is adopted in the data transmission between PL and PS, the utilization rate of cache is effectively improved, block-by-block moving is adopted in the data transmission between PL and PS, the size of a data block is changed in real time according to the size of different data packets, compared with the traditional method that DMA is triggered according to a fixed size, the data transmission efficiency is effectively improved, and the use requirement of a large number of high-speed communication scenes can be met.

Description

Data transmission method and device based on PL and PS

Technical Field

The invention relates to the technical field of communication, in particular to a data transmission method and device based on PL and PS.

Background

In recent years, with the development of satellite communication technology, satellite communication systems bring great convenience to people's work and life, and are more and more favored by people, and meanwhile, the development of satellite communication from narrow-band low-speed data service to broadband multimedia service has led to the explosive increase of communication satellite throughput. Currently, the mainstream satellite operators abroad have no development target of higher flux to meet the increasing satellite communication bandwidth demand.

During data transmission, the traditional method of using the FPGA to perform data acquisition and preprocessing, sending the data to the PC through the PCIE interface, and finally processing the data by the PC is rare, and the mainstream of the method is the FPGA + ARM architecture. The embedded system generally adopts a mode of ARM plus DSP or ARM plus FPGA, wherein ARM mainly completes a control function, and DSP or FPGA mainly completes a data processing function.

The FPGA + ARM architecture is currently divided into two types: the FPGA and the ARM are two independent chips, and the two chips perform data interaction through a GPMC bus and the like; the other is a Zynq chip mode, the chip integrates a processor with an FPGA framework and a processor with an ARM framework, and an AXI bus is used for interaction. At present, no related design scheme capable of considering both cost and transmission performance exists.

Disclosure of Invention

In view of this, the present invention provides a data transmission method and apparatus based on PL and PS, which can achieve both low cost and high performance transmission.

In a first aspect, an embodiment of the present invention provides a data transmission method based on PL and PS, where AXI DMA IP core transmission is adopted in a PL-to-PS direction, AXI CDMA IP core transmission is adopted in a PS-to-PL direction, and both directions adopt a dual ring cache mechanism, and block-by-block shifting is adopted during data transmission.

Further, in the PL-to-PS direction, both the FIFO of the PL and the forward buffer of the DDR are ring mechanisms.

Further, when data is transmitted in the direction from the PL to the PS, the PL generates 1ms interrupt, and the PS reads data from the forward buffer and processes the data after receiving the interrupt.

Further, when data is transmitted in the PS-to-PL direction, both the return buffers of the BRAM and DDR of the PL are ring mechanisms.

Further, when data is transmitted from the PS to the PL, the PL generates 10ms interruption, the PS inquires whether the return buffer has data to be transmitted after receiving the interruption, and if so, the AXI CDMA is triggered to carry out block transfer.

Furthermore, AXI CDMA transfers data in blocks according to the size of different real-time data packets when data is transmitted in the PS-to-PL direction.

Further, the PL-to-PS direction data transmission includes:

s110, applying a continuous space for a forward buffer area in DDR by PS, wherein the forward buffer area is an integral multiple of 512 bytes;

s120, the PS applies for another continuous space in the DDR for a return buffer, and the return buffer is an integral multiple of 128 bytes;

s130, the PS transmits the initial physical address and the size of the forward buffer to the PL;

s140, the PL configures AXI DMA according to the initial physical address of the forward buffer area, transmits the data in the FIFO to the DDR, then generates 1ms interrupt to the PS, records the number of 512 bytes of data moved to the forward buffer area and puts the number value into a forward packet counting register;

s150, after receiving the interrupt, the PS inquires the forward packet counting register, and when the packet number is larger than 0, 512 bytes of data are obtained from the DDR and processed.

Further, the data transmission in the PS-to-PL direction includes:

s210, the data generation module makes a packet and copies data to a return buffer area;

s220, calculating the size of the data to be transmitted in the return buffer;

s230, calculating the address and the size A of the first reading pointer;

s240, calculating the address and the size B of the second reading pointer;

s250, reading the size of the residual space of the BRAM;

s260, when the BRAM has residual space, carrying out CDMA moving of the data block;

the size of the data to be transmitted in the return buffer area is the difference between the read-write pointers of the return buffer area, and the residual space of the BRAM is the difference between the read-write pointers of the BRAM.

Further, step S210 includes:

s211, initializing a read-write pointer;

s212, calculating the size of the generated data to be written into the return buffer area, comparing the size with the residual space of the return buffer area, and entering the step S213 if the residual space is larger than or equal to the length of the data to be written;

s213, calculating the size alpha of the data which can be written in for the first time, wherein the calculation method is that the write pointer is subtracted from the end address of the return buffer area;

s214, comparing the size of the data to be written with alpha, if the size of the data to be written is smaller than or equal to the size of the data to be written, the step S215 is executed, and if the size of the data to be written is larger than the size of the data to be written, the step S216 is executed;

s215, copying data to the return buffer area for the first time;

s216, copying the data to be written with the same size as alpha to the return buffer area, calculating the size of the data to be written for the second time, and copying the data from the initial address of the return buffer area to the return buffer area;

s217, the write pointer is updated.

In a second aspect, an embodiment of the present invention provides an apparatus for performing the PL and PS based data transmission method according to any one of the first aspects, where hardware of the apparatus includes a power supply unit, a data input unit, a data output unit, a serial port unit, and a data storage unit;

the software of the device comprises PS embedded software, PS and PL communication interface software and PL logic software;

the device is based on a Linux system and comprises a u-boot, a kernel and a file system;

the PS and PL communication interfaces comprise a configuration interface, a data interface and an interrupt event interface, wherein the configuration interface is realized by AXI-GP and is used for realizing the basic configuration function from the PS to the PL direction, the data interface is realized by AXI-HP and is used for service data transmission, and the interrupt event interface comprises a GIC interrupt controller connected to the PS by PL interrupt and is used for 1ms and 10ms interrupt events.

The transmission between the PL and the PS of the method of the embodiment of the invention is based on a ring cache mechanism, has less consumed resources, high memory use efficiency and reduced cost, and can effectively improve the data transmission performance based on block-based moving and DMA and CDMA transmission, the downlink speed can reach more than 700Mb/s, the uplink speed can reach more than 160Mb/s, and the use requirements of various high-speed communication scenes are met.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a PL and PS based data transmission apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a downlink system of a PL and PS based data transmission apparatus according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an uplink system of a PL and PS based data transmission apparatus according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a downlink data processing flow of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 5 is a schematic diagram illustrating a downlink data processing principle of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating an uplink data processing flow of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 7 is a schematic diagram illustrating an uplink data processing principle of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 8 is a schematic flow chart of uplink packet generation and data copying to a return buffer according to the PL and PS based data transmission method of the present invention;

fig. 9 is a schematic diagram illustrating the principle of uplink packet generation and data copying to the backhaul buffer of the PL and PS based data transmission method according to the embodiment of the present invention.

Detailed Description

The description of the embodiments of this specification is intended to be taken in conjunction with the accompanying drawings, which are to be considered part of the complete specification. In the drawings, the shape or thickness of the embodiments may be exaggerated and simplified or conveniently indicated. Further, the components of the structures in the drawings are described separately, and it should be noted that the components not shown or described in the drawings are well known to those skilled in the art.

Any reference to directions and orientations to the description of the embodiments herein is merely for convenience of description and should not be construed as limiting the scope of the invention in any way. The following description of the preferred embodiments refers to combinations of features which may be present independently or in combination, and the present invention is not particularly limited to the preferred embodiments. The scope of the invention is defined by the claims.

As shown in fig. 1 to fig. 3, the downstream system of the PL and PS based data transmission device according to the embodiment of the present invention includes a data generation module, a FIFO, a DDR forward ring buffer, a DMA control module, and a PS data processing unit. The data generation block passes data to the FIFO of the PL, which passes data to the DDR forward ring buffer via AXI DMA, after which the PS performs corresponding data processing. The uplink system comprises a data generation module, a DDR postback ring buffer area, a BRAM, an AXI CDMA module and a PL data processing unit. The data generation module transfers data to a DDR return ring buffer, then the PS configures an uplink CDMA module for controlling PL through an AXI _ GP interface, and moves an uplink data packet to an internal BRAM of the PL, and then the PL carries out corresponding data processing.

In the present embodiment, the hardware of the PL and PS based data transmission device (hereinafter referred to as "device") includes a power supply unit, a data input unit, a data output unit, a serial port unit, and a data storage unit. The software of the device includes PS embedded software, PS and PL communication interface software, and PL logic software. The device is based on a Linux system and comprises a u-boot, a kernel and a file system. The PS and PL communication interfaces comprise a configuration interface, a data interface and an interrupt event interface, wherein the configuration interface is realized by AXI-GP and is used for realizing the basic configuration function from the PS to the PL direction, the data interface is realized by AXI-HP and is used for transmitting service data, and the interrupt event interface comprises a GIC interrupt controller connected to the PS by PL interrupt and is used for 1ms and 10ms interrupt events. An interrupt trigger interface and registers characterizing the type of interrupt event are designed from PL to PS. When an interrupt is generated, the PS reads the PL's interrupt status register through the AXI-GP interface. The lowest order bit is the interrupt event flag, and the interrupt period is 1ms. This interrupt is used to trigger the PS to do data processing. The configuration monitoring interface between the PS and the PL is realized through an AXI-GP interface, and a related configuration management register is designed in the FPGA.

In the device of the embodiment, forward data transmission adopts AXI-HP DMA transmission, return data transmission adopts AXI-HP CDMA transmission, FIFO, a forward annular buffer area, a return annular buffer area and BRAM in data transmission are all annular spaces, data transfer is carried out by CDMA using data blocks in PS uplink data processing, and the data blocks are transferred 1-3 times due to the fact that storage spaces are all annular and are divided into 7 situations.

The embodiment of the invention also provides a data transmission method of PL and PS based on the device, which adopts a Zynq-XC7Z020 chip, and the SOC comprises two parts of PS (ARM) and PL (FPGA). In the method of this embodiment, a dual ring buffer mechanism is used for data transmission between PL and PS, and the two mechanisms are respectively: when data is transmitted from PL to PS, FIFO of PL and forward buffer of DDR are both ring mechanism; in the PS-to-PL direction, both the BRAM and DDR return buffers of the PL are ring mechanisms. Meanwhile, when data is transmitted from PL to PS, PL generates 1ms interruption, PS reads data from the forward buffer zone after receiving the interruption and processes the data; when data is transmitted from PS to PL, PL generates 10ms interrupt, PS inquires whether the return buffer area has data to be transmitted after receiving the interrupt, if yes, AXI CDMA is triggered to carry out block transfer, and the block transfer is specifically that AXI CDMA can carry out data transfer according to the size of different real-time data packets.

As shown in fig. 4 and fig. 5, in the method of the present embodiment, PS downlink data transmission (PL-to-PS direction data transmission) includes:

s100, loading the CDMA driver.

as the data between PL and PS takes 512 bytes as unit, the annular operation in the space is convenient, and the first 4 bytes of 512 bytes are data packet headers used for continuity check and other operations.

because the data between PL and PS takes 128 bytes as unit, the annular operation in the space is convenient, and the size of BRAM is 64K and is also an integral multiple of 128 bytes; the PS then applies for an interrupt to receive the 1ms/10ms interrupt generated by the PL.

S130, the PS transmits the initial physical address and the size of the forward buffer area to the PL;

preferably, to the PL via the AXI-GP interface.

S140, the PL configures AXI DMA according to the initial physical address of the forward buffer area, transmits the data in the FIFO to the DDR, then generates 1ms interrupt to the PS, records the quantity of 512 bytes of data which are transferred to the forward buffer area and puts the quantity value into a forward packet counting register;

when the write address is equal to the tail address of the forward buffer area, the return operation is carried out (the write address is updated to the initial address of the forward buffer area) to achieve the annular purpose;

preferably, the FIFO is placed into the DDR through the AXI-HP interface.

S150, after receiving the interrupt, the PS queries a forward packet counting register, and when the packet number is more than 0, 512 bytes of data are obtained from the DDR and are processed;

because of the annular space, the read address is judged whether to be the tail address or not, and then the read pointer is updated.

As shown in fig. 6 and fig. 7, in the method of the present embodiment, PS uplink data transmission (PS-to-PL direction data transmission) includes:

s210, the data generation module uplink packages and copies the data to the return buffer area;

s220, calculating the size of the data to be transmitted in the return buffer area;

s230, calculating the address and the size A of the first reading pointer;

s240, calculating the address and the size B of the second reading pointer;

s250, reading the size of the residual space of the BRAM;

the size of the data to be transmitted in the return buffer is the difference between the read-write pointers of the return buffer, and the BRAM remaining space is the difference between the read-write pointers of the BRAM. Since both the backhaul buffer and BRAM are ring spaces, a total of 7 cases of data block movement are involved: if the write pointer is larger than the read pointer, A is the difference between the read and write pointers of the return buffer area, and B is equal to 0; if the write pointer is smaller than the read pointer, A is the size obtained by subtracting the read pointer from the tail address of the return buffer, and B is the size obtained by subtracting the first address of the return buffer from the write pointer; the size of A1 is equal to the size b of the first written BRAM, and A2 is equal to A minus A1; a2' is equal to the residual space of the BRAM minus the size b of the first written BRAM; b1 is equal to the size B of the first written BRAM minus A; b2 is equal to the size of the data to be transmitted in the return buffer minus A and B1; b' is equal to BRAM headroom minus a. B2' is the BRAM residual space minus a and B1.

As shown in fig. 8 and 9, in the present embodiment, the step S210 (i.e. the flow of uplink packet making and data copying to the backhaul buffer) includes:

s211, initializing a read-write pointer;

s212, calculating the size of the generated data to be written into the return buffer area, comparing the size with the remaining space (difference between the read-write pointers) of the return buffer area, and entering step S213 if the remaining space is greater than or equal to the length of the data to be written;

s215, copying the data to a return buffer area;

s216, copying the data to be written with the same size as alpha to the return buffer area, calculating the size of the data to be written for the second time, and copying the data to be written from the initial address of the return buffer area to the return buffer area;

and S217, updating the write pointer.

In conclusion, the transmission between the PL and the PS in the method of the embodiment of the invention is based on a ring cache mechanism, the consumed resources are less, the use efficiency of the memory is high, the cost is reduced, the data transmission performance can be effectively improved based on block moving, DMA and CDMA transmission, the downlink speed can reach more than 700Mb/s, the uplink speed can reach more than 160Mb/s, and the use requirements of various high-speed communication scenes are met.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A data transmission method based on PL and PS is characterized in that AXIDMAIP core transmission is adopted in the direction from PL to PS, AXICDMAIP core transmission is adopted in the direction from PS to PL, a double ring buffer mechanism is adopted in both directions, and block-by-block shifting is adopted during data transmission.

2. The method of claim 1, wherein the FIFO for PL and the forward buffer for DDR are both ring type mechanism when PL to PS direction data is transmitted.

3. A method according to claim 1, wherein when transmitting data in the PL to PS direction, the PL generates a 1ms interrupt, and the PS reads and processes data from the forward buffer after receiving the interrupt.

4. The method according to claim 1, wherein the backhaul buffers of BRAM and DDR of PL are both ring mechanism when data is transmitted in PS to PL direction.

5. The method according to claim 4, wherein when data is transmitted from PS to PL, PL generates 10ms interrupt, PS inquires whether there is data to be transmitted in the return buffer after receiving the interrupt, and if so, AXI CDMA is triggered to perform block transfer.

6. The PL-and PS-based data transmission method as claimed in claim 4, wherein AXI CDMA performs data transfer on a block-by-block basis according to the size of different real-time data packets when data is transmitted in the PS-to-PL direction.

7. A method of PL and PS based data transmission according to any of claims 1-6, wherein PL to PS direction data transmission comprises:

s140, the PL configures AXIDMA according to the initial physical address of the forward buffer area, transmits the data in the FIFO to the DDR, then generates 1ms interrupt to the PS, records the number of 512 bytes of data moved to the forward buffer area and puts the number value into a forward packet counting register;

s150, the PS queries the forward packet counting register after receiving the interrupt, and acquires 512 bytes of data from the DDR and processes the data when the packet number is larger than 0.

8. The method of claim 7, wherein the PS-to-PL direction data transmission comprises:

s220, calculating the size of the data to be transmitted in the return buffer;

s230, calculating the address and the size A of the first reading pointer;

s240, calculating the address and the size B of the second reading pointer;

s250, reading the size of the residual space of the BRAM;

the size of the data to be transmitted in the return buffer is the difference between the read-write pointers of the return buffer, and the BRAM remaining space is the difference between the read-write pointers of the BRAM.

9. The PL and PS based data transmission method according to claim 8, wherein the step S210 comprises:

s211, initializing a read-write pointer;

s212, calculating the size of the generated data to be written into the return buffer area, comparing the size with the residual space of the return buffer area, and entering the step S213 if the residual space is greater than or equal to the length of the data to be written;

s215, copying data to the return buffer area for the first time;

and S217, updating the write pointer.

10. An apparatus for performing the PL and PS based data transmission method according to any one of claims 1 to 9, wherein hardware of the apparatus comprises a power supply unit, a data input unit, a data output unit, a serial port unit and a data storage unit;