CN114168520B - Optical fiber communication bus device, equipment and system - Google Patents

Abstract

The present disclosure provides an optical fiber communication bus apparatus, device, and system, wherein the optical fiber communication bus apparatus includes: an optoelectronic transceiver module; DDR memory; and an FPGA chip, the FPGA chip comprising: a GTX transceiver coupled with the photoelectric transceiver module; an FC-AE-1553IP core configured to implement the FC-AE-1553 protocol; the cache module is coupled with the FC-AE-1553IP core and the DDR memory and is configured to cache data between the 1553 protocol and the PCIE protocol; and the PCIE hard core controller is coupled with the cache module, comprises a PIO module and a DMA module and is configured to transmit data to the upper computer through the PIO module or the DMA module. According to the method and the device, the FC protocol is adopted for optical communication, the FC-AE-1553 protocol is realized through the FPGA chip, the 1553 protocol is mapped on the upper layer of the FC protocol, the processing speed is improved, the delay of equipment communication on the bus is predictable, and the processing load of an upper computer can be reduced.

Description

Optical fiber communication bus device, equipment and system

Technical Field

The present disclosure relates to the field of optical fiber communication technologies, and in particular, to an optical fiber communication bus device, apparatus, and system.

Background

Terminals in the avionics system communicate by adopting MIL-STD-1553B bus standard, but the real-time performance, bandwidth and anti-interference capability of the terminals are difficult to meet the requirements of the avionics system. The Fiber Channel (FC) protocol is increasingly applied to avionic systems with the advantages of high bandwidth, low delay, strong fault tolerance, adaptability to severe electromagnetic environments such as aerospace and the like. The FC-AE labeling organization establishes the FC-AE-1553 standard for the fiber channel standard to be applied to the avionics field. The standard is to map MIL-STD-1553B bus protocol at the FC-4 layer, and the original communication mode of the MIL-STD-1553B bus protocol is maintained, and meanwhile, the FC-AE-1553 network has the advantage of a fiber channel.

In the related art, an upper computer (also called a host) CPU performs MIL-STD-1553B bus protocol mapping on an FC-4 layer, so that the upper computer CPU has a larger load.

Disclosure of Invention

The present disclosure provides an optical fiber communication bus apparatus, device and system to at least reduce the load of an upper computer.

According to an aspect of the present disclosure, there is provided a fiber optic communication bus device, including: an optoelectronic transceiver module; double data rate synchronous dynamic random access memory (DDR memory); and a Field programmable gate array (Field-Programmable Gate Array, abbreviated as FPGA) chip comprising: a GTX transceiver (Gigabyte Transceiver) coupled to the optoelectronic transceiver module; an FC-AE-1553IP core configured to implement the FC-AE-1553 protocol; the cache module is coupled with the FC-AE-1553IP core and the DDR memory and is configured to cache data between the 1553 protocol and a high-speed serial computer expansion bus standard (peripheral component interconnect express, abbreviated as PCIE) protocol; and a PCIE hard core controller coupled to the cache module, wherein the PCIE hard core controller comprises a programmable input/Output (PIO) module and a direct memory access (Direct Memory Access, DMA) module, and is configured to transmit data to an upper computer through the PIO module or the DMA module.

In some embodiments, the cache module includes: a receive first-in first-out (First In First Out, abbreviated as FIFO) module, the input of the receive FIFO module being coupled to the FC-AE-1553IP core; the DDR control module is coupled with the output end of the receiving FIFO module; and the input end of the transmission FIFO module is coupled with the DDR control module, and the output end of the transmission FIFO module is operatively coupled with the PIO module or the DMA module.

In some embodiments, the DDR memory includes: the first DDR memory and the second DDR memory are mutually independent in reading and writing; the DDR control module is configured to perform data caching between the 1553 protocol and the PCIE protocol in a ping-pong storage mode; wherein, the table tennis storage mode is: writing data to the first DDR memory and reading data from the second DDR memory during a first period; during a second period, data is written to the second DDR memory and data is read from the first DDR memory.

In some embodiments, the PCIE hard core controller is configured to map a low speed interface to the upper computer through the PIO module and to map a high speed interface to the DMA module, wherein the low speed interface includes register reads and writes and the high speed interface includes image data transfers.

In some embodiments, the FPGA chip further comprises: the firmware on-line solidifying module is configured to receive the firmware program sent by the upper computer through the PIO module and write the firmware program into the flash memory of the FPGA chip.

In some embodiments, the fiber optic communication bus device further comprises: PCIE bridging chip; wherein, the FPGA chip includes: the first FPGA chip and the second FPGA chip are coupled with the PCIE bridging chip, and the first FPGA chip and the second FPGA chip are respectively used as different PCIE bus endpoints.

In some embodiments, an optoelectronic transceiver module includes: and the plurality of photoelectric transceivers, wherein part of the photoelectric transceivers are coupled with the first FPGA chip, and the rest of the photoelectric transceivers are coupled with the second FPGA chip.

In some embodiments, a first FPGA chip is coupled to the PXIe board through a first joint test action organization (Joint Test Action Group, simply JTAG) interface, and a second FPGA chip is coupled to the PXIe board through a second JTAG interface, the first and second JTAG interfaces being independent of each other.

According to another aspect of the present disclosure, there is provided a fiber optic communications device including the fiber optic communications bus apparatus of any of the embodiments of the present disclosure.

According to yet another aspect of the present disclosure, there is provided a fiber optic communication system including the fiber optic communication device of any embodiment of the present disclosure.

According to one or more technical schemes provided by the embodiment of the disclosure, the bottom layer adopts the FC protocol for optical communication, the FC-AE-1553 protocol is realized through the FPGA chip, the 1553 protocol is mapped on the upper layer of the FC protocol, the processing speed is improved, the delay of equipment communication on the bus is predictable, and the processing load of an upper computer is reduced.

Drawings

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments, with reference to the following drawings, wherein:

FIG. 1 illustrates a schematic diagram of a fiber optic communication bus device according to an exemplary embodiment of the present disclosure;

fig. 2 illustrates another structural schematic diagram of a fiber optic communication bus device according to an exemplary embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below. It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units.

It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be understood as "one or more" unless the context clearly indicates otherwise.

The names of messages or information interacted between the various devices in the embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

The FC-AE-1553 protocol is a mapping of traditional MIL-STD-1553B bus protocol at the FC-4 layer of a fiber channel to enable deterministic communication in command/response mode in real-time applications (e.g., aviation). Mapping of the traditional bus protocol is realized in the FC-4 layer, so that the design, software and hardware of the existing MIL-STD-1553B network are smoothly updated. The FC-AE-1553 network has the basic characteristics of an MIL-STD-1553B network and good network performance of a fiber channel.

The main topology modes of the FC-AE-1553 protocol are point-to-point, arbitration ring and 3 switching modes, and main equipment of the network comprises a Network Controller (NC), a network Terminal Node (NT), an FC switch and the like.

The embodiment of the disclosure provides an optical fiber communication bus device, which can be applied to the field of aerospace or industry, and the optical fiber communication bus device realizes an FC-AE-1553 protocol through an FPGA so as to at least reduce the load of an upper computer and improve the communication speed. Aspects of the present disclosure are described below with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a fiber optic communication bus device according to an exemplary embodiment of the present disclosure, and as shown in fig. 1, a fiber optic communication bus device 100 includes: an optoelectronic transceiver module 110, a DDR memory 120, and an FPGA chip 130.

The optoelectronic transceiver module 110 is configured to receive the optical signal, convert the optical signal into a corresponding electrical signal, and provide the electrical signal to the FPGA chip 130 for processing. The optoelectronic transceiver module 110 is further configured to receive an electrical signal, convert the electrical signal into a corresponding optical signal, and transmit the optical signal through an optical fiber.

In some embodiments, the optoelectronic transceiver module 110 may employ an optoelectronic transceiver (also referred to as an optoelectronic transducer, a fiber optic transceiver). As one embodiment, each optoelectronic transceiver may provide a multi-channel (e.g., 12-channel) optoelectronic conversion channel, and each optoelectronic transceiver may implement a point-to-point optical communication physical channel (e.g., 6-receive 6-transmit). Various types of fiber optic connectors may be employed with optoelectronic transceivers. In some embodiments, connectors that integrate multiple fiber outputs are employed. As one example, a standard 24-core MT fiber optic contact may be sampled, with receptacles being MPO (Multi-fiber Push On) connectors, each providing 12-way fiber channels, corresponding to 6 terminals.

The FPGA chip 130 is configured to implement the FC-AE-1553 protocol, and communicate with the host computer through a PCIE interface. As shown in fig. 1, the FPGA chip 130 includes: a GTX transceiver 131 coupled to the optoelectronic transceiver module 110; the FC-AE-1553IP core 132 configured to implement the FC-AE-1553 protocol; the buffer module 133 is coupled with the FC-AE-1553IP core 132 and the DDR memory 120, and is configured to buffer data between the 1553 protocol and the PCIE protocol; and a PCIE hard core controller 134, coupled to the buffer module 133, where the PCIE hard core controller 134 implements PCIE protocol, which is an interface for performing data exchange between the optical fiber communication bus device 100 and the host computer. PCIE hard core controller 134 includes PIO module 1341 and DMA module 1342 configured to transfer data to the host via PIO module 1341 or DMA module 1342.

The FC protocol adopts a layered protocol model, namely FC-0, FC-1, FC-2, FC-3 and FC-4 layers, wherein the FC-0 layer defines the physical characteristics of interfaces and media, the FC-1 layer defines the coding and transmission protocol, the FC-2 layer defines the rules of data transmission, the FC-3 layer provides the required general service for some advanced characteristics, and the FC-4 layer defines the mapping from the upper layer protocol to the FC protocol. The FC-AE-1553IP core 132 is configured to map the FC protocol to the 1553 protocol.

In some embodiments, as shown in fig. 1, the caching module 133 may include: a receive FIFO module 1331, the input of the receive FIFO module 1331 being coupled to the FC-AE-1553IP core 132; DDR control module 1332 coupled to the output of receive FIFO module 1331; a transmit FIFO module 1333, an input of the transmit FIFO module 1333 coupled to the DDR control module 1332, and an output of the transmit FIFO module 1333 operatively coupled to the PIO module 1341 or the DMA module 1342. The receive FIFO module 1331 and the transmit FIFO module 1333 can implement the problems of different types of data interfaces, different data bit widths, and different clock domains between the front and rear modules.

In some embodiments, PCIE hard core controller 134 is configured to map low speed interfaces, including but not limited to register reads and writes, to an upper computer through PIO module 1341 and high speed interfaces, including but not limited to image data transfers, to DMA module 132. As an embodiment, PCIE DMA functions may be implemented based on a reusable integration framework (Reusable Integration Framework for FPGA Accelerators, abbreviated as RIFFA) of xnlx XDMA or FPGA accelerator.

In some embodiments, as shown in fig. 1, FPGA chip 130 further includes: the firmware online solidification module 135 is configured to receive the firmware program sent by the upper computer through the PIO module 1341, and write the firmware program into the Flash memory (Flash) of the FPGA chip 130. As an implementation manner, the memory is a peripheral device of the FPGA chip.

In some embodiments, as shown in FIG. 1, DDR memory 120 comprises: the first DDR memory 120A and the second DDR memory 20B, the first DDR memory 120A and the second DDR memory 120B are independent from each other in reading and writing; DDR control module 1332 configured to perform data buffering between 1553 protocols and PCIE protocols in a ping-pong storage manner; wherein, the table tennis storage mode is: during a first period, data is written to the first DDR memory 120A and data is read from the second DDR memory 120B; during the second period, data is written to the second DDR memory 120B and data is read from the first DDR memory 120A. Therefore, the PCIE bus utilization rate of the upper computer during reading and writing is improved.

In some embodiments, FPGA chip 130 is coupled to a PXIe board card through a JTAG interface.

Fig. 2 illustrates another structural schematic diagram of a fiber optic communication bus device according to an exemplary embodiment of the present disclosure, as illustrated in fig. 2, a fiber optic communication bus device 200 includes: the optoelectronic transceiver module 210, a first FPGA chip 220A and a second FPGA chip 220B. The first FPGA chip 220A and the second FPGA chip 220B are coupled to the PCIE bridge chip 230, and the first FPGA chip 220A and the second FPGA chip 220B are respectively used as different PCIE bus endpoints (End points). The first FPGA chip 220A and the second FPGA chip 220B are similar to the FPGA chip 130 shown in fig. 1, and are not described herein.

In some embodiments, the first FPGA chip 220A is coupled to the PXIe board through a first JTAG interface and the second FPGA chip 220B is coupled to the PXIe board through a second JTAG interface, the first and second JTAG interfaces being independent of each other. Thereby, the coupling property is reduced.

As shown in fig. 2, the optoelectronic transceiver module 210 includes: optoelectronic transceivers 211A and 211B, coupled to first FPGA chip 220A; and optoelectronic transceivers 212A and 212B are coupled to a second FPGA chip 220B. It should be appreciated that the first FPGA chip 220A and the second FPGA chip 220B may each be coupled to one or more optoelectronic transceivers, and the embodiments of the present disclosure are not limited in this regard and are illustrated in fig. 2 by way of example only.

As shown in fig. 2, the fiber-optic communication bus device 200 further includes: DDR memories 240A and 240B, coupled to first FPGA chip 220A; DDR memories 240C and 240D are coupled to the second FPGA chip 220B.

An example of a fiber optic communications bus device as shown in fig. 2 is described below.

In this example, a fiber optic communications bus board is provided. The optical fiber communication bus board card adopts a standard PXIe card structure, and has the size of 3U 4HP multiplied by 160 mm. The backboard interface adopts XJ3 and XJ4 connectors in PXIe specification, and signals are PCIEX 4. Photoelectric receiving is realized on a board card, and a connector integrating multipath optical fiber output is adopted to the outside. Two standard 24-core MT fiber contacts were used, with the receptacles MPO, each providing 12 fiber channels, corresponding to 6 terminals.

The on-board core processing chip of the optical fiber communication bus board card is two FPGA chips, each FPGA chip can provide 32 paths of GTX transceivers, and the bandwidth requirement of data transmission between the upper computer and the optical fiber communication bus board card is supported. The board card adopts PCIE bridging chips to respectively take two FPGA chips as different PCIE bus endpoints, each FPGA chip respectively supports PCIE Gen1 multiplied by 2, and the theoretical maximum uplink/downlink bandwidth is 500MB/s; each FPGA chip is respectively provided with two DDR memories for data caching, so that bus communication efficiency is improved.

One or more channels (for example, 4 channels) GTX transceivers are reserved between two FPGA chips and used for data interaction between the FPGA chips, the bandwidth of the GTX transceivers can reach 1GB/s, and the requirements of possible subsequent data interaction between the chips can be fully met; the JTAG interface adopts a non-daisy chain mode, and each FPGA adopts an independent JTAG interface, so that the coupling is reduced, and the debugging efficiency is improved.

The power supply of the optical fiber communication bus board card is a +12V power supply provided by XJ4 in the PXIe standard, and the maximum power supply current can reach 6A, so that the power consumption requirement of the optical fiber communication bus board card is met. The power network can adopt a switching power supply chip produced by the Linear company, and has high overall switching efficiency and low output ripple.

The optical fiber communication bus board card adopts a double FPGA chip design, the on-chip resource occupation exceeds 80%, and the overall power consumption of the board card is more than 30W under the condition of extreme full load, so that a cooling fin is arranged at least in the FPGA chip area to assist in case air cooling.

The FPGA chip has PCIE hard core controller, comprises the functions of a physical layer, a transmission layer, a transaction layer and the like, and provides AXI (Advanced eXtensible Interface) interfaces for a user application layer. The quick development of the user is facilitated. The logic design is developed based on PCIE DMA core XDMA provided by xilox, low-speed interfaces such as register read-write are mapped to an upper computer through a PIO interface, a high-speed interface of an optical fiber terminal suitable for image data transmission is mapped to a DMA interface, CPU scheduling pressure is relieved, and overall system performance is provided.

In the logic design of the optical fiber communication bus board card, each optical fiber bus terminal node adopts an address to be mapped to a space of a base address register (Base Address Register, BAR for short), and the functional logic comprises a local FPGA register control functional module, other IP internal registers and RAM read-write control logic.

The upper computer can directly read the operation logic local register and the functional module internal register through the BAR0 space, so that the operation logic local register is convenient to view and configure. The image transmission interface of the optical fiber bus terminal carries out data transmission in a DMA mode, the DMA mode defines relevant parameters of distributed DMA transmission through descriptors, and the content is realized in a driving and library function.

The FPGA local logic gathers the running state information of the board card, including but not limited to the information of DMA running state, photoelectric converter running state, fiber communication bus board card FPGA code version number, functional module reset state, etc., so that the user can conveniently review the running state of the board card.

After the FPGA finishes the program loading, the flash memory content of the FPGA chip can be rewritten through the firmware on-line curing module, and the program is downloaded in a PCIE bus PIO mode, so that the firmware program can be updated rapidly.

And the DMA control module writes the data into the memory of the upper computer through the PCIE interface in a data Master writing mode. The upper computer finishes the downloading of the control information in the one-time DMA data moving process in a scanner-gateway mode, and the transmission direction is from the upper computer to the board card end. The control information data structure mode is in MDL form. After one time of DMA starting, the DMA control module writes the information of the source, the destination, the length and the like in the decentralized aggregation control information into the X86 memory controller in a PCI bus domain mode, and the memory control completes the inter-domain conversion. And the DMA in a scattered aggregation mode can finish data transmission in a non-physical address continuous mode according to the control information and provide interruption to an upper layer.

The optical fiber communication bus device of the embodiment of the disclosure can be applied to optical fiber communication equipment, such as a Network Controller (NC), a Network Terminal (NT), a protocol bridge and the like in an FC-AE-1553 network.

The optical fiber communication device of the embodiment of the disclosure can be applied to an optical fiber communication system, such as an FC-AE-1553 network.

The above description is of the preferred embodiments of the present disclosure, but is not intended to limit the present disclosure, and any modifications, equivalents, and simple improvements made within the spirit of the present disclosure should be included in the scope of the present disclosure.

Claims (7)

1. A fiber optic communications bus apparatus, comprising:

an optoelectronic transceiver module comprising: a plurality of optoelectronic transceivers;

DDR memory;

PCIE bridging chip; and

a first FPGA chip and a second FPGA chip;

the first FPGA chip and the second FPGA chip are coupled with the PCIE bridging chip, and the first FPGA chip and the second FPGA chip are respectively used as different PCIE bus endpoints;

a part of photoelectric transceivers in the plurality of photoelectric transceivers are coupled with the first FPGA chip, and the rest of photoelectric transceivers in the plurality of photoelectric transceivers are coupled with the second FPGA chip;

the first FPGA chip is coupled to the PXIe board through a first JTAG interface, the second FPGA chip is coupled to the PXIe board through a second JTAG interface, and the first JTAG interface and the second JTAG interface are mutually independent;

the radiating fin is arranged in the area where the first FPGA chip and the second FPGA chip are located and is used for assisting air cooling of the chassis;

wherein the first FPGA chip and the second FPGA chip comprise:

a GTX transceiver coupled to the optoelectronic transceiver module;

an FC-AE-1553IP core configured to implement the FC-AE-1553 protocol;

the cache module is coupled with the FC-AE-1553IP core and the DDR memory and is configured to cache data between a 1553 protocol and a PCIE protocol; and

the PCIE hard core controller is coupled with the cache module, comprises a PIO module and a DMA module and is configured to transmit data to an upper computer through the PIO module or the DMA module;

and data transmission is performed between the first FPGA chip and the second FPGA chip through one or more GTX transceivers.

2. The fiber optic communication bus device of claim 1, wherein the cache module comprises:

the input end of the receiving FIFO module is coupled with the FC-AE-1553IP core;

the DDR control module is coupled with the output end of the receiving FIFO module;

and the input end of the transmission FIFO module is coupled with the DDR control module, and the output end of the transmission FIFO module is operatively coupled with the PIO module or the DMA module.

3. A fiber optic communications bus device according to claim 2, wherein,

the DDR memory includes: the first DDR memory and the second DDR memory are mutually independent in reading and writing;

the DDR control module is configured to perform data caching between a 1553 protocol and a PCIE protocol in a ping-pong storage mode;

wherein, the table tennis storage mode is: during a first period, writing data to the first DDR memory and reading data from the second DDR memory; during a second period, data is written to the second DDR memory and data is read from the first DDR memory.

4. The fiber optic communication bus device of claim 1, wherein the PCIE hard core controller is configured to map a low speed interface to the host computer through the PIO module and a high speed interface to the DMA module, wherein the low speed interface comprises register read-write, and the high speed interface comprises image data transfer.

5. The fiber optic communication bus device of claim 1, wherein the first FPGA chip and the second FPGA chip further comprise:

and the firmware online solidification module is configured to receive the firmware program sent by the upper computer through the PIO module and write the firmware program into the flash memory of the corresponding FPGA chip.

6. A fibre optic communications device comprising a fibre optic communications bus arrangement according to any one of claims 1 to 5.

7. A fiber optic communication system comprising the fiber optic communication device of claim 6.