CN115757222B - Data transmission method and device based on PL and PS - Google Patents

Abstract

The invention relates to a data transmission method and a device based on PL and PS, wherein an AXI DMA IP core is adopted in the PL-PS direction, an AXI CDMA IP core is adopted in the PS-PL direction, the device is suitable for video transmission, satellite communication, factory automation and other scenes, the application is wide, a double-ring buffer mechanism is adopted in the data transmission between PL and PS, the buffer utilization rate is effectively improved, the block-wise moving is adopted in the data transmission between PL and PS, the size of a data block is changed in real time according to the sizes of different data packets, compared with the traditional method of triggering DMA according to the fixed sizes, the data transmission efficiency is effectively improved, and the use requirement of a large number of high-speed communication scenes can be met.

Description

Data transmission method and device based on PL and PS

Technical Field

The invention relates to the technical field of communication, in particular to a data transmission method and device based on PL and PS.

Background

In recent years, with the development of satellite communication technology, satellite communication systems bring great convenience to the work and life of people, and are increasingly favored by people, and meanwhile, satellite communication is developed from narrowband low-speed data service to broadband multimedia service, and the throughput of communication satellites is exploded and increased. Currently, the dominant satellite operators abroad are not targeting higher throughput to meet the increasing satellite communication bandwidth demands.

When data transmission is performed, the traditional method of using an FPGA to perform data acquisition and preprocessing, then sending the data to a PC through a PCIE interface and finally processing the data by the PC is rare, and the main stream is an FPGA+ARM architecture. The embedded system generally adopts a mode of ARM plus DSP or ARM plus FPGA, wherein ARM mainly completes a control function, and the DSP or the FPGA mainly completes a data processing function.

The adoption of fpga+arm architecture is currently divided into two types: one is that the FPGA and the ARM are two independent chips, and the two chips carry out data interaction through GPMC buses and the like; the other is a Zynq chip mode, the chip integrates a processor with two architectures of FPGA and ARM, and an AXI bus is used for interaction. At present, no related design scheme capable of considering both cost and transmission performance exists.

Disclosure of Invention

In view of this, the present invention provides a data transmission method and apparatus based on PL and PS, which can achieve both low cost and high performance transmission.

In a first aspect, an embodiment of the present invention proposes a data transmission method based on PL and PS, in which AXI DMA IP core transmission is adopted in a PL-to-PS direction, AXI CDMA IP core transmission is adopted in a PS-to-PL direction, and a dual ring buffer mechanism is adopted in both directions, and block-wise shifting is adopted in data transmission.

Further, during PL-to-PS data transmission, the FIFO of PL and the forward buffer of DDR are both ring mechanisms.

Further, during the transmission of the PL to PS data, the PL generates a 1ms interrupt, and the PS reads the data from the forward buffer area and processes the data after receiving the interrupt.

Further, during data transmission from PS to PL, the return buffer areas of BRAM and DDR of PL are both ring mechanisms.

Further, when PS transmits data to PL, PL generates 10ms interrupt, PS inquires whether the data to be transmitted exists in the return buffer area after receiving the interrupt, if yes, AXI CDMA is triggered to carry out block moving.

Further, during PS-to-PL data transmission, AXI CDMA performs data moving in blocks according to the sizes of different data packets in real time.

Further, PL to PS direction data transmission includes:

s110, PS applies a continuous space for a forward buffer area in DDR, wherein the forward buffer area is an integer multiple of 512 bytes;

s120, the PS applies for another continuous space in the DDR for a return buffer area, wherein the return buffer area is an integer multiple of 128 bytes;

s130, the PS transmits the initial physical address and the size of the forward buffer area to PL;

s140, PL configures AXI DMA according to the initial physical address of the forward buffer, transmits data in the FIFO to DDR, then generates 1ms interrupt to PS, records the number of 512 bytes of data which has been moved to the forward buffer and puts the number value into a forward packet statistics register;

s150, after receiving the interrupt, PS queries the forward packet statistics register, and when the packet number is greater than 0, 512 bytes of data are obtained from DDR and processed.

Further, the PS to PL direction data transmission includes:

s210, the data generation module uplink makes a packet, copies the data to a return buffer area;

s220, calculating the size of data to be transmitted in the return buffer area;

s230, calculating the address of the first read pointer and the size A;

s240, calculating a second time read pointer address and a size B;

s250, reading the size of a BRAM residual space;

s260, when the BRAM has the residual space, CDMA moving of the data block is carried out;

the size of the data to be transmitted in the return buffer is the difference between the read-write pointers of the return buffer, and the residual space of the BRAM is the difference between the read-write pointers of the BRAM.

Further, step S210 includes:

s211, initializing a read-write pointer;

s212, calculating the generated data size to be written into the return buffer area, comparing the data size with the residual space of the return buffer area, and entering step S213 if the residual space is greater than or equal to the length of the data to be written;

s213, calculating the size alpha of the first writable data, wherein the calculation method is to subtract a write pointer from the end address of the return buffer;

s214, comparing the size of the data to be written with alpha, if the size is smaller than or equal to the size of the data to be written, entering step S215, and if the size is larger than the size of the data to be written, entering step S216;

s215, performing primary data copying to the return buffer area;

s216, copying the data to be written with the same size as alpha to the return buffer area, calculating the size of the data to be written for the second time and copying the data from the initial address of the return buffer area to the return buffer area;

s217, updating the write pointer.

In a second aspect, an embodiment of the present invention proposes an apparatus for performing the PL and PS based data transmission method according to any one of the first aspects, the hardware of the apparatus comprising a power supply unit, a data input unit, a data output unit, a serial port unit, and a data storage unit;

the software of the device comprises PS embedded software, PS and PL communication interface software and PL logic software;

the device is based on a Linux system and comprises a u-boot, a kernel and a file system;

the PS and PL communication interfaces comprise a configuration interface, a data interface and an interrupt event interface, wherein the configuration interface is realized through an AXI-GP and is used for realizing the basic configuration function from PS to PL, the data interface is realized through an AXI-HP and is used for service data transmission, and the interrupt event interface comprises a PL interrupt connected to a GIC interrupt controller of PS and is used for 1ms and 10ms interrupt events.

The transmission between the PL and PS of the method of the embodiment of the invention is based on a ring buffer mechanism, so that the consumption of resources is less, the use efficiency of the memory is high, the cost is reduced, the data transmission performance can be effectively improved based on block-by-block movement and DMA and CDMA transmission, the downlink speed can be more than 700Mb/s, the uplink speed can be more than 160Mb/s, and the use requirement of each high-speed communication scene is met.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a PL and PS based data transmission apparatus according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a downlink system of a PL and PS based data transmission apparatus according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an uplink system of a PL and PS based data transmission apparatus according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a downlink data processing flow of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a downlink data processing principle of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an uplink data processing flow of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 7 is a schematic diagram of an uplink data processing principle of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 8 is a schematic flow chart of uplink packet making, data copying and data returning to a buffer zone of a data transmission method based on PL and PS according to an embodiment of the present invention;

fig. 9 is a schematic diagram of an uplink packet making and data copying to a backhaul buffer according to a data transmission method based on PL and PS in an embodiment of the present invention.

Detailed Description

The description of the embodiments of this specification should be taken in conjunction with the accompanying drawings, which are a complete description of the embodiments. In the drawings, the shape or thickness of the embodiments may be enlarged and indicated simply or conveniently. Furthermore, portions of the structures in the drawings will be described in terms of separate descriptions, and it should be noted that elements not shown or described in the drawings are in a form known to those of ordinary skill in the art.

Any references to directions and orientations in the description of the embodiments herein are for convenience only and should not be construed as limiting the scope of the invention in any way. The following description of the preferred embodiments will refer to combinations of features, which may be present alone or in combination, and the invention is not particularly limited to the preferred embodiments. The scope of the invention is defined by the claims.

As shown in fig. 1 to 3, the downlink system of the PL and PS based data transmission apparatus according to the embodiment of the present invention includes a data generating module, a FIFO, a DDR forward ring buffer, a DMA control module, and a PS data processing unit. The data generation module passes the data to the FIFO of the PL, which passes the data to the DDR forward circular buffer via AXI DMA, after which the PS performs the corresponding data processing. The uplink system comprises a data generation module, a DDR return ring buffer, a BRAM, an AXI CDMA module and a PL data processing unit. The data generating module transmits the data to the DDR back transmission ring buffer, then the PS configures an uplink CDMA module for controlling the PL through an AXI_GP interface, moves the uplink data packet to the internal BRAM of the PL, and then the PL carries out corresponding data processing.

In the present embodiment, hardware of the PL and PS based data transmission device (hereinafter referred to as "device") includes a power supply unit, a data input unit, a data output unit, a serial port unit, and a data storage unit. The software of the device includes PS embedded software, PS and PL communication interface software, and PL logic software. The device is based on a Linux system and comprises a u-boot, a kernel and a file system. The PS and PL communication interfaces comprise a configuration interface, a data interface and an interrupt event interface, wherein the configuration interface is realized through an AXI-GP and is used for realizing the basic configuration function from PS to PL, the data interface is realized through an AXI-HP and is used for transmitting service data, and the interrupt event interface comprises a PL interrupt connected to a GIC interrupt controller of PS and is used for 1ms and 10ms interrupt events. An interrupt trigger interface and registers characterizing interrupt event types are designed from PL to PS. After the interrupt is generated, the PS reads the interrupt status register of the PL through the AXI-GP interface. The lowest bit is an interrupt event flag, and the interrupt period is 1ms. The interrupt is used to trigger the PS to perform data processing. The configuration monitoring interface between PS and PL is realized through AXI-GP interface, and the configuration management register is related to FPGA design.

The forward data transmission of the device in this embodiment adopts AXI-HP DMA transmission, the return data transmission adopts AXI-HP CDMA transmission, the FIFO, the forward ring buffer, the return ring buffer and BRAM in the data transmission are all ring spaces, and the CDMA uses data blocks for data movement in PS uplink data processing, and the storage space is ring, so that 7 cases are divided, and 1-3 times of data block movement are required.

The embodiment of the invention also provides a data transmission method of PL and PS based on the device, which adopts a Zynq-XC7Z020 chip, and the SOC comprises two parts of PS (ARM) and PL (FPGA). The method of the embodiment adopts a double-ring buffer mechanism for data transmission between PL and PS, and comprises the following steps: when PL transmits data to PS, the FIFO of PL and the forward buffer of DDR are both ring mechanisms; when PS transmits data to PL, the return buffer areas of BRAM and DDR of PL are both ring mechanisms. Meanwhile, when PL transmits data to PS, PL generates 1ms interrupt, PS reads data from the forward buffer area and processes the data after receiving the interrupt; when PS transmits data to PL, PL generates 10ms interrupt, PS inquires whether the data to be transmitted exists in the return buffer area after receiving the interrupt, if yes, AXI CDMA is triggered to carry out block moving, and the block moving is concretely that AXI CDMA can carry out data moving according to the sizes of different data packets in real time.

As shown in fig. 4 and 5, in the method of the present embodiment, PS downlink data transmission (PL to PS direction data transmission) includes:

s100, loading the CDMA drive.

S110, PS applies a continuous space for a forward buffer area in DDR, wherein the forward buffer area is an integer multiple of 512 bytes;

since the data between PL and PS takes 512 bytes as a unit, this space is convenient for ring operation, and the first 4 bytes of 512 bytes are used for operations such as continuity check.

S120, the PS applies for another continuous space in the DDR for a return buffer area, wherein the return buffer area is an integer multiple of 128 bytes;

because 128 bytes are used as units of data between PL and PS, the space is convenient for ring operation, and the BRAM is 64K and is an integer multiple of 128 bytes; the PS applies for interrupts, which are used to receive 1ms/10ms interrupts generated by the PL.

S130, the PS transmits the initial physical address and the size of the forward buffer area to the PL;

preferably to PL via AXI-GP interface.

S140, PL configures AXI DMA according to the initial physical address of the forward buffer, transmits data in the FIFO to DDR, then generates 1ms interrupt to PS, records the number of 512 bytes of data which has been moved to the forward buffer and puts the number value into the forward packet statistics register;

when the write address is equal to the tail address of the forward buffer area, a round-trip operation is required (the write address is updated to be the initial address of the forward buffer area), so that the purpose of ring shape is achieved;

preferably, the FIFO is placed into the DDR over the AXI-HP interface.

S150, after the PS receives the interrupt, inquiring a forward packet statistic register, and when the packet number is more than 0, acquiring 512 bytes of data from the DDR and processing the 512 bytes of data;

because of the annular space, an interpretation is made as to whether the read address is a tail address, after which the read pointer is updated.

As shown in fig. 6 and 7, in the method of the present embodiment, PS uplink data transmission (PS to PL data transmission) includes:

s210, the data generation module uplink makes a packet, copies the data to a return buffer area;

s220, calculating the size of data to be transmitted in the return buffer area;

s230, calculating the address of the first read pointer and the size A;

s240, calculating a second time read pointer address and a size B;

s250, reading the size of a BRAM residual space;

s260, when the BRAM has the residual space, CDMA moving of the data block is carried out;

the size of the data to be transmitted in the return buffer is the difference between the read-write pointers of the return buffer, and the residual space of the BRAM is the difference between the read-write pointers of the BRAM. Since the backhaul buffer and BRAM are both annular spaces, a total of 7 cases of data block moves are involved: if the write pointer is larger than the read pointer, A is the difference between the read pointer and the write pointer of the return buffer, and B is equal to 0; if the write pointer is smaller than the read pointer, at this time, A is the size of the tail address of the return buffer minus the read pointer, and B is the size of the write pointer minus the head address of the return buffer; the size of A1 is equal to the size b of the first written BRAM, and A2 is equal to A minus A1; a2' is equal to the BRAM residual space minus the first written BRAM size b; b1 is equal to the first write BRAM size B minus A; b2 is equal to the size of the data to be transmitted in the return buffer area minus A and B1; b' is equal to the BRAM residual space minus a. B2' is BRAM remaining space minus A and B1.

As shown in fig. 8 and 9, in the present embodiment, step S210 (i.e. the flow of uplink packet creation and data copying to the backhaul buffer) includes:

s211, initializing a read-write pointer;

s212, calculating the size of the generated data to be written into the return buffer area, comparing the size with the residual space (the difference between the read pointer and the write pointer) of the return buffer area, and entering step S213 if the residual space is greater than or equal to the length of the data to be written;

s213, calculating the size alpha of the first writable data, wherein the calculation method is to subtract a write pointer from the end address of the return buffer;

s214, comparing the size of the data to be written with alpha, if the size is smaller than or equal to the size of the data to be written, entering step S215, and if the size is larger than the size of the data to be written, entering step S216;

s215, performing primary data copying to a return buffer area;

s216, copying the data to be written with the same size as alpha to the return buffer area, calculating the size of the data to be written for the second time and copying the data from the initial address of the return buffer area to the return buffer area;

s217, updating the write pointer.

In summary, the transmission between the PL and PS methods in the embodiment of the invention is based on a ring buffer mechanism, so that the consumption of resources is low, the use efficiency of the memory is high, the cost is reduced, the data transmission performance can be effectively improved based on block-by-block movement and DMA and CDMA transmission, the downlink rate can be more than 700Mb/s, the uplink rate can be more than 160Mb/s, and the use requirement of each large high-rate communication scene is met.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.

Claims (8)

1. A data transmission method based on PL and PS is characterized in that AXIDMAIP core transmission is adopted in the PL-PS direction, AXICDMAIP core transmission is adopted in the PS-PL direction, a double-ring buffer mechanism is adopted in both directions, and block-by-block shifting is adopted in data transmission;

PL to PS direction data transmission includes:

s110, PS applies a continuous space for a forward buffer area in DDR, wherein the forward buffer area is an integer multiple of 512 bytes;

s120, the PS applies for another continuous space in the DDR for a return buffer area, wherein the return buffer area is an integer multiple of 128 bytes;

s130, the PS transmits the initial physical address and the size of the forward buffer area to PL;

s140, PL configures AXIDMA according to the initial physical address of the forward buffer, transmits data in the FIFO to DDR, then generates 1ms interrupt to PS, records the number of 512 bytes of data which has been moved to the forward buffer and puts the number value into a forward packet statistics register;

s150, after receiving the interrupt, PS queries the forward packet statistics register, and when the packet number is greater than 0, 512 bytes of data are obtained from DDR and processed;

PS to PL direction data transmission includes:

s210, the data generation module uplink makes a packet, copies the data to a return buffer area;

s220, calculating the size of data to be transmitted in the return buffer area;

s230, calculating the address of the first read pointer and the size A;

s240, calculating a second time read pointer address and a size B;

s250, reading the size of a BRAM residual space;

s260, when the BRAM has the residual space, CDMA moving of the data block is carried out;

the size of the data to be transmitted in the return buffer is the difference between the read-write pointers of the return buffer, and the residual space of the BRAM is the difference between the read-write pointers of the BRAM.

2. The PL and PS based data transmission method of claim 1 wherein the FIFO of PL and the forward buffer of DDR are both ring mechanisms when PL to PS direction data transmission.

3. The PL and PS based data transmission method of claim 2 wherein PL generates a 1ms interrupt when PL to PS direction data transmission, PS reads data from the forward buffer and processes after receiving the interrupt.

4. The PL and PS based data transmission method of claim 1 wherein, in the PS-to-PL data transmission, both the BRAM and DDR backhaul buffers of PL are ring mechanisms.

5. The method of claim 4, wherein the PL generates a 10ms interrupt when the PS transmits data in the PL direction, and the PS queries whether the backhaul buffer is to be transmitted or not after receiving the interrupt, and if yes, triggers the block moving by AXICDMA.

6. The PL and PS based data transmission method of claim 4 wherein the AXICDMA performs data moving in blocks according to sizes of real-time different data packets when PS to PL direction data transmission.

7. The PL and PS based data transmission method according to any one of claims 1 to 6, wherein step S210 comprises:

s211, initializing a read-write pointer;

s212, calculating the generated data size to be written into the return buffer area, comparing the data size with the residual space of the return buffer area, and entering step S213 if the residual space is greater than or equal to the length of the data to be written;

s213, calculating the size alpha of the first writable data, wherein the calculation method is to subtract a write pointer from the end address of the return buffer;

s214, comparing the size of the data to be written with alpha, if the size is smaller than or equal to the size of the data to be written, entering step S215, and if the size is larger than the size of the data to be written, entering step S216;

s215, performing primary data copying to the return buffer area;

s216, copying the data to be written with the same size as alpha to the return buffer area, calculating the size of the data to be written for the second time and copying the data from the initial address of the return buffer area to the return buffer area;

s217, updating the write pointer.

8. An apparatus for performing the PL and PS based data transmission method according to any one of claims 1 to 7, wherein the hardware of the apparatus comprises a power supply unit, a data input unit, a data output unit, a serial port unit, and a data storage unit;

the software of the device comprises PS embedded software, PS and PL communication interface software and PL logic software;

the device is based on a Linux system and comprises a u-boot, a kernel and a file system;

the PS and PL communication interfaces comprise a configuration interface, a data interface and an interrupt event interface, wherein the configuration interface is realized through an AXI-GP and is used for realizing the basic configuration function from PS to PL, the data interface is realized through an AXI-HP and is used for service data transmission, and the interrupt event interface comprises a PL interrupt connected to a GIC interrupt controller of PS and is used for 1ms and 10ms interrupt events.

Images