CN115687200B

CN115687200B - PCIe data transmission method and system applied to EPA based on FPGA

Info

Publication number: CN115687200B
Application number: CN202211713522.7A
Authority: CN
Inventors: 谢伟军; 王天林; 金伟江; 劳立辉; 童庆
Original assignee: ZHEJIANG SUPCON RESEARCH CO LTD
Current assignee: ZHEJIANG SUPCON RESEARCH CO LTD
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-06-13
Anticipated expiration: 2042-12-30
Also published as: CN115687200A

Abstract

The invention discloses a PCIe data transmission method and system applied to EPA based on FPGA. Aiming at the problem that the transmission efficiency of the existing EPA PCIe is easily influenced by a hardware platform and an operating system of a processor, the method does not need the processor to intervene data transmission when the EPA works normally, and the FPGA directly accesses the memory of the processor system through PCIe, so that the transmission efficiency of the PCIe is greatly improved, the data processing capacity of the EPA is greatly improved, the application scene of the EPA is expanded, any hardware cost is not increased, the driving design of the processor PCIe is simplified, the load of the processor is reduced, and more other system transactions can be processed by the processor.

Description

PCIe data transmission method and system applied to EPA based on FPGA

Technical Field

The invention belongs to the technical field of high-speed interfaces, and particularly relates to a PCIe data transmission method, system, device and computer equipment applied to EPA based on an FPGA.

Background

PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, EPA (Ethernet for Plant Automation) is a brand-new open real-time Ethernet standard suitable for industrial field devices, a large number of mature IT technologies are applied to an industrial control system, and a brand-new standard is established for real-time work suitable for field devices by utilizing a deterministic communication scheduling strategy of efficient, stable and standard Ethernet and UDP/IP protocols. In conventional PCIe data communication methods based on EPA, for example, in PCIe communication methods between EPA and other processor architecture systems (e.g., CPU systems or SOC systems), handshaking is performed by using an Interrupt (conventional Interrupt Legacy Interrupt or MSI Interrupt) method, so that data communication is performed.

In the conventional PCIe data communication method based on interrupt, under the condition that the communication data volume between the EPA system and the processor is small, the real-time performance of processing can be ensured, but under the condition that the communication data volume between the EPA system and the processor is large, the communication mode of data transmission in an interrupt mode is easy to be interrupted too frequently due to the increase of the number of interrupts, so that the processor and the operating system are difficult to respond to the interrupt in time, the transmission efficiency of PCIe is greatly reduced, the communication delay is increased, and the processing capacity and the real-time performance of system data are affected.

In summary, the conventional PCIe data communication method applied to EPA has the following disadvantages: when large data volume is communicated, the processing capacity and real-time performance of the system are not met due to frequent interrupt response, namely, the traditional EPA PCIe communication mode is only suitable for a low-performance scene of low data volume processing, so that the great waste of processor capacity and PCIe bandwidth is caused, and the application of EPA in the field of large data volume transmission processing is limited.

Disclosure of Invention

The invention aims to provide a PCIe data transmission method and system based on FPGA applied to EPA, which can improve the PCIe transmission performance of an EPA system and greatly reduce the load of a processor participating in transmission on the premise of not increasing the hardware cost, so that the processor can concentrate on data processing or other system transactions.

In order to achieve the above technical effects, the present invention provides a PCIe data transmission system applied to EPA based on FPGA, including: the system comprises a processor system and a processor memory, wherein the processor memory comprises a receiving buffer and a sending buffer; the system comprises an FPGA-based EPA unit which is communicated with the processor system through a PCIe bus, wherein the EPA unit comprises a PCIe communication module, a data buffer management module and an interrupt management module, the PCIe communication module is used for communicating with the processor, the data buffer management module is used for initiating writing and reading operations of data in a memory of the processor, the interrupt management module is used for managing an initiation interval or direct shielding of MSI interrupt, the PCIe communication module comprises a PCIe buffer area, a PCIe data receiving and transmitting protocol stack and a DMA, the PCIe buffer area comprises an EPA sending buffer and an EPA receiving buffer, the data buffer management module is used for triggering and controlling the DMA to realize movement in different directions, and the interrupt management module can be configured by the processor in real time to realize shielding or opening interrupt.

In a preferred embodiment, the data cache management module includes: the processor sends a buffer management module, the processor receives the buffer management module and the DMA trigger module; the processor sends a buffer management module, two head and tail pointers are contained, when the processor initializes the EPA unit, the processor sends a buffer management module by driving the initial address and the upper and lower case of the buffer sent by the processor to the processor according to the system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty or full mark for sending the cache is generated in real time; the processor receives the buffer memory management module, two head and tail pointers are contained, when the processor initializes the EPA unit, the processor receives the buffer memory management module by driving the initial address and the upper and lower case of the buffer memory received by the processor according to the system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and the empty or full mark of the receiving cache is generated in real time; and the DMA triggering module triggers the DMA for sending the cache read data frame from the processor according to the non-empty mark of the processor sending cache management module, and triggers the DMA for receiving the cache write data frame to the processor according to the non-full mark of the processor receiving cache management module when the data needs to be written into the processor receiving cache.

In a preferred embodiment, the interrupt management module may set different interrupt trigger frequencies when configured by the processor, and when an interrupt is turned on, the MSI interrupt is sent periodically according to the processor receiving a non-empty indication from the cache management module.

Based on the same inventive concept, the invention also provides a PCIe data transmission method applied to EPA based on FPGA, which is applied to any one of the data transmission systems, comprising: when the transmission buffer of the processor system is not empty, reading the data length from the transmission buffer of the current processor system and transmitting the frame data, and updating the transmission completion flag of the frame data in the transmission buffer of the processor system after the frame data is transmitted by the EPA unit; reading the data length from the EPA unit's receive buffer and sending the frame data to the processor system's receive buffer in the case that there is data in the EPA unit's receive buffer; before the EPA unit is started to perform formal work, starting addresses and sizes of the receiving buffer and the sending buffer are written into the EPA unit based on the FPGA based on the pre-allocated receiving buffer and the sending buffer in the processor system, and the receiving buffer and the sending buffer are maintained in a ring queue mode.

In a preferred embodiment, the pre-allocated receive buffer and transmit buffer addresses are contiguous and in 2KB as a small unit for storing one frame of EPA data.

In a preferred embodiment, the processor, upon initializing the EPA units, is in accordance with the system application: the EPA unit initializes the head and tail pointers by driving the starting address and the case of the processor sending cache to be written into the processor sending cache management module; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty or full mark for sending the cache is generated in real time; the EPA unit initializes the head and tail pointers by driving the starting address and the case of the processor receiving cache to be written into the processor receiving cache management module; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and the empty or full mark of the receiving buffer is generated in real time.

In a preferred embodiment, the transfer length of the DMA is determined by the frame length of the data packet, and the FPGA actively reads the length of the data packet to be transferred before starting the DMA, and uses the length of the data packet as the transfer length of the DMA, thereby further improving the transfer efficiency.

In a preferred embodiment, the interrupt management module sets different interrupt trigger frequencies based on different working conditions when the interrupt management module is configured by the processor, and when the interrupt is started, the MSI interrupt is sent periodically according to the processor receiving the non-empty indication of the cache management module.

Based on the same inventive concept, the invention also provides a PCIe data transmission device applied to EPA based on FPGA, comprising: the data reading module is used for reading the data length from the transmission buffer memory of the current processor system and transmitting the frame data under the condition that the transmission buffer memory of the processor system is not empty, and updating the transmission completion mark of the frame data in the transmission buffer memory of the processor system after the frame data is transmitted by the EPA unit; the data writing module is used for reading the data length from the receiving buffer memory of the EPA unit and sending the frame data to the receiving buffer memory of the processor system when the data exists in the receiving buffer memory of the EPA unit; before the EPA unit is started to perform formal work, starting addresses and sizes of the receiving buffer and the sending buffer are written into the EPA unit based on the FPGA based on the pre-allocated receiving buffer and the sending buffer in the processor system, and the receiving buffer and the sending buffer are maintained in a ring queue mode.

Based on the same inventive concept, the present invention also provides a computer apparatus comprising: a memory for storing a processing program; and the processor is used for realizing the PCIe data transmission method applied to EPA based on the FPGA according to any one of the above processing programs when executing the processing programs.

By adopting the technical scheme, the invention has the following advantages and positive effects compared with the prior art:

the PCIe data transmission method and system based on the FPGA applied to EPA aims at the problems that the prior EPA PCIe is easy to cause that the processing capacity and the real-time performance of the system cannot meet the requirements due to too frequent interrupt response when in large data volume communication, so that the method and the system cannot be applied to the field of large data volume transmission, and interaction of the two parties is reduced by adopting the way of directly accessing the processor memory through the FPGA PCIe, so that the PCIe transmission efficiency is greatly improved, the hardware cost is not increased, and the hardware is not required to be changed. The method benefits from abundant memory resources of the processor system, greatly improves the data transmission rate between EPA and the processor, expands the application scene of EPA, reduces the load of PCIe transmission to the processor, and enables the processor to concentrate on data processing and other system transactions.

Drawings

FIG. 1 is a schematic diagram of a PCIe transmission system based on an FPGA applied to EPA according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a cache management method according to an embodiment of the invention;

FIG. 3 is a flow chart of a processor transmission flow in an embodiment of the invention;

FIG. 4 is a flow chart of the FPGA sending process in an embodiment of the invention;

FIG. 5 is a flow chart of a receiving process of a processor according to an embodiment of the invention;

FIG. 6 is a flow chart of the FPGA receiving process in an embodiment of the invention;

FIG. 7 is a flow chart of FPGA interrupt management in an embodiment of the invention.

Detailed Description

The invention provides a PCIe data transmission method and a PCIe data transmission system based on the application of an FPGA to EPA, which are further described in detail below with reference to the accompanying drawings and the specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims.

As described above, in the interrupt-based PCIe data communication method, when the amount of data communicated between the EPA system and the processor is small, the real-time performance of processing can be ensured, but in the case of a large amount of data, the communication manner in which data is transmitted in an interrupt manner is easy to interrupt too frequently due to the increase of the number of interrupts, so that it is difficult for the processor and the operating system to respond to the interrupt in time, the transmission efficiency of PCIe is greatly reduced, and the communication delay is increased, thereby affecting the processing amount and the real-time performance of system data.

In order to solve the above problems, an embodiment of the present disclosure provides a PCIe data transmission method and system applied to EPA based on FPGA. According to the method and the system, the PCIe transmission process is performed in a mode of directly accessing the memory of the processor by using the FPGA PCIe, the processor is not needed to be involved, meanwhile, in order to ensure the real-time performance of data processing, an interrupt management function which can be configured by the processor is provided.

Hereinafter, specific examples of the present scheme will be described in more detail with reference to the accompanying drawings.

FIG. 1 shows a schematic diagram of a PCIe transmission system based on an FPGA application to EPA in accordance with an embodiment of the present disclosure. As shown in fig. 1, the system includes an EPA unit, a processor system (including processor memory), a PCIe bus, and an ethernet. The EPA unit is in data communication with the processor system via a PCIe bus.

EPA units (only describing the scope of the present application) include PCIe communications modules, data cache management modules, interrupt management modules.

The PCIe communication module contains PCIe cache area, PCIe data receiving and transmitting protocol stack and DMA.

Regarding the PCIe buffer zone, an EPA send buffer for storing one frame of data to be sent read from the processor system send buffer, and an EPA receive buffer for storing one frame of data received from the ethernet to be written to the processor system receive buffer are included.

With respect to PCIe data transceiving protocol stacks, DMA controlled read and write functions to the processor system cache are performed over the PCIe bus.

The DMA is controlled by the data cache management module, when triggered, different data transfer lengths are obtained according to different transfer directions, when cache read operation is sent from a processor, the cache read length is sent from the current processor, and when cache write operation is received from the processor, the cache read length is received from PCIe; after a frame of data is sent by the EPA, the DMA updates the sending completion flag of the frame of data in the processor sending buffer.

The data buffer management module comprises a processor sending buffer management module, a processor receiving buffer management module and a DMA trigger module.

Regarding a processor sending buffer management module, two head and tail pointers are contained, when the processor initializes EPA, the FPGA initializes the head and tail pointers by driving the starting address and the size of the sending buffer; when EPA works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the FPGA, and the empty or full mark of the sending cache is generated in real time.

Regarding a processor receiving buffer memory management module, two head and tail pointers are contained, when the processor initializes EPA, the FPGA initializes the head and tail pointers by driving the starting address and the size of the receiving buffer memory; when EPA works normally, the head pointer is maintained by FPGA, the tail pointer is maintained by processor, and the empty or full mark of the receiving buffer is generated in real time.

And the DMA triggering module triggers the reading DMA of the sending buffer from the processor according to the non-empty mark of the sending buffer management module, and triggers the writing DMA of the receiving buffer to the processor according to the non-full mark of the receiving buffer management module when the data needs to be written into the receiving buffer of the processor.

The interrupt management module can be configured by the processor in real time, the processor can shield or open the interrupt according to actual needs, and a certain interrupt trigger frequency can be set. When the interrupt is turned on, the MSI interrupt is periodically sent based on the processor receiving a non-empty indication of the cache management module.

The following describes PCIe data transmission methods and systems applied to EPA based on FPGAs according to embodiments of the present disclosure in conjunction with fig. 2, 3, 4, 5, 6, and 7. FIG. 2 illustrates a cache management method for an EPA based PCIe data transfer method and system based on an FPGA according to an embodiment of the present disclosure. Fig. 3 and 4 are flowcharts illustrating a transmission direction in a PCIe data transmission method applied to an EPA based on an FPGA according to an embodiment of the present disclosure, and since the present invention optimizes interaction between a processor and the FPGA, transmission processes of the processor and the FPGA are relatively independent processes, where fig. 3 illustrates a transmission process of the processor, and fig. 4 illustrates a transmission process of the FPGA. Fig. 5 and 6 are flowcharts illustrating a receiving direction in a PCIe data transmission method applied to an EPA based on an FPGA according to an embodiment of the present disclosure, where the receiving process of the processor and the FPGA is also a relatively independent process, and fig. 5 illustrates a receiving process of the processor, and fig. 6 illustrates a receiving process of the FPGA. FIG. 7 illustrates an interrupt management flow in a PCIe data transfer method based on an FPGA application to EPA according to an embodiment of the present disclosure.

Fig. 2 illustrates a buffer management method according to an embodiment of the present disclosure, in which both a transmission buffer and a reception buffer are managed.

The head pointer and the tail pointer of the sending cache and the receiving cache are both positioned in the FPGA, the head pointer of the sending cache is maintained by the processor, the tail pointer is maintained by the FPGA, the head pointer of the receiving cache is maintained by the FPGA, and the tail pointer is maintained by the processor; the cached states are uniformly managed by the FPGA so as to avoid state conflict caused by information non-synchronization.

The buffer takes 2KB as a small space, can store one frame of data, and the blank 2KB in the figure represents idle and the hatched 2KB represents data; for the transmission buffer, the first 4 bytes of the 2KB space represent a transmission completion instruction, 0 represents unsent, 1 represents transmission completion, when the processor writes data to be transmitted, the first 4 bytes are 0, after EPA transmission is completed, the FPGA writes the first 4 bytes of the space into 1, which represents transmission completion. The processor may decide whether or not to retransmit the frame data based on the flag.

The cache is maintained in a ring queue mode, and although two cases of head and tail pointers are listed in the figure, the maintenance method is consistent; the head pointer points to the next space to be written, and the tail pointer points to the space which has been read currently; the tail pointer +1 is equal to the head pointer indicating that the buffer is empty and the head pointer is equal to the tail pointer indicating that the buffer is full.

Fig. 3 shows a flow chart of a processor transmission flow according to an embodiment of the present disclosure.

At step 301, the processor schedules the transmission task, before transmitting the data, it needs to query the FPGA register to determine whether the transmission buffer is full, if so, the transmission task is exited, and when the next transmission task is scheduled, the process continues, and if not, the process proceeds to step 302.

At step 302, the processor acquires a head pointer of the send buffer, writes the data to be sent into the 2KB free space in the send buffer pointed by the head pointer, then points the head pointer +1 to the next 2KB free space, and updates the send buffer head pointer located inside the FPGA.

By means of the method, the processor can judge whether to fill in transmission data to the transmission buffer memory only through the transmission buffer memory state indication of the FPGA, and the transmission task of the processor can be finished only by updating the transmission buffer memory head pointer after filling, and particularly, the processor can write a large amount of data to be transmitted at one time due to the large memory of the processor, so that the number of times of scheduling the transmission task by the processor is reduced, and the load of the processor is effectively reduced.

Fig. 4 shows a flowchart of an FPGA transmission flow according to an embodiment of the present disclosure.

At step 401, if the transmit buffer in the processor is not empty, the FPGA starts a flow of transmitting a frame of data.

At step 402, the FPGA prepends the transmit buffer tail pointer by 1 to the 2KB to transmit space in the transmit buffer, obtaining the length of the data to be transmitted.

At step 403, the FPGA starts DMA reading data from the transmit cache into the EPA transmit cache based on the acquired data length and the transmit cache real address pointed to by the tail pointer of pre +1.

At step 404, whether DMA waiting to read data is complete.

At step 405, the DMA of the read data has been completed, and EPA transmission of this frame of data is enabled.

At step 406, wait for EPA to send whether data in the buffer is being sent.

After this frame data transmission is completed at step 407, the FPGA formally updates the tail pointer +1, updates the transmission completion flag in the processor transmission buffer, and returns to step 401.

By means of the method, the FPGA can continuously process data in the sending buffer memory, the sending flow is independent of interaction with the processor, and the transmission efficiency of PCIe and the sending efficiency of EPA are maximized.

Fig. 5 shows a flowchart of a processor reception flow according to an embodiment of the present disclosure.

The processor enters step 501 according to the periodic inquiry or MSI interrupt, the processor firstly inquires a receiving buffer status register in the FPGA, if the receiving buffer status register is empty, the operation is exited, and if the receiving buffer status register is not empty, the processor enters step 502.

At step 502, the processor pre-adds 1 to the tail pointer to the 2KB data space to be processed in the receiving buffer, then obtains data, processes the data, formally updates the tail pointer +1 after the processing is completed, and then reenters step 501.

By means of the method, the processor can judge whether the received data needs to be processed only through the receiving buffer status indication of the FPGA, and after one frame is processed, the receiving buffer tail pointer is updated, and then next frame processing can be continued until the receiving buffer is empty. The method benefits from the large memory of the processor, and the processor can process a large amount of receiving at one time, so that the times of dispatching and receiving tasks by the processor are reduced, and the data processing efficiency of the processor is greatly improved.

Fig. 6 shows a flowchart of an FPGA receive flow according to an embodiment of the present disclosure.

The FPGA receives a frame of EPA data from the ethernet, and proceeds to step 601, and if not full, the FPGA proceeds to step 602, and if full, the FPGA proceeds to step 606 according to the state of the receiving buffer.

At step 606, the frame EPA data is discarded, the receive overflow flag is set, and overflow packet count statistics are performed.

At step 602, the FPGA obtains the data length in the EPA receive buffer.

At step 603, the FPGA starts DMA writing data to the receive buffer, moves the length of the data in the EPA receive buffer, and writes the data into the 2KB free space in the receive buffer pointed to by the head pointer.

At step 604, it is waited whether the write data DMA is complete.

At step 605, after the FPGA has head pointer +1, the head pointer is updated to point to the 2KB space that receives the next to be written.

Through the mode, the FPGA can continuously process EPA data received from the Ethernet, the FPGA receiving flow is independent of interaction with the processor, and the transmission efficiency of PCIe and the receiving efficiency of EPA are maximized.

FIG. 7 illustrates a flow chart of FPGA interrupt management according to an embodiment of the present disclosure.

At step 701, if an interrupt of the FPGA is enabled, then the next step is performed.

At step 702, the FPGA obtains the status of the receive buffer, and if not empty, the next step is performed.

At step 703, the FPGA determines whether the minimum interval time from the last MSI interrupt has been reached, and if so, performs the next step. Wherein the minimum interrupt interval is written by the processor in real time, ranging from 1us to 10ms.

At step 704, the FPGA sends an MSI interrupt over PCIe.

By means of the method, the minimum interrupt interval can be adjusted in real time by the processor, and the real-time data processing performance and the processor load can be balanced according to actual conditions by the processor.

The PCIe data transmission method based on the FPGA applied to the EPA greatly improves the PCIe transmission efficiency, greatly improves the data transmission rate between the EPA and the processor, expands the application scene of the EPA, simultaneously reduces the load of PCIe transmission to the processor, and enables the processor to concentrate on data processing and other system transactions.

The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is within the scope of the appended claims and their equivalents to fall within the scope of the invention.

Claims

1. A PCIe data transmission system for EPA based on an FPGA, comprising:

the system comprises a processor system and a processor memory, wherein the processor memory comprises a receiving buffer and a sending buffer;

the system comprises an FPGA-based EPA unit which is communicated with the processor system through a PCIe bus, wherein the EPA unit comprises a PCIe communication module, a data buffer management module and an interrupt management module, the PCIe communication module is used for communicating with the processor, the data buffer management module is used for initiating writing and reading operations of data in a memory of the processor, the interrupt management module is used for managing the initiation interval or direct shielding of MSI interrupt, the PCIe communication module comprises a PCIe buffer area, a PCIe data receiving and transmitting protocol stack and a DMA, the PCIe buffer area comprises an EPA sending buffer and an EPA receiving buffer, the data buffer management module is used for triggering and controlling the DMA to realize movement in different directions, and the interrupt management module can be configured by the processor in real time to realize shielding or opening interrupt;

the data cache management module comprises: the processor sends a buffer management module, the processor receives the buffer management module and the DMA trigger module;

the processor sends a buffer management module, two head and tail pointers are contained, when the processor initializes the EPA unit, the processor sends a buffer management module by driving the initial address and the upper and lower case of the buffer sent by the processor to the processor according to the system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty or full mark for sending the cache is generated in real time; the processor receives the buffer memory management module, two head and tail pointers are contained, when the processor initializes the EPA unit, the processor receives the buffer memory management module by driving the initial address and the upper and lower case of the buffer memory received by the processor according to the system application program, and the EPA unit initializes the head and tail pointers; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and the empty or full mark of the receiving cache is generated in real time; and the DMA triggering module triggers the DMA for sending the cache read data frame from the processor according to the non-empty mark of the processor sending cache management module, and triggers the DMA for receiving the cache write data frame to the processor according to the non-full mark of the processor receiving cache management module when the data needs to be written into the processor receiving cache.

2. The FPGA-based PCIe data transmission system for EPA according to claim 1 wherein said interrupt management module may set different interrupt trigger frequencies when configured by said processor, and when an interrupt is turned on, the MSI interrupt is sent periodically according to the processor receiving a non-empty indication from the cache management module.

3. The PCIe data transmission method applied to EPA based on FPGA, applied to the data transmission system according to any one of claims 1 to 2, comprising:

reading the data length from the transmission buffer of the current processor system and transmitting the data under the condition that the transmission buffer of the processor system is not empty, and updating the transmission completion mark of the data in the transmission buffer of the processor system after the data is transmitted by the EPA unit;

reading the data length from the EPA unit's receive cache and sending the data to the processor system's receive cache in the case of data present in the EPA unit's receive cache;

before the formal work of the EPA unit is started, starting addresses and sizes of the receiving buffer and the sending buffer are written into the EPA unit based on the FPGA based on the pre-allocated receiving buffer and the sending buffer in the processor system, and the receiving buffer and the sending buffer are maintained in a ring queue mode;

the processor, upon initializing the EPA unit, is in accordance with the system application:

the EPA unit initializes the head and tail pointers by driving the starting address and the case of the processor sending cache to be written into the processor sending cache management module; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty or full mark for sending the cache is generated in real time; the EPA unit initializes the head and tail pointers by driving the starting address and the case of the processor receiving cache to be written into the processor receiving cache management module; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and the empty or full mark of the receiving buffer is generated in real time.

4. The FPGA-based PCIe data transmission method applied to EPA according to claim 3, wherein the pre-allocated receive buffer and transmit buffer addresses are consecutive and use 2KB as a small unit for storing one frame of EPA data.

5. The PCIe data transmission method applied to EPA based on FPGA according to claim 3, wherein the moving length of DMA is determined by the frame length of data packet, FPGA actively reads the length of data packet to be transmitted before starting DMA, and takes the length of data packet as the moving length of DMA, thereby further improving transmission efficiency.

6. The PCIe data transmission method applied to EPA based on FPGA of claim 3 wherein the interrupt management module sets different interrupt trigger frequencies based on different conditions when configured by said processor, and when an interrupt is turned on, the MSI interrupt is sent periodically according to the processor receiving a non-empty indication from the cache management module.

7. A PCIe data transmission device applied to EPA based on FPGA, comprising:

the data reading module is used for reading the data length from the transmission buffer memory of the current processor system and transmitting the data under the condition that the transmission buffer memory of the processor system is not empty, and updating the transmission completion mark of the data in the transmission buffer memory of the processor system after the data is transmitted by the EPA unit;

the data writing module is used for reading the data length from the receiving cache of the EPA unit and sending the data to the receiving cache of the processor system under the condition that the data exists in the receiving cache of the EPA unit;

before the formal work of the EPA unit is started, starting addresses and sizes of the receiving buffer and the sending buffer are written into the EPA unit based on the FPGA based on the pre-allocated receiving buffer and the sending buffer in the processor system, and the receiving buffer and the sending buffer are maintained in a ring queue mode; the processor, upon initializing the EPA unit, is in accordance with the system application:

the EPA unit initializes the head and tail pointers by driving the starting address and the case of the processor sending cache to be written into the processor sending cache management module; when the EPA unit works normally, the head pointer is maintained by the processor, the tail pointer is maintained by the EPA unit, and an empty or full mark for sending the cache is generated in real time;

the EPA unit initializes the head and tail pointers by driving the starting address and the case of the processor receiving cache to be written into the processor receiving cache management module; when the EPA unit works normally, the head pointer is maintained by the EPA unit, the tail pointer is maintained by the processor, and the empty or full mark of the receiving buffer is generated in real time.

8. A computer device, comprising:

a memory for storing a processing program; a processor, when executing the processing program, implementing the PCIe data transmission method applied to EPA based on FPGA as claimed in any one of claims 3 to 6.