CN114818597A

CN114818597A - Clock verification environment generation method and device, electronic equipment and storage medium

Info

Publication number: CN114818597A
Application number: CN202210425600.7A
Authority: CN
Inventors: 薛静松; 胡旭
Original assignee: Horizon Shanghai Artificial Intelligence Technology Co Ltd
Current assignee: Horizon Shanghai Artificial Intelligence Technology Co Ltd
Priority date: 2022-04-21
Filing date: 2022-04-21
Publication date: 2022-07-29

Abstract

The embodiment of the disclosure discloses a method and a device for generating a clock verification environment, an electronic device and a storage medium, wherein the method comprises the following steps: acquiring clock information corresponding to at least one subsystem of the system on chip; and generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template. The method and the device for generating the target clock verification environment can rapidly and automatically generate the target clock verification environment corresponding to any subsystem of the system on chip based on the clock information corresponding to the subsystem, so that the verification environment of each subsystem does not need to be repeatedly developed, the development workload of the verification environment is effectively reduced, and the verification working efficiency is improved.

Description

Clock verification environment generation method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to chip verification technologies, and in particular, to a method and an apparatus for generating a clock verification environment, an electronic device, and a storage medium.

Background

With the increasing chip scale and the increasing functions, the structure of the clock tree is also more complex, once the clock is in error, the whole chip or a plurality of important functions cannot work normally, and therefore, the verification of the clock tree is more and more important in chip design. In the related art, verification environments are usually required to be developed and verified respectively for clocks of subsystems in the whole system on chip of a chip, but the verification efficiency is low because the subsystems included in the system on chip are often more and complicated and the development workload of the verification environments is large.

Disclosure of Invention

The present disclosure is proposed to solve the technical problem of the large workload of the development of the verification environment. The embodiment of the disclosure provides a clock verification environment generation method and device, an electronic device and a storage medium.

According to an aspect of the embodiments of the present disclosure, there is provided a method for generating a clock verification environment, including: acquiring clock information corresponding to at least one subsystem of the system on chip; and generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template.

According to another aspect of the embodiments of the present disclosure, there is provided a clock verification environment generation apparatus including: the first acquisition module is used for acquiring clock information corresponding to at least one subsystem of the system on chip; and the first processing module is used for generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template.

According to a further aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium storing a computer program for executing the method for generating a clock verification environment according to any one of the above embodiments of the present disclosure.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic apparatus including: a processor; a memory for storing the processor-executable instructions; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for generating a clock verification environment according to any of the embodiments of the disclosure.

Based on the clock verification environment generation method, the clock verification environment generation device, the electronic equipment and the storage medium provided by the embodiment of the disclosure, the target clock verification environment corresponding to any subsystem of the system on chip can be quickly and automatically generated based on the clock information corresponding to the subsystem by establishing the subsystem clock verification environment template, so that the verification environment of each subsystem does not need to be repeatedly developed, the verification environment development workload is effectively reduced, and the verification working efficiency is improved.

The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure, and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally represent like parts or steps.

FIG. 1 is an exemplary application scenario of a method of generating a clock verification environment provided by the present disclosure;

FIG. 2 is a flowchart illustrating a method for generating a clock verification environment according to an exemplary embodiment of the present disclosure;

FIG. 3 is a flowchart illustrating a method for generating a clock verification environment according to another exemplary embodiment of the disclosure;

FIG. 4 is a flowchart illustrating a method for generating a clock verification environment according to yet another exemplary embodiment of the present disclosure;

FIG. 5 is a pseudo-code diagram of a clock enumeration structure according to an exemplary embodiment of the present disclosure;

FIG. 6 is a flowchart of step 402 provided by an exemplary embodiment of the present disclosure;

FIG. 7 is a schematic block diagram of a clock verification environment provided by an exemplary embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a structure data format of an auto _ model according to an exemplary embodiment of the disclosure;

FIG. 9 is a flowchart of step 201 provided by an exemplary embodiment of the present disclosure;

FIG. 10 is a schematic diagram of an automated clock verification process provided by an exemplary embodiment of the present disclosure;

FIG. 11 is a schematic structural diagram of a device for generating a clock verification environment according to an exemplary embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a clock verification environment generation apparatus according to another exemplary embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a clock verification environment generation apparatus according to still another exemplary embodiment of the present disclosure;

fig. 14 is a schematic structural diagram of an application embodiment of the electronic device of the present disclosure.

Detailed Description

Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.

It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

It will be understood by those of skill in the art that the terms "first," "second," and the like in the embodiments of the present disclosure are used merely to distinguish one element from another, and are not intended to imply any particular technical meaning, nor is the necessary logical order between them.

It is also understood that in embodiments of the present disclosure, "a plurality" may refer to two or more and "at least one" may refer to one, two or more.

It is also to be understood that any reference to any component, data, or structure in the embodiments of the disclosure, may be generally understood as one or more, unless explicitly defined otherwise or stated otherwise.

In addition, the term "and/or" in the present disclosure is only one kind of association relationship describing an associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.

It should also be understood that the description of the embodiments in the present disclosure emphasizes the differences between the embodiments, and the same or similar parts may be referred to each other, and are not repeated for brevity.

Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

The disclosed embodiments may be applied to electronic devices such as terminal devices, computer systems, servers, etc., which are operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well known terminal devices, computing systems, environments, and/or configurations that may be suitable for use with electronic devices, such as terminal devices, computer systems, servers, and the like, include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network pcs, minicomputer systems, mainframe computer systems, distributed cloud computing environments that include any of the above, and the like.

Electronic devices such as terminal devices, computer systems, servers, etc. may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system/server may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

Summary of the disclosure

In the process of implementing the present disclosure, the inventor finds that, when a chip is designed to verify a clock tree, verification environments are generally required to be developed respectively for clocks of subsystems in the whole system on chip of the chip to be verified, but because the subsystems included in the system on chip are often more and complicated, the development workload of the verification environments is large, and thus the verification work efficiency is low.

Brief description of the drawings

Fig. 1 is an exemplary application scenario of the clock verification environment generation method provided by the present disclosure.

Aiming at each subsystem of a system on chip (SoC), such as a peripheral subsystem, a storage subsystem, a CPU (central processing unit) and the like, each subsystem needs a corresponding clock generator to provide a clock for the subsystem so that the subsystem can normally work, and for the verification of the system on chip clock, by utilizing the method for generating the clock verification environment provided by the disclosure, the clock information of each subsystem can be synthesized, a subsystem clock verification environment template is established through parameterization of the clock verification environment, when any subsystem needs to be verified, the clock verification environment corresponding to the subsystem can be quickly and effectively generated based on the subsystem clock verification environment template for performing clock verification on the subsystem, and the verification environment does not need to be respectively developed aiming at each subsystem clock, so that the verification work efficiency is effectively improved.

Exemplary method

Fig. 2 is a flowchart illustrating a method for generating a clock verification environment according to an exemplary embodiment of the disclosure. The embodiment can be applied to electronic devices, such as a server, a terminal, and the like, and as shown in fig. 2, includes the following steps:

step 201, clock information corresponding to at least one subsystem of the system on chip is obtained.

The System-on-a-chip (SoC) refers to a complete System integrated on a single chip. The complete system typically includes a Central Processing Unit (CPU), memory, and peripheral circuits, among others. The system on chip may be a system on chip for any field or scene, such as a system on chip for automatic driving, without limitation. The subsystem refers to the components of the on-chip system, such as the CPU, memory, and peripheral circuits. The division of the specific subsystems can be set according to actual requirements, and the disclosure is not limited. The clock information corresponding to the subsystem refers to relevant information of a clock generator in the subsystem, for example, the clock information may include at least one of a clock number, a clock signal name, a frequency value selected by an input clock source MUX (selector), a default value of the MUX, a frequency division coefficient, a frequency division default value, whether glitches occur in frequency division, whether gating enable is register controllable or top layer fixed and normally open, a clock level value after clock turn-off, whether glitches are introduced in clock source switching, and the like. The specific clock information can be set according to actual requirements.

Step 202, generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template.

The subsystem clock verification environment template is established by synthesizing the clock information of each subsystem in advance, comprises parameter variables required by environment components of the clock verification environment of each subsystem and the connection relation between the environment components, and can also comprise initial values of the variables, and the initial values can be specifically set according to actual requirements. The method quantizes different clock parameters required by the clock verification environments of different subsystems to form a subsystem clock verification environment template capable of supporting different subsystems, and can support different subsystems through variable enabling for parameters required by one subsystem and parameters not required by the other subsystem, so that when the clock verification environment of the subsystems is generated, the parameters can be transmitted and assigned for the variables, different parameters transmitted by different subsystems can be realized, the clock verification environments corresponding to the subsystems can be automatically generated, the verification environments do not need to be developed respectively for each subsystem, and the verification working efficiency is greatly improved. For the verification of a plurality of subsystems, each subsystem can independently generate a target clock verification environment corresponding to the subsystem based on the clock information of the subsystem and a subsystem clock verification environment template.

Optionally, clock information corresponding to at least one subsystem of the system on chip may be provided through a verification case, that is, when the clock to be tested of the subsystem needs to be verified, the verification case corresponding to the clock to be tested of the subsystem may be developed, where the verification case is a description of a verification task, and includes related information such as a verification target, a verification environment, input data, a verification step, an expected result, and the like. The relevant environment information for creating the verification environment included in the verification use case in the present disclosure may be a storage address of clock information corresponding to the subsystem, subsystem clock verification environment template information, and the like. By executing the verification case, the clock information corresponding to the corresponding subsystem can be automatically acquired from the corresponding storage area, and then the target clock verification environment corresponding to the subsystem is generated based on the clock information corresponding to the subsystem and the subsystem clock verification environment template.

The subsystem clock verification environment template is not limited to a subsystem of a system on chip, and can be used for constructing a subsystem clock verification environment template with the maximum capability by integrating clock information required by various systems on chip, so that the universality is improved.

According to the method for generating the clock verification environment, the subsystem clock verification environment template is established, and the target clock verification environment corresponding to any subsystem of the system on chip can be quickly and automatically generated based on the clock information corresponding to the subsystem, so that the verification environment of each subsystem does not need to be repeatedly developed, the development workload of the verification environment is effectively reduced, and the verification working efficiency is improved.

In an alternative example, fig. 3 is a flowchart illustrating a method for generating a clock verification environment according to another exemplary embodiment of the present disclosure, in this example, step 202 may specifically include the following steps:

step 2021, rendering the subsystem clock verification environment template according to a preset rendering mode based on the clock information corresponding to the subsystem, and obtaining a target clock verification environment corresponding to the subsystem.

The preset rendering mode can adopt any implementable mode, for example, rendering is carried out in a template mode based on a template engine, the real value is replaced by the station position variable through dynamic assignment, and then the final response character string is returned, and the specific rendering principle is not repeated.

In an optional example, the rendering, based on the clock information corresponding to the subsystem, the subsystem clock verification environment template according to a preset rendering mode in step 2021 to obtain the target clock verification environment corresponding to the subsystem includes: traversing the subsystem clock verification environment template, determining the value of a preset variable in each environment component in the subsystem clock verification environment template according to the clock information corresponding to the subsystem, and obtaining the target clock verification environment corresponding to the subsystem.

The environment component is a code module used for implementing each function of the verification process in the verification environment, and may include a sequencer, a sequence, transaction data, a driver, a function coverage rate statistics device, a monitor, a score board, a reference model, an input interface, an output interface, and the like, which may be specifically set according to actual requirements. The basic function code of the environment component is preset, and when the verification environment is generated, corresponding parameters need to be provided for the environment component according to actual verification requirements, so that the environment component can realize the required verification function. According to the method and the system, parameters of the environment components required by the clock verification environment of each subsystem are quantized to form a subsystem clock verification environment template capable of supporting different subsystems, and when the corresponding clock verification environment is generated for the subsystem requiring clock verification, the parameters corresponding to the subsystem are assigned to corresponding preset variables in the subsystem clock verification environment template, so that the parameter values required by each environment component under the subsystem can be determined, and clock verification of the subsystem can be achieved based on the assigned environment components. For example, the subsystem name corresponds to a variable subsys _ name, and during verification, the real name of the subsystem is assigned to the variable subsys _ name; for example, the frequency point value selected by the clock source MUX is input to the dependent variable MUX. The specific variable setting rule can be set according to actual requirements, and the disclosure is not limited.

In an optional example, before generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and the pre-established subsystem clock verification environment template in step 202, the method of the present disclosure further includes:

step 301, establishing a subsystem clock verification environment template based on the clock information corresponding to each subsystem of the system on chip.

The clock information corresponding to each subsystem of the system on chip can be obtained based on the characteristics of each clock generator in each subsystem. The environment components in the established subsystem clock verification environment template and the parameter variables in the environment components can integrate the requirements of all subsystems, the support function of the maximum capacity is set, the requirements of all subsystem clock verification environments are covered, and in actual verification, each subsystem can generate a clock verification environment meeting the requirements of the subsystem through enabling of the parameter variables and parameter transmission.

Fig. 4 is a flowchart illustrating a method for generating a clock verification environment according to still another exemplary embodiment of the disclosure.

In an optional example, the establishing, in step 301, a subsystem clock verification environment template based on clock information respectively corresponding to subsystems of the system on chip includes:

3011, determining preset variables corresponding to the environmental components and initial values corresponding to the preset variables based on clock information corresponding to each subsystem of the system on chip;

the preset variables are used as station variables, station positions are carried out on corresponding parameters in the template, and the preset variables can be comprehensively set according to clock information corresponding to each subsystem respectively. For example, for an environment component a, in the verification of the subsystem 1, a class B parameter needs to be transmitted, and in the verification of the subsystem 2, a class C parameter needs to be transmitted, then a variable B corresponding to the class B parameter and a variable C corresponding to the class C parameter can be set in the environment component, and in the actual parameter transmission, the state of the variable C can be set to disable for the subsystem 1, and the state of the variable B can be set to enable for the subsystem 1, so that the environment component in the template can support the subsystem 1 and the subsystem 2, and for the parameters of the same type but different values, the support of different subsystems can be realized through variable assignment. The different types of parameters refer to parameters indicating different clock information, such as a clock number and a clock signal name, and the frequency point value and the frequency division coefficient selected by the input clock source MUX are different types of parameters. Therefore, the preset variable which can support each subsystem by each environment component can be determined by integrating the clock information corresponding to each subsystem. The initial value of each preset variable may be set according to actual requirements, and is not particularly limited.

And step 3012, establishing a connection relationship between the environment components, and obtaining a subsystem clock verification environment template.

The purpose of establishing the connection relation among the environment components is to enable the environment components to mutually transmit information or data in the verification process so as to realize the verification function by matching work. Taking the UVM verification environment as an example, during verification, the environment components need to cooperate with each other to realize chip verification. The overall architecture of the verification environment is determined, different environment components implement different functions, such as a clock data component (clk _ transaction component) for generating clock excitation configuration information, including, for example, frequency division coefficients, multiplexing, clock gating, etc., a clock excitation generator component for transmitting the clock excitation configuration information generated by the clock data component to a clock driver (clk _ driver), which can analyze the clock excitation configuration information and drive to a clock to be tested, and the clock to be tested responds to the clock excitation configuration information to obtain a response result, etc. The completion of the verification work requires that all environment components are connected according to respective functions, so that the process of creating the subsystem clock verification environment template needs to establish the connection relation among all environment components besides determining the required environment components and preset variables in the environment components, so that the environment components can be automatically generated and the connection among all environment components can be established when the verification environment is actually produced, and the full-automatic generation of the verification environment is realized.

In an optional example, after generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and the pre-established subsystem clock verification environment template in step 202, the method of the present disclosure further includes:

step 203, establishing a connection relationship between the target clock verification environment and the clock to be tested of the subsystem, so that the target clock verification environment drives the excitation to the clock to be tested.

The connection relation between the target clock verification environment and the corresponding clock to be tested is used for driving the excitation generated by the target clock verification environment to the clock to be tested during clock verification.

For example, a clock enumeration structure of a subsystem in a verification environment may be automatically generated based on clock information corresponding to the subsystem, and a connection between a target clock verification environment and a clock under test (DUT) of the corresponding subsystem may be automatically generated by indexing using the clock enumeration structure.

For example, fig. 5 is a pseudo code diagram of a clock enumeration structure according to an exemplary embodiment of the present disclosure. The method includes the steps that enum { } peri _ sys _ clc _ e represents enumeration on a peri _ sys _ clk subsystem, content in parentheses { } is an enumeration value and represents a clock name, left and right content of four ═ below respectively represent a verification environment interface and a clock interface to be tested, peri _ sys _ clk _ if.clk _ name [0] represents clk _ pci _ aux, namely, the enumeration value is assigned to variables clk _ name [0] -clk _ name [3 ]. The principles of a specific enumeration structure are not described in detail herein. The corresponding relation between the target clock verification environment and the interfaces of the clocks to be tested is established through the enumeration structure, so that the connecting line between the target clock verification environment and the clocks to be tested of the corresponding subsystem can be automatically established based on the corresponding relation of the interfaces.

In an optional example, after establishing the connection relationship between the target clock verification environment and the clock under test of the subsystem in step 203, the method of the present disclosure further includes:

and 204, verifying the to-be-tested clock of the corresponding subsystem based on the target clock verification environment to obtain a verification result corresponding to the to-be-tested clock.

Specifically, after a target clock verification environment corresponding to the subsystem is generated and connection with the clock to be tested is established, the clock to be tested can be verified. The target clock verification environment generates excitation corresponding to a clock to be tested of the subsystem and drives the clock to be tested, the clock to be tested responds to the excitation, the target clock verification environment monitors actual data of the clock to be tested, such as actual frequency, actual duty ratio and actual gating state of the clock to be tested, and the actual frequency, the actual duty ratio and the expected gating state are compared with the expected frequency, the expected duty ratio and the expected gating state, and a comparison result is output.

Based on the clock verification environment generation method disclosed by the invention, the relevant verification responsible persons of each subsystem can perform clock verification based on the independent clock verification environment, and compared with the existing end-to-end verification which requires cooperation among the responsible persons of each subsystem, the verification disclosed by the invention realizes the decoupling of the clock verification of each subsystem, and the verification working efficiency is greatly improved.

In an alternative example, fig. 6 is a flowchart of step 204 provided in an exemplary embodiment of the present disclosure, and fig. 7 is a structural diagram of a clock verification environment provided in an exemplary embodiment of the present disclosure. In this example, the target clock verification environment includes a clock data component, a clock stimulus generator component, a clock driver, a reference model, a scoreboard, and a monitor; the verifying the to-be-tested clock of the subsystem corresponding to the target clock based on the target clock verifying environment in step 204 to obtain a verifying result corresponding to the to-be-tested clock, including:

the clock data component is used to generate clock excitation configuration information, step 2041.

The clock excitation configuration information includes a frequency division coefficient, multiple paths of selection, clock gating, and the like, and may be specifically set according to actual requirements. The clock data component (clk _ transaction component) is used to describe the information passed by each environment component, and is the basic data structure for each environment component to pass information.

The clock stimuli generator component is operable to communicate clock stimuli configuration information to the clock driver, step 2042.

The clock excitation generator component (clk _ seqr component) is responsible for transmitting clock excitation configuration information generated by the clock data component to the clock driver (clk _ driver component), so that the clock driver drives the clock excitation configuration information to a clock under test (DUT) of a corresponding subsystem.

Step 2043, the clock driver is configured to drive the clock excitation configuration information to the clock to be tested based on the connection relationship between the target clock verification environment and the clock to be tested of the subsystem, so that the clock to be tested responds to the clock excitation configuration information to obtain a response result.

The clock driver can be configured through the register configuration interface, and the clock excitation configuration information is written into the corresponding register, so that the clock excitation configuration information is driven to the clock to be tested.

The clock driver is also used to pass clock excitation configuration information to the reference model, step 2044.

In an alternative example, the clock driver may package the clock excitation configuration information into a structure (auto _ model) to be transferred to the reference model (reference model).

And 2045, determining expected data of the clock to be measured according to the clock excitation configuration information by using the reference model, and transmitting the expected data to the scoring board.

Specifically, an auto _ model (automation model) is configured in the reference model, for example, the auto _ model is generated based on a script and configured in the reference model, the reference model simulates the behavior of the DUT based on the clock information and the clock excitation configuration information in the auto _ model, calculates the expected frequency, the expected duty ratio, the expected gating state, and the like of the current clock to be measured, and packages the expected frequency, the expected duty ratio, the expected gating state, and the like, and then transmits the package to a scoreboard (scoreboard). FIG. 8 is a schematic diagram of a structure data format of an auto _ model according to an exemplary embodiment of the disclosure. Wherein peri _ sys _ CLK represents a structural body, which may include a plurality of clocks, CLK _ pci represents a clock name, PCIE _ CLK _ CFG _ ADDR represents a configured register address, mux represents a selector, div represents frequency division, 24000 + 96000 represents an expected frequency corresponding to each mux, PCIE _ CGM _ CTL _ ADDR represents a register address for gating control, and CGM level represents a clock gating off value. The specific structure data may be set according to actual requirements, and is not limited to the above. Based on the auto _ model, in conjunction with the clock excitation configuration information passed by the clock driver, a desired frequency, a desired duty cycle, a desired gating state, etc. are calculated.

Step 2046, the monitor is used to monitor the actual data of the clock to be measured, and transmit the data to the scoreboard.

The actual data of the clock to be measured is the actual data generated by the clock to be measured responding to the excitation, for example, the monitor samples the clock signal of the clock to be measured, and calculates the actual frequency, duty ratio, gating state and the like according to the sampling result, and the specific working principle of the monitor is not described herein again.

And 2047, comparing the actual data with the expected data by the score counting board to obtain and output a comparison result.

The scoring board is used for comparing the data such as the actual frequency, the actual duty ratio and the actual gating state monitored by the monitor with the corresponding data such as the expected frequency, the expected duty ratio and the expected gating state respectively and inputting a comparison result.

In an optional example, fig. 9 is a schematic flowchart of step 201 provided in an exemplary embodiment of the present disclosure, in this example, the acquiring clock information corresponding to at least one subsystem of the system on chip in step 201 includes:

in step 2011, based on the clock of each subsystem of the system on chip, the subsystem clock feature description information corresponding to each subsystem is obtained.

The subsystem clock characteristic description information is related information describing characteristics of a subsystem clock generator, for example, for a peripheral subsystem, the characteristics of the clock generator may include a clock number, a clock name, an input clock source frequency point, a frequency division coefficient, a frequency division default value, a gating enable, a clock off value, whether a MUX has glitch, and the like. The specific subsystem clock characteristic description information can be set according to actual requirements.

For example, a clock characterization table file corresponding to each subsystem may be created for each subsystem, and each subsystem corresponds to one clock characterization table file. Each clock characterization table file records the characteristics of each clock generator in the subsystem. As shown in table 1, in an actual application, a table format capable of covering all subsystems, that is, a table field covers characteristics of all subsystems, may be set for a peripheral subsystem partial clock characteristic table, and may be specifically set according to actual requirements.

TABLE 1

Step 2012, determining clock information corresponding to at least one subsystem based on the subsystem clock characteristic description information corresponding to each subsystem.

Specifically, the subsystem clock characteristic description information may be analyzed based on a preset analysis rule, and converted into a required target format for storage, so as to be used for subsequent generation and verification of the clock verification environment.

Illustratively, the content of each field is extracted from the clock characteristic description table file corresponding to each subsystem based on a preset parsing rule, and a clock information database corresponding to each subsystem is created, where the clock information database includes: the clock source comprises a clock number, a clock signal name, a frequency point value selected by the MUX when the clock source is input, a default value of the MUX, a frequency division coefficient, a frequency division default value, whether the frequency division has burrs or not, whether gating enable is register controllable or top layer fixed connection normally open, a clock level value after clock turn-off, whether the clock source is switched to introduce the burrs or not and the like. The specific parsing rule can be set according to actual requirements.

The method adopts a table mode to describe the clock characteristics of the subsystem, so that cross-platform multiplexing and subsequent version iteration updating can be conveniently carried out.

In one optional example, generation of the clock verification environment and clock verification of the present disclosure is implemented based on a UVM verification platform. The method is beneficial to constructing a complex subsystem clock verification environment, reduces the verification convergence time of the clock, reduces the subsequent development workload, is convenient for iterative use of a plurality of projects, effectively saves the labor cost and improves the completeness of verification.

In an alternative example, the method of generating the clock verification environment of the present disclosure may be implemented in any practicable language.

In an optional example, the clock verification environment generation method disclosed by the present disclosure may be implemented based on an efficient high-level data structure and object-oriented programming, and may be combined with any implementable standard library, so as to provide convenience for developers to work, and effectively save the workload of repeated development and verification of each subsystem clock verification environment in the SoC.

In an alternative example, fig. 10 is a schematic diagram of an automated clock verification process provided by an exemplary embodiment of the present disclosure. The verification process comprises the following steps:

1. and acquiring a clock characteristic description table of each subsystem of the SoC.

The clock tree division is carried out on the complex SoC system according to the subsystems, subsystem clock characteristic description table files are created, and the characteristics of each clock generator in the subsystems are recorded in each table.

2. And the script analyzes the clock characteristic description table of each subsystem to obtain the clock information corresponding to each subsystem, and stores the clock information into the clock information database of the corresponding subsystem.

And analyzing all clock information in the clock characteristic description table of each subsystem through a script, and creating a subsystem clock information database of the whole SoC. The information database comprises: the clock source comprises a clock number, a clock signal name, a frequency point value selected by the MUX when the clock source is input, a default value of the MUX, a frequency division coefficient, a frequency division default value, whether the frequency division has burrs or not, whether gating enable is register controllable or top layer fixed connection normally open, a clock level value after clock turn-off, whether the clock source is switched to introduce the burrs or not and the like.

3. It is determined whether all subsystems have been traversed. If yes, turning to the step 4, otherwise, returning to the step 2, and continuing to analyze the clock characteristic description table of the next subsystem.

4. And the script generation subsystem clock UVM verifies the environment template.

And building a verification environment template of the subsystem clock tree (namely the subsystem clock verification environment template) based on the UVM verification methodology. And expressing the content of each subsystem verification environment needing to be changed by using variables in the template so as to perform templated rendering through transmitting parameters in the subsequent verification process and establish a clock verification environment corresponding to each subsystem. And automatically generating a subsystem clock enumeration structure in the UVM environment based on the clock information in the information database, and during subsequent verification, automatically generating the connection between the clock verification environment and the DUT by using the enumeration structure to perform indexing.

5. And rendering the sub-system clock UVM verification environment template by adopting a template engine based on the clock information corresponding to each subsystem respectively to generate the clock verification environment corresponding to each subsystem respectively.

And rendering through a template engine according to the generated subsystem clock UVM verification environment template, so that clock verification environments corresponding to the systems respectively can be generated for verification.

6. It is determined whether all subsystems have been traversed. If yes, ending, otherwise, returning to the step 5 to continue the rendering of the next subsystem.

Any of the clock verification environment generation methods provided by the embodiments of the present disclosure may be performed by any suitable device having data processing capabilities, including but not limited to: terminal equipment, a server and the like. Alternatively, any one of the clock verification environment generation methods provided by the embodiments of the present disclosure may be executed by a processor, for example, the processor may execute any one of the clock verification environment generation methods mentioned in the embodiments of the present disclosure by calling a corresponding instruction stored in a memory. And will not be described in detail below.

Exemplary devices

Fig. 11 is a schematic structural diagram of a clock verification environment generation apparatus according to an exemplary embodiment of the present disclosure. The apparatus of this embodiment may be used to implement the corresponding method embodiment of the present disclosure, and the apparatus shown in fig. 11 includes: a first obtaining module 501 and a first processing module 502.

A first obtaining module 501, configured to obtain clock information corresponding to at least one subsystem of a system on chip; the first processing module 502 is configured to generate a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem acquired by the first acquiring module 501 and a pre-established subsystem clock verification environment template.

Fig. 12 is a schematic structural diagram of a clock verification environment generation apparatus according to another exemplary embodiment of the present disclosure.

In one optional example, the first processing module 502 includes: the first processing unit 5021 is configured to render the subsystem clock verification environment template according to a preset rendering mode based on the clock information corresponding to the subsystem, and obtain a target clock verification environment corresponding to the subsystem.

In one optional example, the apparatus of the present disclosure further comprises: the second processing module 601 is configured to establish a subsystem clock verification environment template based on clock information corresponding to each subsystem of the system on chip.

In an alternative example, fig. 13 is a schematic structural diagram of a clock verification environment generation apparatus according to still another exemplary embodiment of the present disclosure. In this example, the second processing module 601 includes:

the second processing unit 6011 is configured to determine preset variables corresponding to the environment components and initial values corresponding to the preset variables based on clock information corresponding to each subsystem of the system on chip, and establish a connection relationship between the environment components to obtain a subsystem clock verification environment template.

In an optional example, the first processing unit 5021 is specifically configured to: traversing the subsystem clock verification environment template, determining the value of a preset variable in each environment component in the subsystem clock verification environment template according to the clock information corresponding to the subsystem, and obtaining the target clock verification environment corresponding to the subsystem.

In one optional example, the apparatus of the present disclosure further comprises: the third processing module 503 is configured to establish a connection relationship between the target clock verification environment and the clock to be tested of the subsystem, so that the target clock verification environment drives the stimulus to the clock to be tested.

In one optional example, the apparatus of the present disclosure further comprises: the fourth processing module 504 is configured to verify the clock to be tested of the subsystem corresponding to the target clock verification environment based on the target clock verification environment, and obtain a verification result corresponding to the clock to be tested.

In one optional example, the target clock verification environment includes a clock data component, a clock stimulus generator component, a clock driver, a reference model, a scoreboard, and a monitor; the fourth processing module 504 is specifically configured to: generating clock excitation configuration information based on the clock data component; communicating clock stimulus configuration information to a clock driver based on a clock stimulus generator component; driving the clock excitation configuration information to a clock to be tested based on the connection relation between the clock driver and the clock to be tested of the subsystem through the target clock verification environment, so that the clock to be tested responds to the clock excitation configuration information to obtain a response result; transferring clock excitation configuration information to a reference model based on a clock driver; determining expected data of the clock to be tested according to the clock excitation configuration information based on the reference model, and transmitting the expected data to the scoring board; monitoring actual data of a clock to be measured based on a monitor, and transmitting the actual data to a scoring board; and comparing the actual data with the expected data based on the score board, and obtaining and outputting a comparison result.

In an optional example, the first obtaining module 501 includes: the acquisition unit 5011 and the determination unit 5012. The acquiring unit 5011 is configured to acquire, based on clocks of subsystems of the system on chip, subsystem clock characteristic description information corresponding to each subsystem; the determining unit 5012 is configured to determine clock information corresponding to at least one subsystem based on the subsystem clock characteristic description information corresponding to each of the subsystems acquired by the acquiring unit 5011.

Exemplary electronic device

An embodiment of the present disclosure further provides an electronic device, including: a memory for storing a computer program;

a processor, configured to execute the computer program stored in the memory, and when the computer program is executed, implement the method for generating a clock verification environment according to any of the above embodiments of the present disclosure.

Fig. 14 is a schematic structural diagram of an application embodiment of the electronic device of the present disclosure. In this embodiment, the electronic device 10 includes one or more processors 11 and a memory 12.

The processor 11 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

Memory 12 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, Random Access Memory (RAM), cache memory (cache), and/or the like. The non-volatile memory may include, for example, Read Only Memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium and executed by processor 11 to implement the methods of the various embodiments of the disclosure described above and/or other desired functionality. Various contents such as an input signal, a signal component, a noise component, etc. may also be stored in the computer-readable storage medium.

In one example, the electronic device 10 may further include: an input device 13 and an output device 14, which are interconnected by a bus system and/or other form of connection mechanism (not shown).

The input means 13 may be, for example, a microphone or a microphone array as described above for capturing an input signal of a sound source.

The input device 13 may also include, for example, a keyboard, a mouse, and the like.

The output device 14 may output various information including the determined distance information, direction information, and the like to the outside. The output devices 14 may include, for example, a display, speakers, a printer, and a communication network and its connected remote output devices, among others.

Of course, for simplicity, only some of the components of the electronic device 10 relevant to the present disclosure are shown in fig. 14, omitting components such as buses, input/output interfaces, and the like. In addition, the electronic device 10 may include any other suitable components depending on the particular application.

Exemplary computer program product and computer-readable storage Medium

In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product comprising computer program instructions that, when executed by a processor, cause the processor to perform steps in methods according to various embodiments of the present disclosure as described in the "exemplary methods" section of this specification above.

The computer program product may write program code for carrying out operations for embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, embodiments of the present disclosure may also be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps in methods according to various embodiments of the present disclosure as described in the "exemplary methods" section above of this specification.

The computer-readable storage medium may take any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure is not intended to be limited to the specific details so described.

In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The block diagrams of devices, apparatuses, systems referred to in this disclosure are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".

The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order for the steps of the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be embodied as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

It is also noted that in the devices, apparatuses, and methods of the present disclosure, each component or step can be decomposed and/or recombined. These decompositions and/or recombinations are to be considered equivalents of the present disclosure.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.

Claims

1. A method of generating a clock verification environment, comprising:

acquiring clock information corresponding to at least one subsystem of the system on chip;

and generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template.

2. The method of claim 1, wherein the generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template comprises:

rendering the subsystem clock verification environment template according to a preset rendering mode based on the clock information corresponding to the subsystem, and obtaining a target clock verification environment corresponding to the subsystem.

3. The method of claim 1, wherein before generating the target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template, the method further comprises:

and establishing a subsystem clock verification environment template based on the clock information respectively corresponding to each subsystem of the system on chip.

4. The method of claim 3, wherein the establishing the subsystem clock verification environment template based on the clock information corresponding to each subsystem of the system on chip comprises:

and determining preset variables corresponding to the environment components and initial values corresponding to the preset variables based on clock information corresponding to the subsystems of the system on chip, and establishing a connection relation between the environment components to obtain a subsystem clock verification environment template.

5. The method of claim 2, wherein the rendering the subsystem clock verification environment template according to a preset rendering mode based on the clock information corresponding to the subsystem to obtain the target clock verification environment corresponding to the subsystem comprises:

traversing the subsystem clock verification environment template, determining the value of a preset variable in each environment component in the subsystem clock verification environment template according to the clock information corresponding to the subsystem, and obtaining a target clock verification environment corresponding to the subsystem.

6. The method of claim 1, wherein after generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template, the method further comprises:

and establishing a connection relation between the target clock verification environment and a clock to be tested of the subsystem, so that the target clock verification environment drives excitation to the clock to be tested.

7. The method of claim 6, wherein after the establishing a connection relationship between the target clock verification environment and a clock under test of the subsystem, further comprising:

and verifying the to-be-tested clock of the subsystem corresponding to the target clock verification environment based on the target clock verification environment to obtain a verification result corresponding to the to-be-tested clock.

8. The method of claim 7, wherein the target clock verification environment comprises a clock data component, a clock stimulus generator component, a clock driver, a reference model, a scoreboard, and a monitor; the verifying the to-be-tested clock of the subsystem corresponding to the target clock verification environment based on the target clock verification environment to obtain a verification result corresponding to the to-be-tested clock includes:

the clock data component is used for generating clock excitation configuration information;

the clock excitation generator component is used for transmitting the clock excitation configuration information to the clock driver;

the clock driver is used for driving the clock excitation configuration information to the clock to be tested based on the connection relation between the target clock verification environment and the clock to be tested of the subsystem, so that the clock to be tested responds to the clock excitation configuration information to obtain a response result;

the clock driver is further configured to communicate the clock excitation configuration information to the reference model;

the reference model is used for determining expected data of the clock to be tested according to the clock excitation configuration information and transmitting the expected data to the scoring board;

the monitor is used for monitoring the actual data of the clock to be tested and transmitting the actual data to the scoring board;

and the scoring board is used for comparing the actual data with the expected data to obtain and output a comparison result.

9. The method of any one of claims 1-8, wherein the obtaining clock information corresponding to at least one subsystem of the system-on-chip comprises:

acquiring subsystem clock characteristic description information corresponding to each subsystem based on the clock of each subsystem of the system on chip;

and determining the clock information corresponding to the at least one subsystem based on the subsystem clock characteristic description information corresponding to each subsystem.

10. An apparatus for generating a clock verification environment, comprising:

the first acquisition module is used for acquiring clock information corresponding to at least one subsystem of the system on chip;

and the first processing module is used for generating a target clock verification environment corresponding to the subsystem based on the clock information corresponding to the subsystem and a pre-established subsystem clock verification environment template.

11. A computer-readable storage medium storing a computer program for executing the method for generating a system-on-chip clock verification environment according to any one of claims 1 to 9.

12. An electronic device, the electronic device comprising:

a processor;

a memory for storing the processor-executable instructions;

the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for generating a system-on-chip clock verification environment as claimed in any one of claims 1 to 9.