CN112286750A - GPIO (general purpose input/output) verification method and device, electronic equipment and medium - Google Patents
GPIO (general purpose input/output) verification method and device, electronic equipment and medium Download PDFInfo
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Abstract
The application provides a GPIO verification method, a device, an electronic device and a medium, wherein the method comprises the following steps: acquiring first information for verifying the current function, and reading second information to be detected of the GPIO module; comparing the first information with the second information to obtain a verification result of the current function; when the verification result is that the verification is successful, verifying the next function; and when the verification result is that the verification fails, stopping the verification and outputting corresponding verification information. According to the method and the device, the first information of the current verified function is compared with the second information to be detected, the verification result is obtained, the verification efficiency is improved by automatically analyzing the verification result, the verification of the next function is executed after the verification is successful, the detection of all functions is covered, the verification is stopped when the verification fails, the occurrence of follow-up continuous errors caused by the preceding stage errors is prevented, the verification efficiency is improved, the designer can quickly position the wrong position through the output verification information, and the accuracy of the positioning errors is improved.
Description
Technical Field
The application relates to the technical field of GPIO verification, in particular to a GPIO verification method, a GPIO verification device, electronic equipment and a medium.
Background
In the server, a BMC (Baseboard management Controller) chip needs to receive operating state information from a Central Processing Unit (CPU) and control various devices on a motherboard, such as a Serial port, a Universal Serial Bus (USB) port, a fan, and the like, so that the BMC chip generates many external interface pins, and often needs a GPIO (General-purpose-input/output) module to multiplex the interfaces in order to reduce the number of the interfaces. For example, in the BMC, 244 GPIO pins are implemented, which can support the multiplexing of 732 interfaces in total, thereby greatly reducing the number of pins. For the GPIO module, the following functions are mainly included: GPIO input and output functions, interrupt, Debounce functions and multiplexing functions. The verification of GPIOs in the related art is mainly excited by writing tests, but it is difficult to cover all the functions of GPIOs, and the functions of GPIOs are inefficient.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a GPIO verification method, a GPIO verification device, electronic equipment and a GPIO verification medium, which can improve the efficiency of function verification and the accuracy of error position positioning. The specific scheme is as follows:
the application provides a GPIO verification method, which comprises the following steps:
acquiring first information for verifying the current function, and reading second information to be detected of the GPIO module;
comparing the first information with the second information to obtain a verification result of the current function;
when the verification result is that the verification is successful, verifying the next function;
and when the verification result is that the verification fails, stopping the verification and outputting corresponding verification information.
Preferably, the acquiring first information used for verifying the current function and reading second information to be detected of the GPIO module includes:
if the verification of the current function is read-write verification, acquiring a first address and write data sent by a bus generator; the first address is an address obtained by an address index list through a counter, the write data is data generated by a random number generator of the bus generator, and the first information corresponds to the write data;
reading read data corresponding to the first address in the GPIO module, wherein the second information corresponds to the read data;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the write data and the read data meet preset conditions or not;
if the preset condition is met, determining that the verification result is read-write verification success;
and if the preset condition is not met, determining that the verification result is read-write verification failure, and outputting the first address, the read data and the write data.
Preferably, the acquiring first information used for verifying the current function and reading second information to be detected of the GPIO module includes:
if the verification of the current function is interrupt verification, acquiring a first input signal input by an external signal generator into the GPIO module; the first input signal is screened out by utilizing the read data of a direction register configured in the bus transaction generator according to the received signal to be detected of the external signal generator;
reading a first numerical value in a receiving data register of the GPIO module corresponding to the first input signal;
reading a second numerical value corresponding to the first input signal in an interrupt state register in the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the first numerical value and the second numerical value meet a preset verification condition;
if so, determining that the verification result is successful in interrupt verification;
if not, determining that the verification result is the interruption verification failure.
Preferably, the acquiring first information used for verifying the current function and reading second information to be detected of the GPIO module includes:
if the verification of the current function is the input and output function verification, acquiring data of a direction register in a bus transaction generator;
screening out an input signal and an output signal of an external signal generator for the GPIO module according to the data;
reading a first corresponding value of a receiving data register and a second corresponding value of a sending data register of the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the input signal is consistent with the first corresponding value or not and whether the output signal is consistent with the second corresponding value or not;
if the input function and the output function are consistent, determining that the verification result is that the input and output function verification is successful;
and if the input and output functions are inconsistent, determining that the verification result is input and output function verification failure.
Preferably, the acquiring first information used for verifying the current function and reading second information to be detected of the GPIO module includes:
if the verification of the current function is anti-jitter function verification, acquiring a second input signal in an external signal generator, and determining a level count value of the second input signal;
when the level count value reaches a preset anti-jitter threshold value, taking the second input signal as an effective signal;
reading a signal of a receiving data register of the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the effective signal is consistent with a signal of a receiving data register of the GPIO module or not;
if the verification result is consistent with the anti-shaking function verification result, the anti-shaking function verification is determined to be successful;
and if the verification result is inconsistent, determining that the verification result is the anti-jitter function verification failure.
Preferably, the acquiring first information used for verifying the current function and reading second information to be detected of the GPIO module includes:
if the verification of the current function is interface multiplexing verification, acquiring a multiplexing signal of a signal multiplexing generator, wherein the multiplexing signal is input into the GPIO module;
acquiring an output signal of an external signal generator, wherein the output signal is output by the multiplexing signal through the external signal generator;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the multiplexing signal is consistent with the output signal;
if the verification result is consistent with the interface multiplexing verification result, the verification result is determined to be that the interface multiplexing verification is successful;
and if the verification result is inconsistent, determining that the verification result is interface multiplexing verification failure.
Preferably, the method further comprises the following steps:
and acquiring a verification instruction, and verifying the corresponding function according to the function information in the verification instruction.
The application provides a GPIO verifying attachment, includes:
the acquisition module is used for acquiring first information used for verifying the current function and reading second information to be detected of the GPIO module;
a verification result obtaining module, configured to compare the first information with the second information to obtain a verification result of the current function;
the next function verifying module is used for verifying the next function when the verifying result is that the verification is successful;
and the verification stopping module is used for stopping verification and outputting corresponding verification information when the verification result is verification failure.
The application provides an electronic device, including:
a memory for storing a computer program;
and the processor is used for realizing the steps of the GPIO verification method when executing the computer program.
The present application provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the GPIO verification method as described above.
The application provides a GPIO verification method, which comprises the following steps: acquiring first information for verifying the current function, and reading second information to be detected of the GPIO module; comparing the first information with the second information to obtain a verification result of the current function; when the verification result is that the verification is successful, verifying the next function; and when the verification result is that the verification fails, stopping the verification and outputting corresponding verification information.
Therefore, according to the method and the device, the first information of the current verified function is compared with the second information to be detected to obtain the verified result, the verified result is automatically analyzed, the verification efficiency is improved, the verification of the next function is executed after the verification is successful, the detection of all functions is covered, the verification is stopped when the verification fails, the occurrence of subsequent continuous errors caused by the errors of the preceding stage is prevented, the verification efficiency is improved, designers can quickly position the wrong position through the output verification information, and the accuracy of the positioning errors is improved.
This application still provides a GPIO verification device, electronic equipment and medium simultaneously, all has above-mentioned beneficial effect, and it is no longer repeated here.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a GPIO verification method provided in an embodiment of the present application;
fig. 2 is a schematic diagram of an entire verification platform according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of a verification provided by an embodiment of the present application;
fig. 4 is a schematic structural diagram of a GPIO verification device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For the GPIO module, the following functions are mainly included: GPIO input and output functions, interrupt, Debounce functions and multiplexing functions. The verification of GPIOs in the related art is mainly excited by writing tests, but it is difficult to cover all the functions of GPIOs, and the functions of GPIOs are inefficient.
Based on the above technical problem, the present embodiment provides a GPIO verification method, which can improve the efficiency of function verification and the accuracy of error location positioning, specifically referring to fig. 1, where fig. 1 is a flowchart of the GPIO verification method provided in the present embodiment, and specifically includes:
s101, acquiring first information for verifying the current function, and reading second information to be detected of the GPIO module;
the present embodiment does not limit the current functions. It is understood that the verification of the function of the GPIO module includes, but is not limited to: read-write verification, interrupt verification, input-output function verification, anti-jitter function verification, and interface multiplexing verification. In this embodiment, the current function may be a read/write function, an interrupt function, an input/output function, an anti-jitter function, an interface multiplexing function, and may be set by a user in a user-defined manner as long as the purpose of this embodiment can be achieved. Wherein the first information is standard information as the second information. It is to be understood that the second information is different for different current functions. For example, the current function 1 corresponds to the second information 1; the current function 2 corresponds to the second information 2; the current function 3 corresponds to the second information 3.
S102, comparing the first information with the second information to obtain a verification result of the current function;
in this embodiment, the first information and the second information may be automatically analyzed to obtain the verification result, so that the verification efficiency is improved, where the verification result includes a verification success and a verification failure.
S103, when the verification result is that the verification is successful, verifying the next function;
in this embodiment, after the verification is successful, the verification of the next function is performed, and as a result, in this embodiment, multiple functions may be verified. In an implementation, when the functions verified by the system are function a, function b, and function c, function b is verified after function a is successfully verified, if function b is successfully verified, function c is verified, and then verification is stopped, and at this time, verification of all functions is completed, and when function b fails, verification is stopped. Further, when the verification is successful, the method may further include outputting a verification result, that is, a verification result of successful verification.
And S104, stopping verification and outputting corresponding verification information when the verification result is that the verification fails.
When the verification fails, the verification is stopped, so that continuous errors of subsequent functional verification caused by previous-stage errors are prevented, and the verification efficiency is improved; and outputting corresponding verification information, wherein the verification information comprises a verification result, the first information, the second information and relevant information.
Further, in order to improve the flexibility of GPIO function verification, the GPIO verification method further includes:
and acquiring a verification instruction, and verifying the corresponding function according to the function information in the verification instruction.
It can be understood that, in order to improve the flexibility of the verification platform, an additional control signal for verification may be added to select a function to be verified, specifically, the corresponding function is verified according to the function information in the verification instruction, further, after the verification is completed, the location of the error is located through the printed file, and the verification platform mainly performs a test based on a random number, does not need to generate many excitation signals, has high randomness, and can implement multiple times of iterative verification through the control signal, thereby improving the coverage rate of the verification.
Based on the technical scheme, the embodiment compares the first information of the current verified function with the second information to be detected to obtain a verified result, automatically analyzes the verified result to improve verification efficiency, executes verification of the next function after verification is successful, covers detection of all functions, stops verification when verification fails, prevents occurrence of subsequent continuous errors caused by previous stage errors, improves verification efficiency, enables designers to quickly position wrong positions through output verification information, and improves accuracy of positioning errors.
Referring to fig. 2, fig. 2 is a schematic diagram of an entire verification platform according to an embodiment of the present application, including:
wherein, the DUT (Design under Test, Design to be tested) is the GPIO module.
The address index list is used for storing address information of a relevant register of the GPIO module, the address information of the GPIO module is stored in a memory before verification, and in the verification process, the address index list can calculate the address of the register in the forms of counting by a counter and the like, is used for providing a configuration address for functions of register reading and writing, interruption, basic input and output under GPIO, debounce, module interface multiplexing and the like, and sends the address to the bus transaction generator.
The bus transaction generator is used for generating control signals based on a bus protocol and providing the DUT with stimulation simulating a system bus. The bus transaction generator mainly comprises two parts: a read register module and a write register module. Moreover, the Bus transaction generator can flexibly implement a plurality of Bus protocols, such as an AHB (Advanced High Performance Bus), an APB (Advanced Peripheral Bus) Bus protocol, and the like, through configuration such as macro definition. The bus address is from the address transmitted by the address index list, the bus data can be generated by an internal random number generator, the complexity caused by handwriting the bus data is avoided, the verification complexity can be simplified, and the coverage rate and the randomness of the verification can be improved through multiple iterations.
The signal multiplexing generator is used for simulating signals generated by other modules needing multiplexing, and the signals include input signals, direction control signals and output signals, wherein the other modules include Serial Peripheral Interfaces (SPI) and the like. The input signal and the direction control signal are generated by an internal random number generator, and the output signal is stored in an internal memory.
The external signal generator is used for simulating signals interacted with the system from the outside, and comprises an input signal and an output signal. The input signal and the direction control signal are generated by an internal random number generator, and the output signal is stored in an internal memory.
The comparison and conclusion generation chip (comparison and conclusion generation module) is used for verifying the results of the functions of register read-write, interruption, basic input and output under GPIO, debounce, module interface multiplexing and the like of the GPIO module.
In an implementation manner, the present embodiment provides a specific verification of a GPIO function, specifically, acquiring first information used for verifying a current function, and reading second information to be detected of a GPIO module, where the method includes: if the verification of the current function is read-write verification, acquiring a first address and write data sent by a bus generator; the first address is an address obtained by the address index list through a counter, the write data is data generated by a random number generator of the bus generator, and the first information corresponds to the write data; reading read data corresponding to a first address in the GPIO module, wherein the second information corresponds to the read data;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including: judging whether the write data and the read data meet preset conditions or not; if the preset condition is met, determining that the verification result is successful read-write verification; and if the preset condition is not met, determining that the verification result is read-write verification failure, and outputting a first address, read data and write data.
Wherein, if the current function of the verification is reading and writing, the bus generator obtains a first address from the address index list through the counter, then the bus generator generates write data by using the random number generator, wherein, the writing data is used as standard data, namely first information, the writing data is written into a first address of an AND register of the GPIO module through a bus generator, then, the comparison and conclusion generating chip obtains the first address and the write data from the bus generator, reads the read data of the register corresponding to the first address from the GPIO module, the read data is used as the second information, then the read data and the write data are judged according to preset conditions, if the preset conditions are met, the read-write verification is successful, if the preset condition is not met, the read-write verification fails, and the first address, the read data and the write data are output simultaneously, so that a user can see the wrong position conveniently.
In brief, for the register read-write function of the GPIO module, the address and data of the write operation and the address and data of the read operation generated in the bus transaction generator are sent to the comparison and conclusion generating chip, the read-write data of the same address are compared, that is, whether the preset condition is met is determined (not limited to simple equal comparison, but also comprehensive determination of the un-writable bit, the read-only bit, the register with dependency relationship, and the data bit is included in the module).
In another implementation manner, the present embodiment provides a specific verification of a GPIO function, specifically, acquiring first information used for verifying a current function, and reading second information to be detected of a GPIO module, where the method includes: if the verification of the current function is interrupt verification, acquiring a first input signal input by an external signal generator into the GPIO module; the first input signal is screened out by using the read data of the direction register configured in the bus transaction generator according to the received signal to be detected of the external signal generator; reading a first numerical value in a receiving data register of the GPIO module corresponding to the first input signal; reading a second numerical value corresponding to the first input signal in an interrupt state register in the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including: judging whether the first numerical value and the second numerical value meet a preset verification condition or not; if so, determining that the verification result is that the interrupt verification is successful; if not, determining that the verification result is the interruption verification failure.
Further elaborating on the interrupt, when the GPIO input function is used, a corresponding interrupt, such as an interrupt in the form of a high level, a rising edge, or the like, may be selectively generated, that is, when a first input signal input into the system from the outside (an external signal generator) is 1 (a last first input signal is 0), if the high level interrupt is selected at this time, the GPIO may generate an interrupt signal to trigger the CPU to perform a corresponding interrupt operation. In this embodiment, the preset verification condition is not limited, and it needs to be concluded by integrating information such as configured interrupt manner, for example, when the configuration rising edge triggers the interrupt, the interrupt is generated only when the first input signal changes from 0 to 1, and no interrupt is generated when the first input signal changes from 1 to 1.
For the interrupt function, the signal to be detected in the external signal generator is transmitted to the comparison and conclusion generation chip, the first input signal in the external signal generator is screened out by reading the data of the direction register configured in the bus transaction generator, and is comprehensively compared with the interrupt trigger register, the interrupt state register and the receiving data register of the GPIO module, for example, when the first input signal is 1 (the last first input signal is 0), the interrupt trigger state of the first input signal is configured to be high level, at the moment, the corresponding bit (the second value) of the interrupt state register is compared with the corresponding bit (the first value) in the receiving data register, if the first input signal is 1, the interrupt is generated correctly, the comparison result is output to a file correctly, and if the first input signal is not correct, the relevant input signal, the receiving state register and the data register are output, The information such as the interrupt trigger register, the interrupt status register, the direction register, etc. is also output to the file.
In an implementation manner, the present embodiment provides a specific verification of a GPIO function, specifically, acquiring first information used for verifying a current function, and reading second information to be detected of a GPIO module, where the method includes: if the verification of the current function is the input and output function verification, acquiring data of a direction register in the bus transaction generator; screening out an input signal and an output signal of the external signal generator for the GPIO module according to the data; reading a first corresponding value of a receiving data register and a second corresponding value of a sending data register of the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including: judging whether the input signal is consistent with the first corresponding value or not and whether the output signal is consistent with the second corresponding value or not; if the input function and the output function are consistent, determining that the verification result is that the input and output function verification is successful; and if the input and output functions are inconsistent, determining that the verification result is that the input and output function verification fails.
The GPIO module itself needs to configure corresponding registers, such as a data register and a direction register, so that the system can communicate with the outside through the GPIO module, and at this time, the CPU in the system usually controls and communicates.
For the basic input and output function under the GPIO, an input signal and an output signal in an external signal generator are screened out by reading data of a direction register configured in a bus transaction generator, a first corresponding value of the input signal and a receiving data register and a second corresponding value of the output signal and a sending data register are compared in a comparison and conclusion generating chip, whether the input and output function is correct or not is judged, if the input and output function is correct, the comparison result is output to a file, and if the comparison result is incorrect, the values of the input signal, the receiving data register, the output signal and the sending data register are also output to the file.
In an implementation manner, the present embodiment provides a specific verification of a GPIO function, specifically, acquiring first information used for verifying a current function, and reading second information to be detected of a GPIO module, where the method includes: if the verification of the current function is anti-jitter function verification, acquiring a second input signal in an external signal generator, and determining a level count value of the second input signal; when the level counting value reaches a preset anti-jitter threshold value, taking the second input signal as an effective signal; reading a signal of a receiving data register of the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including: judging whether the effective signal is consistent with the signal of a data receiving register of the GPIO module or not; if the verification result is consistent with the anti-shaking function verification result, the anti-shaking function verification is determined to be successful; and if the verification result is inconsistent, determining that the verification result is that the anti-jitter function fails to verify.
The Debounce function is specifically that when the GPIO input function is used, a corresponding Debounce parameter may be selected and used, so as to prevent interference of external burrs and other uncertain factors, and ensure system stability. For example, when the debounce parameter is set to 10, when the externally input high level or low level continues for more than 10 clock cycles, the data is considered to be valid data, and the input data is stored in the corresponding register, so that the CPU can read and perform subsequent operations.
For the debounce function, the comparison and conclusion generation chip integrates a debounce calculation unit mainly composed of two counters, when the second input signal is 1, adding 1 to the count value of the high level counter in each period and clearing the count value of the low level counter, when the input signal is 0, adding 1 to the count value of the low level counter in each period and clearing the count value of the high level counter, when the counting value of one counter reaches the preset debounce value of the GPIO, the second input signal received on behalf of the GPIO is a valid input signal (valid signal), which is stored at this time, and compares the data with the signal (corresponding value, general signal is expressed by random number) of the data register received in the GPIO module, if the result is the same, the comparison result is output to the file correctly, if the result is different, the debounce register, the direction register, the received data register and the effective input signal are also output to the file.
In an implementation manner, the present embodiment provides a specific verification of a GPIO function, specifically, acquiring first information used for verifying a current function, and reading second information to be detected of a GPIO module, where the method includes: if the verification of the current function is interface multiplexing verification, acquiring a multiplexing signal of a signal multiplexing generator, wherein the multiplexing signal is input into a GPIO module; acquiring an output signal of an external signal generator, wherein the output signal is output by multiplexing signals through the external signal generator;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including: judging whether the multiplexing signal is consistent with the output signal; if the verification result is consistent with the interface multiplexing verification result, the verification result is determined to be that the interface multiplexing verification is successful; and if the verification result is inconsistent, determining that the interface multiplexing verification fails.
The multiplexing function is to configure a GPIO internal interface, and interface multiplexing of other modules in the system can be achieved, for example, interfaces of modules such as I2C (Inter-Integrated Circuit) and lpc (low pin count bus) can perform data interaction with the outside through the GPIO interface. For the module interface multiplexing function, the signal multiplexing generator configures GPIO as the multiplexing function, and configures the internal input/output and direction control signal of the system to simulate the real system use environment, the comparison and conclusion generating chip judges and compares the configuration, input/output and control signal of the signal multiplexing generator and the input/output signal of the external signal generator to judge the correctness of the multiplexing function, if the result is correct, the comparison result is output to the file correctly, and if the result is different, the signals of the two signal generators are also output to the file.
Based on the above embodiments, the present embodiment is further explained with respect to GPIO verification: referring to fig. 3, fig. 3 is a flowchart of a verification method according to an embodiment of the present disclosure.
In the embodiment, after the verification of the part I is performed, the verification of the part II is performed again after the verification passes, and the verification of the part III is performed after the verification passes until the verification stopping instruction is received, and the verification is stopped. And I part register read-write verification. Firstly, sequentially generating address information of each register, then sequentially configuring each register by generating a bus protocol write signal (numerical values are generated by random numbers), writing write data into a data register of the GPIO, reading out the numerical values (read data) of each register, comparing and obtaining a conclusion. And (II) part. Different register addresses (required registers such as part I) are generated for different functions, corresponding registers are firstly configured through bus writing (generated in a random number mode), written into data registers, external signals are configured (generated in a random number mode) and signal values are stored, then values of the registers of the corresponding functions are read, and finally comparison is carried out to obtain a conclusion. And (III) part. Firstly, configuring and storing external input and output signals (generated by a random number mode), then configuring and storing multiplexing signals (generated by a random number mode), including internal multiplexing selection and multiplexed input and output and direction control signals, and finally comparing and drawing a conclusion.
In order to improve the flexibility of the verification platform, an additional control signal for verification can be added to select a function to be verified, after verification is completed, a designer can easily locate an error position through a printed file, the verification platform is mainly tested based on random numbers, a plurality of excitation signals are not required to be generated, the randomness is high, multiple times of iteration verification can be realized through the control signal, and the coverage rate of verification is improved.
Therefore, the method for quickly verifying the GPIO does not need to take too long time for design and verification personnel to generate excitation and compare simulation results, can quickly and effectively verify the functions of the GPIO module, can automatically analyze the verification results, and only needs to look up the corresponding codes of the printing information to position errors, thereby improving the verification efficiency and the verification coverage rate, enabling the verification and design personnel to quickly position the error positions, greatly improving the verification efficiency and ensuring the smooth verification of other modules in the system. Moreover, the module is based on Verilog design, is completely compatible with design codes, and can accelerate verification speed, save labor force and improve verification efficiency in the RTL design stage of the chip.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a GPIO verification device provided in an embodiment of the present application, where the GPIO verification device described below and the GPIO verification method described above may be referred to in a corresponding manner, and all related modules are disposed in a central comparison and conclusion generation chip, and the schematic structural diagram includes:
the acquiring module 201 is configured to acquire first information used for verifying a current function, and read second information to be detected of the GPIO module;
a verification result obtaining module 202, configured to compare the first information with the second information to obtain a verification result of the current function;
a next function verifying module 203, configured to verify a next function when the verification result is that the verification is successful;
and a stop verification module 204, configured to stop verification and output corresponding verification information when the verification result is that the verification fails.
Preferably, the obtaining module 201 includes:
the data writing address acquisition unit is used for acquiring a first address and data writing sent by the bus generator if the verification of the current function is read-write verification; the first address is an address obtained by the address index list through a counter, the write data is data generated by a random number generator of the bus generator, and the first information corresponds to the write data;
the read data acquisition unit is used for reading read data corresponding to the first address in the GPIO module, and the second information corresponds to the read data;
correspondingly, the verification result obtaining module 202 includes:
the read-write judging unit is used for judging whether the write data and the read data meet preset conditions or not;
the first read-write verification result determining unit is used for determining that the verification result is the read-write verification success if the preset condition is met;
and the second read-write verification result determining unit is used for determining that the verification result is read-write verification failure if the preset condition is not met, and outputting the first address, the read data and the write data.
Preferably, the obtaining module 201 includes:
the first input signal and address acquisition unit is used for acquiring a first input signal which is input into the GPIO module by the external signal generator if the verification of the current function is interrupt verification; the first input signal is screened out by using the read data of the direction register configured in the bus transaction generator according to the received signal to be detected of the external signal generator;
the first numerical value acquisition unit is used for reading a first numerical value in a receiving data register of the GPIO module corresponding to the first input signal;
the second numerical value acquisition unit is used for reading a second numerical value corresponding to the first input signal in an interrupt state register in the GPIO module;
correspondingly, the verification result obtaining module 202 includes:
the numerical value judging unit is used for judging whether the first numerical value and the second numerical value meet a preset verification condition;
the first interrupt verification result determining unit is used for determining that the verification result is successful in interrupt verification if the first interrupt verification result is met;
and the second interruption verification result unit is used for determining that the verification result is interruption verification failure if the interruption verification result does not meet the requirement.
Preferably, the obtaining module 201 includes:
the data acquisition unit is used for acquiring data of a direction register in the bus transaction generator if the verification of the current function is the input and output function verification;
the signal screening unit is used for screening out input signals and output signals of the external signal generator for the GPIO module according to the data;
the corresponding value acquisition unit is used for reading a first corresponding value of a receiving data register and a second corresponding value of a sending data register of the GPIO module;
correspondingly, the verification result obtaining module 202 includes:
a signal and corresponding value judging unit for judging whether the input signal is consistent with the first corresponding value and whether the output signal is consistent with the second corresponding value;
the first input/output function verification result determining unit is used for determining that the verification result is successful in input/output function verification if the input/output function verification results are consistent with each other;
and the second input/output function verification result determining unit is used for determining that the verification result is input/output function verification failure if the verification result is inconsistent with the input/output function verification result.
Preferably, the obtaining module 201 includes:
the second input signal acquisition unit is used for acquiring a second input signal in the external signal generator and determining a level count value of the second input signal if the verification of the current function is the anti-jitter function verification;
the effective signal determining unit is used for taking the second input signal as an effective signal after the level counting value reaches a preset anti-jitter threshold value;
the receiving data register signal acquisition unit is used for reading the signal of the receiving data register of the GPIO module;
correspondingly, the verification result obtaining module 202 includes:
the signal judgment unit is used for judging whether the effective signal is consistent with the signal of the receiving data register of the GPIO module;
the first anti-shake function verification result unit is used for determining that the verification result is successful in anti-shake function verification if the first anti-shake function verification result unit is consistent with the first anti-shake function verification result unit;
and the second anti-shake function verification result unit is used for determining that the verification result is anti-shake function verification failure if the verification result is inconsistent.
Preferably, the obtaining module 201 includes:
the multiplexing signal acquisition unit is used for acquiring a multiplexing signal of the signal multiplexing generator if the verification of the current function is interface multiplexing verification, wherein the multiplexing signal is input into the GPIO module;
an output signal acquisition unit for acquiring an output signal of the external signal generator, wherein the output signal is a multiplexed signal output by the external signal generator;
correspondingly, the verification result obtaining module 202 includes:
a multiplexed signal judgment unit for judging whether the multiplexed signal is consistent with the output signal;
the first interface multiplexing verification result unit is used for determining that the verification result is successful in interface multiplexing verification if the first interface multiplexing verification result is consistent with the first interface multiplexing verification result;
and the second interface multiplexing verification result unit is used for determining that the verification result is interface multiplexing verification failure if the verification result is inconsistent.
Preferably, the method further comprises the following steps:
and the instruction acquisition module is used for acquiring the verification instruction and verifying the corresponding function according to the function information in the verification instruction.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
In the following, an electronic device provided by an embodiment of the present application is introduced, and the electronic device described below and the method described above may be referred to correspondingly.
The embodiment provides an electronic device, including:
a memory for storing a computer program;
and the processor is used for realizing the steps of the GPIO verification method when executing the computer program.
Since the embodiment of the electronic device portion and the embodiment of the method portion correspond to each other, please refer to the description of the embodiment of the method portion for the embodiment of the electronic device portion, which is not repeated here.
The following describes a computer-readable storage medium provided by embodiments of the present application, and the computer-readable storage medium described below and the method described above may be referred to correspondingly.
The present embodiment provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the GPIO authentication method as above.
Since the embodiment of the computer-readable storage medium portion and the embodiment of the method portion correspond to each other, please refer to the description of the embodiment of the method portion for the embodiment of the computer-readable storage medium portion, which is not repeated here.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
A GPIO verification method, apparatus, electronic device, and medium provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A GPIO verification method is characterized by comprising the following steps:
acquiring first information for verifying the current function, and reading second information to be detected of the GPIO module;
comparing the first information with the second information to obtain a verification result of the current function;
when the verification result is that the verification is successful, verifying the next function;
and when the verification result is that the verification fails, stopping the verification and outputting corresponding verification information.
2. The GPIO verification method of claim 1, wherein the obtaining first information for verifying a current function and reading second information to be detected of the GPIO module comprises:
if the verification of the current function is read-write verification, acquiring a first address and write data sent by a bus generator; the first address is an address obtained by an address index list through a counter, the write data is data generated by a random number generator of the bus generator, and the first information corresponds to the write data;
reading read data corresponding to the first address in the GPIO module, wherein the second information corresponds to the read data;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the write data and the read data meet preset conditions or not;
if the preset condition is met, determining that the verification result is read-write verification success;
and if the preset condition is not met, determining that the verification result is read-write verification failure, and outputting the first address, the read data and the write data.
3. The GPIO verification method of claim 1, wherein the obtaining first information for verifying a current function and reading second information to be detected of the GPIO module comprises:
if the verification of the current function is interrupt verification, acquiring a first input signal input by an external signal generator into the GPIO module; the first input signal is screened out by utilizing the read data of a direction register configured in the bus transaction generator according to the received signal to be detected of the external signal generator;
reading a first numerical value in a receiving data register of the GPIO module corresponding to the first input signal;
reading a second numerical value corresponding to the first input signal in an interrupt state register in the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the first numerical value and the second numerical value meet a preset verification condition;
if so, determining that the verification result is successful in interrupt verification;
if not, determining that the verification result is the interruption verification failure.
4. The GPIO verification method of claim 1, wherein the obtaining first information for verifying a current function and reading second information to be detected of the GPIO module comprises:
if the verification of the current function is the input and output function verification, acquiring data of a direction register in a bus transaction generator;
screening out an input signal and an output signal of an external signal generator for the GPIO module according to the data;
reading a first corresponding value of a receiving data register and a second corresponding value of a sending data register of the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the input signal is consistent with the first corresponding value or not and whether the output signal is consistent with the second corresponding value or not;
if the input function and the output function are consistent, determining that the verification result is that the input and output function verification is successful;
and if the input and output functions are inconsistent, determining that the verification result is input and output function verification failure.
5. The GPIO verification method of claim 1, wherein the obtaining first information for verifying a current function and reading second information to be detected of the GPIO module comprises:
if the verification of the current function is anti-jitter function verification, acquiring a second input signal in an external signal generator, and determining a level count value of the second input signal;
when the level count value reaches a preset anti-jitter threshold value, taking the second input signal as an effective signal;
reading a signal of a receiving data register of the GPIO module;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the effective signal is consistent with a signal of a receiving data register of the GPIO module or not;
if the verification result is consistent with the anti-shaking function verification result, the anti-shaking function verification is determined to be successful;
and if the verification result is inconsistent, determining that the verification result is the anti-jitter function verification failure.
6. The GPIO verification method of claim 1, wherein the obtaining first information for verifying a current function and reading second information to be detected of the GPIO module comprises:
if the verification of the current function is interface multiplexing verification, acquiring a multiplexing signal of a signal multiplexing generator, wherein the multiplexing signal is input into the GPIO module;
acquiring an output signal of an external signal generator, wherein the output signal is output by the multiplexing signal through the external signal generator;
correspondingly, comparing the first information with the second information to obtain a verification result of the current function, including:
judging whether the multiplexing signal is consistent with the output signal;
if the verification result is consistent with the interface multiplexing verification result, the verification result is determined to be that the interface multiplexing verification is successful;
and if the verification result is inconsistent, determining that the verification result is interface multiplexing verification failure.
7. The GPIO verification method of claim 1, further comprising:
and acquiring a verification instruction, and verifying the corresponding function according to the function information in the verification instruction.
8. A GPIO verification device, comprising:
the acquisition module is used for acquiring first information used for verifying the current function and reading second information to be detected of the GPIO module;
a verification result obtaining module, configured to compare the first information with the second information to obtain a verification result of the current function;
the next function verifying module is used for verifying the next function when the verifying result is that the verification is successful;
and the verification stopping module is used for stopping verification and outputting corresponding verification information when the verification result is verification failure.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the GPIO verification method as claimed in any one of claims 1 to 7 when executing the computer program.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the GPIO verification method as claimed in any one of claims 1 to 7.
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Application publication date: 20210129 |