CN115422866A

CN115422866A - Method for simulating logic system design on simulator and related equipment

Info

Publication number: CN115422866A
Application number: CN202210864665.1A
Authority: CN
Inventors: 徐欣
Original assignee: Xinhuazhang Technology Co ltd
Current assignee: Xinhuazhang Technology Co ltd
Priority date: 2021-07-21
Filing date: 2022-07-21
Publication date: 2022-12-02
Also published as: CN113283203A

Abstract

The present disclosure provides a method and related apparatus for simulating a logic system design on a simulator. The method comprises the following steps: obtaining a description of a detection module, the description of the detection module comprising a trigger condition, the trigger condition comprising a plurality of signals; cutting the logic system design into a plurality of blocks, the plurality of blocks including a first block and a second block, the first and second blocks being assigned to a first FPGA and a second FPGA, respectively; decomposing the trigger condition into a plurality of sub-conditions corresponding to the plurality of blocks, wherein the sub-conditions include a first sub-condition and a second sub-condition, the first sub-condition corresponds to the first block, and the second sub-condition corresponds to the second block; running the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, to determine whether the trigger condition is satisfied.

Description

Method for simulating logic system design on simulator and related equipment

Technical Field

The present disclosure relates to the field of computer software technologies, and in particular, to a method and related device for simulating a logic system design on a simulator.

Background

An Emulator (Emulator) can emulate and debug a logic system design. The logic System design may be, for example, a design for an Application Specific Integrated Circuit (ASIC) or System-On-Chip (SOC) for a Specific Application. Accordingly, a logic system Design being tested in a simulator may also be referred to as a Design Under Test (DUT). The simulator may simulate the DUT via one or more configurable components, such as a Field Programmable Gate Array (FPGA), including performing various operations of the DUT to test and verify the functionality of the DUT prior to manufacturing.

In the verification process, it is necessary to execute a trigger condition and perform signal detection when the trigger condition is satisfied. However, to determine the trigger condition, the trigger condition is usually compiled to generate a netlist of the corresponding circuit structure and loaded into a simulator, and this way cannot flexibly adjust the specific condition; or the trigger condition needs to be converted into a control instruction, and the control unit executes judgment calculation, so that for the complex trigger condition, the simulator resource may be excessively occupied, and the performance of the simulator is affected.

Disclosure of Invention

In view of the above, the present disclosure provides a method and related apparatus for simulating a logic system design on a simulator.

In a first aspect of the disclosure, a method for simulating a logic system design on a simulator is provided, wherein the simulator comprises a plurality of FPGAs. The method comprises the following steps: obtaining a description of a detection module, the description of the detection module comprising a trigger condition, the trigger condition comprising a plurality of signals; cutting the logic system design into a plurality of blocks, the plurality of blocks including a first block and a second block, the first and second blocks being assigned to a first FPGA and a second FPGA, respectively; decomposing the trigger condition into a plurality of sub-conditions corresponding to the plurality of blocks, wherein the sub-conditions include a first sub-condition and a second sub-condition, the first sub-condition corresponds to the first block, and the second sub-condition corresponds to the second block; running the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, to determine whether the trigger condition is satisfied.

In a second aspect of the present disclosure, an electronic device for simulating a logic system design is provided, the electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of the first aspect when executing the program.

In a third aspect of the disclosure, a non-transitory computer-readable storage medium is provided that stores a set of instructions for an electronic device, the set of instructions being configured to cause the electronic device to perform the method of the first aspect.

Drawings

In order to more clearly illustrate the present disclosure or the technical solutions in the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1A shows a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

FIG. 1B illustrates a schematic diagram of an exemplary compiler, according to embodiments of the present disclosure.

FIG. 2 shows a schematic diagram of an exemplary simulation system according to an embodiment of the present disclosure.

Fig. 3A shows a schematic diagram of an exemplary depiction of a detection module according to an embodiment of the disclosure.

FIG. 3B shows a schematic diagram of a multiple lookup table connection structure according to an embodiment of the present disclosure.

FIG. 4 sets forth a flow chart illustrating an exemplary method for simulating a logic system design according to embodiments of the present disclosure.

FIG. 5 shows a schematic diagram of a simulator in accordance with an embodiment of the present disclosure.

FIG. 6 sets forth a flow chart illustrating an exemplary method for simulating a logic system design on a simulator according to embodiments of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

As described above, in order to perform functional verification on a Design Under Test (DUT), it is often necessary to determine a trigger condition and trigger a next signal detection operation when the trigger condition is satisfied, such as detecting a target signal, obtaining a relevant signal waveform, and the like. The key to this process is how the trigger condition is executed. There are two implementations of the execution trigger condition in the related art: one way is to compile specific conditions into a netlist corresponding to the circuit structure and load the netlist into a configurable component (such as a Field Programmable Gate Array (FPGA)) of the simulator, so as to realize the judgment of the specific conditions through the specific circuit structure. The trigger condition is converted into an actual circuit solidified in the simulator, so that the flexibility is lacked, and the trigger condition cannot be adjusted according to actual requirements. Another way to convert a specific condition into a control instruction is to perform a decision calculation by the control unit, and when the trigger condition is more complicated, the simulator needs to spend more resources to perform the decision calculation, which may affect the performance of the simulator.

In view of this, the disclosed embodiments provide a method for simulating a logic system design on a simulator, which reduces the computational pressure of a single FPGA and the communication pressure of acquiring data by adaptively decomposing and running trigger conditions on a corresponding FPGA. Meanwhile, the flexibility of the system can be improved by locally processing the signals of the trigger sub-conditions by the control units in the plurality of FPGAs, only software configuration is needed to be carried out on the control units, and corresponding signal values are calculated, but the FPGAs do not need to be reconfigured to form corresponding hardware connection relations to be specially used for obtaining the signal values. By adopting the method for utilizing the lookup table provided by the embodiment, the value of the trigger condition can be rapidly inquired and determined without consuming excessive computing resources, the influence of the trigger condition judgment on the performance of the simulator can be effectively avoided, meanwhile, the trigger condition can be flexibly adjusted according to the actual condition, and the flexibility of processing the trigger condition is kept.

Fig. 1A shows a schematic structural diagram of an electronic device 100 provided in this embodiment.

The electronic device 100 may be, for example, a computer host. The electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein processor 102, memory 104, network interface 106, and peripheral interface 108 are communicatively coupled to each other within the device via bus 110.

Processor 102 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions related to the techniques described in this disclosure. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1A, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as shown in fig. 1A, the stored data may include program instructions (e.g., for implementing aspects of the present disclosure) as well as data to be processed (e.g., memory 104 may store temporary code generated during the compilation process). The processor 102 may also access stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile memory devices or non-volatile memory devices. In some embodiments, the memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSDs), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communications with other external devices to the electronic device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

The peripheral interface 108 may be configured to connect the electronic device 100 with one or more peripheral devices to enable input and output of information. For example, the peripheral devices may include input devices such as keyboards, mice, touch pads, touch screens, microphones, various sensors, and output devices such as displays, speakers, vibrators, indicator lights, and the like. In some embodiments, the peripheral interface 108 may be connected to an emulator (emulator) for transferring configuration files to the emulator. The configuration file may include, for example, a gate level netlist, machine code, etc.

The bus 110 may be configured to transfer information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), and so forth.

It should be noted that although the above-described device only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the device may also include other components necessary to achieve normal operation. In addition, those skilled in the art will appreciate that the above-described apparatus may also include only the components necessary to implement the embodiments of the present disclosure, and need not include all of the components illustrated in the figures.

FIG. 1B illustrates a schematic diagram of an example compiler 120, according to an embodiment of the present disclosure. In some embodiments, compiler 120 may run on electronic device 100 of FIG. 1A.

Compiler 120 may generate a computer program of object code based on the computer code to be compiled. The computer code to be compiled may also be referred to as source code. Here, the source code refers to source code of a logic system design. Typically, the source language in which the source code is written is a high level programming language. The high-level programming language may be, for example, a software programming language such as C + +, java, or a hardware description language such as VHDL, verilog, systemveilog. The object code may be, for example, assembly code, machine code, or the like.

The compiler 120 may be stored, for example, in the memory 104 shown in FIG. 1A and executed by the processor 102.

As shown in FIG. 1B, compiler 120 may include a front end 122, a middle end 124, and a back end 126.

Front end 122 may be used to analyze the lexical, syntactic, semantic properties of the source code according to a particular source language.

After lexical, grammatical, and semantic analysis of the source code is complete, the middle-end 124 may convert the source code into an intermediate representation (or intermediate code) and may optimize the intermediate representation. For example, middle end 124 may remove useless code, remove inaccessible code, clear unused variables, and the like. The optimized intermediate representation may then be passed to the back end 126 for further processing.

The back-end 126 may further optimize the intermediate representation according to the architecture of the target processor (e.g., processor 102 of FIG. 1A) and generate the target code. In some embodiments, the object code may be a gate level netlist as well as machine code. The gate-level netlist can be used to configure the FPGA to implement predetermined circuits and functions, while the machine code can be executed by a processing unit (e.g., a control unit in an emulator).

For example, compiler 120 may generate an abstract syntax tree from the source code, then generate an intermediate representation based on the abstract syntax tree, and finally generate machine code that is related to the hardware architecture.

It is to be understood that the structure of the compiler is not limited to the example of fig. 1B. For example, front end 122 and middle end 124 may be collectively referred to as a front end of a compiler, or middle end 124 and back end 126 may be collectively referred to as a back end of a compiler.

FIG. 2 shows a schematic diagram of an exemplary simulation system 200 according to an embodiment of the present disclosure. The simulation system 200 may include the electronic device 100 and a simulator 210. For example, simulator 210 may be a HuaEmu simulation tool available from Chihua Chapter technologies, inc. The emulator may include a Field Programmable Gate Array (FPGA). The gate-level netlist is configured into the FPGA of the simulator, so that the FPGA simulates a logic system design. It will be appreciated that an emulator can include multiple FPGAs, and each FPGA can emulate only a portion (e.g., one or more modules) of a logic system design.

As shown in FIG. 2, compiler 120 running on electronic device 100 may generate configuration files 204, including gate-level netlist and machine code, from the source code of logic system design 202. A portion (e.g., a gate level netlist) of the configuration file 204 may be loaded onto an FPGA of the simulator 210 via, for example, the peripheral interface 108 of the electronic device 100, and another portion (e.g., machine code) of the configuration file 204 may be loaded onto a control unit of the simulator 210 via, for example, the peripheral interface 108 of the electronic device 100. The control unit may be part of the FPGA or separate from the FPGA.

Simulator 210 may perform a simulation of logic system design 202 based on configuration file 204. Wherein the simulator 210 may perform a trigger condition determination according to the configuration file 204, and trigger a signal detection operation when the trigger condition is satisfied. For example, the emulator 210 may execute a trigger condition of decision "a > b & & a > c & & a & b & & a | c & & b < c", in response to which the trigger condition is established, i.e., when the value of the expression "a > b & & a > c & & a & b & & a | c & & b < c" is true, the signal detection operation is triggered. The simulator 210 may output the simulation result 206, wherein the simulation result 206 may include a signal detection result (e.g., a value of a target signal, a waveform of a correlation signal, etc.). For example, the simulation system 200 may output the signal detection results to an output device (e.g., displayed on a display) via the peripheral interface 108 of FIG. 1A.

Fig. 3A shows a schematic diagram of an exemplary depiction 300 of a detection module according to an embodiment of the disclosure.

As shown in FIG. 3A, compiler 120 may obtain a description 300 of a detection module (monitor) in a logic system design. The description 300 of the detection module may include a trigger condition 310 "(a > b & & a > c & & a & b & & a | c & & c)" and a trigger instruction "trigger". The trigger condition 310 may be a boolean expression including a plurality of input signals (e.g., a, b, c, etc.), among others. When the trigger condition 310 is satisfied, i.e., the value of "(a > b & & a > c & & a & b & & a | c & & c)" is true, the detection module may execute a trigger instruction "trigger" to trigger a signal detection operation.

Compiler 120 may generate a netlist file (netlist file) for a detection module based on description 300 of the detection module. A first portion corresponding to a trigger condition 310 may be included in the netlist file. Because the trigger condition 310 has a plurality of input signals (e.g., signals a, b, c, etc.) and the plurality of input signals often have more complicated operational relationships, it is difficult to directly calculate the value of the trigger condition 310 as a whole according to the values of the plurality of input signals. When generating a netlist file for a detection module based on a description 300 of the detection module, compiler 120 may decompose a description of the detection module into a plurality of sub-conditions according to the operational logic relationships of trigger conditions 310.

In one example, the compiler 120 may decompose the trigger condition 310 "(a > b & & a > c & & a & b & & a | c & & c)" into a first sub-condition "(a > b)", a second sub-condition "(a > c)", a third sub-condition "(a & b)", a fourth sub-condition "(a | c)", a fifth sub-condition "(c)" and a sixth sub-condition "((a > b) & (a > c) & (a & b) & (a | c) & (c))" input with output results of the first to fifth sub-conditions. Of the six sub-conditions resulting from the decomposition of trigger condition 310, the first through fifth sub-conditions belong to a first-level sub-condition, the sixth sub-condition belongs to a second-level sub-condition, the output of the plurality of sub-conditions (i.e., the first through fifth sub-conditions) in the first level is used as the input of the sixth sub-condition in the second level, and the output of the sixth sub-condition is the value of trigger condition 310.

In another example, the compiler 120 may decompose the trigger condition 310 "(a > b & & a > c & & a & b & & a | c & & c)" into a first sub-condition "(a > b & & a > c)", a second sub-condition "(a & b & & a | c)", a third sub-condition "(c)", a fourth sub-condition "((a > b & & a > c) & & (a & b & & a | c))" input with an output result of the first and second sub-conditions, and a fifth sub-condition "((a > b & & a > c) & & (a & b & & a | c)) & (c))", input with an output result of the third and fourth sub-conditions. In the five sub-conditions obtained by decomposing the trigger condition 310, the first sub-condition and the second sub-condition belong to a first-stage sub-condition, the third sub-condition and the fourth sub-condition belong to a second-stage sub-condition, the fifth sub-condition belongs to a third-stage sub-condition, an output of the first sub-condition and the second sub-condition in the first stage is used as an input of a fourth sub-condition in the second stage, an output of the third sub-condition and the fourth sub-condition in the second stage is used as an input of a fifth sub-condition in the third stage, and an output of the fifth sub-condition is a value of the trigger condition 310.

For the plurality of sub-conditions obtained by decomposing the trigger condition 310, there is a certain correspondence between the values of the plurality of inputs of the sub-conditions and the outputs, and a Look-Up Table (LUT) may be used to directly query and determine the corresponding outputs according to the values of the plurality of inputs, so the compiler 120 may generate a plurality of corresponding Look-Up tables in the first portion of the netlist file corresponding to the trigger condition 310 according to the plurality of sub-conditions obtained by decomposing the trigger condition 310. The look-up table also has a plurality of inputs and outputs corresponding to the plurality of inputs corresponding to the sub-conditions.

Fig. 3B shows a schematic diagram of a plurality of look-up table connection structures 320 according to an embodiment of the present disclosure.

Taking the trigger condition 310 "(a > b & & a > c & & a & b & & a | c & & c)" as an example, the trigger condition 310 may be decomposed into a first sub-condition "(a > b & & a > c)", a second sub-condition "(a & b & & a | c)", a third sub-condition "(c)", a fourth sub-condition "((a > b & & a > c) & (a & b & & a | c))" and a fifth sub-condition "((a > b & & a > c) & (a & b & & a | c)) & (c))". The compiler 120 may generate five lookup tables corresponding to the five sub-conditions, respectively, and the inputs and outputs of the five lookup tables correspond to the inputs and outputs of the corresponding sub-conditions, respectively. Specifically, the look-up table 3202 corresponds to a first sub-condition "(a > b & & a > c)" having three inputs a, b, c and one output, and the look-up table 3202 also has three corresponding inputs and one output. The look-up table 3204 corresponds to a second sub-condition "(a & b & & a | c)", which has three inputs a, b, c and one output, and the look-up table 3204 also has three corresponding inputs and one output. The lookup table 3206 corresponds to a fourth sub-condition "((a > b & & a > c) & & (a & b & & a | c))", the fourth sub-condition having two inputs and one output, and the lookup table 3206 also has corresponding two inputs and one output. Look-up table 3208 corresponds to a third sub-condition "(c)", which has one input of c and one output, and look-up table 3208 also has one input and one output. The lookup table 3210 corresponds to a fifth sub-condition "(((a > b & & a > c) & & & (a & b & & a | c)) & & (c))", the fifth sub-condition having two inputs and one output, the lookup table 3210 also having corresponding two inputs and one output.

As shown in fig. 3B, the linkage relationship of the five lookup tables generated by the compiler 120 is also the same as that of the five sub-conditions. Of the five sub-conditions, the output of the first and second sub-conditions in the first stage are used as the input of the fourth sub-condition in the second stage, and accordingly, the outputs of the lookup tables 3202 and 3204 are the inputs of the lookup table 3206. The outputs of the third and fourth sub-conditions in the second stage are used as the inputs of the fifth sub-condition in the third stage, and the outputs of the lookup tables 3206 and 3208 are used as the inputs of the lookup table 3210.

Compiler 120 may generate a configuration file (e.g., configuration file 204 in fig. 2) based on a first portion of the netlist file that corresponds to trigger condition 310. After generating the corresponding configuration file based on the netlist file, simulation system 200 may configure a plurality of look-up tables in simulator 210 according to the configuration file.

The look-up table is a true mapping table from input to output, which may be implemented by being present in memory. In some embodiments, the simulation system 200 may configure a plurality of look-up tables in the memory of the control unit of the simulator 210. Where the simulator 210 may include one or more Field Programmable Gate Arrays (FPGAs), in some embodiments, the simulation system 200 may configure a plurality of look-up tables in a control unit (e.g., a control core) on the FPGA. In some embodiments, the simulator 210 may further include a control unit for general purpose calculations in addition to the FPGA, and the look-up table may also be configured in the memory of these non-FPGA control units.

In some embodiments, the simulation system 200 may configure the plurality of lookup tables in a plurality of storage units of the memory to implement the plurality of lookup tables, and the plurality of storage units respectively store the truth mapping tables of the plurality of lookup tables.

By configuring a plurality of lookup tables in the simulator 210 according to the configuration file, the simulator 210 may sequentially query and determine values of a corresponding plurality of sub-conditions using the plurality of configured lookup tables and values of a plurality of input signals in the trigger condition 310, and determine the value of the trigger condition 310 according to the values of the plurality of sub-conditions to determine whether the trigger condition 310 is satisfied.

Taking the plurality of lookup tables shown in fig. 3B as an example, the lookup table 3202 corresponds to the first sub-condition "(a > B & & a > c)" of the trigger condition 310, and outputs of the first sub-condition "(a > B & & a > c)" corresponding to the three input signals a, B, c may be query-determined using the corresponding truth value mapping table of the lookup table 3202 stored in the storage unit, assuming y1, according to values of the three input signals a, B, c of the first sub-condition. The look-up table 3204 corresponds to the second sub-condition "(a & b & & a | c)" of the trigger condition 310, and determines an output of the second sub-condition "(a & b & & a | c)" by a query of a corresponding truth mapping table of the look-up table 3204, assuming y2, according to values of the three input signals a, b, c. The lookup table 3206 corresponds to a fourth sub-condition "((a > b & & a > c) & & (a & b & & a | c))" of the trigger condition 310, whose inputs are an output y1 of the first sub-condition and an output y2 of the second sub-condition, and the output of the fourth sub-condition is determined by a corresponding truth mapping table query of the lookup table 3206 according to values of y1, y2. The output of the fifth sub-condition, which is the output of the trigger condition 310, can be finally determined in the same manner.

There may be situations where the control unit in the emulator 210 has limited memory resources. When the number of the storage units of the memory of the control unit is not enough to configure a plurality of lookup tables at the same time, the simulation system 200 may configure a partial lookup table first, and the simulator 210 may query and determine the outputs of the corresponding plurality of sub-conditions by using the configured partial lookup table, and when the query of the output of one of the plurality of sub-conditions is determined, release the storage unit of the lookup table corresponding to the sub-condition, and then implement the lookup table that is not configured in advance by using the released storage unit.

For example, in the case that the memory of the control unit only includes four storage units, and five lookup tables as shown in fig. 3B are implemented by using the control unit, the simulation system 200 may first select the lookup table 3202, the lookup table 3204, the lookup table 3206, and the lookup table 3208 to configure, first configure the four lookup tables in the four storage units of the control unit memory, and determine the outputs of the corresponding first sub-condition, second sub-condition, fourth sub-condition, and third sub-condition by using the previously configured lookup table 3202, lookup table 3204, lookup table 3206, and lookup table 3208. When the output query of one of the first sub-condition, the second sub-condition, the fourth sub-condition and the third sub-condition (e.g., the third sub-condition) is determined, the storage unit of the lookup table (e.g., the lookup table 3208) corresponding to the sub-condition is released. The freed memory locations may be used to configure a previously unconfigured lookup table 3210. Similarly, when the memory of the control unit only comprises three memory units, the three lookup tables are selected for configuration, when the three lookup tables correspond to the three sub-conditions and the sub-conditions output inquiry is determined, the corresponding memory unit is released, and the released memory unit is used for configuring the other two lookup tables which are not configured before.

FIG. 4 illustrates a flowchart of an exemplary method 400 for simulating a logic system design, in accordance with an embodiment of the disclosure.

The method 400 for simulating a logic system design may be performed by the simulation system 200 shown in FIG. 2. The simulation system 200 may include an electronic device 100 and a simulator 210. The electronic device 100 may run software such as a compiler 120. The method 400 may include the following steps.

At step 402, compiler 120 may obtain a description of a detection module (e.g., description 300 shown in FIG. 3A), which may include a trigger condition (e.g., trigger condition 310 in FIG. 3A).

At step 404, compiler 120 may generate a netlist file for the detection module based on the description of the detection module. Wherein the netlist file may include a first portion corresponding to the trigger condition, which may include a plurality of lookup tables corresponding to the trigger condition (e.g., lookup table 3202, lookup table 3204, lookup table 3206, lookup table 3208, lookup table 3210 in fig. 3B).

In some embodiments, compiler 120 may decompose the trigger condition into a plurality of sub-conditions that may be divided into a plurality of stages including at least a first stage and a second stage, wherein an output of a sub-condition in the first stage is used as an input to a sub-condition in the second stage.

In some embodiments, compiler 120 may generate the plurality of look-up tables according to the plurality of sub-conditions, respectively. One of the plurality of lookup tables may include a plurality of inputs and outputs corresponding to the plurality of inputs.

At step 406, compiler 120 may generate a configuration file (e.g., configuration file 204 in fig. 2) based on the first portion;

at step 408, the simulation system 200 may configure the plurality of look-up tables in the control unit of the simulator 210 according to the configuration file to determine whether the trigger condition is satisfied according to the plurality of look-up tables. Wherein the control unit may be implemented on an FPGA in the emulator 210.

In some embodiments, the simulation system 200 may implement the plurality of look-up tables in a memory of a control unit of the simulator 210 using a plurality of storage locations of the memory.

In some embodiments, simulator 210 may determine the output of a plurality of sub-conditions using a plurality of look-up table queries, and in response to one of the plurality of sub-conditions completing processing, simulator 210 may release the memory location of the sub-condition corresponding look-up table, configuring the released memory location as the look-up table corresponding to the sub-condition that did not complete processing.

With the increase of the design scale of the logic system, the logic system design cannot be realized on one FPGA. Thus, it is common practice to partition a logic system design into a plurality of blocks, including a first block and a second block. And are implemented on multiple FPGAs, respectively. As discussed with reference to fig. 3A, the trigger condition 310 may include a plurality of signals (e.g., signals a, b, and c). Since logic system design 202 is partitioned, signals a and b may be partitioned into a first block, and signal c may be partitioned into a second block.

It is common practice to configure a control unit (e.g., a processor) on one FPGA and to introduce signals in blocks running on other FPGAs to this control unit through inter-chip communication. However, the technical problem of this method is that valuable communication resources between multiple FPGAs need to be occupied, and at the same time, the processing capability of the control unit of a single FPGA is limited, and the requirement for the computing resources of a single FPGA is also high when the control unit is concentrated on one FPGA for operation. Furthermore, the signals involved in different trigger conditions may be different, which results in the simulation system 200 needing to configure the different trigger conditions separately each time.

In order to solve the above technical problem, embodiments of the present application further provide a method for simulating a logic system design on a simulator, where the simulator may include a plurality of FPGAs. The simulation system 200 can implement the determination of whether the trigger condition is satisfied on the plurality of FPGAs.

FIG. 5 shows a schematic diagram of a simulator 210 according to an embodiment of the disclosure.

As shown in FIG. 5, simulator 210 may include FPGA 510 and FPGA 520. Logic system design 202 may be partitioned into first block 512 and second block 522. Where signals a and b in the trigger condition 310 are included in the first block 512 and signal c is included in the second block 522. The first block 512 may be implemented on the FPGA 510 and the second block 522 may be implemented on the FPGA 520.

A control unit 514 and a bus 516 may also be configured on FPGA 510. Similarly, a control unit 524 and a bus 526 may also be configured on FPGA 520. Control unit 514 and control unit 516 are communicatively coupled.

As described above, in a case where the logic system design is too bulky, the logic system design 202 needs to be cut into a plurality of blocks. Fig. 5 exemplarily shows only the first block 512 and the second block 522. It will be appreciated that the logic system design 202 may be cut into more pieces as needed.

The trigger condition 310 may also be decomposed into a plurality of sub-conditions (e.g., a > b & & a & b, a > c & & a | c, and c, etc.) corresponding to the first block 512 and the second block 522. Here, the first sub-condition may be a > b & & a & b, and corresponds to the first block 512. The second sub-condition may be c, and the second sub-condition may correspond to the second block 522.

In this way, the first and second sub-conditions and the first and second blocks may be run on FPGA 510 and FPGA520, respectively, to determine whether the trigger condition 310 is satisfied.

In some embodiments, control unit 514 may be configured on FPGA 510. The control unit 514 may be a small processor with certain computing and caching capabilities. The control unit 514 is connected to the first block 512 as a DUT via a bus 516. A first block 512 runs on FPGA 510 and can generate signals including signals a and b. The control unit 514 may determine the values of the signals a and b and determine an output value (e.g., "1" or "0") of the first sub-condition according to the values of the signals a and b.

The values of signals a and b are not necessarily transmitted directly from the first block 512 to the control unit 514 via the bus 516. In some embodiments, the control unit 514 may read the signal values associated with signals a and b in the first block 512. For example, the control unit 514 may read the values of the critical flip-flops (flip-flops) in the first block 512 and calculate the values of the signals a and b according to the description of the first block 512 (e.g., the description of the circuit structure of the first block 512). It follows that the control unit 514 does not need the first block 512 to transmit the signals a and b directly to the control unit 514.

Thus, when the trigger condition 310 and the first sub-condition need to be adjusted, only software configuration needs to be performed in the control unit 514 to calculate the value of the corresponding signal, and the FPGA 510 does not need to be reconfigured to form the corresponding hardware connection relationship.

After acquiring the values of signals a and b, the control unit 514 may calculate the output of the first sub-condition. For example, the simulation system 200 may generate a first lookup table corresponding to the first sub-condition and implement the first lookup table in a memory of the control unit 514 using a plurality of storage units of the memory. The related description has been provided above and will not be described herein. The inputs to the first look-up table may be the signals a and b.

Similarly, control unit 524 is configured on FPGA520, and a second sub-condition (e.g., "c") is run on control unit 524 and the output value of the second sub-condition is determined.

In some embodiments, the calculation of the final trigger condition 310 may be centralized on one control unit, e.g., centralized to the control unit 514. Therefore, the control unit 524 may transmit the output value of the second sub-condition to the control unit 514, and acquire the output values of the plurality of sub-conditions by the control unit 514, and determine whether the trigger condition 310 is satisfied.

FIG. 6 illustrates a flowchart of an exemplary method 600 for simulating a logic system design on a simulator in accordance with an embodiment of the present disclosure.

The method 600 for simulating a logic system design on a simulator may be performed by the simulation system 200 shown in FIG. 2. The simulation system 200 may include an electronic device 100 and a simulator 210. Simulator 210 may include multiple FPGAs. The electronic device 100 may run software such as a compiler 120. The method 600 may include the following steps.

At step 602, the simulation system 200 may obtain a description of a detection module (e.g., the description 300 shown in FIG. 3A) that includes a trigger condition (e.g., the trigger condition 310 shown in FIG. 3A) that includes a plurality of signals (e.g., signals a, b, and c).

At step 604, simulation system 200 may cut the logic system design (e.g., logic system design 202 shown in FIG. 2) into a plurality of blocks (e.g., blocks 512 and 522 shown in FIG. 5) including first and second blocks assigned to a first FPGA (e.g., FPGA 510 shown in FIG. 5) and a second FPGA (e.g., FPGA520 shown in FIG. 5), respectively.

At step 606, the simulation system 200 may decompose the trigger condition into a plurality of sub-conditions corresponding to the plurality of blocks, wherein the sub-conditions include a first sub-condition (e.g., "a > b & & a & b" in the trigger condition 310 shown in FIG. 3A) corresponding to the first block and a second sub-condition (e.g., "c" in the trigger condition 310 shown in FIG. 3A) corresponding to the second block.

At step 608, simulation system 200 can run the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, to determine whether the trigger condition is satisfied.

In some embodiments, the first sub-condition is associated with at least one target signal, and the simulation system 200 running the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, further comprises: configuring a first control unit (e.g., control unit 514 shown in fig. 5) on the first FPGA; running the first block on the first FPGA to generate the at least one target signal (e.g., signals a and b); determining, by the first control unit, a value of the at least one target signal; and determining a first output value (e.g., "1" or "0") of the first sub-condition based on the determined value of the at least one target signal.

In some embodiments, determining, by the first control unit, the value of the at least one target signal further comprises: reading, by the first control unit, a signal value associated with the at least one target signal from the first block (e.g., a value of a key-flop (flip-flop) in first block 512); determining, by the first control unit, a value of the at least one target signal based on the signal value and a description of the first block (e.g., a description of a circuit structure of first block 512).

In some embodiments, the simulation system 200 determining the output value of the first sub-condition based on the determined value of the at least one target signal further comprises: generating a first look-up table corresponding to the first sub-condition, the input of the first look-up table being the at least one target signal; implementing the first lookup table in a memory of the first control unit with a plurality of storage locations of the memory.

In some embodiments, method 600 may further include: configuring a second control unit (e.g., control unit 524 shown in FIG. 5) on the second FPGA (e.g., FPGA520 shown in FIG. 5); running the second sub-condition (e.g., "c" in trigger condition 310 shown in FIG. 3A) on the second control unit; determining a second output value of the second sub-condition; and sending the second output value to the first control unit.

In some embodiments, running the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, to determine whether the trigger condition is satisfied further comprises: acquiring, by the first control unit, a plurality of output values of the plurality of sub-conditions; and determining, by the first control unit, whether the trigger condition is satisfied based on the plurality of output values.

The embodiment of the present disclosure reduces the computation pressure of a single FPGA and the communication pressure of the acquired data by adaptively decomposing the trigger condition and running it on the corresponding FPGA. Meanwhile, the flexibility of the system can be improved by locally processing the signals of the trigger sub-conditions by the control units on the plurality of FPGAs, only software configuration needs to be carried out on the control units to calculate corresponding signal values, and the FPGAs do not need to be reconfigured to form corresponding hardware connection relations to be specially used for obtaining the signal values. By adopting the method for utilizing the lookup table provided by the embodiment, the value of the trigger condition can be quickly inquired and determined without consuming too much computing resources, the influence on the performance of the simulator caused by executing the trigger condition judgment can be effectively avoided, meanwhile, the trigger condition can be conveniently and flexibly adjusted according to the actual condition, and the flexibility of processing the trigger condition is kept.

Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present disclosure also provides an electronic device, which may include a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, the method for simulating a logic system design on a simulator according to any of the above embodiments is implemented.

It should be noted that the method of the present disclosure may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and is completed by the mutual cooperation of a plurality of devices. In the case of such a distributed scenario, one of the plurality of devices may only perform one or more steps of the method of the present disclosure, and the plurality of devices may interact with each other to complete the method.

It should be noted that the above description describes certain embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Based on the same inventive concept, corresponding to any of the embodiment methods described above, the present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the method for simulating a logic system design on a simulator as described in any of the embodiments above.

Computer-readable media of the present embodiments, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method for designing a simulation logic system according to any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which are not described herein again.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, also technical features between the above embodiments or different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of brevity.

In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, devices may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.

The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made without departing from the spirit or scope of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A method for simulating a logic system design on a simulator, wherein the simulator includes a plurality of FPGAs, the method comprising:

obtaining a description of a detection module, the description of the detection module comprising a trigger condition, the trigger condition comprising a plurality of signals;

cutting the logic system design into a plurality of blocks, the plurality of blocks including a first block and a second block, the first and second blocks being assigned to a first FPGA and a second FPGA, respectively;

decomposing the trigger condition into a plurality of sub-conditions corresponding to the plurality of blocks, wherein the sub-conditions include a first sub-condition and a second sub-condition, the first sub-condition corresponds to the first block, and the second sub-condition corresponds to the second block;

running the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, to determine whether the trigger condition is satisfied.

2. The method of claim 1, wherein the first sub-condition is associated with at least one target signal, the running the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, further comprising:

configuring a first control unit on the first FPGA;

running the first block on the first FPGA to generate the at least one target signal;

determining, by the first control unit, a value of the at least one target signal; and

determining a first output value of the first sub-condition based on the determined value of the at least one target signal.

3. The method of claim 2, wherein determining, by the first control unit, the value of the at least one target signal further comprises:

reading, by the first control unit, a signal value associated with the at least one target signal from the first block;

determining, by the first control unit, a value of the at least one target signal based on the signal value and the description of the first block.

4. The method of claim 2 or 3, wherein determining a first output value of the first sub-condition based on the determined value of the at least one target signal further comprises:

generating a first lookup table corresponding to the first sub-condition, the input of the first lookup table being the at least one target signal;

implementing the first lookup table in a memory of the first control unit with a plurality of storage locations of the memory.

5. The method of claim 2, further comprising:

configuring a second control unit on the second FPGA;

running the second sub-condition on the second control unit;

determining a second output value of the second sub-condition; and

sending the second output value to the first control unit.

6. The method of claim 5, wherein running the plurality of sub-conditions and the plurality of blocks on the plurality of FPGAs, respectively, to determine whether the trigger condition is satisfied further comprises:

acquiring, by the first control unit, a plurality of output values of the plurality of sub-conditions; and

determining, by the first control unit, whether the trigger condition is satisfied based on the plurality of output values.

7. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 6 when executing the program.

8. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 6.