CN111949321A - Firmware code execution method, memory storage device and memory control circuit unit - Google Patents
Firmware code execution method, memory storage device and memory control circuit unit Download PDFInfo
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- CN111949321A CN111949321A CN202010848254.4A CN202010848254A CN111949321A CN 111949321 A CN111949321 A CN 111949321A CN 202010848254 A CN202010848254 A CN 202010848254A CN 111949321 A CN111949321 A CN 111949321A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
Abstract
The invention provides a firmware code execution method, a memory storage device and a memory control circuit unit. The method comprises the following steps: executing the firmware code in the read-only memory; after executing the first part of the firmware code, inquiring reference information in a reference memory according to index information in the firmware code; and determining to continue to execute the second part of the firmware code or switch to execute the alternative program code in the reference memory according to the reference information so as to complete the starting program. Therefore, the use flexibility of the memory storage device (or the memory control circuit unit) can be improved, and/or the service life of the memory storage device (or the memory control circuit unit) can be prolonged.
Description
Technical Field
The present invention relates to a memory management technology, and more particularly, to a firmware code execution method, a memory storage device, and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
Most memory storage devices or their control chips store firmware code for startup. When the computer is started, the control chip of the memory storage device can execute the firmware code to complete a starting program or a starting program such as system initialization. Generally, before the Memory storage device or its control chip is shipped from a factory, the firmware code is pre-programmed into a Read Only Memory (ROM) of the Memory storage device or its control chip to prevent the device from being modified by a user during operation. However, this also results in the firmware code in the rom not being corrected or updated. If the firmware code in the ROM is required to be updated, the whole process of the ROM needs to be redone.
Disclosure of Invention
The invention provides a firmware code execution method, a memory storage device and a memory control circuit unit, which can dynamically adjust the execution result of the firmware code which cannot be modified in a read-only memory.
An exemplary embodiment of the present invention provides a method for executing firmware code, which is applied to a memory storage device, wherein the memory storage device includes a read only memory and a reference memory. The execution method of the firmware code comprises the following steps: executing the firmware code in the read-only memory; after the first part of the firmware code is executed, inquiring reference information in the reference memory according to index information in the firmware code; and determining to continue to execute the second part of the firmware code or switch to execute the alternative program code in the reference memory according to the reference information so as to complete the starting program.
In an exemplary embodiment of the invention, the step of determining to continue executing the second part of the firmware code or switching to executing the alternative program code in the reference memory according to the reference information comprises: if the reference information comprises first identification information, continuing to execute the second part of the firmware code after executing the first part of the firmware code; and if the reference information comprises second identification information, switching to executing the alternative program code in the reference memory after executing the first part of the firmware code.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a host interface, a rewritable nonvolatile memory module and a memory control circuit unit. The host interface is used for connecting to a host system. The memory control circuit unit is connected to the host interface and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the firmware code in the read-only memory. After executing the first part of the firmware code, the memory control circuit unit is further configured to query reference information in a reference memory according to index information in the firmware code. The memory control circuit unit is further configured to determine to continue to execute the second portion of the firmware code or switch to execute the alternative program code in the reference memory according to the reference information to complete a boot process.
An exemplary embodiment of the present invention further provides a memory control circuit unit, which includes a read only memory, a reference memory and a memory control circuit. The read-only memory is used for storing the firmware code. The reference memory is used for storing reference information. The memory control circuit is connected to the read only memory and the reference memory. The memory control circuit is used for executing the firmware codes in the read-only memory. After executing the first part of the firmware code, the memory control circuit is further configured to query the reference information in the reference memory according to the index information in the firmware code. The memory control circuit is further configured to determine to continue executing the second portion of the firmware code or switch to executing the alternative program code in the reference memory according to the reference information to complete a boot process.
In an example embodiment of the present invention, the reference memory includes an electronic fuse structure.
In an exemplary embodiment of the present invention, the reference memory includes a random access memory.
In an exemplary embodiment of the invention, the operation of determining to continue executing the second part of the firmware code or switching to executing the alternative program code in the reference memory according to the reference information comprises: if the reference information comprises first identification information, continuing to execute the second part of the firmware code after executing the first part of the firmware code; and if the reference information comprises second identification information, switching to executing the alternative program code in the reference memory after executing the first part of the firmware code.
In an exemplary embodiment of the invention, the boot procedure includes powering on or waking up the memory storage device.
Based on the above, after the first part of the firmware code is executed, the reference information in the reference memory can be queried according to the index information in the firmware code. Then, it is determined to continue executing the second part of the firmware code or switch to executing the alternative program code in the reference memory according to the reference information to complete the boot process. Therefore, the execution result of the firmware code in the read-only memory can be dynamically adjusted without reworking the process of the read-only memory, so that the use flexibility of the memory storage device (or the memory control circuit unit) is improved and/or the service life of the memory storage device (or the memory control circuit unit) is prolonged.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 2 is a diagram illustrating the execution of firmware code adjustment according to an exemplary embodiment of the present invention;
FIG. 3 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;
fig. 4 is a flowchart illustrating a method for executing firmware code according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a diagram illustrating a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 1, a memory storage device 10 includes a memory control circuit unit 11 and a rewritable nonvolatile memory module 12. The memory control circuit unit 11 is connected to the rewritable nonvolatile memory module 12. The memory control circuit unit 11 may include at least one control chip and controls the rewritable nonvolatile memory module 12. In an exemplary embodiment, the memory control circuit unit 11 may also be used to control the whole or part of the operation of the memory storage device 10. The rewritable non-volatile memory module 12 may include any type of non-volatile memory cells and is used to store data non-volatile.
In an exemplary embodiment, the memory control circuit unit 11 includes a Read Only Memory (ROM)111, a reference memory 112, and a memory control circuit 113. The read only memory 111 is used to store data in a nonvolatile manner. In particular, the data in the rom 111 is burned into the rom before the memory storage device 10 or the memory control circuit unit 11 is shipped, and cannot be modified after the memory storage device 10 or the memory control circuit unit 11 is shipped.
The reference memory 112 is used to store data, either volatile or non-volatile. In contrast to the read only memory 111, the data stored in the reference memory 112 may be modified after the memory storage device 10 or the memory control circuit unit 11 is shipped. Thereby, after the memory storage device 10 or the memory control circuit unit 11 is shipped, the data in the reference memory 112 can be used to reinforce or update the data in the rom 111 that cannot be modified.
The memory control circuit 113 is connected to the read only memory 111 and the reference memory 112. The memory control circuit 113 is used for accessing the rom 111 and the reference memory 112 and sending a control command to control the rewritable nonvolatile memory module 12 (or the memory storage device 10) according to the access result of the rom 111 (and the reference memory 112). For example, the memory control circuit 113 may include a memory controller, or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable controller, Application Specific Integrated Circuit (ASIC), Programmable Logic Device (PLD), or other similar Device or combination of devices.
In an exemplary embodiment, the data stored in the rom 111 includes the firmware code 101. When the power-on signal is detected, the memory control circuit 113 can read and execute the firmware code 101 from the rom 111 to perform a boot process. For example, the boot process may be a boot process (also referred to as an initialization process) or a wake-up process. The boot program is used to boot the memory storage device 10. The wake-up procedure is used to wake up the memory storage device 10 from a standby, hibernation, or sleep state. In response to the execution of the firmware code 101, the memory control circuit 113 can send at least one access command to the rewritable nonvolatile memory module 12 to read data from a specific physical address in the rewritable nonvolatile memory module 12 and/or write data to a specific physical address in the rewritable nonvolatile memory module 12 during the boot-up procedure.
In an exemplary embodiment, the data stored in the reference memory 112 includes the reference information 102 and the alternative program code 103. After executing a portion (also referred to as a first portion) of the firmware code 101, the memory control circuit 113 may query the reference information 102 in the reference memory 112 according to the index information in the firmware code 101. The memory control circuit 113 can determine to continue to execute another part (also referred to as a second part) of the firmware code 101 or switch to execute the alternative program code 103 in the reference memory 112 according to the reference information 102 to complete the boot process. It should be noted that the second part of the firmware code 101 is preset to be executed after the first part of the firmware code 101. Thus, if switching to executing the alternative program code 103, the second portion of the firmware code 101 may be skipped over from being executed.
Assume that the firmware code 101 originally burned in the rom 111 is set for a specific type of memory storage device or the firmware code 101 has an error. Conventionally, if the firmware code 101 is compatible with other types of memory storage devices or errors in the firmware code 101 are corrected, a rework process is generally required to burn new firmware codes into the rom 111, but this increases the cost of manufacturers. In an exemplary embodiment, by switching to executing the replacement code 103 (and skipping over the second portion of the firmware code 101), the original execution result of the firmware code 101 can be changed to achieve the same or similar effect as directly updating the firmware code 101.
In an exemplary embodiment, it is assumed that the at least one first access instruction may be issued in response to execution of the second portion of the firmware code 101. The at least one first access instruction may indicate an access physical address a. After switching to execution of the alternative program code 103, the at least one second access instruction may be issued in response to execution of the alternative program code 103. The at least one second access instruction may indicate an access to physical address B. Physical address a is different from physical address B.
In an exemplary embodiment, it is assumed that at least one third access instruction may be issued in response to execution of the second portion of the firmware code 101. The at least one third access command can instruct to write the data C to the physical address a of the rewritable nonvolatile memory module 12. After switching to execution of the alternative program code 103, the at least one fourth access instruction may be issued in response to execution of the alternative program code 103. The at least one fourth access command can instruct to write the data D to the physical address a (or the physical address B) of the rewritable nonvolatile memory module 12. Data D is different from data C.
In an example embodiment, different control instructions may also be issued in response to execution of the second portion of the firmware code 101 and in response to execution of the replacement program code 103. The different control instructions may be used to control or configure the electronic components in memory storage device 10 differently. Alternatively, in an exemplary embodiment, at least a portion of the system information of the memory storage device 10 may be configured differently in the boot program in response to the execution of the second portion of the firmware code 101 and in response to the execution of the alternative program code 103, and the invention is not limited thereto.
Fig. 2 is a diagram illustrating a result of adjusting firmware code according to an exemplary embodiment of the present invention. Referring to fig. 1 and 2, in an example embodiment, the memory control circuit 113 includes a memory controller 21. The firmware code 101 includes firmware codes 201 and 202. Firmware code 201 is the first part of firmware code 101. Firmware code 202 is the second part of firmware code 101. The firmware code 202 is subsequent to the firmware code 201, and the Index information Index (1) is inserted between the firmware codes 201 and 202.
When the boot signal or the boot signal is detected, the memory controller 21 may execute the firmware 101 to execute the boot program. In the boot process, the memory controller 21 may first execute the firmware code 201. After executing the firmware code 201, the memory controller 21 may read the Index information Index (1) when the position P (1) is reached. The memory controller 21 may query the reference information 102 from the reference memory 112 according to the Index information Index (1) and determine to continue executing the firmware code 202 or switch to executing the 112-substituted program code 103 in the reference memory according to the query result.
In an exemplary embodiment, if the query result reflects that the identification information corresponding to the Index information Index (1) in the reference information 102 is the first identification information (e.g., the enabling information OFF). After executing the firmware code 201, the memory controller 21 may continue to execute the firmware code 202 according to the query result. In other words, in the exemplary embodiment, the memory controller 21 will continuously execute the firmware codes 201 and 202 in the firmware code 101.
In an exemplary embodiment, if the query result reflects the identification information corresponding to the Index information Index (1) in the reference information 102 as the second identification information (e.g., enabling information ON). After executing the firmware code 201, the memory controller 21 may switch to execute the alternative program code 103 in the reference memory 112 according to the query result. In other words, in the exemplary embodiment, the memory controller 21 will continuously execute the firmware code 201 in the firmware code 101 and the replacement program code 103 in the reference memory 112. Furthermore, in this example embodiment, firmware code 202 would be skipped over from being executed.
It is noted that although the exemplary embodiment of FIG. 2 only divides the firmware code into two portions. However, in another exemplary embodiment, the firmware code may be divided into more portions, and the index information may be inserted between any two consecutive portions. In the execution process of the firmware code, if a certain index information is read, the index information can be used for inquiring the reference information and determining whether to execute the firmware code of the subsequent part or switch to execute the corresponding alternative program code in the reference memory according to the inquiry result.
In an example embodiment, the reference memory 112 of FIG. 1 includes an electronic fuse (eFuse) structure. Reference information 102 and/or alternative programming code 103 may be stored in this electronic fuse structure.
In an example embodiment, the reference memory 112 of FIG. 1 includes a Random Access Memory (RAM). Reference information 102 and/or alternative programming code 103 may be stored in such random access memory.
FIG. 3 is a diagram illustrating a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 3, the memory storage device 30 includes a connection interface unit 31, a memory control circuit unit 32, and a rewritable nonvolatile memory module 33. It is noted that the memory control circuit unit 32 can include the memory control circuit unit 11 of FIG. 1, and the rewritable nonvolatile memory module 33 can include the rewritable nonvolatile memory module 12 of FIG. 1.
The connection interface unit 31 is used to connect the memory storage device 30 to a host system. In the present exemplary embodiment, the connection interface unit 31 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 31 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Memory (Flash) interface standard, the CF interface standard, the Device Electronic interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 31 may be packaged with the memory control circuit unit 32 in a chip, or the connection interface unit 31 may be disposed outside a chip including the memory control circuit unit 32.
The memory control circuit unit 32 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 33 according to commands of a host system.
The rewritable nonvolatile memory module 33 is connected to the memory control circuit unit 32 and is used for storing data written by the host system. The rewritable nonvolatile memory module 33 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 33 stores one or more bits with a change in voltage (also called a threshold voltage). For example, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 33 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 33 may constitute a plurality of physical program cells, and the physical program cells may constitute a plurality of physical erase cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical programming unit is faster than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.
In an example embodiment, the physical programming cell is the smallest cell programmed. That is, the physical programming cell is the smallest cell to which data is written. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical program units are physical pages, the physical program units generally include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
Fig. 4 is a flowchart illustrating a method for executing firmware code according to an exemplary embodiment of the present invention. Referring to fig. 4, in step S401, the firmware code in the rom is executed. In step S402, after executing the first part of the firmware code, the reference information in the reference memory is queried according to the index information in the firmware code. In step S403, it is determined to continue to execute the second part of the firmware code or switch to execute the alternative program code in the reference memory according to the reference information, so as to complete the boot process.
However, the steps in fig. 4 have been described in detail above, and are not described again here. It is noted that, the steps in fig. 4 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 4 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.
In summary, after the first part of the fixed code is executed, the reference information in the reference memory may be queried according to the index information in the fixed code. Then, it is determined to continue executing the second part of the firmware code or switch to executing the alternative program code in the reference memory according to the reference information to complete the boot process. Therefore, the execution result of the firmware code in the read-only memory can be dynamically adjusted without reworking the process of the read-only memory, so that the use flexibility of the memory storage device (or the memory control circuit unit) is improved and/or the service life of the memory storage device (or the memory control circuit unit) is prolonged.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (15)
1. The execution method of the firmware code is used for a memory storage device, wherein the memory storage device comprises a read-only memory and a reference memory, and the execution method of the firmware code comprises the following steps:
executing the firmware code in the read-only memory;
after the first part of the firmware code is executed, inquiring reference information in the reference memory according to index information in the firmware code; and
and determining to continue to execute the second part of the firmware code or switch to execute the alternative program code in the reference memory according to the reference information so as to finish the starting program.
2. The method of claim 1, wherein the reference memory comprises an electronic fuse structure.
3. The method of claim 1, wherein the reference memory comprises a random access memory.
4. The method for executing firmware code according to claim 1, wherein the step of deciding to continue executing the second portion of the firmware code or to switch to executing the alternative program code in the reference memory according to the reference information comprises:
if the reference information comprises first identification information, continuing to execute the second part of the firmware code after executing the first part of the firmware code; and
if the reference information includes second identification information, switching to executing the alternative program code in the reference memory after executing the first portion of the firmware code.
5. The method for executing firmware code according to claim 1, wherein the boot-up procedure comprises powering on or waking up the memory storage device.
6. A memory storage device, comprising:
a host interface for connecting to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit connected to the host interface and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for executing firmware codes in the read only memory,
after executing the first part of the firmware code, the memory control circuit unit is further configured to query reference information in a reference memory according to the index information in the firmware code, and
the memory control circuit unit is further configured to determine to continue to execute the second portion of the firmware code or switch to execute the alternative program code in the reference memory according to the reference information to complete a boot process.
7. The memory storage device of claim 6, wherein the reference memory comprises an electronic fuse structure.
8. The memory storage device of claim 6, wherein the reference memory comprises a random access memory.
9. The memory storage device of claim 6, wherein deciding to continue executing the second portion of the firmware code or switch to executing the alternative program code in the reference memory according to the reference information comprises:
if the reference information comprises first identification information, continuing to execute the second part of the firmware code after executing the first part of the firmware code; and
if the reference information includes second identification information, switching to executing the alternative program code in the reference memory after executing the first portion of the firmware code.
10. The memory storage device of claim 6, wherein the boot procedure comprises powering on or waking up the memory storage device.
11. A memory control circuit unit, comprising:
the read-only memory is used for storing the firmware code;
a reference memory for storing reference information; and
a memory control circuit connected to the read only memory and the reference memory,
wherein the memory control circuit is used for executing the firmware code in the read only memory,
after executing the first part of the firmware code, the memory control circuit is further configured to query the reference information in the reference memory according to the index information in the firmware code, and
the memory control circuit is further configured to determine to continue executing the second portion of the firmware code or switch to executing the alternative program code in the reference memory according to the reference information to complete a boot process.
12. The memory control circuit cell of claim 11, wherein the reference memory comprises an electronic fuse structure.
13. The memory control circuit cell of claim 11, wherein the reference memory comprises a random access memory.
14. The memory control circuitry unit of claim 11, wherein deciding to continue executing the second portion of the firmware code or switch to executing the alternative program code in the reference memory according to the reference information comprises:
if the reference information comprises first identification information, continuing to execute the second part of the firmware code after executing the first part of the firmware code; and
if the reference information includes second identification information, switching to executing the alternative program code in the reference memory after executing the first portion of the firmware code.
15. The memory control circuitry unit of claim 11, wherein the boot-up procedure comprises powering-on or waking up the memory storage device.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112820341A (en) * | 2021-03-03 | 2021-05-18 | 群联电子股份有限公司 | Memory checking method, memory checking device and memory checking system |
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