CN112860194B

CN112860194B - Memory control method, memory storage device and memory control circuit unit

Info

Publication number: CN112860194B
Application number: CN202110292363.7A
Authority: CN
Inventors: 杨宇翔; 林纬; 刘安城; 刘宇恒; 赖淳熙; 詹庭鑑
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2021-03-18
Filing date: 2021-03-18
Publication date: 2024-01-23
Anticipated expiration: 2041-03-18
Also published as: CN112860194A

Abstract

The invention provides a memory control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: programming a plurality of first memory cells in a first physical erase unit in a rewritable nonvolatile memory module; and applying an electrical pulse to at least one word line of the rewritable non-volatile memory module, wherein the at least one word line is connected to a plurality of second memory cells in the first physically erased cells, the plurality of second memory cells including the plurality of first memory cells being programmed, and the electrical pulse is not used to read, program or erase the plurality of second memory cells. Therefore, the data storage capacity and/or the data erasing efficiency of the memory cell can be improved.

Description

Memory control method, memory storage device and memory control circuit unit

Technical Field

The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.

Background

Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, such that consumer demand for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., flash memory) has characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for being built in the above-exemplified various portable multimedia devices.

The memory cells in the rewritable nonvolatile memory module are used for storing data by injecting charges into the memory cells. However, the charge injected into the memory cell may be lost with increasing data storage time, increasing data access operations, and/or temperature changes, resulting in increased decoding difficulty in subsequent data reads. In addition, the lost charge may also be used to oppose the erase voltage during subsequent erasing of the memory cell, resulting in reduced erase efficiency of the memory cell.

Disclosure of Invention

The invention provides a memory control method, a memory storage device and a memory control circuit unit, which can improve the data storage capacity and/or the data erasing efficiency of a storage unit.

An exemplary embodiment of the present invention provides a memory control method for a rewritable nonvolatile memory module including a plurality of physical erasing units, the memory control method comprising: programming a plurality of first memory cells in a first physical erase unit of the plurality of physical erase units; and applying an electrical pulse to at least one word line of the rewritable non-volatile memory module, wherein the at least one word line is connected to a plurality of second memory cells in the first physically erased cells, the plurality of second memory cells including the plurality of first memory cells being programmed, and the electrical pulse is not used to read, program or erase the plurality of second memory cells.

In an exemplary embodiment of the present invention, the step of applying the electronic pulse to the at least one word line includes: applying the electron pulse with a positive voltage to the at least one word line.

In an exemplary embodiment of the invention, the memory control method further includes: the step of applying the electronic pulse to the at least one word line is repeated every time interval.

In an exemplary embodiment of the invention, the memory control method further includes: obtaining a temperature of the rewritable non-volatile memory module; and adjusting the time interval according to the temperature.

In an exemplary embodiment of the present invention, the step of applying the electronic pulse to the at least one word line includes: applying the electronic pulse with a negative voltage to the at least one word line.

In an exemplary embodiment of the invention, the memory control method further includes: after applying the electrical pulse to the at least one word line, erasing the plurality of second memory cells.

The exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for being connected to a host system. The rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for sending a write command sequence to instruct to program a plurality of first memory cells in a first physical erasing unit in the plurality of physical erasing units. The rewritable nonvolatile memory module is used for applying an electronic pulse to at least one word line. The at least one word line is connected to a plurality of second memory cells in the first physically erased cell. The plurality of second memory cells includes the plurality of first memory cells programmed. The electronic pulse is not used for reading, programming or erasing the second memory cells.

In an example embodiment of the present invention, the rewritable nonvolatile memory module is configured to: the operation of applying the electronic pulse to the at least one word line is repeatedly performed every time interval.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: obtaining a temperature of the rewritable non-volatile memory module; and adjusting the time interval according to the temperature.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: after applying the electronic pulse to the at least one word line, an erase command sequence is sent to instruct erasing the plurality of second memory cells.

The exemplary embodiments of the present invention further provide a memory control circuit unit, which includes a host interface, a memory interface, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to a rewritable non-volatile memory module. The rewritable nonvolatile memory module comprises a plurality of physical erasing units. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used for sending a write command sequence to instruct to program a plurality of first memory cells in a first physical erasing unit in the plurality of physical erasing units. The memory management circuit is further configured to send a special control instruction to instruct application of an electronic pulse to at least one word line of the rewritable non-volatile memory module. The at least one word line is connected to a plurality of second memory cells in the first physically erased cell. The plurality of second memory cells includes the plurality of first memory cells programmed. The electronic pulse is not used for reading, programming or erasing the second memory cells.

In an example embodiment of the present invention, the operation of applying the electronic pulse to the at least one word line includes: applying the electron pulse with a positive voltage to the at least one word line.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: and repeatedly sending the special control instruction every time interval.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: obtaining a temperature of the rewritable non-volatile memory module; and adjusting the time interval according to the temperature.

In an example embodiment of the present invention, the operation of applying the electronic pulse to the at least one word line includes: applying the electronic pulse with a negative voltage to the at least one word line.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: after applying the electronic pulse to the at least one word line, an erase command sequence is sent to instruct erasing the plurality of second memory cells.

In an exemplary embodiment of the present invention, the electron pulse is used to change the number of electrons in the tunnel oxide layer of at least one of the plurality of second memory cells.

In an exemplary embodiment of the invention, the plurality of second memory cells includes all memory cells in the first physically erased cell.

Based on the above, after programming a plurality of first memory cells in the first physical erase unit, an electrical pulse can be applied to at least one word line of the rewritable nonvolatile memory module. The at least one word line is connected to a plurality of second memory cells in the first physically erased cell. The plurality of second memory cells includes the plurality of first memory cells programmed. In particular, the electrical pulse is not used to read, program or erase the second memory cells. Therefore, the data storage capacity and/or the data erasing efficiency of the memory cell can be improved.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5A is a schematic diagram of a memory cell array according to an example embodiment of the invention;

FIG. 5B is a schematic diagram of a memory cell according to an example embodiment of the invention;

FIG. 5C is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;

FIG. 7 is a schematic diagram of a programmable memory cell according to an example embodiment of the invention;

FIG. 8A is a schematic diagram illustrating the application of an electronic pulse with a positive voltage to a memory cell according to an example embodiment of the present invention;

FIG. 8B is a schematic diagram illustrating voltage ranges of an electronic pulse with positive voltage according to an example embodiment of the invention;

FIG. 9A is a schematic diagram of applying an electrical pulse with a negative voltage to a memory cell according to an example embodiment of the invention;

FIG. 9B is a schematic diagram illustrating voltage ranges of an electronic pulse with negative voltage according to an example embodiment of the invention;

Fig. 10 is a flowchart illustrating a memory control method according to an example embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are all connected to a system bus 110.

In an exemplary embodiment, host system 11 is coupled to memory storage device 10 via data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.

In an exemplary embodiment, the processor 111, the ram 112, the rom 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by a wired or wireless connection through the data transmission interface 114. The memory storage device 10 may be, for example, a usb flash disk 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless fidelity (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207. In an example embodiment, the host system is a computer system. In an example embodiment, the host system is any system that may substantially cooperate with a memory storage device to store data.

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the invention. Referring to fig. 3, in an exemplary embodiment, the host system 31 may also be a system such as a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded storage device 34 includes embedded storage devices of various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 that directly connect the memory module to a substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In an example embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard compliant with a parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, an institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, a High-Speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, s) interface standard, an ehcp interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.

The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable nonvolatile memory module 406 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable nonvolatile memory module 406 has a plurality of memory states as the threshold voltage is changed. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

FIG. 5A is a schematic diagram of a memory cell array according to an example embodiment of the invention. Referring to fig. 5A, a memory cell array 510 includes a plurality of memory cells 502 for storing data, a plurality of select gate drain (select gate drain, SGD) transistors 512 and a plurality of select gate source (select gate source, SGS) transistors 514, a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 connecting the memory cells 502. Memory cells 502 are arranged in an array at the intersections of bit lines 504 and word lines 506, as shown in FIG. 5A. The rewritable nonvolatile memory module 406 may include a plurality of memory cell arrays 510. Such memory cell arrays 510 may be stacked horizontally and/or vertically.

FIG. 5B is a schematic diagram of a memory cell according to an example embodiment of the invention. Referring to fig. 5B, the memory cell 502 is also referred to as a flash memory device. The memory cell 502 includes a control gate 521, an inter-polysilicon dielectric layer (Interpoly Dielectric) 522, a charge trapping layer (charge trapping layer) 523, a Tunneling Oxide layer (Tunneling Oxide) 524, and a Substrate (Substrate) 525. Control gate 521 may be connected to word line 506 of fig. 5A. The charge trapping layer 523 is used to store electrons. The control gate 521, the inter-polysilicon dielectric layer 522, the charge trapping layer 523 and the tunnel oxide layer 524 are sequentially stacked on the substrate 525.

When data is to be written into the memory cell 502 (i.e., programming the memory cell 502), electrons are injected into the charge trapping layer 523 by applying a write voltage (also referred to as a program voltage) to change the voltage (i.e., threshold voltage) of the memory cell 502. The threshold voltage may be used to reflect the data storage state of the memory cell 502. For example, different threshold voltages of memory cell 502 may reflect different data storage states of memory cell 502. By adjusting the voltage of the memory cell 502 to a certain voltage position, data storage of the memory cell 502 can be achieved. On the other hand, when the stored data is to be removed from the memory cell 502, the injected electrons can be removed from the charge trapping layer 523 by applying an erase voltage. The erased memory cell 502 may revert to a pre-programmed state.

FIG. 5C is a schematic block diagram of a rewritable nonvolatile memory module according to an example embodiment of the present invention. Referring to fig. 5C, the rewritable nonvolatile memory module 406 includes a memory cell array 510, a word line control circuit 531, a bit line control circuit 532, a column decoder 533, a data input/output buffer 534 and a control circuit 535.

The word line control circuit 531 is used to control the voltage applied to the word line 506 of fig. 5A. The bit line control circuit 532 is used to control the voltage applied to the bit line 504 of FIG. 5A. The row decoder 533 is configured to select the corresponding bit line according to the decoded column address in the write command sequence or the read command sequence. The data input/output buffer 534 is used to temporarily store data. The control circuit 535 may control the word line control circuit 531, the bit line control circuit 532, the row decoder 533, and the data input/output buffer 534 to write data to the memory cell array 510 or read data from the memory cell array 510.

In an example embodiment, the memory cells in the rewritable nonvolatile memory module 406 may constitute a plurality of physical program cells, and the physical program cells may constitute a plurality of physical erase cells. Specifically, memory cells on the same word line may constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be categorized into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is that belonging to the lower physical programming cell, and the most significant bit (Most Significant Bit, MSB) of a memory cell is that belonging to the upper physical programming cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In an exemplary embodiment, the physical programming unit is a minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units may include data bits and redundancy bits. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and a physical sector has a size of 512 bytes (B). However, in other exemplary embodiments, 8, 16 or a greater or lesser number of physical fans may be included in the data bit zone, and the size of each physical fan may be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

FIG. 6 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to fig. 6, the memory control circuit unit 404 includes a memory management circuit 602, a host interface 604, and a memory interface 606.

The memory management circuit 602 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 602 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is operating. The operation of the memory management circuit 602 is described as follows, which is equivalent to the description of the operation of the memory control circuit unit 404.

In an example embodiment, the control instructions of the memory management circuit 602 are implemented in firmware. For example, the memory management circuit 602 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another example embodiment, the control instructions of the memory management circuit 602 may also be stored in program code form in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 602 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 602. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.

Furthermore, in another example embodiment, the control instructions of the memory management circuit 602 may also be implemented in a hardware type. For example, the memory management circuit 602 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage memory cells or groups of memory cells of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 602 may also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 604 is coupled to the memory management circuitry 602. The memory management circuitry 602 may communicate with the host system 11 through a host interface 604. The host interface 604 may be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transferred by host system 11 may be transferred to memory management circuitry 602 via host interface 604. In addition, the memory management circuitry 602 may communicate data to the host system 11 through the host interface 604. In an example embodiment, host interface 604 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 604 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.

The memory interface 606 is coupled to the memory management circuitry 602 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 606. Specifically, if the memory management circuit 602 is to access the rewritable nonvolatile memory module 406, the memory interface 606 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These sequences of instructions are, for example, generated by memory management circuitry 602 and transferred to rewritable non-volatile memory module 406 through memory interface 606. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.

In an example embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 608, a buffer memory 610, and a power management circuit 612.

An error checking and correction circuit (also referred to as a decoding circuit) 608 is coupled to the memory management circuit 602 and is configured to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 602 receives a write command from the host system 11, the error checking and correcting circuit 608 generates a corresponding error correction code (error correcting code, ECC) and/or error detection code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 602 writes the data corresponding to the write command and the corresponding error correction code and/or error detection code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 602 reads data from the rewritable nonvolatile memory module 406, it reads the error correction code and/or error detection code corresponding to the data, and the error checking and correction circuit 608 performs an error checking and correction operation on the read data according to the error correction code and/or error detection code.

The power management circuit 612 is coupled to the memory management circuit 602 and is used to control the power of the memory storage device 10. The buffer memory 610 is connected to the memory management circuit 602 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

In an example embodiment, the rewritable non-volatile memory module 406 of fig. 4 is also referred to as a flash memory module, the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module, and/or the memory management circuit 602 of fig. 6 is also referred to as a flash memory management circuit.

The memory management circuit 602 may configure the logic to map the physical units in the rewritable non-volatile memory module 406. For example, a logical unit may refer to a logical address, a logical program unit, a logical erase unit, or be made up of multiple consecutive or non-consecutive logical addresses. For example, a physical unit may refer to a physical address, a physical program unit, a physical erase unit, or consist of multiple consecutive or non-consecutive physical addresses. In addition, a logical unit may be mapped to one or more physical units.

The memory management circuit 602 may record a mapping relationship (also referred to as a logical-to-physical mapping relationship) between logical units and physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 602 can perform data access to the memory storage device 10 according to the logical-to-physical mapping table.

In an example embodiment, the memory management circuit 602 may send a sequence of write instructions to the rewritable nonvolatile memory module 406. The write command sequence may be used to instruct the rewritable nonvolatile memory module 406 to program a plurality of memory cells (also referred to as first memory cells) in a certain physical erase unit (also referred to as first physical erase unit). Such first memory units may belong to the same physical programming unit. The programmed first memory cell may be used to store data. For example, this sequence of write instructions may be sent in response to a write instruction from host system 11. The first memory unit is used for storing data corresponding to the writing instruction.

FIG. 7 is a schematic diagram of a programmable memory cell according to an example embodiment of the invention. Referring to fig. 7, after programming the memory cell 502, electrons can be injected into the charge trapping layer 523 of the memory cell 502, thereby changing the voltage (i.e., threshold voltage) of the memory cell 502. In addition, the amount of electrons injected into the charge trapping layer 523 may be different to reflect the bit value of one or more bits stored by the memory cell 502.

It should be noted that as the storage time of the data in the memory cell 502 increases, the data access operation to the memory cell 502 increases, and/or the temperature of the memory cell 502 changes, electrons stored in the charge trapping layer 523 may gradually be lost. For example, some electrons may be lost from the charge trapping layer 523 to the tunnel oxide layer 524, as shown in fig. 7. Once the number of electrons lost exceeds a predetermined value, an excessive voltage offset may cause the memory state of the memory cell 502 to change, for example, from the original memory bit "0" (i.e., the correct bit) to the memory bit "1" (i.e., the error bit). As more and more memory cells 502 experience voltage shifts, more erroneous bits may be entrained in the data subsequently read from such memory cells 502, resulting in increased decoding difficulty in subsequently reading the data.

In an example embodiment, after programming the first memory cells in the first physical erase unit, the memory management circuit 602 may send special control instructions to the rewritable nonvolatile memory module 406. This special control command may instruct the rewritable nonvolatile memory module 406 to apply an electrical pulse to at least one word line. The at least one word line is connected to a plurality of memory cells (also referred to as second memory cells) in the first physically erased cell. The plurality of second memory cells includes the first memory cell programmed.

It should be noted that the electrical pulse is not used to read, program or erase the second plurality of memory cells, as compared to the write voltage used to write data, the read voltage used to read data, and/or the erase voltage used to erase data. That is, the electronic pulse is not used to read data from the programmed memory cell, nor does the electronic pulse change the memory state of the programmed memory cell.

In an example embodiment, the electron pulse is used to change the number of electrons in the tunnel oxide layer of at least one of the plurality of second memory cells (or the first memory cells). By changing the number of electrons in the tunnel oxide layer of the programmed memory cell, the data quality of the data stored in the memory cell and/or the operation stability during subsequent operations such as erasing can be improved.

In an example embodiment, the second memory cell may include all memory cells in the first physically erased cell. In an example embodiment, the second memory cell may include a first memory cell and a portion of the other memory cells in the first physical erase cell. In an example embodiment, the second memory cell may include only the first memory cell.

In an exemplary embodiment, the electrical pulse may have a positive voltage. That is, after programming a plurality of first memory cells in the first physically erased cell, an electrical pulse with the positive voltage may be applied to a plurality of second memory cells in the first physically erased cell that include the first memory cells. The electron pulse with positive voltage can be used to slightly increase the number of electrons in the tunnel oxide layer of at least one of the plurality of second memory cells.

Fig. 8A is a schematic diagram illustrating the application of an electronic pulse with a positive voltage to a memory cell according to an example embodiment of the present invention. Referring to FIG. 8A, a memory cell 502 is used as an example of a second memory cell. After applying an electron pulse PS (+) with a positive voltage to the control gate 521 of the memory cell 502, a portion of electrons may be attracted from the substrate 525 to the tunnel oxide layer 524 and stay in the tunnel oxide layer 524. Such electrons residing in tunnel oxide layer 524 repel electrons that were originally injected into charge trapping layer 523 by programming memory cell 502, thereby reducing the probability of electrons in charge trapping layer 523 losing to tunnel oxide layer 524. Once the probability of electrons in the charge trapping layer 523 losing to the tunnel oxide layer 524 decreases, the probability of shifting the threshold voltage of the memory cell 502 correspondingly decreases, thereby improving the data quality of the data stored in the memory cell 502.

In an example embodiment, the voltage of the electrical pulse PS (+) may be slightly higher than the voltage of the substrate 525 (also referred to as the channel voltage) of the memory cell 502. Thus, after the electron pulse PS (+) is applied to the memory cell 502, a portion of the free electrons originally in the substrate 525 may be attracted to the tunnel oxide layer 524.

Fig. 8B is a schematic diagram illustrating voltage ranges of an electronic pulse with positive voltage according to an example embodiment of the invention. Referring to fig. 8A and 8B, in an exemplary embodiment, it is assumed that the first memory cell (or the second memory cell) is operated in TLC programming mode (i.e., one memory cell may be used to store 3 bits). The threshold voltage distribution 810 of the first memory cell (or the second memory cell) may include 8 states, er and a through G, respectively. These 8 states correspond to different data storage states, respectively, e.g., state Er corresponds to bit "111", while state G corresponds to "000", etc. It should be noted that the state Er is also referred to as an erase state. That is, after erasing a certain memory cell, the erased memory cell is in state Er.

In an exemplary embodiment, the voltage of the electronic pulse PS (+) may be approximately between the voltages VL (0) and VH (0). Voltage VL (0) is a default voltage level corresponding to state a. Voltage VH (0) is a default voltage level corresponding to state G. Alternatively, in an exemplary embodiment, assuming that there is an intermediate voltage level (e.g., at the vertical axis of fig. 8B) between the default voltage level corresponding to state Er and the default voltage level corresponding to state a, the voltage of the electronic pulse PS (+) may be between the intermediate voltage level and the default voltage level corresponding to any state (states a to G) to the right of the intermediate voltage level. Alternatively, in an exemplary embodiment, the electrical pulse PS (+) may be provided with a relatively positive voltage compared to the substrate 525 (or channel) of the memory cell 502.

In an example embodiment, the memory management circuit 602 may repeatedly send the special control instruction to the rewritable nonvolatile memory module 406 every time interval elapses. Thus, the rewritable nonvolatile memory module 406 can repeatedly perform the operation of applying the positive voltage to the at least one word line (or the second memory cell) every time interval, so as to continuously improve or maintain the data quality of the data stored in the first memory cell (or the second memory cell).

In an example embodiment, the memory management circuit 602 may obtain the temperature of the rewritable nonvolatile memory module 406. For example, this temperature may be detected by a temperature sensor of the memory storage device 10 or the host system 11. In an example embodiment, the temperature of the rewritable non-volatile memory module 406 may also reflect the internal temperature of the memory storage device 10 or the external ambient temperature.

In an example embodiment, the memory management circuit 602 may adjust the time interval based on this temperature. In an example embodiment, the length of the time interval may be inversely related to the temperature. For example, as the temperature of the rewritable nonvolatile memory module 406 gradually increases, the memory management circuit 602 may gradually shorten the time length of the time interval. Conversely, when the temperature of the rewritable nonvolatile memory module 406 gradually decreases, the memory management circuit 602 may gradually extend the time length of the time interval. For example, when the temperature of the rewritable nonvolatile memory module 406 is 80 degrees, the memory management circuit 602 may send the special control instruction once every 5 seconds and/or the rewritable nonvolatile memory module 406 may perform an operation of applying an electronic pulse with a positive voltage (e.g., the electronic pulse PS (+) in fig. 8A) to the at least one word line (or the second memory cell) once every 5 seconds. When the temperature of the rewritable nonvolatile memory module 406 is reduced to 60 degrees, the memory management circuit 602 may send the special control command once every 10 seconds and/or the rewritable nonvolatile memory module 406 may perform an operation of applying an electronic pulse with a positive voltage (e.g., the electronic pulse PS (+) in fig. 8A) to the at least one word line (or the second memory cell) once every 10 seconds.

In an exemplary embodiment, the electrical pulse may have a negative voltage. That is, after programming the plurality of first memory cells in the first physically erased cell, the electronic pulse with the negative voltage may be applied to the plurality of second memory cells in the first physically erased cell that include the first memory cells. The negative voltage-carrying electron pulse is used for slightly reducing the electron number in the tunneling oxide layer of at least one of the plurality of second memory cells.

FIG. 9A is a schematic diagram illustrating applying an electrical pulse with a negative voltage to a memory cell according to an example embodiment of the invention. Referring to FIG. 9A, a memory cell 502 is used as an example of a second memory cell. After applying the negative voltage-carrying electron pulse PS (-) to the control gate 521 of the memory cell 502, a portion of the electrons may be repelled from the tunnel oxide layer 524 into the substrate 525. Thereafter, when the erase voltage is applied to the control gate 521 by erasing the memory cell 502, electrons in the charge trapping layer 523 can be cleared more cleanly, thereby improving the erase efficiency of the memory cell 502.

In an example embodiment, the voltage of the electrical pulse PS (-) may be slightly lower than the voltage of the substrate 525 (i.e., the channel voltage) of the memory cell 502. Thus, after the electron pulse PS (-) is applied to the memory cell 502, a portion of the free electrons originally in the tunnel oxide layer 524 may be repelled by the electron pulse PS (-) and dissipated into the substrate 525.

Fig. 9B is a schematic diagram illustrating voltage ranges of an electronic pulse with negative voltage according to an example embodiment of the invention. Referring to fig. 9A and 9B, similar to the exemplary embodiment of fig. 8B, in an exemplary embodiment of fig. 9B, it is also assumed that the first memory cell (or the second memory cell) is operated in TLC programming mode.

In an exemplary embodiment, the voltage of the electric pulse PS (-) may be approximately between the voltages VL (1) and VH (1). Voltage VL (1) is a default voltage level for state Er. Voltage VH (1) is a default voltage level corresponding to state a. Alternatively, in an exemplary embodiment, assuming that the default voltage level corresponding to the state Er and the default voltage level corresponding to the state a have an intermediate voltage level (e.g., at the vertical axis of fig. 9B), the voltage of the electronic pulse PS (-) may be between the default voltage level corresponding to the state Er and the intermediate voltage level. Alternatively, in an exemplary embodiment, the electrical pulse PS (-) may be provided with a relatively negative voltage compared to the substrate 525 (or channel) of the memory cell 502.

In an example embodiment, the memory management circuit 602 may mark the data stored in the first physically erased cell as invalid. For example, the operation of marking the data stored in the first physical erase unit as invalid may be performed automatically by the memory management circuit 602 in response to a data deletion of the host system 11 or a data movement (e.g., garbage collection) within the memory management circuit 602. After marking the data stored in the first physical erase unit as invalid, the memory management circuit 602 may send the special control command to instruct the rewritable nonvolatile memory module 406 to apply an electronic pulse with a negative voltage (e.g., the electronic pulse PS (-) in fig. 9A) to the at least one word line (or the second memory unit). Thereafter, the memory management circuit 602 may send an erase command sequence to the rewritable nonvolatile memory module 406 to instruct the rewritable nonvolatile memory module 406 to erase the first physical erase unit.

In an example embodiment, after programming the first memory cell, the memory management circuit 602 may continue to instruct the rewritable nonvolatile memory module 406 to apply an electronic pulse with a positive voltage (e.g., the electronic pulse PS (+) in fig. 8A) to the second memory cell through the special control instruction to maintain or increase the data storage capacity of the first memory cell (or the second memory cell). However, after marking the data stored in the first physically erased cell as invalid (and prior to actually erasing the first physically erased cell), the memory management circuit 602 may instead instruct the rewritable nonvolatile memory module 406 to apply an electronic pulse with a negative voltage (e.g., the electronic pulse PS (-) in fig. 9A) to the second memory cell by the special control command to improve the subsequent erasing efficiency of the first memory cell (or the second memory cell).

It should be noted that in the foregoing exemplary embodiments, the rewritable nonvolatile memory module 406 is exemplified by applying a specific electronic pulse to the second memory cell in response to an instruction (i.e., a special control instruction) from the memory management circuit 602. However, in an exemplary embodiment, the rewritable nonvolatile memory module 406 may also be configured to automatically perform the operation of applying the electronic pulse with the positive voltage (e.g., the electronic pulse PS (+) in fig. 8A) to the second memory cell without the instruction of the memory management circuit 602 after programming the first memory cell, and/or to automatically perform the operation of applying the electronic pulse with the negative voltage (e.g., the electronic pulse PS (-) in fig. 9A) to the second memory cell without the instruction of the memory management circuit 602 before erasing the first physical erase cell.

Fig. 10 is a flowchart illustrating a memory control method according to an example embodiment of the present invention. Referring to fig. 10, in step S1001, a first entity in a programmable rewritable nonvolatile memory module erases a plurality of first memory cells in the cells. In step S1002, an electronic pulse is applied to at least one word line of the rewritable nonvolatile memory module, wherein the at least one word line is connected to a plurality of second memory cells in the first physically erased cells, the plurality of second memory cells includes the plurality of first memory cells programmed, and the electronic pulse is not used to read, program or erase the plurality of second memory cells.

However, the steps in fig. 10 are described in detail above, and will not be described again here. It should be noted that each step in fig. 10 may be implemented as a plurality of program codes or circuits, and the present invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, in a rewritable nonvolatile memory module, a specific electrical pulse may be applied to a second memory cell including the first memory cell when the first memory cell is in a different state (e.g., after being programmed or before being erased). Thus, the data storage capacity and/or the data erasing efficiency of the memory cells can be improved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A memory control method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical erase units, the memory control method comprising:

programming a plurality of first memory cells in a first physical erase unit of the plurality of physical erase units; and

applying an electron pulse to at least one word line of the rewritable non-volatile memory module, wherein the at least one word line is connected to a plurality of second memory cells in the first physically erased cells, the plurality of second memory cells including the plurality of first memory cells being programmed, wherein the electron pulse is used to change the number of electrons in a tunnel oxide layer of at least one of the plurality of second memory cells, and the electron pulse is not used to read, program or erase the plurality of second memory cells.

2. The memory control method of claim 1, wherein the step of applying the electronic pulse to the at least one word line comprises:

applying the electron pulse with a positive voltage to the at least one word line.

3. The memory control method according to claim 1, further comprising:

the step of applying the electronic pulse to the at least one word line is repeated every time interval.

4. The memory control method according to claim 3, further comprising:

obtaining a temperature of the rewritable non-volatile memory module; and

and adjusting the time interval according to the temperature.

5. The memory control method of claim 1, wherein the step of applying the electronic pulse to the at least one word line comprises:

applying the electronic pulse with a negative voltage to the at least one word line.

6. The memory control method according to claim 1, further comprising:

after applying the electrical pulse to the at least one word line, erasing the plurality of second memory cells.

7. The memory control method of claim 1, wherein the plurality of second memory cells includes all memory cells in the first physically erased cell.

8. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

the rewritable nonvolatile memory module comprises a plurality of entity erasing units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for sending a write command sequence to instruct to program a plurality of first memory units in a first physical erasing unit in the plurality of physical erasing units,

the rewritable nonvolatile memory module is used for applying an electronic pulse to at least one word line, the at least one word line is connected to a plurality of second memory cells in the first physical erasing unit, the plurality of second memory cells comprise the plurality of first memory cells which are programmed, wherein the electronic pulse is used for changing the electron number in a tunneling oxide layer of at least one of the plurality of second memory cells, and the electronic pulse is not used for reading, programming or erasing the plurality of second memory cells.

9. The memory storage device of claim 8, wherein the operation of applying the electronic pulse to the at least one word line comprises:

10. The memory storage device of claim 8, wherein the rewritable non-volatile memory module is to:

the operation of applying the electronic pulse to the at least one word line is repeatedly performed every time interval.

11. The memory storage device of claim 10, wherein the memory control circuit unit is further to:

obtaining a temperature of the rewritable non-volatile memory module; and

and adjusting the time interval according to the temperature.

12. The memory storage device of claim 8, wherein the operation of applying the electronic pulse to the connection to the at least one word line comprises:

13. The memory storage device of claim 8, wherein the memory control circuit unit is further to:

after applying the electronic pulse to the at least one word line, an erase command sequence is sent to instruct erasing the plurality of second memory cells.

14. The memory storage device of claim 8, wherein the plurality of second memory cells comprises all of the memory cells in the first physically erased cell.

15. A memory control circuit unit, comprising:

a host interface for connecting to a host system;

a memory interface for connecting to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to send a write command sequence to instruct programming of a plurality of first memory cells in a first physical erase unit of the plurality of physical erase units,

the memory management circuit is further configured to send a special control instruction to instruct application of an electronic pulse to at least one word line of the rewritable nonvolatile memory module, the at least one word line being connected to a plurality of second memory cells in the first physical erase unit, the plurality of second memory cells including the plurality of first memory cells being programmed, wherein the electronic pulse is configured to change an electron number in a tunnel oxide of at least one of the plurality of second memory cells, and the electronic pulse is not configured to read, program, or erase the plurality of second memory cells.

16. The memory control circuit unit of claim 15, wherein the operation of applying the electronic pulse to the at least one word line comprises:

17. The memory control circuit unit of claim 15, wherein the memory management circuit is further to:

and repeatedly sending the special control instruction every time interval.

18. The memory control circuit unit of claim 17, wherein the memory management circuit is further to:

obtaining a temperature of the rewritable non-volatile memory module; and

and adjusting the time interval according to the temperature.

19. The memory control circuit unit of claim 15, wherein applying the electronic pulse to the connection to the at least one word line comprises:

20. The memory control circuit unit of claim 15, wherein the memory management circuit is further to:

21. The memory control circuit unit of claim 15, wherein the plurality of second memory cells comprises all of the memory cells in the first physical erase unit.