JP2008251154A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device such as capable of executing an automatic reading operation of data from a specific address of a nonvolatile memory array, while a normal reading operation of the nonvolatile memory array is executed, which is responsive to a reading command and a reading address. <P>SOLUTION: The nonvolatile semiconductor memory device is equipped with the nonvolatile memory array 121 and a control circuit 120. In response to the reading command and reading address from the outside, the control circuit 120 executes the normal reading operation of data from the nonvolatile memory array 121 and outputs the normal reading data to the outside. In response to a specific signal PRE supplied from the outside when a power source is applied, the control circuit 120 executes the automatic reading operation of data from the specific address (0-order address) of the nonvolatile memory array so that the automatic reading data from this specific address are output to the outside. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of electrically writing and erasing stored information, for example, a flash memory having an area for storing management table information for managing a defective address having a function of replacing a defective area in a memory array It is related to effective technology.

  Flash memory uses a non-volatile memory element consisting of a double-gate MOSFET having a control gate and a floating gate as a memory cell, and changes the threshold voltage of the MOSFET by changing the amount of charge stored in the floating gate. Information is stored.

  The flash memory changes the threshold voltage during the write / erase operation to the memory cell. However, with the current manufacturing technology, even if the write / erase is performed under the same conditions, the change in the threshold voltage depends on the characteristics of the memory cell. Variations occur in the way, and in some cases, a defective memory cell whose threshold voltage does not change sufficiently may occur.

  In the conventional general flash memory, when a defective memory cell in which the threshold voltage does not sufficiently change is generated as described above, an alternative function for replacing a predetermined storage area including the defective memory cell with another normal storage area is provided. In addition, an area for storing management table information for managing defective addresses is often provided in the memory array.

  However, the conventional flash memory is generally adapted to rewrite management table information for managing defective addresses by an external controller. In addition, flash memory is called ECC when configuring a system using flash memory because the reliability of read data is lower than that of mask ROM or RAM due to variations in threshold voltages of memory cells or changes over time. An error check and correction function is provided to an external controller to improve data reliability. For this reason, the conventional flash memory has a problem that the burden on the system developer when developing a new system using the flash memory is large.

  In the conventional flash memory, the storage area including the defective memory cell is used as a system area for storing data important for the system such as table data, format information, and address conversion information for managing the position of the file on the memory. If this happens, the memory may not be recognized or the system may not operate normally.

  An object of the present invention is to reduce the burden on a system developer in an electrically writable / erasable nonvolatile semiconductor memory device such as a flash memory.

  Another object of the present invention is that in an electrically writable / erasable nonvolatile semiconductor memory device such as a flash memory, the system operates even if data important for the system such as management table data and address conversion information is damaged. It is to be able to avoid an abnormal state that disappears.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the first invention of the present application relates to a memory cell group and a defective memory cell including a defective memory cell incapable of normal writing or erasing in an electrically writable / erasable nonvolatile semiconductor memory device such as a flash memory. Replacement processing function that replaces memory cell groups that do not contain memory cells, and rewriting that replaces memory cell groups so that the number of data rewrites for each memory cell group is ascertained and there is no significant difference in the number of rewrites among multiple memory cell groups A number averaging processing function and an error correction function for detecting and correcting an error in data stored in the memory array are provided, and the first address conversion information by the alternative processing function and the rewrite number averaging processing function are used. Second address conversion information is stored in a predetermined area of the memory array, and the second address conversion information is stored in the memory cell group. The address conversion information and the second address conversion information is obtained by configured to chronologically plurality storage.

  According to the above means, since the nonvolatile semiconductor memory device has an alternative processing function and an error correction function, it is not necessary to perform an alternative process and an error correction process by an external controller, thereby reducing the burden on the system developer. At the same time, since a plurality of address translation information is stored, even if one of the address translation information is lost, it is possible to avoid an abnormal state where the system does not operate by substituting the other address translation information. Become.

  Preferably, the memory array is provided with two or more regions that do not affect each other when the power is cut off during a write or erase operation to any of the memory cell groups. The first address conversion information and the second address conversion information are configured to be stored in order in two or more areas. As a result, even if the data in any area for storing the address translation information is lost by the write or erase operation, the address translation information stored in the other area is not lost, and the system does not operate. An abnormal state can be avoided reliably.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, since the nonvolatile semiconductor memory device has an alternative processing function and an error correction function, it is not necessary to perform an alternative process and an error correction process by an external controller, thereby reducing the burden on the system developer. At the same time, since a plurality of address translation information is stored, even if one of the address translation information is lost, it is possible to avoid an abnormal state where the system does not operate by substituting the other address translation information. Become.

  In addition, since a plurality of address translation information is sequentially stored in two or more areas, even if data in any area for storing address translation information is lost by a write or erase operation, it is stored in another area. The address translation information that is present is not lost, and an abnormal state that prevents the system from operating can be surely avoided.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a block diagram of an embodiment of a flash memory as an example of a nonvolatile semiconductor memory device effective by applying the present invention. The flash memory of this embodiment includes a host interface unit 101 that inputs / outputs signals to / from a controller such as an external host CPU, an interface control unit 110 that controls the host interface unit 101, and a plurality of nonvolatile memories. A flash memory array 121 in which storage elements (memory cells) are arranged in a matrix, a storage unit 120 including its peripheral circuits, and a management unit 130 for managing defective addresses and the like, are formed of single crystal silicon. It is formed on such a single semiconductor chip.

  The existing flash memory includes a plurality of types of chips with different external terminal specifications. The flash memory of this embodiment includes a chip with a specification called NAND type, a chip with a specification called AND type, and a SAND ( It is configured so that it can operate as any of the chips of the specification called “SuperAND” type, and the chip that operates as a bonding option, that is, a predetermined bonding pad B connected to the host interface unit 101 . It is determined according to the setting state of O. Different specifications have different types and arrangement of external terminals.

  Although not particularly limited, in this embodiment, the flash memory array 121 of the storage unit 110 is configured as an AND type in which a plurality of memory cells are connected in parallel between a bit line and a source line. When the interface unit 110 is set to “AND” in the setting by the bonding option, an external command input to the interface unit 110 is supplied to the storage unit 110 as it is.

  The interface control unit 110 converts a NAND specification command into an AND specification command and supplies it to the storage unit when the interface unit 110 is set to “NAND” according to the setting by the bonding option. 111, and when the interface unit 110 is set to SAND, a SAND / AND interface 112 that analyzes a command of the SAND specification and generates a control signal for the storage unit 110 and the management unit 130, and these interfaces 111 or 112 And an interface selection circuit 113 that selects the signal from the management unit 130 and the signal from the management unit 130 to the storage unit 120.

  The storage unit 120 supplies a flash memory array unit 121 including a nonvolatile storage element, a power supply circuit 122 that generates a voltage necessary for writing and erasing data in the memory array unit 121, and the flash memory array unit 121. The write address, the write data, the read address, and the two buffer memories 123A and 123B that temporarily hold the read data read from the flash memory array unit 121, and an area including a defective memory cell are defined in a predetermined unit ( For example, a repair circuit 124 for converting an address when a normal area is replaced with a segment of 128 sectors), an activation signal for the power supply circuit 122, and an address input via the host interface unit 101. Supply to the relief circuit 124 or read data And a AND control circuit 125. which converts the like of the write data.

  In addition to the memory array, the flash memory array unit 121 includes a decoder that decodes addresses and selects word lines, a sense amplifier that amplifies bit line signals, and the like. The memory cells constituting the memory array 121 are MOSFETs having a floating gate and a control gate, and store information by changing the threshold voltage according to the amount of charge injected into the floating gate. The Further, although not particularly limited, the buffer memories 123A and 123B are configured by SRAM. Whether or not to perform segment unit substitution by the relief circuit 124 is determined based on the result of the wafer test.

  The management unit 130 includes an inter-circuit block interface 131 that exchanges signals between the interface control unit 110 and the management unit 130, and a sequencer 132 that includes a controller of a program control system such as a CPU that controls the operation inside the chip. A sequence ROM 133 for storing the operation of the sequencer in the form of a microprogram comprising control codes, a register 134 used by the sequencer, a work RAM 135 for developing an address conversion table and providing a work area for the sequencer 132 The ECC circuit 136 performs error checking and correction, and a DMA transfer control circuit 137 that controls data transfer between the storage unit 120 and the work RAM 135 or the ECC circuit 136.

  In the flash memory according to the present embodiment, the memory array 121 is configured to perform writing in units of memory cells (hereinafter referred to as sectors) composed of 2112 bytes connected to one word line. Further, the memory array 121 is managed by dividing it into a normal area and a spare area that replaces a sector including a defective memory cell in the normal area. A defective address management table that associates the sectors in the normal area with the sectors in the spare area is generated by the management unit 130 and stored in the flash memory array 121. Further, the defective address management table is developed and referred to in the work RAM 135 during normal operation. When the address inputted from the outside designates a sector including a defective memory cell, it is converted to an address designating an alternative sector in the spare area by referring to the defective address management table, and the flash The memory array 121 is accessed. As a result, the defective sector is replaced.

  Further, in the flash memory of this embodiment, the substitution process is performed by two types of methods. FIG. 2 shows the concept of the alternative processing of the first method. In this first type of replacement processing, the flash memory array 121 is divided into a normal area and a spare area that replaces a sector including a defective memory cell in the normal area. Each sector is divided into a data area for storing original data (user data) and a sector management information area for storing an MGM code and an error correction code indicating whether or not the sector includes a defective memory cell. ing. The normal area is composed of N (for example, N = 64) segments each having n (for example, n = 128) sectors. The spare area also includes N segments (however, the number of sectors is variable) corresponding to the N segments in the normal area, and the segments in the normal area correspond 1: 1 with the segments in the spare area.

  The sector management information in the management table is composed of an entry ENT including an information column ADL indicating the position of a replacement-source defective sector and a flag FLG indicating whether the replacement sector is a good sector or a defective sector. For example, when the alternative sector Nn + 2 in FIG. 2 is defective, “1” is set in the flag of the corresponding entry. In each entry of the management table, information indicating the position of the defective sector is registered as an offset value OFS from the head address of each segment. Each entry of the sector management information in the management table corresponds to each sector of the spare area in a 1: 1 ratio.

  As a result of the write operation, for example, when the sector of the physical address “2” in FIG. 2 is a bad sector, the management unit 130 replaces the sector 0 in the alternate area corresponding to the segment 0 in the normal area to which the sector belongs. Data is stored in (for example, Nn + 1). If the data can be stored safely, the offset value “0002h” of the replacement source sector is stored in the entry of the management table corresponding to this sector, and the flag is set to “0”. Further, when accessing the sector in segment 0 of the normal area, the management unit 130 calculates an offset value from the address of the sector and sequentially refers to the entry of segment 0 in the management table to determine whether the sector is a bad sector. If it is registered as a bad sector, the sector in the spare area corresponding to the entry is accessed. At this time, address conversion is performed.

  In this alternative method, since the normal area is divided into segments and managed as an offset value instead of a physical address as sector position information registered in the defective address management table, the data amount of the table, that is, the storage capacity of the work RAM 135 can be reduced. Can be reduced. Also, the management table search time can be shortened.

  FIG. 3 shows the concept of alternative processing of the second method. In the first type of substitution process, the flash memory array is divided into the normal area and the substitution area respectively. On the other hand, in the second substitution process, defective sectors generated in the whole normal area are not divided. One sector in one replacement area is used for replacement. In this method, since it is necessary to use a physical address as bad sector position information to be registered in the management table, the amount of data in the table, that is, the storage capacity of the work RAM 135 increases, and the search time for the management table also increases. Can be used efficiently, and there is no need to calculate an offset or the like. Specifically, in the first method, when bad sectors are concentrated in a certain segment later, it is necessary to change the size of the segment in the spare area. In the second method, such a change is required. Is unnecessary.

  Note that the first alternative processing method is applied to the alternative processing of the defective sector detected at the test stage, instead of selecting and applying either the first alternative processing or the second alternative processing. The second alternative processing method may be applied to the replacement processing of the defective sector generated in the normal use state after shipment. In addition, as shown in FIG. 4, an alternative segment area in which the maximum alternative sector number is variable, an alternative segment area in which the maximum alternative sector number is fixed, and a spare alternative area are provided in the alternative area. The first alternative processing method using an alternative segment area whose maximum alternative sector number is variable is applied to the alternative process, and the maximum alternative sector number is fixed up to an intermediate stage in the alternative process of defective sectors that occur in the normal use state after shipment. The first alternative processing method using the alternative segment area is applied, and when a segment that has used all the sectors of the alternative segment is generated, the second alternative processing method using the spare alternative area is applied. You may do it.

  In FIG. 5, the first alternative processing method using the alternative segment area in which the maximum number of alternative sectors is fixed is applied to the replacement process of the defective sector that occurs in the normal use state, and all the sectors of the alternative segment are used. When a completed segment is generated, the processing procedure of the management unit in the system using the flash memory to which the second alternative processing method using the spare alternative area is applied is shown. When an external control device such as a host CPU (hereinafter referred to as an external device) sends a command and an address to the flash memory, the flash memory receives this and first calculates the corresponding segment and offset based on the received logical address. (Steps S1, S2).

  Next, it is determined whether or not the sector to be accessed is a defective sector by referring to the segment management information in the defect management table (steps S3 and S4). If it is a bad sector, address conversion is performed to designate an alternative sector in the alternative segment corresponding to the entry (step S5). On the other hand, if it is determined in step S4 that the sector is not a defective sector, it is determined whether or not the sector to be accessed is a defective sector by referring to the spare replacement area management information in the defect management table (steps S6 and S7). If it is a bad sector, address conversion is performed to designate a corresponding alternative sector in the spare alternative area (step S8).

  On the other hand, if the sector is not a bad sector in the determinations in steps S4 and S7, the corresponding sector in the normal area is designated as it is (step S9). Thereafter, the designated sector is accessed to read or write data (step S10). Then, when the received command is a read command, the read data is transmitted to the external device, and when the received command is a write command, a signal or status indicating the end of writing is transmitted to the external device, and the process ends (step S11).

  FIG. 6 shows a configuration example of each sector of the normal area and the alternative area. The sector is divided into, for example, a 2096-byte data area and a 16-byte sector management area. Of these, the configuration of the data area is shown in FIG. 6A, and the flash memory is set to AND or NAND specifications. The configuration of the sector management area is shown in FIG. FIG. 6C shows the configuration of the sector management area when the flash memory is set to the SAND specification.

  As shown in FIG. 6A, the data area of each sector includes four 512-byte page areas Page 0 to Page 3 and an 8-byte management area for storing management information corresponding to each page area. And an area for storing 16-byte error correction codes ECC0 and ECC1. A data area change command is prepared in the flash memory of this embodiment, and when only a read command is input, data of 512-byte page areas Page0 to Page3 is read out of the chip. When a read command is input after a data area change command is input, 520-byte data including 512-byte page areas Page 0 to Page 3 and the next 8-byte data is read out of the chip. Yes. Instead of using the command to change the data unit, a plurality of commands may be prepared, or the read data unit may be changed according to the mode set by the bonding option. Further, the management area after each page area may be used to store the ECC code of the data in the corresponding page area.

  As shown in FIG. 6B, the sector management area includes an area for storing an MGM code indicating whether the sector is a good sector, an area for storing a sector identification code, and a history of the management area. An area for storing a management header for managing data, an area for storing management information (array, number of erasures) for rewrite count averaging processing (WL processing), and an area for storing error correction codes CECC0, CECC1, and HECC Composed. As shown in FIG. 6C, the sector management area when set to the SAND specification is made smaller than the case where the area for storing the management information for the rewrite number averaging process is NAND or AND. While the set number of times is stored, the area for storing the management header is enlarged.

  7 and 8 show examples of the configuration of each sector in the management table area. 7 shows the overall configuration of the sector, and FIGS. 8A to 8D show the detailed configuration of each area shown in FIG. As shown in FIG. 7, each sector of the management table area includes an area setting area for storing information indicating the management table area, a swap management area for storing information to be replaced in segment units, and an alternative segment. Are divided into an area for storing management information, an area for storing management information for the spare replacement area, and an area for storing management information for the rewrite count averaging process. Although not shown in FIG. 7, an area for storing an error correction code is also provided at the end. 8A shows the configuration of the swap management area, FIG. 8B shows the configuration of the alternative segment management area, FIG. 8C shows the configuration of the spare alternative area management area, and FIG. 8D shows the rewrite count averaging process. The configuration of each management area is shown below.

  Next, the rewrite count averaging process will be described.

  In the conventional rewrite frequency averaging process in the flash memory, when the rewrite frequency of a certain sector reaches a predetermined number, the sector having the smallest rewrite frequency is searched for and the address is changed. On the other hand, the rewrite frequency averaging process in the flash memory according to the present embodiment, as shown in FIG. 9, rewrites a certain sector in units of blocks in which the flash memory array is, for example, 1024 sectors. When the number of times reaches a predetermined number, the address is sequentially rotated one block at a time so that the data of the sector is stored in the sector at the same offset position of the adjacent block.

  Specifically, in FIG. 9, for example, if the predetermined number of rewrites in the sector of offset 1 in block 0 reaches m (for example, m = 1000) as shown in (A) → (B), (C) As shown in FIG. 2, the data B of the offset 1 sector of the block 0 is transferred to the sector of the offset 1 of the block 1 and written, and the data G of the sector of the offset 1 of the block 1 is written to the sector of the offset 1 of the block 2 The data and the number of rewrites are stored by sequentially shifting between the blocks, such as shifting and writing, and transferring the data J of the offset 1 sector of the block 2 to the offset 1 sector of the block 3 and writing. In addition, the number of times shifted for each offset is written and stored in the rewrite count averaging process management area in conjunction with the shift of the data write area.

  When the number of rewrites of a certain sector reaches a predetermined number, the conventional rewrite number averaging process of searching for the sector with the smallest number of rewrites and replacing the address takes a considerable time until the sector with the smallest number of rewrites is found. And the size of the address conversion table is increased. On the other hand, according to the rewrite frequency averaging process of the shift method of this embodiment, the process of determining the sector to which data is transferred is simple and completes in a short time, and the transfer destination address can be obtained by calculation. There is an advantage that an address conversion table becomes unnecessary. Since it is only necessary to store the number of shifts of several bits in the rewrite number averaging process management area for storing the number of shifts, the storage area can be made much smaller than when the address is stored.

  Next, the work RAM 135 will be described.

  In the flash memory according to the present embodiment, the table data stored in the management table area of the memory array 121 is read and expanded when the power is turned on, and the memory array 121 is updated even when the table data is updated while the power is on. The data in the work RAM 135 is stored in the management table area of the memory array 121 when the power is turned off. In addition, in this embodiment, as shown in FIG. 10, table data is stored by alternately using two management table areas prepared in the memory array, and each management table area is further divided into a plurality of management table areas. The area is divided into 8 areas (for example, 8) and stored in order. If the table data is updated while the power is on, the management table data on the work RAM may be rewritten and the table data in the corresponding management table area of the memory array 121 may be rewritten.

  As described above, the table data stored in the management table area of the flash memory array 121 is read into the work RAM 135 and expanded, thereby determining whether or not the access address is a bad sector address and the address of the alternative sector. Acquisition can be performed in a short time. In addition, by configuring the table data to be stored alternately in the two management table areas, even if all the data in one management table area is lost due to power interruption during rewriting, etc. The data can be reproduced. In addition, by configuring each management table area to be divided into a plurality of areas and storing them in order, rewrite averaging processing within the management table area is realized, and the number of rewrites exceeds the rewrite tolerance and the data It is possible to avoid a decrease in reliability.

  In this embodiment, since the table data has a data amount that can fit in a data area of one sector having a storage capacity of 2096 bytes, one management table storage area corresponds to one sector, and the management table area 0 and 1 is provided corresponding to one block. In FIG. 10, the management header indicates the temporal order of the management table stored in each area. This means that the management table stored in the area with the largest management header is the latest table, and the management table stored in the area with the smallest management header is the oldest table. . Therefore, when the sequencer 132 reads all table data having the largest value by referring to all the management headers in the management table area in the flash memory array 121, it becomes the latest management table.

  In FIG. 10, the management table stored in the management header “15” area of the management table area (1) is read to the work RAM 135 and updated in accordance with the writing to the flash memory array. ) In the management header “0” area. “15” is described in the management header of the management table immediately after being read into the work RAM, the sector address “2007h” in which the table is stored is described in the main address column, and one column is stored in the spare table address column. The sector address “217Fh” (management header = “14”) in which the management table was previously stored is described.

  Then, the management table loaded on the RAM is updated, the management header of the management table is changed from “15” to “16”, and the management table area in which the table is stored next in the main table address field The sector address “2178h” of the area (management header = “0” in FIG. 10) with the smallest management header value of (0) is described, and the sector stored when read in the spare table address column An address “2007h” (management header = “15”) is described. When the power is shut off, the management table data on the RAM is stored according to the sector address in the updated main table address column.

  Here, the term “preliminary table” is used because, according to the management table storage method of this embodiment, when the current or latest management table data is lost or damaged for some reason, one table is used. This is because the previous management table can be read and used. If there is an abnormality in the previous management table data, the previous management table data can be used. As a result, data important to the system can be repaired, and it is possible to avoid as much as possible an abnormal situation in which the memory cannot be recognized or the system cannot be started.

  FIG. 11 shows a configuration example of the work RAM 135. As shown in FIG. 11, the work RAM 135 includes a good sector code storage area GCA, an identification code storage area DCA, a management header storage area MHA, a setting storage area RNA for the rewrite frequency averaging process, a defect management table storage area IMA, Rewrite number averaging process management table storage area RMA, sequencer work area WKA, main table address storage area MAA indicating the management table at the time of reading, address at which the management table at the previous reading was stored Is composed of a spare table address storage area RAA.

  Data other than the work area WKA is read from the flash memory array 121 when the power is turned on and developed in each area of the work RAM 135. Updating the defect management table associated with replacement processing when a new defective sector is detected during operation, or updating the management table associated with the rewrite count averaging process when a sector that has reached the predetermined number of rewrites occurs Is performed on the work RAM 135. The main table address and the spare table address are updated when data in the work RAM 135 is stored in the flash memory array 121.

  FIG. 12 shows a processing procedure for reading data in the management table area from the flash memory array 121 to the work RAM 135 when the power is turned on.

  The sequencer 132 first searches the management table area (0) of the flash memory array (step S21). Then, the identification code is checked to determine whether there is valid management table data (step S22). If there is no valid management table data in the management table area (0), the process proceeds to step S33, the management table area (1) is searched, the identification code is checked, and there is valid management table data. Is determined (step S34). If there is no valid management table data in the management table area (1), the process ends as an error.

  On the other hand, if there is a valid management table in the management table area (1) in step S34, the management header is referred to and the data of the table having the maximum management header in the management table area (1) is stored in the work RAM. And the address of the table is registered as the main table address (step S35). Then, the process proceeds to a table copy process (step S40) for copying the table data to the management table area (0). To avoid the situation where there is no valid table data in both management table areas by copying the data in the other management table area when the data in one management table area is destroyed. is there.

  If the identification code is checked in step S22 and it is determined that there is valid management table data in the management table area (0), the process proceeds to step S23, and management headers are obtained from all sectors in the management table area (0). Read and load the table data with the maximum management header into the work RAM, and register the address of the table as the main table address (step S24). Next, the management table area (1) is searched (step S25). Then, the identification code is checked to determine whether there is valid management table data (step S26). Here, when there is no valid management table data in the management table area (1), the process proceeds to the table copy process in step S40, and the data read from the management table area (0) is copied to the management table area (1). To do.

  If it is determined in step S26 that there is a valid management table in the management table area (1), the process proceeds to step S27, the management header is read from all sectors in the management table area (1), and the management table area (1) is managed. The header having the maximum value is compared with the management header having the maximum value in the management table area (0) (step S28). When the maximum value of the management header in the management table area (1) is larger, the process proceeds from step S29 to step S30, and the table data of the sector having the maximum management header in the management table area (1) is processed. The data is loaded into the RAM, and the address of the table is registered as a main table address, and the address of the table of the sector having the maximum management header in the management table area (0) is registered as a spare table address (step S31). On the other hand, when it is determined in step S29 that the maximum value of the management header in the management table area (0) is larger than the maximum value of the management header in the management table area (1), the process proceeds to step S32 and the management table area The sector table address having the maximum management header in (1) is registered as a spare table address.

  FIG. 13 shows a detailed procedure of the table copy process in step S40 of the flowchart of FIG.

  In this table copy process, it is first determined whether or not the found table is in the management table area (0) (step S41). If the found table is in the management table area (0), the head address of the management table area (1) in the area setting information is set as the table storage head address in the flash memory array in step S42. If the found table is in the management table area (1), the head address of the management table area (0) in the area setting information is set as the table storage head address in the flash memory array in step S43. Then, the table data already loaded into the work RAM is written into the flash memory array from the storage head address (step S44).

  Then, it is determined whether or not the writing is normally completed. When the writing is normally completed, the head address is registered as a spare table address in the spare table address column of the work RAM (steps S45 and S46). If the writing is not completed normally in step S44, the next sector in the same management table area is set as the address for storing the table data in step S47, and the table loaded in the work RAM is returned to step S44. Write data. If the table data cannot be written normally even if writing is attempted for all sectors in the management table area, the process ends as a write error (step S48).

  FIG. 14 shows a procedure of processing for storing data in the management table area from the work RAM 135 to the flash memory array 121.

  In this table storing process, first, the table management header on the work RAM is incremented (+1) (step S51). Next, the address next to the spare table address is set as the table storage destination address in the flash memory array (step S52). Then, the table data on the work RAM is written to the storage destination address of the flash memory array (step S53).

  Then, it is determined whether or not the writing is normally completed. When the writing is normally completed, the table address is exchanged. That is, the main table address is registered as a spare table address in the spare table address column of the work RAM, and the latest table address of the flash memory array is registered as the main table address in the spare table address column of the work RAM (steps S54 and S55). . If the writing is not completed normally in step S54, the next sector in the same management table area is set as the address for storing the table data in step S56, and the table stored in the work RAM is returned to step S53. Write data to the flash memory array. If the table data cannot be written normally even if writing is attempted for all sectors in the management table area, the process ends as a write error (step S57). When the table storage process is executed when the power is turned off, it is not necessary to replace the table address in step S55.

  FIG. 15 shows the procedure of address conversion processing in the flash memory of this embodiment. The address conversion process is executed when a data read, write or erase command with an access address is input.

  In the address conversion process, first, the management information of the rewrite count averaging process is read from the work RAM, and the block shift number corresponding to the access address is selected (step S61). Next, the access address is converted according to the selected block shift number (step S62). Then, an offset value is calculated based on the converted address, and the management information of the corresponding segment on the defect management table is selected using the offset value (step S63). Then, the management table is searched to determine whether the sector at the address is registered as a bad sector (step S64). Here, if the sector to be accessed is registered as a bad sector, the alternative address conversion for obtaining the alternative sector address of the corresponding alternative segment is performed (step S65). On the other hand, if the sector to be accessed is not registered as a bad sector in step S64, the final address is not converted (step S66).

  Next, the operation when the flash memory of this embodiment is turned on will be described with reference to FIG. In the flash memory of this embodiment, although not particularly limited, a power supply voltage detection circuit for detecting the level of the power supply voltage is provided in the host interface unit 101, and a rise detection signal of the power supply voltage detected by the power supply voltage detection circuit is an interface. This is supplied to the control unit 110 and the internal circuit is activated (step S71). When the interface control unit 110 receives the rising detection signal, it issues a start command to the management unit 130 (step S72).

  Then, in the management unit 130, the sequencer 132 is initialized, and processing for loading management table data from the flash unit 120 to the work RAM 135 is executed (steps S73 and S74). When loading of the management table data is completed, a termination signal is sent from the management unit 130 to the interface control unit 110, and the interface control unit 110 receives a PRE (preload enable) signal input from an external device at an effective level (for example, high level). Level) is asserted, and when the PRE signal is not asserted, a transition is made to a standby state waiting for an external command input (steps S75 and S76).

  On the other hand, when the PRE signal is asserted, the data in the sector at address 0 of the flash memory array 121 is shifted to an automatic read state in which data can be output to the outside via the buffer memory 123A (step S77). When the standby state or the automatic reading state is entered in step S76, the ready / busy signal / MRES output from a predetermined external terminal is changed to a high level (or low level) indicating the ready state. It is configured.

  FIG. 17 shows the timing for automatic reading at power-on. This automatic reading is executed when the external device asserts the PRE signal to a high level when the power is turned on.

  When the flash memory is activated with the PRE signal being asserted at the high level when the power is turned on, an activation command is sent to the management unit 130 to initialize the management unit, and then the management table is loaded. After completion, the interface control unit 110 supplies an automatic read command and an address indicating address 0 to the management unit 130. Then, the sequencer 132 refers to this management table, performs address conversion when necessary, and supplies the converted address and read command to the flash unit 120. As a result, the data of the sector at address 0 of the flash memory array 121 is read out and stored in the buffer memory 123A.

  Next, the sequencer 132 sends the read data to the ECC circuit 136 to perform error checking and correction. When the ECC processing is completed, a signal indicating that transfer is possible is sent from the management unit 130 to the interface control unit 110. The interface control unit 110 changes the signal / MRES indicating the ready or busy state of the operation output from the host interface unit 101 to a high level. When the external device detects the change in the signal / MRES and inputs the read clock RCK to the flash memory, the data held in the buffer memory 113A is transferred to the external device via the host interface unit 101.

  FIG. 18 shows a procedure in the case where a writing abnormality occurs in the writing process. In this specification, the case where data is written to all memory cells in the data area of one sector is referred to as writing, and the case where data is written to a part of memory cells in the data area of one sector is rewritten. And write and rewrite are distinguished.

  The write operation (step S81) ends in response to the write command from the external device, and when a write abnormality is detected by the verify operation, a signal notifying the abnormal end is sent from the storage unit 120 to the management unit 130 (step S82). ). Then, the management unit registers the write address as a defective address in the management table in the work RAM 135 (step S83). Then, address conversion to replace the normal sector in the alternative area is performed, and the write command and address are sent to the storage unit 120 using the converted address as the write address (step S84). Then, the storage unit performs writing to the replaced sector (step S85). When the writing ends normally, a signal notifying the normal end is sent from the storage unit to the management unit.

  Next, the management unit checks whether an erasure error flag is set, and when the flag is set, stores the management table in the work RAM in the flash memory array (steps S86 and S87). When the erase error flag is not set, or after the management table is stored in the flash memory array, the number of rewrites of the sector in which the management table has been rewritten is checked. The interface controller controls the host interface unit and outputs an end signal to the outside of the chip (step S88). When the number of rewrites exceeds the predetermined number, the end signal is sent to the interface control unit after performing block shift by the rewrite number averaging process, and the interface control unit controls the host interface unit to send the end signal to the outside of the chip. Is output (step S89).

  Regarding the erasure flag, the data in the sector to be written is first erased in the write operation in step S81. Therefore, if an abnormality occurs during the data erasure, an erase flag is set and a substitution process is performed to perform the work in the work RAM. The management table is updated. Therefore, in this embodiment, it is checked whether or not the erase error flag is set after the writing is completed, and when the erase flag is set, the management table in the work RAM is stored in the flash memory array.

  FIG. 19 shows a procedure when an erasure error occurs in the data erasure process in the flash memory of this embodiment. This erasing process includes erasing before writing by an erasing command from the external device and a writing command.

  When the data erasing operation (step S91) of the sector designated in accordance with the erasing command or the writing command from the external device is completed, and the erasing abnormality is detected by the verifying operation, the memory unit 120 abnormally terminates with respect to the management unit 130. Is sent (step S92). Then, the management unit registers the erase address or write address as a defective address in the management table in the work RAM (step S93). Then, address conversion to replace the normal sector in the alternative area is performed, and the erase command and address are sent to the storage unit using the converted address as the erase address (step S94). Then, the storage unit executes erasure on the replaced sector (step S95). When the erasure ends normally, a signal notifying the normal end is sent from the storage unit to the management unit. Although not particularly limited, when a signal notifying abnormal termination is sent in step S92, the management unit performs a process of increasing the threshold voltage of the memory cell of the sector that has performed the erase operation, and the threshold voltage is You may make it make the threshold voltage of the memory cell which is 0 v or less (depletion state) be 0 v or more.

  Next, after setting the erase error flag, the management unit sends an end signal to the interface control unit, and the interface control unit controls the host interface unit and outputs the end signal to the outside of the chip (step S96). When erasing is performed according to the write command, the process proceeds to the write process of FIG. 18 without outputting the end signal.

  FIG. 20 shows the flow of a normal data read operation in the flash memory of this embodiment. The normal data reading is started when a read command and a read address are input from the external device to the flash memory. The read address is composed of a sector address SA and a column address CA designating arbitrary byte data in the sector.

  The input read command is sent to the management unit by controlling the interface control unit, and the management unit performs address conversion using the management table. This address conversion includes an address that has been block-shifted by the rewrite frequency averaging process and an address that has been replaced by the defective address replacement process. After the address conversion, a read command and converted addresses SA ′ and CA are sent from the management unit to the storage unit. Then, in the storage unit, the data of the designated sector of the flash memory array 121 and the data of the next sector are read and held in the buffer memories 123A and 123B, respectively.

  When the reading of data to the buffer memory is completed, a signal notifying the completion is sent from the storage unit to the management unit, and in response to this signal, the management unit controls the DMA control circuit 137 and the ECC circuit 136 to first store the data in the buffer memory 123A. When the ECC processing is completed, the interface control unit is notified that transfer is possible, and the interface control unit uses the signal / RB indicating ready / busy to notify the external device that it has become ready. Inform.

  Then, the data in the buffer memory 123A is output to the outside of the chip according to the input of the clock from the external device and transferred to the external device. In parallel with the data transfer, an error detection and correction process is performed on the data in the buffer memory 123B. When this ECC process is completed, the interface controller is informed that the data in the buffer memory 123B can be transferred. When the transfer of the data in the buffer memory 123A is completed, the data in the buffer memory 123B is transferred in response to a request from the external device. Transfer starts.

  FIG. 21 shows a flow of sequential read operation in the flash memory of this embodiment. This sequential read is started by inputting a sequential read command and a read address from the external device to the flash memory, so that all data after the read address can be read as long as the external device continues to input the clock. It is a function. Sequential reading is performed in a procedure similar to the normal reading in FIG.

  The normal reading in FIG. 20 is different from the normal reading in FIG. 20 in that the data is first read to the first buffer memory 123A and the second buffer memory 123B, and the data in one buffer memory 123A is transferred to the outside. In the meantime, error correction processing is performed on the data in the other buffer memory 123B, whereas in sequential reading, data reading to one buffer memory 123A and error correction are performed, and the other device is informed that transfer is possible to an external device. In addition to reading data to the buffer memory 123B, error correction processing is performed on the data in the other buffer memory 123B while the data in the one buffer memory 123A is being transferred to the outside. After memory data transfer is completed Each time lies in sending a sequential read command to the management unit from the face control unit.

  FIG. 22 shows the flow of data rewrite operation in the flash memory of this embodiment. Data rewriting is started when a rewrite command, a rewrite address, and rewrite data are input from the external device to the flash memory. The write address is only the sector address SA that designates a sector, but the rewrite address is composed of a sector address SA and a column address CA that designates arbitrary byte data in the sector. The input rewrite data is temporarily stored in the first buffer memory 123A. When the interface control unit receives the rewrite command, it issues a read command to the management unit and counts the number of bytes of the rewritten data to be input to inform the management unit of the transfer data size.

  Then, the management unit performs address conversion using the management table, and sends the read command and the converted addresses SA ′ and CA to the storage unit. In the storage unit, the data (2096 bytes) of the data area of the designated sector of the flash memory array 121 and the management data (16 bytes) of the sector management area are read and held in the second buffer memory 123B. When the reading of data to the buffer memory 123B is completed, a signal notifying the completion is sent from the storage unit to the management unit, and the management unit controls the DMA control circuit 137 and the ECC circuit 136 according to this signal, and the data in the buffer memory 123B Error detection correction processing is performed on

  When the ECC processing is completed, the management unit controls the DMA control circuit 137 to transfer the rewritten data held in the first buffer memory 123A to the second buffer memory 123B and synthesize the data. Specifically, the rewrite data stored in the first buffer memory 123A is the data at the position specified by the column address CA by the external device among 21162 bytes of data read from the flash memory array. Replace with Then, the management unit controls the DMA control circuit 137 and the ECC circuit 136 to generate an ECC code for the data in the second buffer memory 123B after rewriting.

  Thereafter, an erase command and an address are sent to the storage unit to erase data in the sector to be rewritten. When the erasing is completed, an end signal is output from the storage unit to the management unit. Therefore, the management unit sends a write command and an address to the storage unit to write the data in the buffer memory 123B to the sector to be rewritten. When the writing is completed, an end signal is output from the storage unit to the management unit. Therefore, the management unit sends an end signal to the interface control unit, and the interface control unit controls the host interface unit and outputs an end signal to the external device.

  FIG. 23 shows a flow of data erasing operation in the flash memory of this embodiment. Data erasure is started by inputting an erase command and an erase address from the external device to the flash memory. In this embodiment, erasing is performed on a sector basis.

  When an erase command is input, the interface control unit 110 sends a clear signal to the first buffer memory 123A to clear all data, and sends a read command and an address to the management unit 12. This address is an address that designates a sector to be erased. As shown in FIG. 6, the read command is sent to each sector provided with a management area for storing sector management information in addition to a data area for storing original data. This is because the management information is also erased when the command is executed, and is saved in the buffer memory in advance.

  When receiving the read command, the management unit performs address conversion using the management table, and sends the read command and the converted addresses SA ′ and CA to the storage unit. In the storage unit, the data (2096 bytes) of the data area of the designated sector of the flash memory array 121 and the management data (16 bytes) of the sector management area are read and held in the second buffer memory 123B. When the reading of data to the buffer memory 123B is completed, a signal notifying the completion is sent from the storage unit to the management unit, and the management unit controls the DMA control circuit 137 and the ECC circuit 136 according to this signal, and the data in the buffer memory 123B Error detection correction processing is performed on

  When the ECC processing is completed, the management unit controls the DMA control circuit 137 to clear the clear data (data corresponding to the erased state of the memory cell) held in the first buffer memory 123A to the second buffer memory 123B. Transfer to synthesize data. Specifically, 2096-byte data excluding 16-byte sector management information stored in the sector management area among 21162-byte data of one sector read from the flash memory array is stored in the first buffer memory. Replace with the clear data held in 123A. Then, the management unit controls the DMA control circuit 137 and the ECC circuit 136 to generate an ECC code for the data in the second buffer memory 123B after rewriting.

  Thereafter, an erase command and an address are sent to the storage unit to erase data in the sector to be erased. When the erasing is completed, an end signal is output from the storage unit to the management unit. Therefore, the management unit sends a write command and an address to the storage unit to write the data in the buffer memory 123B to the sector to be rewritten. As a result, the ECC code and the sector management information saved in the second buffer memory 123B are written in the designated sector. When the writing is completed, an end signal is output from the storage unit to the management unit. Therefore, the management unit sends an end signal to the interface control unit, and the interface control unit controls the host interface unit and outputs an end signal to the external device.

  FIG. 24 shows the flow of the transition to the deep standby mode and the return operation from the deep standby mode to the normal operation mode in the flash memory of this embodiment.

  The flash memory of this embodiment includes a deep standby mode for completely turning off the boosting charge pump in the power supply circuit 122 of the storage unit 120, a command for shifting the chip to the deep standby mode, and a deep standby mode. There is a command to restore from. When a deep standby transition command is input from the external device to the flash memory, a deep standby signal instructing transition from the interface control unit to the storage unit to the deep standby mode is asserted.

  Then, the storage unit cuts off the clock supplied to the boosting charge pump in the power supply circuit 122 or stops the operation of the clock generation circuit to turn off the charge pump. Thereby, the flash memory is brought into a state where the power consumption is very low. When a return command from deep standby is input from the external device to the flash memory, a deep standby signal supplied from the interface control unit to the storage unit is negated. Then, the storage unit restarts the supply of the clock to the boosting charge pump in the power supply circuit 122 or activates the clock generation circuit to turn on the charge pump. As a result, a high voltage necessary for writing to and erasing the memory array is generated.

  FIG. 25 shows a flow of operations similar to an operation (see FIG. 17) performed at the time of power-on called so-called hot restart in the flash memory of this embodiment.

  In the automatic reading at the time of power-on in FIG. 17, after the loading of the management table is completed, the interface control unit 110 supplies the read command and the address indicating the address 0 of the memory array 121 to the management unit 130. In contrast to the data being read and output to the outside, in the hot restart of FIG. 25, when the PRE signal input to a predetermined external terminal of the flash memory is changed to a low level, this operation is ready or busy. After the signal / MRES indicating the busy state is changed to the low level indicating the busy state, the read command and the address indicating the memory array address 0 are sent to the management unit without loading the management table, and the start address of the memory array is Data is read and output to the outside. The reason why the management table is not loaded is that hot restart is an operation performed while the power is turned on, and the management table loaded when the power is turned on is already held in the work RAM.

  The PRE signal may be changed to a low level by an external device such as the host CPU. However, as shown in FIG. 26, a reset switch R-SW is connected to an external terminal to which the PRE signal of the flash memory 100 is input. The system is configured so that a signal / MRES indicating ready or busy output from the flash memory 100 is input to the reset terminal of the host CPU 200, and at the start of the system at the beginning (address 0) of the memory array of the flash memory. By storing the program to be executed, the flash memory can function as a boot device.

  For example, when the power switch of the system is turned on by turning on a power switch (not shown) with the reset switch R-SW set to the power supply voltage terminal Vcc side as shown in FIG. 26, the power supply voltage Vcc is changed as shown in FIG. As the signal rises, the PRE signal rises to a high level. Therefore, at this time, the flash memory automatically reads the data at address 0 of the memory array according to the operation of FIG. 17, and when ready to output to the outside of the chip, the signal / MRES indicating ready or busy is at a high level indicating the ready state. To change. In the system of FIG. 26, since this signal is input to the reset terminal of the host CPU, the reset of the CPU is released and the boot operation in which the CPU reads data from the flash memory can be started.

  When the reset switch R-SW is switched to the ground side while the power is on, the PRE signal falls to the low level as shown in FIG. 27B. At this time, the flash memory operates in the hot restart operation of FIG. First, the signal / MRES is changed to a low level, and then data at address 0 in the memory array is automatically read. Then, when it becomes possible to output to the outside of the read chip, the signal / MRES is changed to a high level. In the system of FIG. 26, since this signal is input to the reset terminal of the host CPU, the reset of the CPU is released and the boot operation in which the CPU reads data from the flash memory can be started.

  Next, other functions provided in the flash memory of this embodiment will be described.

  The flash memory according to this embodiment includes a plurality of test commands. FIG. 28 shows an operation procedure when two test commands are input. When the first test command is input, the management unit 130 refers to the spare replacement area management information (FIG. 7C) of the management table in the flash memory array 121 as shown in FIG. The total number of alternative sectors is calculated by adding the number of entries (step S101), and the number of used alternative sectors in the alternative area is written to the normal area of the flash memory array (step S102). Therefore, by reading out the number of used alternative sectors at the time of product selection, if the number of unused alternative sectors is less than the predetermined number, it is determined that the product is defective. It is possible to improve the reliability of the product by assuring the number that can be more than a certain value.

  When the second test command is input, as shown in FIG. 28B, the management unit 130 stores the spare replacement area management information (FIG. 7C) of the management table in the flash memory array 121. By referring to and adding the number of entries, the total number of alternative sectors is calculated (step S111), and the number of used alternative sectors written to the memory array at the input of the first test command is read (step S111). S112) It is determined whether or not the number of used alternative sectors has increased (step S113). If it has increased, a flag is set (step S114). If it has not increased, the process ends without setting the flag. For example, when an aging test is performed, this flag is input by inputting a first test command before the test, inputting a second test command after the test, and confirming the flag. By determining that a product with a flag that is referred to is a defective product, it is possible to prevent a product whose defective sector increases in a short time from being shipped as a good product.

  In step S102 of FIG. 28A, the number of used alternative sectors may be written into the work RAM 135 instead of being written into the flash memory array. Also, the flag set in step S114 of FIG. 28B may be provided in the flash memory array 121 or in the work RAM 135. Further, the determination of whether or not the number of used alternative sectors has increased in step S113 in FIG. 28B may be simply a determination of whether or not it has increased, but it is determined whether or not it has increased by a predetermined number or more. You may make it do.

  Next, another embodiment of the flash memory of the present invention will be described. In this embodiment, access to the memory array is denied when the management table loaded from the flash memory array to the work RAM cannot be normally read when the power is turned on. As means for realizing this, for example, it is determined whether or not the management table can be read normally, and a flag is set when the management table is read normally, as shown in FIG. When an access command to the memory array is input (step S121), the management table loaded flag is referred to (step S122) to determine whether it is normally loaded (step S123). Access to the flash memory array is permitted (step S124), and if not loaded normally, access to the flash memory array is denied and a signal indicating a table error is output (step S125) or status Configuration that allows the management unit to execute the process of setting a predetermined bit in the register That methods are conceivable.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the embodiment, a binary flash memory capable of storing 1-bit data in one storage element (memory cell) has been described. However, the present invention stores data of 2 bits or more in one storage element. The present invention can also be applied to a multi-value flash memory.

  Further, in the above embodiment, the description of the specific configuration of the memory array is omitted, but the present invention is a so-called AND type or NOR in which a plurality of storage elements are connected in parallel between a bit line and a source line. The present invention can be applied not only to a flash memory of a type but also to a so-called NAND flash memory in which memory elements are connected in series. Furthermore, the memory cell is not limited to a two-layer gate type memory cell having a floating gate and a control gate, and may be a MONOS type memory cell having a charge storage layer made of a nitride film between the control gate and the channel. In this case, the charge storage layer may store charges and store 1-bit information, or the charge storage layer may partially store charges and store information of 2 bits or more.

In the above description, the case where the invention made by the present inventor is mainly applied to the flash memory which is the field of use behind the present invention has been described. However, the present invention is not limited thereto, and The present invention can be widely used for semiconductor memories having a nonvolatile memory element that stores information by changing a threshold voltage by application.

1 is a block diagram showing an embodiment of a flash memory as an example of a nonvolatile semiconductor memory device effective by applying the present invention. It is explanatory drawing which shows the concept of the alternative process of the 1st system in the flash memory of an Example. It is explanatory drawing which shows the concept of the alternative process of the 2nd system in the flash memory of an Example. It is explanatory drawing which shows the structure of the whole flash memory of an Example. It is a flowchart which shows the process sequence of the management part in the flash memory of an Example. 2 shows an example of the configuration of each sector of a normal area and an alternative area in the flash memory of the embodiment, where (A) is a data area configuration, and (B) is a sector management when the flash memory is set to AND or NAND specifications. (C) is an explanatory diagram showing the configuration of the sector management area when the flash memory is set to the SAND specification. It is explanatory drawing which shows the example of schematic structure of the management table in the flash memory of an Example. It is explanatory drawing which shows the detailed structural example of each area | region which comprises the management table in the flash memory of an Example. It is explanatory drawing which shows the concept of the rewrite frequency averaging process in the flash memory of an Example. It is explanatory drawing which shows the method of the log | history management of the management table in the flash memory of an Example. It is explanatory drawing which shows the structural example of the work RAM in the flash memory of an Example. It is a flowchart which shows the procedure of the process which reads the data of a management table area | region from the flash memory array at the time of power activation in the flash memory of an Example to work RAM. It is a flowchart which shows the detailed procedure of the table copy process in the flowchart of FIG. It is a flowchart which shows the procedure of the process which stores the data of a management table area | region from the work RAM in the flash memory of an Example to a flash memory array. It is a flowchart which shows the procedure of the address conversion process in the flash memory of a present Example. It is a flowchart which shows the procedure of the process at the time of power activation in the flash memory of a present Example. It is a timing chart which shows the timing in the case of performing automatic reading at the time of power-on. It is a flowchart which shows the procedure in case writing abnormality generate | occur | produces in the writing process in the flash memory of a present Example. It is a flowchart which shows the procedure when deletion abnormality generate | occur | produces in the data deletion process in the flash memory of a present Example. 6 is a timing chart showing a flow of a normal data read operation in the flash memory according to the present embodiment. 3 is a timing chart showing the flow of sequential read operation in the flash memory of the present embodiment. 4 is a timing chart showing a flow of data rewrite operation in the flash memory according to the embodiment. 4 is a timing chart showing a flow of data erasing operation in the flash memory according to the embodiment. 4 is a timing chart showing a flow of a transition to a deep standby mode and a return operation from the deep standby mode to the normal operation mode in the flash memory according to the embodiment. 3 is a timing chart showing a flow of an operation performed at power-on called hot restart in the flash memory of the present embodiment. 1 is a system configuration diagram illustrating a configuration example of a system using a flash memory according to an embodiment. 27 is a timing chart showing signal timings between the CPU and the flash memory in the system of FIG. It is a flowchart which shows the procedure of operation | movement when the command for a test in the flash memory of a present Example is input. It is a flowchart which shows the procedure of the process at the time of power-on in the other Example of the flash memory of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Host interface part 110 Interface control part 120 Memory | storage part 121 Flash memory array 122 Power supply circuit 123 Buffer memory 130 Management part 132 Sequencer 136 Error detection correction circuit

Claims (4)

Comprising a non-volatile memory array array and a control circuit;
The nonvolatile memory array includes a plurality of nonvolatile memory elements that can electrically write and erase stored information and store information corresponding to a threshold voltage, and perform writing and erasing in a predetermined unit. Configured as
In response to a read command and a read address from an external control device connected to the outside, the control circuit executes a normal read operation of data from the nonvolatile memory array and controls the normal read data to the external control. Output to the device,
In response to a specific signal supplied from the external control device when the power is turned on, the control circuit performs an automatic data read operation from a specific address of the nonvolatile memory array, and the automatic read data is transferred to the external memory. A non-volatile semiconductor memory device that outputs to a control device. A first buffer memory and a second buffer memory connected to the nonvolatile memory array;
In the normal read operation, the control circuit executes reading from the nonvolatile memory array and output to the external control device by using both the first buffer memory and the second buffer memory. Is what
In the automatic reading operation, the control circuit uses one of the first buffer memory and the second buffer memory to read from the specific address of the non-volatile memory array and the external control device. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is configured to execute an output to an output. The nonvolatile memory array includes a plurality of sectors each including a predetermined number of nonvolatile storage elements as a unit of writing, and each sector of the plurality of sectors is configured to include an error correction code.
In the normal read operation, error detection and correction processing is executed for the first data held in the first buffer memory, and then error detection and correction is executed for the second data held in the second buffer memory. The process is executed,
The error detection and correction process is performed on the data from the specific address held in the one of the first buffer memory and the second buffer memory in the automatic reading operation. 3. The nonvolatile semiconductor memory device according to 2. The control circuit determines whether or not the specific signal supplied from the external control device when the power is turned on is asserted to an effective level,
The control circuit executes the automatic read operation from the specific address of the nonvolatile memory array in response to the specific signal supplied when the power is turned on being asserted to the effective level. And
The control circuit shifts to a standby state waiting for an external command input in response to the fact that the specific signal supplied when the power is turned on is not asserted to the effective level. 4. The nonvolatile semiconductor memory device according to any one of 3 above.

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