CN105761754B

CN105761754B - Memory cell programming method, memory control circuit unit and memory device

Info

Publication number: CN105761754B
Application number: CN201410799120.2A
Authority: CN
Inventors: 林纬; 许祐诚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2014-12-19
Filing date: 2014-12-19
Publication date: 2020-01-07
Anticipated expiration: 2034-12-19
Also published as: CN105761754A

Abstract

The invention provides a programming method for a memory cell, a memory control circuit unit and a memory device. The method for programming the memory cell comprises grouping the physical erasing cells of the rewritable nonvolatile memory module into at least a first region and a second region, wherein the first group of programming parameters is preset for writing the first type of data into the lower physical programming cells of the physical erasing cells belonging to the first region and the upper physical programming cells of the physical erasing cells of the first region are not used for storing data. The method further comprises: adjusting the first set of programming parameters to obtain a second set of programming parameters; and writing the second type of data into lower physical programming cells of the physical erase cells belonging to the second region using the second set of programming parameters, wherein upper physical programming cells of the physical erase cells of the second region are not used to store data.

Description

Memory cell programming method, memory control circuit unit and memory device

Technical Field

The present invention relates to a memory cell programming method, and more particularly, to a memory cell programming method for a rewritable nonvolatile memory module, a memory control circuit unit and a memory device.

Background

Digital cameras, cell phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebooks. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years.

With the progress of semiconductor manufacturing processes, the present technology has developed a flash memory module having a memory cell capable of storing a plurality of bits of data. Specifically, data writing (or programming) of a flash memory module is performed by applying a voltage to a specific terminal of the flash memory device (e.g., a control gate voltage changes the amount of electrons in a charge trapping layer in the gate), thereby changing the conduction state of the channel of the memory cell to assume different memory states. For example, in a Multi-Level Cell (MLC) NAND flash memory, when the lower page data is 1 and the upper page data is 1, the control circuit controls the word line control circuit to keep the memory state of the memory Cell at "11" without changing the gate voltage of the memory Cell; when the lower page data is 1 and the upper page data is 0, the word line control circuit changes the gate voltage of the memory cell under the control of the control circuit, so as to change the memory state of the memory cell to "10"; when the lower page data is 0 and the upper page data is 0, the word line control circuit changes the gate voltage of the memory cell under the control of the control circuit, so as to change the memory state of the memory cell to "00"; when the lower page data is 0 and the upper page data is 1, the word line control circuit changes the gate voltage of the memory cell under the control of the control circuit, so as to change the memory state of the memory cell to "01". That is, when reading data, the control circuit identifies the memory state of the memory cell according to the gate voltage of the memory cell.

During programming, the memory cell ages with multiple injections and removals of electrons, resulting in an increase in electron writing speed and a wider threshold voltage distribution. Therefore, after multiple programming, the memory cell may not be able to correctly identify its memory state, resulting in an erroneous bit. In addition, when the data stored in the same memory cell is read for multiple times, for example, for hundreds of thousands to millions of times, the read data may be erroneous, and even the data stored in the multiple-read physically erased cell may be abnormal or lost. Such phenomenon is known as "read-disturb" (read-disturb) as is customary to those of ordinary skill in the art. In particular, the flash memory module stores system data (e.g., Firmware Code (FAT), File Allocation Table (FAT)) of the flash memory storage system, and the system data is frequently read during the operation of the flash memory storage system.

Accordingly, it is an objective of those skilled in the art to program a memory cell with appropriate programming parameters to avoid rapid degradation of the memory cell, while preferably controlling the amount of electrons in a charge trapping layer in the gate to prevent read disturb.

Disclosure of Invention

The invention provides a memory cell programming method, a memory control circuit unit and a memory device, which can prolong the service life of a memory cell and avoid the occurrence of reading interference.

An exemplary embodiment of the present invention provides a memory cell programming method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erase units, and each physical erase unit has a plurality of physical program units. The memory cell programming method comprises the following steps: writing the first type of data into one of the physical programming cells using a first set of programming parameters; and writing the second type of data into one of the physical programming units by using the second set of programming parameters, wherein at least part of the parameters in the first set of programming parameters are different from the second set of programming parameters, and the number of data bits of the memory cells of the physical programming units in which the first type of data is written by using the first set of programming parameters is the same as the number of data bits of the memory cells of the physical programming units in which the second type of data is written by using the second set of programming parameters.

In an exemplary embodiment of the invention, the physical programming units written with the second type of data among the physical programming units map corresponding logical addresses, and the physical programming units written with the first type of data do not map corresponding logical addresses.

In an exemplary embodiment of the present invention, the number of data bits of the memory cell of the physical programming unit in which the first type of data is written with the first set of programming parameters is 1 bit and the number of data bits of the memory cell of the physical programming unit in which the second type of data is written with the second set of programming parameters is 1 bit.

In an exemplary embodiment of the invention, the method for programming a memory cell further includes: the physical erase units are grouped into at least a first region and a second region. The step of writing the first type of data into the physical programming units using the first set of programming parameters includes: writing a first type of data to physically erased cells belonging to the first region using a first set of programming parameters, and writing a second type of data to the physically erased cells using a second set of programming parameters comprises: the second type of data is written to the physically erased cells belonging to the second region using a second set of programming parameters.

In an exemplary embodiment of the present invention, the plurality of physical programming units of each physical erase unit includes a plurality of lower physical programming units and a plurality of upper physical programming units. The first set of programming parameters is predetermined for the physically erased cells belonging to the first region, and upper ones of the physically erased cells of the first region are not used for storing data. The second set of programming parameters is for the physically erased cells belonging to the second region, and upper ones of the physically erased cells of the second region are not used for storing data.

In an exemplary embodiment of the invention, the method for programming a memory cell further includes: the first set of programming parameters is adjusted to obtain a second set of programming parameters.

In an exemplary embodiment of the invention, the method for programming a memory cell further includes: receiving a data; judging whether the data belongs to second class data or not; if the data does not belong to the second type of data, writing the data into at least one first physically erased cell among the physically erased cells of the first area by using the first set of programming parameters; and if the data belongs to the second type of data, writing the data into at least one second entity erasing unit in the entity erasing units of the second area by using the second set of programming parameters.

In an exemplary embodiment of the invention, the method for programming a memory cell further includes: identifying at least one logic unit for storing the data; judging whether the at least one logic unit is mapped to a physical erasing unit of the second area; and identifying the data as belonging to the second type of data if the at least one logic unit is mapped to the physically erased unit of the second area.

In an exemplary embodiment of the invention, the method for programming a memory cell further includes: performing an erase operation on the first physically erased cell by using a single-level cell erase command; and performing an erase operation on the second physically erased cell using the multi-level cell erase command.

In an exemplary embodiment of the invention, the first set of programming parameters includes at least one of a first incremental step pulse program adjustment value, a first initial write voltage, a first verify voltage, a first read voltage, a first turn-on voltage, and a first erase voltage.

In an exemplary embodiment of the invention, a data retention capability or a read disturb resistance of the physical program cells programmed with the first set of programming parameters is better than a data retention capability or a read disturb resistance of the physical program cells programmed with the second set of programming parameters.

In an exemplary embodiment of the invention, a life span of the physical program unit programmed with the second set of programming parameters is better than a life span of the physical program unit programmed with the first set of programming parameters.

In an exemplary embodiment of the invention, a voltage interval between a first state and a second state of a statistical distribution map of threshold voltages of memory cells of the physical program cells programmed with the first set of programming parameters is greater than a voltage interval between a first state and a second state of a statistical distribution map of threshold voltages of memory cells of the physical program cells programmed with the second set of programming parameters.

In an exemplary embodiment of the invention, the step of adjusting the first set of programming parameters to obtain the second set of programming parameters includes: the first verifying voltage of the first set of program parameters is adjusted to obtain a voltage as a second verifying voltage of the second set of program parameters, wherein the first verifying voltage of the first set of program parameters is greater than the second verifying voltage of the second set of program parameters.

In an exemplary embodiment of the invention, the step of adjusting the first set of programming parameters to obtain the second set of programming parameters includes: the first incremental step program adjustment value of the first set of program parameters is adjusted to obtain a value as the second incremental step program adjustment value of the second set of program parameters.

In an exemplary embodiment of the invention, the first type of data is firmware code and the first area is a system area for independently storing the firmware code, and the second type of data is user data and the second area is a temporary storage area for temporarily storing the user data.

In an exemplary embodiment of the invention, the method for programming a memory cell further includes: performing an erase operation on the physical programming units storing the first type of data using a first set of parameters; and performing the erase operation on the physical programming cells storing the second type of data using the second set of parameters.

An exemplary embodiment of the present invention provides a memory control circuit unit for accessing a rewritable nonvolatile memory module, wherein the memory control circuit unit includes: host interface, memory interface and memory management circuit. The host interface is electrically connected to the host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit is provided with a plurality of entity programming units. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit writes a first type of data into one of the physical programming cells using a first set of programming parameters; and writing the second type of data into one of the physical programming units by using the second set of programming parameters, wherein at least part of the parameters in the first set of programming parameters are different from the second set of programming parameters, and the number of data bits of the memory cells of the physical programming units in which the first type of data is written by using the first set of programming parameters is the same as the number of data bits of the memory cells of the physical programming units in which the second type of data is written by using the second set of programming parameters.

An exemplary embodiment of the present invention provides a memory storage device, which includes: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is electrically connected to the host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit is provided with a plurality of entity programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit writes a first type of data into one of the physical programming units using a first set of programming parameters; and writing the second type of data into one of the physical programming units by using the second set of programming parameters, wherein at least part of the parameters in the first set of programming parameters are different from the second set of programming parameters, and the number of data bits of the memory cells of the physical programming units in which the first type of data is written by using the first set of programming parameters is the same as the number of data bits of the memory cells of the physical programming units in which the second type of data is written by using the second set of programming parameters.

In an exemplary embodiment of the invention, the memory control circuit unit groups the physically erased cells into at least a first region and a second region. And, in the operation of writing the first type of data into the plurality of physical programming units using the first set of programming parameters, the memory control circuit unit writes the first type of data into the physical erase units belonging to the first area using the first set of programming parameters, and in the operation of writing the second type of data into the plurality of physical programming units using the second set of programming parameters, the memory control circuit unit writes the second type of data into the physical erase units belonging to the second area using the second set of programming parameters.

In an exemplary embodiment of the invention, the memory control circuit unit adjusts the first set of programming parameters to obtain the second set of programming parameters.

In an exemplary embodiment of the invention, the memory control circuit unit receives data and determines whether the data belongs to the second type of data. If the data does not belong to the second type of data, the memory control circuit unit writes the data into at least one first physical erasing unit in the physical erasing units in the first area by using the first set of programming parameters. If the data belongs to the second type of data, the memory control circuit unit writes the data into at least one second entity erasing unit in the entity erasing units in the second area by using the second group of programming parameters.

In an exemplary embodiment of the invention, the memory control circuit unit identifies at least one logic unit to store the data, and determines whether the at least one logic unit is mapped to a physically erased cell of the second area. If the at least one logic unit is mapped to the physically erased unit in the second area, the memory control circuit unit identifies that the data belongs to the second type of data.

In an exemplary embodiment of the invention, the memory control circuit unit performs an erase operation on the first physically erased cell by using a single-level cell erase command, and performs an erase operation on the second physically erased cell by using a multi-level cell erase command.

In an exemplary embodiment of the invention, the memory control circuit unit adjusts a first verifying voltage of a first set of program parameters to obtain a voltage as a second verifying voltage of a second set of program parameters, wherein the first verifying voltage of the first set of program parameters is greater than the second verifying voltage of the second set of program parameters.

In an exemplary embodiment of the invention, the memory control circuit unit adjusts a first incremental step pulse program adjustment value of a first set of program parameters to obtain a value as a second incremental step pulse program adjustment value of a second set of program parameters, wherein the first incremental step pulse program adjustment value of the first set of program parameters is smaller than the second incremental step pulse program adjustment value of the second set of program parameters.

In an exemplary embodiment of the invention, the memory control circuit unit performs an erase operation on the physical programming units storing the first type of data using a first set of parameters, and performs the erase operation on the physical programming units storing the second type of data using a second set of parameters.

Based on the above, the memory cell programming method, the memory control circuit unit and the memory device according to the exemplary embodiments of the invention can select different programming parameters to write data according to the area of the data to be stored, thereby prolonging the lifetime of the memory cell and simultaneously considering the storage of important system data.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a block diagram of a host system and a memory storage device according to an example embodiment;

FIG. 2 is a diagram illustrating a computer, an input/output device, and a memory storage device according to an example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment;

FIG. 4 is a diagram illustrating the structure of a memory storage device according to an example embodiment;

FIG. 5 is a block diagram of a rewritable nonvolatile memory module according to an example embodiment;

FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment;

FIG. 7 is a schematic diagram illustrating programming of a memory cell according to an example embodiment;

FIG. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment;

FIGS. 9, 10, 11 and 12 are exemplary diagrams illustrating managing physically erased cells according to an exemplary embodiment;

FIG. 13 is a block diagram of a memory control circuit unit according to an example embodiment;

FIG. 14 is a diagram illustrating data buffering, according to an example;

FIG. 15 is a diagram illustrating a data merge process, according to an example;

FIG. 16 is a graph illustrating a statistical distribution of memory cells in an example of physically erased cells in a system area programmed using a first set of programming parameters, in accordance with an example embodiment;

FIG. 17 is a graph illustrating a statistical distribution of memory cells in an example of physically erased cells using a second set of programming parameters for programming a temporary memory area, in accordance with an exemplary embodiment;

FIG. 18 is a graph illustrating a statistical distribution of memory cells in an example of physically erased cells in a system area programmed using a first set of programming parameters, in accordance with another example embodiment;

FIG. 19 is a graph illustrating a statistical distribution of memory cells in an example of physically erased cells using a second set of programming parameters for programming a temporary memory area, in accordance with another exemplary embodiment;

FIG. 20 is a flowchart illustrating a method of programming a memory cell according to an example embodiment.

Description of reference numerals:

1000: a host system;

1100: a computer;

1102: a microprocessor;

1104: random Access Memory (RAM);

1106: input/output (I/O) devices;

1108: a system bus;

1110: a data transmission interface;

1202: a mouse;

1204: a keyboard;

1206: a display;

1208: a printer;

1212: a portable disk;

1214: a memory card;

1216: a solid state disk;

1310: a digital camera;

1312: an SD card;

1314: an MMC card;

1316: a memory stick;

1318: a CF card;

1320: an embedded storage device;

100: a memory storage device;

102: a connection interface unit;

104: a memory control circuit unit;

106: a rewritable non-volatile memory module;

2202: an array of memory cells;

2204: a word line control circuit;

2206: a bit line control circuit;

2208: a row decoder;

2210: a data input/output buffer memory;

2212: a control circuit;

702: a storage unit;

704: a bit line;

706: a word line;

708: a source line;

712: a select gate drain transistor;

714: a select gate-source transistor;

VA: a first preset read voltage;

VB: a second preset read voltage;

VC: a third preset read voltage;

VD: a fourth preset read voltage;

VE: a fifth preset read voltage;

VF: a sixth preset read voltage;

VG: a seventh preset read voltage;

202: a memory management circuit;

410(0) to 410 (N): a physical erase unit;

502: a data area;

504: an idle area;

506: a system area;

508: temporarily storing the storage area;

510: a substitution region;

LBA (0) to LBA (h): a logic unit;

204: a host interface;

206: a memory interface;

208: an error checking and correcting circuit;

210: a buffer memory;

212: a power management circuit;

VV 1: a first verify voltage;

VV 2: a second verify voltage;

s2001, S2003, S2005, S2007: and (5) carrying out the following steps.

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a block diagram of a host system and a memory storage device according to an example embodiment.

Referring to FIG. 1, a host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106. The computer 1100 includes a microprocessor 1102, a Random Access Memory (RAM) 1104, a system bus 1108, and a data transfer interface 1110. The I/O devices 1106 include a mouse 1202, a keyboard 1204, a display 1206 and a printer 1208 as shown in FIG. 2 (FIG. 2 is a schematic diagram of a computer, I/O devices and memory storage devices according to an example embodiment). It should be understood that the devices shown in FIG. 2 are not limited to the I/O device 1106, and that the I/O device 1106 may include other devices as well.

In the embodiment of the invention, the memory storage device 100 is electrically connected to other components of the host system 1000 through the data transmission interface 1110. Data may be written to or read from memory storage device 100 by operation of microprocessor 1102, random access memory 1104, and input/output device 1106. For example, the memory storage device 100 may be a rewritable nonvolatile memory storage device such as a flash drive 1212, a memory card 1214, or a Solid State Drive (SSD) 1216 shown in fig. 2.

In general, host system 1000 is any system that can substantially cooperate with memory storage device 100 to store data. Although the host system 1000 is illustrated as a computer system in the present exemplary embodiment, the host system 1000 may be a digital camera, a video camera, a communication device, an audio player, a video player, or the like in another exemplary embodiment of the present invention. For example, when the host system is a digital camera 1310, the rewritable nonvolatile memory storage device is an SD card 1312, an MMC card 1314, a memory stick 1316, a CF card 1318 or an embedded storage device 1320 (as shown in fig. 3, fig. 3 is a schematic diagram of the host system and the memory storage device according to an example embodiment). The Embedded storage 1320 includes an Embedded multimedia card (eMMC). It should be noted that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 4 is a block diagram illustrating a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 100 includes a connection interface unit 102, a memory control circuit unit 104, and a rewritable nonvolatile memory module 106.

In the exemplary embodiment, the connection interface unit 102 is compatible with a Universal Serial Bus (USB) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 102 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (SATA) standard, the Secure Digital (SD) interface standard, the Serial Advanced Technology Attachment (SATA) standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the memory stick (MemoryStick) interface standard, the Multimedia Memory Card (MMC) interface standard, eMMC interface standard, UFS interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standards.

The memory control circuit unit 104 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 106 according to commands of the host system 1000.

The rewritable nonvolatile memory module 106 is electrically connected to the memory control circuit unit 104 and is used for storing data written by the host system 1000. Specifically, the memory cells of the rewritable nonvolatile memory module 106 constitute a plurality of physical programming units to store data. In the present exemplary embodiment, the rewritable nonvolatile memory module 106 is a Three Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 106 may also be a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

FIG. 5 is a block diagram of a rewritable nonvolatile memory module according to an example embodiment.

Referring to fig. 5, the rewritable nonvolatile memory module 106 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.

FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment.

Referring to fig. 5 and 6, a memory cell array 2202 includes a plurality of memory cells 702 for storing data, a plurality of Select Gate Drain (SGD) transistors 712, a plurality of Select Gate Source (SGS) transistors 714, and a plurality of bit lines 704, a plurality of word lines 706, and a common source line 708 (see fig. 6) connecting the memory cells. Memory cells 702 are arranged in an array at the intersections of bit lines 704 and word lines 706. When a write command or a read command is received from the memory control circuit 104, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the column decoder 2208 and the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 controls voltages applied to the word lines 706, the bit line control circuit 2206 controls voltages applied to the bit lines 704, the column decoder 2208 selects a corresponding bit line according to a decoded row address in the command, and the data input/output buffer 2210 is used for temporarily storing the data.

The memory cells in the rewritable nonvolatile memory module 106 represent multiple bits (bits) of data with multiple gate voltages. Data writing (or programming) of the memory cells of the memory cell array 2202 utilizes a voltage applied to a particular terminal, such as a control gate voltage, to change the amount of electrons in a charge trapping layer in the gate, thereby changing the conduction state of the channel of the memory cell to assume different memory states.

FIG. 7 is a schematic diagram illustrating programming of a memory cell according to an example embodiment.

Referring to fig. 7, in the present exemplary embodiment, the programming of the memory cell is accomplished by a pulsed write/verify threshold voltage method. Specifically, when data is to be written into the memory cells, the memory control circuit unit 104 sets an initial write voltage and a write voltage pulse time, and instructs the control circuit 2212 of the rewritable nonvolatile memory module 106 to program the memory cells using the set initial write voltage and write voltage pulse time, so as to write the data. The memory control circuit unit 104 then verifies the memory cells using the verification voltage to determine whether the memory cells are in the correct storage state. If the memory cell is not programmed to the correct memory state, the memory control circuit unit 104 instructs the control circuit 2212 to add an Incremental-step-pulse-programming (ISPP) adjustment value to the currently applied write voltage as a new write voltage (also called a re-write voltage) and to program the memory cell again according to the new write voltage and the write voltage pulse time. Conversely, if the memory cell has been programmed to the correct memory state, it indicates that the data has been correctly written to the memory cell. For example, the initial write Voltage is set to 16 volts (V), the write Voltage pulse duration is set to 18 microseconds (μ s) and the delta step pulse program adjustment value is set to 0.6V, but the invention is not limited thereto.

The read operation of a memory cell in the memory cell array 2202 is performed by applying a read voltage to a control gate (control gate) to identify data stored in the memory cell by the conduction state of a channel (a path for electrically connecting a bit line and a source line, for example, a path between a source and a drain of the memory cell) of the memory cell.

Fig. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment, which is exemplified by a TLC NAND type flash memory.

Referring to fig. 8, the storage states of the memory cells of the rewritable nonvolatile memory module 106 include the Least Significant Bit (LSB) of the 1 st Bit counted from the left side, the middle Significant Bit (CSB) of the 2 nd Bit counted from the left side, and the Most Significant Bit (MSB) of the 3 rd Bit counted from the left side, where the LSB corresponds to the lower entity programming unit, the CSB corresponds to the middle entity programming unit, and the MSB corresponds to the upper entity programming unit. In this example, the gate voltage of each memory cell can be divided into 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010" and "011") according to the first preset read voltage VA, the second preset read voltage VB, the third preset read voltage VC, the fourth preset read voltage VD, the fifth preset read voltage VE, the sixth preset read voltage VF and the seventh preset read voltage VG. In particular, the plurality of memory cells arranged on the same word line may constitute 3 physical program cells, wherein a physical program cell constituted by the LSB of the memory cells is referred to as a lower physical program cell, a physical program cell constituted by the CSB of the memory cells is referred to as a middle physical program cell, and a physical program cell constituted by the MSB of the memory cells is referred to as an upper physical program cell.

FIGS. 9, 10, 11 and 12 are exemplary diagrams illustrating managing physically erased cells according to an exemplary embodiment.

Referring to fig. 9, the memory control circuit unit 104 (or the memory management circuit 202) performs a write operation on the memory cells 702 of the rewritable and nonvolatile memory module 106 in units of physical programming cells and performs an erase operation on the memory cells 702 of the rewritable and nonvolatile memory module 106 in units of physical erasing cells. Specifically, the memory cells 702 of the rewritable nonvolatile memory module 106 constitute a plurality of physical programming units, and the physical programming units constitute a plurality of physical erasing units 400(0) -400 (N). The physical erase cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming cell is the smallest cell programmed. That is, one physical programming cell is the smallest unit of written data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit area includes a plurality of physical access addresses for storing user data, and the redundancy bit area stores system data (e.g., control information and error correction codes). For example, taking the rewritable non-volatile memory module 106 belonging to TLC NAND flash memory as an example, the LSBs of the memory cells located on the same word line form a next physical programming unit; CSB of memory cells on the same word line constitute a middle entity programming unit; and the MSBs of the memory cells on the same word line constitute an upper physical programming unit. That is, the entity programming units in the entity erasing units of the rewritable nonvolatile memory module 106 can be divided into lower entity programming units, middle entity programming units and upper entity programming units (as shown in FIG. 10).

Referring to FIG. 11, in the exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) logically groups the physical erase units 410(0) -410 (N) into a data area 502, an idle area 504, a system area 506, a temporary storage area 508 and a replacement area 510.

The physically erased cells logically belonging to the data area 502 and the idle area 504 are used for storing data from the host system 1000. Specifically, the physical erase units in the data area 502 are regarded as physical erase units with stored data, and the physical erase units in the idle area 504 are used to replace the physical erase units in the data area 502. That is, when receiving a write command and data to be written from the host system 1000, the memory control circuit unit 104 (or the memory management circuit 202) extracts the physical erase unit from the idle area 504 and writes the data into the extracted physical erase unit to replace the physical erase unit in the data area 502.

The physical erase unit logically belonging to the system area 506 is used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased cells of the rewritable nonvolatile memory module, the number of physically programmed cells of each physically erased cell, the firmware code of the memory storage device 100, and so on.

The physical erase unit logically belonging to the temporary storage area 508 is used as a temporary physical erase unit in the temporary physical erase unit group corresponding to the logical unit to temporarily store the data written by the host system 1000. The detailed method and steps for temporarily storing data will be described later with reference to the accompanying drawings.

The physically erased cells logically belonging to the replacement area 510 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 510 and the physically erased cells in the data area 502 are damaged, the memory management circuit 202 extracts the normal physically erased cells from the replacement area 510 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 502, the idle area 504, the system area 506 and the replacement area 510 may vary according to different memory specifications. Moreover, it should be appreciated that the grouping relationship of the physically erased cells associated with the data area 502, the idle area 504, the system area 506 and the replacement area 510 may dynamically change during the operation of the memory storage device 100. For example, when the physically erased cells in the idle area 504 are damaged and replaced by the physically erased cells in the replacement area 510, the physically erased cells in the replacement area 510 are associated with the idle area 504.

Referring to fig. 12, the memory control circuit unit 104 (or the memory management circuit 202) configures logical units LBA (0) -LBA (h) to map the physical erase units of the data area 502, where each logical unit has a plurality of logical sub-units to map the physical program units of the corresponding physical erase units. Moreover, when the host system 1000 wants to write data to the logical units or update the data stored in the logical units, the memory control circuit unit 104 (or the memory management circuit 202) extracts a physical erase unit from the idle area 504 to write data, so as to replace the physical erase unit in the data area 502. In the present exemplary embodiment, the logical subunit may be a logical page or a logical sector.

In order to identify the physical erase unit in which the data of each logic unit is stored, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) records the mapping between the logic units and the physical erase units. Moreover, when the host system 1000 intends to access data in the logical sub-unit, the memory control circuit unit 104 (or the memory management circuit 202) confirms the logical unit to which the logical sub-unit belongs, and issues a corresponding command sequence to the rewritable nonvolatile memory module 106 to access data in the physical erase unit mapped by the logical unit. For example, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) stores a logical-to-physical address mapping table in the rewritable nonvolatile memory module 106 to record the physical erase unit mapped by each logical unit, and the memory control circuit unit 104 (or the memory management circuit 202) loads the logical-to-physical address mapping table into the buffer memory 208 to maintain when data is to be accessed.

FIG. 13 is a block diagram of a memory control circuit unit according to an example embodiment. It should be understood that the structure of the memory control circuit unit shown in fig. 13 is only an example, and the invention is not limited thereto.

Referring to FIG. 13, the memory control circuit unit 104 includes a memory management circuit 202, a host interface 204, a memory interface 206 and an error checking and correcting circuit 208.

The memory management circuit 202 is used to control the overall operation of the memory control circuit unit 104. Specifically, the memory management circuit 202 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 100.

In the exemplary embodiment, the control instructions of the memory management circuit 202 are implemented in firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 100 is operating, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be stored in a program code form in a specific area of the rewritable non-volatile memory module 106 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a driver code, and when the memory control circuit unit 104 is enabled, the microprocessor unit first executes the driver code segment to load the control command stored in the rewritable nonvolatile memory module 106 into the ram of the memory management circuit 202. Then, the microprocessor unit will run these control commands to perform the operations of data writing, reading and erasing.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be implemented in a hardware type. For example, the memory management circuit 202 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the physical erase cells of the rewritable nonvolatile memory module 106; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 106 so as to write data into the rewritable nonvolatile memory module 106; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 106 so as to read data from the rewritable nonvolatile memory module 106; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 106 so as to erase data from the rewritable nonvolatile memory module 106; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 106 and data read from the rewritable nonvolatile memory module 106.

The host interface 204 is electrically connected to the memory management circuit 202 and is used for receiving and recognizing commands and data transmitted by the host system 1000. That is, commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204. In the exemplary embodiment, the host interface 204 is compatible with the USB standard. However, it should be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the SD standard, the SATA standard, the UHS-I interface standard, the UHS-II interface standard, the MS standard, the MMC standard, the eMMC interface standard, the UFS interface standard, the CF standard, the IDE standard, or other suitable data transfer standard.

The memory interface 206 is electrically connected to the memory management circuit 202 and is used for accessing the rewritable nonvolatile memory module 106. That is, the data to be written into the rewritable nonvolatile memory module 106 is converted into a format accepted by the rewritable nonvolatile memory module 106 through the memory interface 206.

The error checking and correcting circuit 208 is electrically connected to the memory management circuit 202 and is used for performing an error correction procedure to ensure the correctness of data. Specifically, when the memory management circuit 202 reads data from the rewritable nonvolatile memory module 106, the error checking and correcting circuit 208 performs an error correcting procedure on the read data. For example, in the exemplary embodiment, the error checking and correcting circuit 208 is a Low Density Parity Check (LDPC) circuit and stores a Log Likelihood Ratio (LLR) value lookup table. When the memory management circuit 202 reads data from the rewritable nonvolatile memory module 106, the error checking and correcting circuit 208 performs an error correcting process according to the read data and the corresponding LLR values in the lookup table. It is worth mentioning that in another exemplary embodiment, the error checking and correcting circuit 208 may also be a Turbo Code (Turbo Code) circuit.

In an exemplary embodiment of the invention, the memory control circuit unit 104 further includes a buffer memory 210 and a power management circuit 212.

The buffer memory 210 is electrically connected to the memory management circuit 202 and is used for temporarily storing data and instructions from the host system 1000 or data from the rewritable nonvolatile memory module 106.

The power management circuit 212 is electrically connected to the memory management circuit 202 and is used for controlling the power of the memory storage device 100.

In an exemplary embodiment of the invention, when the host system 1000 wants to store data to the logical units mapped by the data area 502, the memory control circuit unit 104 (or the memory management circuit 202) will first temporarily store the data by using the physical erase units of the temporary storage area 508. Specifically, when a write command instructing to store data into the logical unit is received from the host system 1000, the memory control circuit unit 104 (or the memory management circuit 202) extracts several physically erased units from the temporary storage area 508 as temporary physically erased units corresponding to the logical unit, and temporarily stores the data into the next physically programmed units of the temporary physically erased units in a single page manner. Then, the memory control circuit unit 104 (or the memory management circuit 202) writes the data in the temporary physical erase unit to the corresponding physical erase unit in a multi-page manner and maps the logical unit to the corresponding physical erase unit. Herein, the data to be stored in the logical unit mapped to the data area 502 is also referred to as the second type data or user data.

Here, the single page method is a method in which only 1 bit of data is stored in a memory cell. That is, for a memory cell capable of storing multiple bits, in the single page mode, the memory control circuit unit 104 (or the memory management circuit 202) only performs a data write operation on the lower entity programming unit. Since the temporary physical erase unit is operated in a single page manner, in the exemplary embodiment, only one third of the capacity of one temporary physical erase unit is used and the group of temporary physical erase units corresponding to one logic unit includes 3 temporary physical erase units to provide enough space for storing data of one logic unit. In the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) operates the physical erase unit of the temporary memory area 508 using a single page method.

The multi-page scheme is to store data using a lower physical programming unit, a middle physical programming unit, and an upper physical programming unit. That is, for memory cells capable of storing multiple bits, when writing data using the multi-page scheme, the memory control circuit unit 104 (or the memory management circuit 202) performs programming on the lower physical program cell, the middle physical program cell and the upper physical program cell of one physical program cell group. It should be noted that in an exemplary embodiment, when the physically erased cells are operated in a multi-page manner, the physically programmed cells of the same group of physically programmed cells are programmed simultaneously or in a phase. Furthermore, the life of the physically erased cells operating with multiple pages is shorter than that of the physically erased cells operating with a single page. Specifically, the number of times each physically erased cell can be written or erased is limited, and when the number of times a physically erased cell is written exceeds a threshold, the physically erased cell may be damaged and cannot be written with data any more, wherein the threshold corresponding to the physically erased cell operating in the multi-page manner is lower than the threshold corresponding to the physically erased cell operating in the single-page manner. In the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) operates the physical erase units associated with the data area 502 in a multi-page manner.

In the exemplary embodiment, when a physical erase unit is divided into the temporary memory area 508, the physical erase unit can only be used in the temporary memory area 508, and will not be mixed with the physical erase units in the idle area 504 and the data area 502. That is, the memory control circuit unit 104 (or the memory management circuit 202) operates the physical erase units of the temporary storage area 508 and the idle area 504 independently. For example, after a physical erase unit is divided into the temporary storage area 508, the memory control circuit unit 104 (or the memory management circuit 202) operates the physical erase unit in the temporary storage area 508 in a single page manner until the physical erase unit is damaged.

Fig. 14 is a diagram illustrating data buffering according to an example.

Referring to fig. 14, when the memory storage device 100 receives a write command from the host system 1000, which indicates to store the update data to the 0 th to 257 th logical sub-units of the logical unit LBA (0), assuming that in the present example embodiment, the memory control circuit unit 104 (or the memory management circuit 202) extracts 3 physical erase units 410(T +1), 410(T +2), and 410(T +3) from the temporary storage area 508 as temporary physical erase units of the corresponding logical unit LBA (0), the memory control circuit unit 104 (or the memory management circuit 202) writes the update data belonging to the logical unit LBA (0) by using the temporary physical erase unit 410(T +1), the temporary physical erase unit 410(T +2), and the temporary physical erase unit 410(T +3) of the corresponding logical unit LBA (0).

For example, the memory control circuit unit 104 (or the memory management circuit 202) sequentially writes the update data of the 0 th to 85 th logical sub-units to be stored in the logical unit LBA (0) to the lower physical programming unit of the temporary physical erase unit 410(T +1), sequentially writes the update data of the 86 th to 171 th logical sub-units to be stored in the logical unit LBA (0) to the lower physical programming unit of the temporary physical erase unit 410(T +2), and sequentially writes the update data of the 172 th to 257 th logical sub-units to be stored in the logical unit LBA (0) to the lower physical programming unit of the temporary physical erase unit 410(T + 3).

In the present exemplary embodiment, after the update data to be stored by the host system 1000 is written into the temporary physical erase unit 410(T +1), the temporary physical erase unit 410(T +2), and the temporary physical erase unit 410(T +3) of the corresponding logical unit LBA (0), the memory control circuit unit 104 (or the memory management circuit 202) transmits a Response (Response) notifying that the command is completed to the host system 1000. Then, when the memory storage device 100 is in the idle state for a period of time (e.g., 30 seconds without receiving any command from the host system 1000) or the number of empty physical erase units in the temporary storage area 508 and the idle area 504 is smaller than a predetermined threshold, the memory control circuit unit 104 (or the memory management circuit 202) merges valid data belonging to a logical unit from the temporary physical erase unit of the corresponding logical unit into an empty physical erase unit and maps the logical unit to the physical erase unit. For example, the predetermined threshold is set to 3. However, it should be understood that the present invention is not limited thereto, and the predetermined threshold value may be other suitable values. Herein, the operation of copying the valid data belonging to a logical unit from the temporary physical erase unit group corresponding to the logical unit to a physical erase unit corresponding to the logical unit in the data area 502 is referred to as a data merge operation.

FIG. 15 is a diagram illustrating a data merging procedure according to an example.

Assume that the temporary erase unit 410(T +1), the temporary erase unit 410(T +2), and the temporary erase unit 410(T +3) corresponding to the logical unit LBA (0) have stored valid data of all logical sub-units of the logical unit LBA (0) (as shown in fig. 7) and the memory management circuit 202 selects to perform the data merge operation on the logical unit LBA (0).

First, as shown in FIG. 15, the memory control circuit unit 104 (or the memory management circuit 202) extracts a physical erase cell from the idle region 504 as a physical erase cell 410(F +1) for rotation. Specifically, the memory control circuit unit 104 (or the memory management circuit 202) selects an empty physical erase unit or a physical erase unit with invalid data stored therein from the idle area 504. In particular, if the extracted physical erase cell is a physical erase cell storing invalid data, the memory control circuit unit 104 (or the memory management circuit 202) performs an erase operation on the physical erase cell. That is, the invalid data on the physically erased cells must be erased first.

Referring to FIG. 15, the memory control circuit unit 104 (or the memory management circuit 202) copies the valid data of the 0 th to 85 th logical sub-units belonging to the logical unit LBA (0) from the lower physical program unit of the temporary physical erase unit 410(T +1) to the corresponding pages (e.g., 0 th to 85 th physical program units) of the physical erase unit 410(F + 1). Then, the memory control circuit unit 104 (or the memory management circuit 202) copies the valid data of the 86 th to 171 th logical sub-units belonging to the logical unit LBA (0) from the lower physical program unit of the temporary physical erase unit 410(T +2) to the corresponding pages (e.g., the 86 th to 171 th physical program units) of the physical erase unit 410(F + 1). Then, the memory control circuit unit 104 (or the memory management circuit 202) copies the valid data of the 172 nd to 257 th logical sub-units belonging to the logical unit LBA (0) from the lower physical program unit of the temporary physical erase unit 410(T +3) to the corresponding pages (e.g., 172 nd to 257 th physical program units) of the first physical erase unit 410(F + 1).

It is noted that, as described above, the physically erased cells to be associated with the data area 502 are operated in a multi-page manner, and thus, the writing to the physically erased cells 410(F +1) is performed simultaneously or in a stepwise manner in units of the physically programmed cell groups. Specifically, in an exemplary embodiment, the 0 th, 1 th, and 2 nd physical program cells of the physical erase cell 410(F +1) are simultaneously programmed to write data belonging to the 0 th, 1 th, and 2 nd logical sub-cells of the logical cell LBA (0); the 3 rd, 4 th, and 5 th physical program cells of the physical erase cell 410(F +1) are simultaneously programmed to write data belonging to the 3 rd, 4 th, and 5 th logical sub-cells of the logical unit LBA (0); and so on, the data of other logical sub-units are written into the first physically erased unit 410(F +1) in units of physically programmed unit groups.

Finally, the memory control circuit unit 104 (or the memory management circuit 202) maps the logical unit LBA (0) to the physical erase unit 410(F +1) in the logical-to-physical address mapping table and performs an erase operation on the temporary physical erase units 410(T +1) -410 (T +3) corresponding to the logical unit. That is, when the next write command is executed, the erased temporary physical erase units 410(T +1) -410 (T +3) can be selected as the temporary physical erase units of the logic units to be written.

In addition to the temporary memory area 508, in the exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) also operates the physical erase unit belonging to the system area 506 in a single page manner. Specifically, if the data (e.g., firmware code) stored in the system area 506 is lost, the memory storage device 100 is not operable, and therefore the memory control circuit unit 104 (or the memory management circuit 202) is designed to write the data to the next physically programmed unit of the physically erased units in the system area 506. For example, in the present exemplary embodiment, a set of programming parameters (hereinafter referred to as a first set of programming parameters) including an incremental step pulse program adjustment value (hereinafter referred to as a first incremental step pulse program adjustment value), an initial write voltage (hereinafter referred to as a first initial write voltage), a verify voltage (hereinafter referred to as a first verify voltage), a read voltage (hereinafter referred to as a first read voltage), a turn-on voltage (hereinafter referred to as a first turn-on voltage), and an erase voltage (hereinafter referred to as a first erase voltage) is preset for programming data to the physically erased cells below the physically erased cells of the system area 506. Herein, data to be stored to the logical unit of the physical program unit of the mapping system area 506 is referred to as first type data or system data.

As described above, when the memory storage device 100 receives data from the host system 1000 to be stored in the logical unit of the physical erase unit of the mapped data area 502 (i.e., the received write data belongs to the second type of data), the memory control circuit unit 104 (or the memory management circuit 202) temporarily stores the data in the physical erase unit of the temporary storage area 508 operating in a single page manner. For example, in the present exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) adjusts the first set of programming parameters preset for the physically erased cells of the system area 506 to generate another set of programming parameters (hereinafter referred to as the second set of programming parameters) for the physically erased cells of the temporary storage area 508.

That is, in the exemplary embodiment, for the system area 506 and the temporary storage area 508, which also store only 1 bit of data per memory cell, the memory control circuit unit 104 (or the memory management circuit 202) writes the first type of data and the second type of data to the corresponding physical programming units using the first set of programming parameters and the second set of programming parameters, respectively.

For example, in an exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) may obtain a voltage by lowering a first verify voltage of the first set of programming parameters as a second verify voltage of the second set of programming parameters.

FIG. 16 is a graph illustrating a statistical distribution of memory cells in an example of physically erased cells of a system area programmed using a first set of programming parameters, according to an example embodiment, and FIG. 17 is a graph illustrating a statistical distribution of memory cells in an example of physically erased cells of a temporary storage area programmed using a second set of programming parameters, according to an example embodiment.

Referring to FIG. 16, the physically erased cells in the system area 506 are operated in a single page manner, so that the gate voltages of the memory cells need to be differentiated into two memory states. Since the first verify voltage VV1 of the first set of programming parameters is set at a higher voltage, the memory control circuit unit 104 (or the memory management circuit 202) needs to perform a larger number of programming operations when writing data to the physically erased cells of the system area 506 by the pulse-write/verify-threshold-voltage method using the first set of programming parameters. In particular, since the physically erased cells of the system area 506 are storing important and frequently read data (e.g., firmware codes), the first verify voltage VV1 of the first set of programming parameters is set to a higher voltage to clearly distinguish between the memory state identified as '1' (also referred to as the first state) and the memory state identified as '0' (also referred to as the second state), thereby more avoiding the identification error during reading. That is, the voltage spacing between the first state and the second state of the statistical distribution of threshold voltages of the memory cells of the physically programmed cells programmed with the first set of programming parameters is greater than the voltage spacing between the first state and the second state of the statistical distribution of threshold voltages of the memory cells of the physically programmed cells programmed with the second set of programming parameters. Accordingly, the data retention or read disturb resistance of a physically programmed cell programmed with the first set of programming parameters will be better than the data retention or read disturb resistance of a physically programmed cell programmed with the second set of programming parameters.

Referring to FIG. 17, similarly, since the physically erased cells in the temporary storage area 508 are operated in a single page, the gate voltages of the memory cells need to be differentiated into two storage states. In particular, since the second verifying voltage VV2 of the second set of programming parameters is smaller than that of the first set of programming parameters, when the memory control circuit unit 104 (or the memory management circuit 202) programs data to the physically erased cells in the temporary storage area 508 by the pulse write/verify threshold voltage method using the second set of programming parameters, the memory cells can complete the data writing through the verification of the second verifying voltage VV2 in a smaller number of programming operations. Since the physically erased cells in the temporary storage area 508 can complete the data writing operation with a smaller number of programming operations, compared to the physically erased cells in the system area 506, the programming operation has a lower influence on the physically erased cells in the temporary storage area 508. In particular, since the temporary storage area 508 is used for temporarily storing data, the physically erased cells in the temporary storage area 508 are frequently programmed, and therefore, the lifetime of the physically erased cells in the temporary storage area 508 can be effectively prolonged by using the second set of programming parameters with the smaller second verification voltage VV 2. Accordingly, the life span of the physical programming cells programmed with the second set of programming parameters will be better than the life span of the physical programming cells programmed with the first set of programming parameters.

For example, in another exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) may also obtain the adjustment value obtained by increasing the first incremental step program adjustment value of the first set of programming parameters as the second incremental step program adjustment value of the second set of programming parameters.

FIG. 18 is a graph illustrating a statistical distribution of memory cells in an example of programming physically erased cells of a system area using a first set of programming parameters, according to another example embodiment, and FIG. 19 is a graph illustrating a statistical distribution of memory cells in an example of programming physically erased cells of a temporary storage area using a second set of programming parameters, according to another example embodiment.

Referring to FIG. 18, the physically erased cells in the system area 506 are operated in a single page, so that the gate voltages of the memory cells need to be differentiated into two memory states. Since the first incremental step pulse program adjustment value of the first set of programming parameters is set to a smaller value, the memory control circuit unit 104 (or the memory management circuit 202) needs to perform more programming operations to pass the verification voltage verification when writing data to the physically erased cells of the system area 506 by the pulse write/verify threshold voltage method using the first set of programming parameters. However, since the first incremental step pulse program adjustment value is small and the write voltage amplification per program is small, the electron amount of the charge trapping layer in the gate is more precisely controlled. Accordingly, the memory cells of the physically erased cells of the system area 506 programmed by using the first set of programming parameters can be programmed to a more correct state, thereby effectively avoiding the occurrence of read disturb.

Referring to FIG. 19, since the physically erased cells in the temporary storage area 508 are operated in a single page, the gate voltages of the memory cells need to be differentiated into two storage states. In particular, since the second incremental step pulse program adjustment value of the second set of programming parameters is larger than that of the first set of programming parameters, when the memory control circuit unit 104 (or the memory management circuit 202) uses the second set of programming parameters to program data into the physically erased cells in the temporary storage area 508 by the pulse write/verify threshold voltage method, the memory cells can complete the data writing through the verification of the verify voltage in a smaller number of programming operations. Since the physically erased cells in the temporary storage area 508 can complete the data writing operation with a smaller number of programming operations, compared to the physically erased cells in the system area 506, the programming operation has a lower influence on the physically erased cells in the temporary storage area 508. In particular, since the temporary storage area 508 is used for temporarily storing data, the physically erased cells in the temporary storage area 508 are frequently programmed, and therefore, the lifetime of the physically erased cells in the temporary storage area 508 can be effectively prolonged by using the second set of programming parameters with larger second incremental step pulse program adjustment values.

It should be understood that fig. 16-19 are merely examples of adjusting the first set of programming parameters to generate the second set of programming parameters, and the invention is not limited thereto. In other exemplary embodiments, the memory control circuit unit 104 (or the memory management circuit 202) may adjust at least one of the first incremental step pulse program adjustment value, the first initial write voltage, the first verify voltage, the first read voltage, the first turn-on voltage, and the first erase voltage of the first set of programming parameters to obtain the second incremental step pulse program adjustment value, the second initial write voltage, the second verify voltage, the second read voltage, the second turn-on voltage, and the second erase voltage of the second set of programming parameters.

Referring to fig. 20, in step S2001, the memory control circuit unit 104 (or the memory management circuit 202) receives data to be stored. For example, the memory storage device 100 receives an incoming command and data corresponding to the incoming command from the host system 1000, wherein the incoming command indicates a logical address for storing the data.

In step S2003, the memory control circuit unit 104 (or the memory management circuit 202) determines whether the received data belongs to the second type of data to be written into the physical erase unit of the second area (e.g., the temporary storage area 508). For example, in the present exemplary embodiment, the allocated logical units are physical erase units mapped to the data area 502, and therefore, when the received data is to be stored to the allocated logical units, the memory control circuit unit 104 (or the memory management circuit 202) identifies that the received data belongs to the second type of data to be buffered to the temporary storage area 508.

If the received data does not belong to the second type of data (i.e., the first type of data belonging to the physical erase cells to be written to the first region (e.g., system 506 above), in step S2005, the memory control circuit unit 104 (or the memory management circuit 202) writes the data to at least one physical erase cell (hereinafter referred to as a first physical erase cell) among the physical erase cells of the first region using the first set of programming parameters.

If the received data belongs to the second type of data, in step S2007, the memory control circuit unit 104 (or the memory management circuit 202) writes the data into at least one of the physically erased cells of the second area (hereinafter referred to as a second physically erased cell) by using the second set of programming parameters.

As described above, the physical erase units of the system area 506 and the temporary storage area 508 are operated in a single page, however, in the present exemplary embodiment, the rewritable nonvolatile memory module 106 is a TLCNAND type flash memory and all the physical erase units are erased by multi-level cell erase commands before data is written. That is, in the present exemplary embodiment, although the physically erased cells of the system area 506 and the temporary storage area 508 can store 3 bits of data, the memory control circuit unit 104 (or the memory management circuit 202) uses the first set of programming parameters and the second set of programming parameters to operate the physically erased cells of the system area 506 and the temporary storage area 508, so as to use only the lower physically programmed cells.

It should be noted that in another exemplary embodiment of the present invention, the memory control circuit unit 104 (or the memory management circuit 202) may also perform an erase operation on the physically erased cells of the system area 506 by using a single-level cell erase command before writing data into the physically erased cells of the system area 506, so that the physically erased cells of the system area 506 can only store 1 bit of data. In particular, the data stored in the physically erased cells of the system area 506 is more stable and reliable under this operation. For example, in this example, before the first physically erased cell is written with data, the memory control circuit unit 104 (or the memory management circuit 202) uses a single-level cell erase command to perform an erase operation on the first physically erased cell, and before the second physically erased cell is written with data, the memory control circuit unit 104 (or the memory management circuit 202) uses a multi-level cell erase command to perform an erase operation on the second physically erased cell.

In summary, the memory cell programming method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention use different programming parameters to program the memory cells according to different storage requirements of the system area and the buffer area, which are all operated in a single page manner, so as to prevent the data stored in the system area from being read and interfered, and prevent the physically erased cells temporarily stored in the storage area from being rapidly degraded.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory cell programming method is used for a rewritable nonvolatile memory module and is characterized in that the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit is provided with a plurality of entity programming units, each entity programming unit comprises a plurality of lower entity programming units and a plurality of upper entity programming units, and the memory cell programming method comprises the following steps:

writing a first type of data into a first physical programming cell of a first physical erase cell of the plurality of physical erase cells using a first set of programming parameters; and

writing a second type of data to a first physical program cell of a second physical erase cell of the plurality of physical erase cells using a second set of programming parameters,

wherein at least some of the first set of programming parameters are different from the second set of programming parameters, and wherein the physically programmed cells on the first physically erased cells written to the first type of data with the first set of programming parameters are not programmed and the physically programmed cells on the second physically erased cells written to the second type of data with the second set of programming parameters are not programmed.

2. The method of claim 1, wherein a first entity programmed cell of the second entity erased cells written with the second type of data among the entity programmed cells maps a corresponding logical address, and a first entity programmed cell of the first entity erased cells written with the first type of data does not map a corresponding logical address.

3. The method of claim 1, wherein the number of bits of data of the memory cell of the first physical program cell of the first physical erase cell written with the first set of programming parameters to the first type of data is 1 bit and the number of bits of data of the memory cell of the first physical program cell of the second physical erase cell written with the second set of programming parameters to the second type of data is 1 bit.

4. The method of programming a memory cell of claim 3, further comprising:

grouping the entity erasing units into at least a first area and a second area;

the first physically erased cell belongs to the first region, and the second physically erased cell belongs to the second region.

5. The memory cell programming method of claim 4,

wherein the first set of programming parameters is pre-configured for the first region of physically erased cells, wherein upper physically programmed cells of the first region of physically erased cells are not used to store data;

wherein the second set of programming parameters is for the physically erased cells of the second region and upper ones of the physically erased cells of the second region are not used for storing data.

6. The method of programming a memory cell of claim 5, further comprising:

the first set of programming parameters is adjusted to obtain the second set of programming parameters.

7. The method of programming a memory cell of claim 4, further comprising:

receiving a data;

judging whether the data belongs to the second class of data;

if the data does not belong to the second type of data, writing the data into at least one physically erased cell of the physically erased cells of the first region by using the first set of programming parameters; and

if the data belongs to the second type of data, the data is written into at least one of the physically erased cells of the second region using the second set of programming parameters.

8. The method of programming a memory cell of claim 7, further comprising:

identifying at least one logic unit in which the data is to be stored;

determining whether the at least one logic unit is mapped to the plurality of physical erase units in the second area; and

if the at least one logic unit is mapped to the physically erased cells in the second area, the data is identified as belonging to the second type of data.

9. The method of programming a memory cell of claim 1, further comprising:

performing an erase operation on the first physically erased cell using a single-level cell erase command; and

the erase operation is performed on the second physically erased cell using a multi-level cell erase command.

10. The method of claim 1, wherein the first set of programming parameters includes at least one of a first incremental step pulse program adjust value, a first initial write voltage, a first verify voltage, a first read voltage, a first turn-on voltage, and a first erase voltage.

11. The method of claim 1, wherein data retention or anti-disturb capability of physical program cells programmed with the first set of programming parameters is better than data retention or anti-disturb capability of physical program cells programmed with the second set of programming parameters.

12. The method of claim 1, wherein the life span of one of the physical program cells programmed with the second set of programming parameters is better than the life span of one of the physical program cells programmed with the first set of programming parameters.

13. The method of claim 1, wherein a voltage separation between a first state and a second state of a statistical distribution of threshold voltages of memory cells of physical program cells programmed with the first set of programming parameters is greater than a voltage separation between a first state and a second state of a statistical distribution of threshold voltages of memory cells of physical program cells programmed with the second set of programming parameters.

14. The method of claim 6, wherein the step of adjusting the first set of programming parameters to obtain the second set of programming parameters comprises:

adjusting a first verify voltage of the first set of programming parameters to obtain a voltage as a second verify voltage of the second set of programming parameters,

wherein the first verify voltage for the first set of programming parameters is greater than the second verify voltage for the second set of programming parameters.

15. The method of claim 6, wherein the step of adjusting the first set of programming parameters to obtain the second set of programming parameters comprises:

adjusting a first incremental step pulse program adjustment value of the first set of programming parameters to obtain a value as a second incremental step pulse program adjustment value of the second set of programming parameters,

wherein the first incremental step pulse program adjustment value for the first set of programming parameters is less than the second incremental step pulse program adjustment value for the second set of programming parameters.

16. The method of claim 7, wherein the first type of data is a firmware code and the first area is a system area for independently storing the firmware code,

wherein the second type data is a user data and the second area is a temporary storage area for temporarily storing the user data.

17. The method of programming a memory cell of claim 4, further comprising:

performing an erase operation on the physical programming unit storing the first type of data using the first set of programming parameters; and

the erase operation is performed on the physical programming cells storing the second type of data using the second set of programming parameters.

18. A memory control circuit unit for accessing a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface for electrically connecting to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of entity erasing units, each entity erasing unit has a plurality of entity programming units, and each entity programming unit comprises a plurality of lower entity programming units and a plurality of upper entity programming units; and

a memory management circuit electrically connected to the host interface and the memory interface,

wherein the memory management circuit writes a first type of data to a first one of the physically erased cells using a first set of programming parameters and writes a second type of data to a second one of the physically erased cells using a second set of programming parameters,

wherein at least some of the first set of programming parameters are different from the second set of programming parameters, and upper physically programmed cells of the first physically erased cells written with the first set of programming parameters to the first type of data are not programmed and upper physically programmed cells of the second physically erased cells written with the second set of programming parameters to the second type of data are not programmed.

19. The memory control circuit unit of claim 18, wherein a first entity programmed cell of the second entity-erased cells written with the second type of data among the entity programmed cells maps a corresponding logical address, and a first entity programmed cell of the first entity-erased cells written with the first type of data does not map a corresponding logical address.

20. A memory storage device, comprising:

a connection interface unit for electrically connecting to a host system;

the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit is provided with a plurality of entity programming units, and each entity programming unit comprises a plurality of lower entity programming units and a plurality of upper entity programming units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit writes a first type of data into a first physical programming cell of a first one of the plurality of physically erased cells using a first set of programming parameters and writes a second type of data into a first physical programming cell of a second one of the plurality of physically erased cells using a second set of programming parameters,

21. The memory storage device of claim 20, wherein a first entity programmed cell of the second entity-erased cells written with the second type of data among the entity programmed cells maps a corresponding logical address, and a first entity programmed cell of the first entity-erased cells written with the first type of data does not map a corresponding logical address.

22. The memory storage device of claim 20, wherein the number of bits of data written into the memory cells of the first physical programming cells of the first physical erase cells of the first type of data with the first set of programming parameters is 1 bit and the number of bits of data written into the memory cells of the first physical programming cells of the second physical erase cells of the second type of data with the second set of programming parameters is 1 bit.

23. The memory storage device of claim 22, wherein the memory control circuit unit groups the physically erased cells into at least a first region and a second region,

24. The memory storage device of claim 23, wherein the first set of programming parameters is predetermined for the first region of physically erased cells and upper ones of the first region of physically erased cells are not used for storing data;

25. The memory storage device of claim 24, wherein the memory control circuit unit adjusts the first set of programming parameters to obtain the second set of programming parameters.

26. The memory storage device of claim 25, wherein the memory control circuit unit receives a data and determines whether the data belongs to the second class of data,

if the data does not belong to the second type of data, the memory control circuit unit writes the data into at least one of the plurality of physical erase cells of the first region using the first set of programming parameters,

if the data belongs to the second type of data, the memory control circuit unit writes the data into at least one entity erasing unit in the entity erasing units in the second area by using the second set of programming parameters.

27. The memory storage device of claim 26, wherein the memory control circuit unit identifies at least one logic cell to store the data and determines whether the at least one logic cell is mapped to the physically erased cells of the second region,

if the at least one logic unit is mapped to the physically erased cells in the second area, the memory control circuit unit identifies that the data belongs to the second type of data.

28. The memory storage device of claim 20, wherein the memory control circuitry unit performs an erase operation on the first physically erased cell using a single level cell erase command and the second physically erased cell using a multi-level cell erase command.

29. The memory storage device of claim 20, wherein the first set of programming parameters includes at least one of a first incremental step pulse program adjust value, a first initial write voltage, a first verify voltage, a first read voltage, a first turn-on voltage, and a first erase voltage.

30. The memory storage device of claim 25, wherein in the operation of adjusting the first set of programming parameters to obtain the second set of programming parameters, the memory control circuit unit adjusts a first verify voltage of the first set of programming parameters to obtain a voltage as a second verify voltage of the second set of programming parameters, wherein the first verify voltage of the first set of programming parameters is greater than the second verify voltage of the second set of programming parameters.

31. The memory storage device of claim 25, wherein in the operation of adjusting the first set of programming parameters to obtain the second set of programming parameters, the memory control circuit unit adjusts a first incremental step pulse program adjustment value of the first set of programming parameters to obtain a value as a second incremental step pulse program adjustment value of the second set of programming parameters, wherein the first incremental step pulse program adjustment value of the first set of programming parameters is smaller than the second incremental step pulse program adjustment value of the second set of programming parameters.

32. The memory storage device of claim 23 wherein the first type of data is a firmware code and the first region is a system region for independently storing the firmware code,

33. The memory storage device of claim 20, wherein the memory control circuit unit performs an erase operation on one of the physical programming cells storing the first type of data using the first set of programming parameters, and performs the erase operation on one of the physical programming cells storing the second type of data using the second set of programming parameters.

34. The memory storage device of claim 20, wherein data retention or read disturb resistance of physical program cells among the physical program cells programmed with the first set of programming parameters is better than data retention or read disturb resistance of physical program cells programmed with the second set of programming parameters.

35. The memory storage device of claim 20, wherein a life of a physical program cell among the physical program cells programmed with the second set of programming parameters is better than a life of a physical program cell programmed with the first set of programming parameters.

36. The memory storage device of claim 20 wherein the voltage spacing between the first state and the second state of the statistical distribution of threshold voltages of the memory cells of the physical program cells programmed with the first set of programming parameters is greater than the voltage spacing between the first state and the second state of the statistical distribution of threshold voltages of the memory cells of the physical program cells programmed with the second set of programming parameters.