CN109918132B - Instruction installation method and device, electronic equipment and storage medium - Google Patents
Instruction installation method and device, electronic equipment and storage medium Download PDFInfo
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- CN109918132B CN109918132B CN201910234150.1A CN201910234150A CN109918132B CN 109918132 B CN109918132 B CN 109918132B CN 201910234150 A CN201910234150 A CN 201910234150A CN 109918132 B CN109918132 B CN 109918132B
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Abstract
The embodiment of the invention provides an instruction installation method and device, wherein the method comprises the following steps: allocating at least one fixed area from a memory address space as a buffer according to a comparison result of the maximum value of the fixed area of the processor and the size of the buffer for storing the local instruction sequence in the virtual machine, compiling a target jump instruction in the virtual machine instruction sequence into a local jump instruction in the local instruction sequence, installing the local instruction sequence into the target fixed area of the buffer, realizing the control of the allocation of the buffer by taking the fixed area as a unit, and then compiling and installing of the local instruction sequence can be controlled, the jump instruction address and the jump target address of the regional jump instruction are ensured to be located in the same fixed region, the safety risk caused by generation of the regional jump instruction is avoided, the regional jump instruction is generated by automatic compiling, the quality of the jump instruction generated by compiling is improved, and the execution performance of the jump instruction on the virtual machine is optimized.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to an instruction installation method, an instruction installation apparatus, an electronic device, and a readable storage medium.
Background
A Virtual Machine (VM) is mainly virtualized into a computer by a software (or with a small amount of hardware support), and the virtualized computer usually supports a corresponding instruction set, which is called a Virtual Machine instruction set. The virtual Machine relies on a local physical Machine (Host Machine) through which execution engines simulate execution on the local Machine of a given sequence of virtual Machine instructions (object program).
The execution engine of the virtual machine may be implemented by an interpreter. Because the interpreter has the characteristics of high portability, low implementation cost, small memory occupation and the like, most of the execution engines of the virtual machines comprise the interpreter. The interpreter performs instruction fetching, instruction dispatching, operand fetching, and execution in units of one virtual machine instruction. However, the performance of the simple interpretation execution is low, so a dynamic compiling system is introduced into the virtual machine to improve the performance of the virtual machine.
The compiler is the core of the dynamic compilation system. The compiler compiles a set of continuous virtual machine instruction sequences (basic blocks, functions or methods) into a local CPU instruction sequence in its entirety, called a local method, and then directly executes the compiled local method by hardware. Since the compiler eliminates the processes of repeated instruction fetching and instruction dispatching, and simultaneously performs a large amount of effective optimization during compiling, the performance of the compiler is often more than 10 times that of the interpreter. The Compiler is also called Just-in-time Compiler (JIT) because it is dynamically compiled during the running of the program. Dynamic compilation is the key to determining the performance of a virtual machine.
Unlike the static compilation such as the traditional C/C + +, the dynamic compilation behavior occurs during the program running period, and additional compilation overhead is introduced. Studies have shown that the time distribution of program execution has a distinct local feature, i.e. the majority of the program execution time is concentrated on a small portion of code. In order to reduce the overhead generated by dynamic compilation as much as possible, dynamic compilation systems of modern virtual machines are usually designed and implemented according to the "selective compilation" theory. The core idea is as follows: only the frequently executed part (called hot spot) in the compiler program is compiled, and the uncompiled part is interpreted to be executed.
The method generates a corresponding local method after compiling. The local method will then be copied into a code buffer waiting to be executed. Code buffers are dedicated memory areas in a virtual machine for storing local methods. The process of copying the local method to the code buffer is also referred to as installation of the local method.
The applicant finds that, in the dynamic compiling process, the generation of the jump instruction is an important factor influencing the performance of the virtual machine. The jump instruction fully utilizing hardware support is a precondition for generating efficient jump instructions by compiling. In general, jump instructions directly supported by hardware can be classified into three categories:
first, PC relative jump (PC-relative branch), the general pattern of this type of instruction is: branch-opcode condition offset, which typically represents beq/bne instructions in the MIPS (Microprocessor with interlocked pipeline stages) architecture, and the jcc class of x86 instructions. Such instructions are characterized by a jump if and only if the condition is satisfied, and the target address of the jump is an offset relative to the current jump instruction (or the instruction next to the current jump instruction). For example, on a MIPS machine, beq s0, s1,32 indicates that a jump is made if and only if the values of register s0 and register s1 are equal, the target address of the jump being the next instruction address of the instruction plus an offset 32. The coding ranges of the offsets offset of the relative jumps of the PCs with different architectures are different greatly. For example, x86 machines support offset encoding of three lengths of 8 bits, 16 bits, and 32 bits, whereas MIPS supports only an offset encoding length of 16 bits. The shorter the encoding length of Offset, the narrower the range of PC to jump, and the smaller the usable range of the instruction.
Because the PC relative jump instruction directly supports condition judgment and has higher execution efficiency, the compiler preferentially considers the condition jump semantics of the program realized by the PC relative jump instruction on the premise that the jump range can be reached. When the jump range is not reachable, the compiler can also adopt other types of instruction equivalents to realize conditional jump semantics, but the execution cost is generally higher.
Second, a PC-region branch (PC-region branch), the general pattern of this type of instruction is: branch-opcode position-in-region, the most classical representation of this class of instructions is the j instruction of the MIPS architecture. The characteristic of this instruction is that the jump is unconditional, but the high-k bits of the instruction address of the jump instruction and the target address of the jump must be the same.
The PC region jump instruction is high in execution efficiency because branch prediction is not needed. However, the instruction is limited by the address space, and the instruction is currently only applicable to a few scenarios in which the instruction address space is fixed (such as kernel and boot program). Almost all user mode programs have unfixed instruction address space, so that the compiler is difficult to generate the instructions, and the instructions are not supported in mainstream compiler products such as gcc.
Third, PC absolute jump, the general pattern of this type of instruction is: a jump-opcode target, which typically represents jr/jalr instructions for MIPS architecture and jmp class instructions for x 86. Such instruction jumps are also unconditional and can jump to any target address. Such instructions may be further subdivided into jump to immediate target addresses, and jump to register target addresses. The jump to the target address of the register has high universality and flexibility and is most widely applied. But because of the difficulty of such instruction branch prediction, its execution overhead is typically greater than PC relative jumps and PC region jumps. Therefore, if possible, the mainstream compiler avoids generating such instructions as much as possible.
In summary, the compiler generates the PC relative jump instruction first, followed by the PC absolute jump. Due to the limitation of a jump address space, a compiler is very difficult to generate PC area jump instructions, and the instructions are not supported in a product-level compiler until now. However, because the execution efficiency of the jump instruction in the PC area is high, the lack of compiler support causes the hardware performance not to be fully utilized, thereby affecting the performance of the jump instruction.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide an instruction installation method, an instruction installation device, an electronic device, and a readable storage medium, so as to solve the problem that a region jump instruction cannot be automatically compiled due to the limitation of a jump-limited address space.
In order to solve the above problem, the present invention provides an instruction installation method, including:
allocating at least one fixed area from a memory address space as a buffer according to a comparison result of the maximum value of the fixed area of the processor and the size of the buffer for storing the local instruction sequence in the virtual machine;
compiling a target jump instruction in a virtual machine instruction sequence into a region jump instruction in a local instruction sequence;
and installing the local instruction sequence into a target fixed area of the buffer area, so that the jump instruction address and the jump target address of the area jump instruction are positioned in the same fixed area.
Optionally, the allocating at least one fixed region from the memory address space as a buffer according to a comparison result between a maximum value of the fixed region of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence includes:
and if the size of the buffer area does not exceed the maximum value of the fixed area, randomly selecting an available fixed area from the memory address space as the buffer area.
Optionally, the allocating at least one fixed region from the memory address space as a buffer according to a comparison result between a maximum value of the fixed region of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence includes:
and if the size of the buffer area exceeds the maximum value of the fixed area, selecting a plurality of continuous fixed areas from the memory address space as the buffer area.
Optionally, the target jump instruction includes an inter-sequence jump instruction, and the compiling the target jump instruction in the virtual machine instruction sequence into a region jump instruction in the native instruction sequence includes:
judging whether a jump instruction address and a jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area or not;
and if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area, compiling the inter-sequence jump instruction into an area jump instruction.
Optionally, the buffer includes a plurality of fixed regions, and the installing the native instruction sequence into a target fixed region of the buffer such that a jump instruction address and a jump target address of the region jump instruction are located in the same fixed region includes:
selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the occupied space of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction;
installing the native instruction sequence into a target fixed region of the buffer.
Optionally, the method further comprises:
and if the target fixed area with enough space for storing the local instruction sequence cannot be selected from the plurality of fixed areas of the buffer area, informing the virtual machine to close the dynamic compilation.
Correspondingly, the invention also provides an instruction installation device, which comprises:
the buffer area distribution module is used for distributing at least one fixed area from the memory address space as a buffer area according to the comparison result of the maximum value of the fixed area of the processor and the size of the buffer area for storing the local instruction sequence in the virtual machine;
the instruction compiling module is used for compiling the target jump instruction in the virtual machine instruction sequence into the region jump instruction in the local instruction sequence;
and the sequence installation module is used for installing the local instruction sequence into a target fixed area of the buffer area, so that the jump instruction address and the jump target address of the area jump instruction are positioned in the same fixed area.
Optionally, the buffer allocation module includes:
and the first selection submodule is used for selecting an available fixed area from the memory address space as the buffer area if the size of the buffer area does not exceed the maximum value of the fixed area.
Optionally, the buffer allocation module includes:
and the second selection submodule is used for selecting a plurality of continuous fixed areas from the memory address space as the buffer area if the size of the buffer area exceeds the maximum value of the fixed area.
Optionally, the target jump instruction includes an inter-sequence jump instruction, and the instruction compiling module includes:
the judging submodule is used for judging whether the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being positioned in the same fixed area or not;
and the compiling submodule is used for compiling the inter-sequence jump instruction into a region jump instruction if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed region.
Optionally, the buffer includes a plurality of fixed regions, and the sequence installation module includes:
the area selection submodule is used for selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the space occupation size of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction;
and the installation submodule is used for installing the local instruction sequence into a target fixed area of the buffer area.
Optionally, the apparatus further comprises:
and the notification module is used for notifying the virtual machine to close the dynamic compilation if a target fixed area with enough space for storing the local instruction sequence cannot be selected from the plurality of fixed areas of the buffer.
Accordingly, the present invention also provides an electronic device comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured for execution by the one or more processors, the one or more programs including instructions for:
allocating at least one fixed area from a memory address space as a buffer according to a comparison result of the maximum value of the fixed area of the processor and the size of the buffer for storing the local instruction sequence in the virtual machine;
compiling a target jump instruction in a virtual machine instruction sequence into a region jump instruction in a local instruction sequence;
and installing the local instruction sequence into a target fixed area of the buffer area, so that the jump instruction address and the jump target address of the area jump instruction are positioned in the same fixed area.
Optionally, the allocating at least one fixed region from the memory address space as a buffer according to a comparison result between a maximum value of the fixed region of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence includes:
and if the size of the buffer area does not exceed the maximum value of the fixed area, randomly selecting an available fixed area from the memory address space as the buffer area.
Optionally, the allocating at least one fixed region from the memory address space as a buffer according to a comparison result between a maximum value of the fixed region of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence includes:
and if the size of the buffer area exceeds the maximum value of the fixed area, selecting a plurality of continuous fixed areas from the memory address space as the buffer area.
Optionally, the target jump instruction includes an inter-sequence jump instruction, and the compiling the target jump instruction in the virtual machine instruction sequence into a region jump instruction in the native instruction sequence includes:
judging whether a jump instruction address and a jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area or not;
and if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area, compiling the inter-sequence jump instruction into an area jump instruction.
Optionally, the buffer includes a plurality of fixed regions, and the installing the native instruction sequence into a target fixed region of the buffer such that a jump instruction address and a jump target address of the region jump instruction are located in the same fixed region includes:
selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the occupied space of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction;
installing the native instruction sequence into a target fixed region of the buffer.
Optionally, the method further comprises:
and if the target fixed area with enough space for storing the local instruction sequence cannot be selected from the plurality of fixed areas of the buffer area, informing the virtual machine to close the dynamic compilation.
Accordingly, the present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by a processor of the electronic device, the electronic device can execute the instruction installation method.
According to the embodiment of the invention, at least one fixed area is allocated from a memory address space as a buffer area according to the comparison result of the maximum value of the fixed area of a processor and the size of the buffer area for storing the local instruction sequence in the virtual machine, the target jump instruction in the virtual machine instruction sequence is compiled into the area jump instruction in the local instruction sequence, the local instruction sequence is installed in the target fixed area of the buffer area, the allocation of the buffer area is controlled by taking the fixed area as a unit, the compilation and the installation of the local instruction sequence can be controlled, the jump instruction address and the jump target address of the area jump instruction are ensured to be positioned in the same fixed area, the safety risk brought by the area jump instruction is avoided, the area jump instruction is automatically compiled and generated, and the quality of the jump instruction generated by compiling is improved, the execution performance of the jump instruction on the virtual machine is optimized.
Drawings
FIG. 1 is a flow chart illustrating steps of a method for installing instructions according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating steps of a method for installing instructions according to a second embodiment of the present invention;
FIG. 3 is a block diagram showing an embodiment of an instruction installation apparatus according to a third embodiment of the present invention;
FIG. 4 illustrates a block diagram of an electronic device for instruction installation, according to an example embodiment.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, a flowchart illustrating steps of an instruction installation method according to a first embodiment of the present invention may specifically include the following steps:
In the embodiment of the present invention, an instruction sequence executed on a virtual machine is denoted as a virtual machine instruction sequence, and the virtual machine instruction sequence is compiled into an instruction sequence executable by a processor on a physical machine and denoted as a local instruction sequence. After the virtual machine dynamically compiles the virtual machine instruction sequence into the native instruction sequence, the native instruction sequence is copied into the buffer to wait for execution. Generally, the buffer for storing the native instruction sequence is obtained by randomly allocating a memory address space when the virtual machine is started, and it is difficult to ensure that the instruction address of the jump instruction and the high-k bit of the jump target address are the same, so that the allocation mode of the buffer needs to be controlled.
A series of consecutive instruction address spaces, and the high k bits that satisfy all instruction addresses within the region are the same, are referred to as a fixed region. The value of k subtracted from the total length of the instruction address is the encodable length of the fixed area, and the larger the encodable length is, the larger the theoretical spatial maximum of the fixed area is. The specific value of k is determined by the specific implementation of the architecture of the corresponding processor. For example, a MIPS 64-bit architecture k-36 can encode a length of 28 bits with a fixed area maximum of 256M. On the 32-bit architecture of MIPS, k is 4, the encodable length is 28 bits, and the fixed-area maximum is 256M. That is, the fixed-area maximum of the processor is determined in advance by hardware, and the size of the buffer required for the virtual machine to store the native instruction sequence is also determined in advance.
In the embodiment of the invention, when the virtual machine allocates the buffer, the control strategy of the buffer allocation is determined according to the comparison result of the size of the buffer required by the virtual machine for storing the local instruction sequence and the maximum value of the fixed area of the processor. The specific implementation includes various situations, for example, if the size of the buffer does not exceed the maximum value of the fixed area, an available fixed area may be arbitrarily selected from the memory address space as the buffer, or if the size of the buffer exceeds the maximum value of the fixed area, a plurality of fixed areas are selected from the memory address space as the buffer, or any other suitable allocation manner, which is not limited in this embodiment of the present invention.
It should be noted that the size of the buffer is not necessarily an integer multiple of the maximum value of the fixed area, and when one or more fixed areas are allocated from the memory address space, the size of the actual allocation may be determined according to the size of the buffer, for example, when the size of the buffer is 2.5 times of the maximum value of the fixed area, two complete fixed areas are allocated first, then a half of the third fixed area is allocated as a fixed area, and finally a buffer composed of three fixed areas is obtained, where the two fixed areas are the same size, and one fixed area is only a half of the complete fixed area.
And 102, compiling the target jump instruction in the virtual machine instruction sequence into a region jump instruction in the local instruction sequence.
In the embodiment of the invention, the jump instruction in the virtual machine instruction sequence usually generates a relative jump instruction firstly and then generates an absolute jump instruction, but under certain conditions, the relative jump instruction cannot be generated, and the execution overhead of the absolute jump instruction is usually larger than that of the relative jump instruction and the area jump instruction. Therefore, a target jump instruction in the virtual machine instruction sequence is compiled into a region jump instruction in the local instruction sequence, wherein the target jump instruction refers to all or part of the jump instructions in the virtual machine instruction sequence.
In the embodiment of the present invention, since the allocation of the buffer is controlled in units of the fixed area, more target jump instructions can be applied to generate the area jump instruction. The method comprises the steps that control strategies of jump instruction compiling are determined according to different buffer area allocations, if a buffer area only comprises a fixed area, jump in an instruction sequence and jump between the instruction sequences are both suitable for generating an area jump instruction, if the buffer area comprises a plurality of fixed areas, the jump in the instruction sequence is suitable for generating the area jump instruction, the jump between the instruction sequences needs to be additionally judged, and whether a jump instruction address and a jump target address corresponding to the jump instruction between the sequences have the condition of being located in the same fixed area or not is judged; and if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being positioned in the same fixed area, the inter-sequence jump instruction is suitable for generating the area jump instruction, otherwise, the inter-sequence jump instruction is not suitable for generating the area jump instruction.
In the embodiment of the present invention, since the native instruction sequence includes the local jump instruction, the native instruction sequence needs to be installed in the same fixed area of the buffer, that is, the target fixed area, and the jump instruction address and the jump target address of the local jump instruction are located in the same fixed area.
Specifically, the difference of the buffer allocation determines the control policy of instruction sequence installation, for example, if the buffer only includes a fixed area, the buffer only needs to have enough space for installing the local instruction sequence, and then the jump instruction address and the jump target address of the local jump instruction will be located in the fixed area, and the execution condition of the local jump instruction will not be satisfied, so the local instruction sequence can be freely installed on the premise that the local instruction sequence does not exceed the range of the buffer after installation. If the buffer contains a plurality of fixed areas, an available target fixed area needs to be selected, that is, a fixed area with enough space for installing the native instruction sequence is selected, and then the native instruction sequence is installed in the target fixed area. Any suitable installation manner may be used specifically, and the embodiment of the present invention is not limited thereto.
According to the embodiment of the invention, at least one fixed area is allocated from a memory address space as a buffer area according to the comparison result of the maximum value of the fixed area of a processor and the size of the buffer area for storing the local instruction sequence in the virtual machine, the target jump instruction in the virtual machine instruction sequence is compiled into the area jump instruction in the local instruction sequence, the local instruction sequence is installed in the target fixed area of the buffer area, the allocation of the buffer area is controlled by taking the fixed area as a unit, the compilation and the installation of the local instruction sequence can be controlled, the jump instruction address and the jump target address of the area jump instruction are ensured to be positioned in the same fixed area, the safety risk brought by the area jump instruction is avoided, the area jump instruction is automatically compiled and generated, and the quality of the jump instruction generated by compiling is improved, the execution performance of the jump instruction on the virtual machine is optimized.
Referring to fig. 2, a flowchart illustrating steps of an instruction installation method according to a second embodiment of the present invention is shown, which may specifically include the following steps:
In this embodiment of the present invention, optionally, according to a comparison result between a maximum value of the fixed area of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence, an implementation manner of allocating at least one fixed area from the memory address space as the buffer may include: and if the size of the buffer area does not exceed the maximum value of the fixed area, randomly selecting an available fixed area from the memory address space as the buffer area.
For example, the maximum value of a fixed region supported by an MIPS-compatible processor is X, the size of a buffer region required by the actual operation of a Java virtual machine is usually Y, and since the size of the buffer region is smaller than the maximum value of the fixed region, the buffer region is allocated within the initial X memory address space range, all the buffer regions are located in the same fixed region, and any region jump instruction in the buffer region can jump to any position in the buffer region.
In this embodiment of the present invention, optionally, according to a comparison result between a maximum value of the fixed area of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence, another implementation manner for allocating at least one fixed area from the memory address space as the buffer may include: and if the size of the buffer area exceeds the maximum value of the fixed area, selecting a plurality of continuous fixed areas from the memory address space as the buffer area.
The plurality of fixed areas are selected as the buffer area, and preferably, a plurality of continuous fixed areas, namely adjacent fixed areas, are selected, so that the locality of the program can be better, and the execution efficiency is further improved.
In the embodiment of the present invention, the target jump instruction includes an inter-sequence jump instruction, and in order to avoid a situation that a jump instruction address and a jump target address cannot be located in the same fixed area in the inter-sequence jump instruction, in the compiling process, it is determined whether a jump instruction address and a jump target address corresponding to the inter-sequence jump instruction have a condition located in the same fixed area, for example, a difference between the jump instruction address and the jump target address is calculated, and if the difference is smaller than the size of the fixed area, the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have a condition located in the same fixed area, or any other suitable condition, which is not limited in this embodiment of the present invention.
In the embodiment of the invention, if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area, namely the inter-sequence jump instruction is screened and can be compiled into the area jump instruction, so that a part of the jump instructions which can not enable the jump instruction address and the jump target address to be located in the same fixed area can be removed in advance before installation, and the removed part of the jump instructions are generated into other types of jump instructions, thereby avoiding the trouble of recompilation caused by the fact that the installation can not be subsequently carried out, and reducing useless expenses caused by unnecessary compilation.
And 204, selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the occupied space of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction.
In the embodiment of the present invention, when the buffer includes a plurality of fixed areas, a target fixed area having a space enough to store the local instruction sequence is selected from the plurality of fixed areas of the buffer according to the occupied space of the local instruction sequence, the jump instruction address and the jump target address of the area jump instruction.
The selection of the target fixed area needs to satisfy two conditions simultaneously, namely that the available space in the target fixed area is larger than the occupied space of the local instruction sequence, and the jump instruction address and the jump target address of the area jump instruction can be located in the target fixed area simultaneously.
In practical application, in order to ensure that after a local instruction sequence is installed, especially for a local jump instruction compiled from an inter-sequence jump instruction, a jump instruction address and a jump target address of the local jump instruction are located in the same fixed area, it may be set that an available space in the fixed area exceeds N times of a space occupation size of the local instruction sequence, and then the available space is selected as the target fixed area, or any other suitable condition, which is not limited in this embodiment of the present invention.
In the embodiment of the present invention, if the target fixed area with enough space for storing the native instruction sequence cannot be selected from the plurality of fixed areas of the buffer, step 204 is not executed, and instead, the virtual machine is notified that the space of the buffer is insufficient, and the dynamic compiling function is turned off.
In the embodiment of the invention, the data are continuously installed in the target fixed area of the buffer area according to the sequence generated by the local instruction sequence until the space of the target fixed area is insufficient.
According to the embodiment of the invention, at least one fixed area is allocated from a memory address space as a buffer area according to the comparison result of the maximum value of the fixed area of a processor and the size of the buffer area for storing the local instruction sequence in the virtual machine, the target jump instruction in the virtual machine instruction sequence is compiled into the area jump instruction in the local instruction sequence, the local instruction sequence is installed in the target fixed area of the buffer area, the allocation of the buffer area is controlled by taking the fixed area as a unit, the compilation and the installation of the local instruction sequence can be controlled, the jump instruction address and the jump target address of the area jump instruction are ensured to be positioned in the same fixed area, the safety risk brought by the area jump instruction is avoided, the area jump instruction is automatically compiled and generated, and the quality of the jump instruction generated by compiling is improved, the execution performance of the jump instruction on the virtual machine is optimized.
Furthermore, by judging whether the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction are in the same fixed area or not, a part of jump instructions which cannot enable the jump instruction address and the jump target address to be in the same fixed area are removed in advance, the removed part of jump instructions are generated into other types of jump instructions, the trouble of recompilation caused by the fact that installation cannot be subsequently performed is avoided, and useless expenses caused by unnecessary compilation are reduced.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Referring to fig. 3, a block diagram of a structure of an embodiment of an instruction installation apparatus according to a third embodiment of the present invention is shown, and specifically, the instruction installation apparatus may include the following modules:
a buffer allocation module 301, configured to allocate at least one fixed region from a memory address space as a buffer according to a comparison result between a maximum value of the fixed region of the processor and a size of a buffer in the virtual machine, where the buffer stores a local instruction sequence;
an instruction compiling module 302, configured to compile a target jump instruction in a virtual machine instruction sequence into a region jump instruction in a local instruction sequence;
a sequence installing module 303, configured to install the local instruction sequence into a target fixed area of the buffer, so that a jump instruction address and a jump target address of the area jump instruction are located in the same fixed area.
In this embodiment of the present invention, optionally, the buffer allocation module includes:
and the first selection submodule is used for selecting an available fixed area from the memory address space as the buffer area if the size of the buffer area does not exceed the maximum value of the fixed area.
In this embodiment of the present invention, optionally, the buffer allocation module includes:
and the second selection submodule is used for selecting a plurality of continuous fixed areas from the memory address space as the buffer area if the size of the buffer area exceeds the maximum value of the fixed area.
In this embodiment of the present invention, optionally, the target jump instruction includes an inter-sequence jump instruction, and the instruction compiling module includes:
the judging submodule is used for judging whether the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being positioned in the same fixed area or not;
and the compiling submodule is used for compiling the inter-sequence jump instruction into a region jump instruction if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed region.
In this embodiment of the present invention, optionally, the buffer area includes a plurality of fixed areas, and the sequence installation module includes:
the area selection submodule is used for selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the space occupation size of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction;
and the installation submodule is used for installing the local instruction sequence into a target fixed area of the buffer area.
In this embodiment of the present invention, optionally, the apparatus further includes:
and the notification module is used for notifying the virtual machine to close the dynamic compilation if a target fixed area with enough space for storing the local instruction sequence cannot be selected from the plurality of fixed areas of the buffer.
According to the embodiment of the invention, at least one fixed area is allocated from a memory address space as a buffer area according to the comparison result of the maximum value of the fixed area of a processor and the size of the buffer area for storing the local instruction sequence in the virtual machine, the target jump instruction in the virtual machine instruction sequence is compiled into the area jump instruction in the local instruction sequence, the local instruction sequence is installed in the target fixed area of the buffer area, the allocation of the buffer area is controlled by taking the fixed area as a unit, the compilation and the installation of the local instruction sequence can be controlled, the jump instruction address and the jump target address of the area jump instruction are ensured to be positioned in the same fixed area, the safety risk brought by the area jump instruction is avoided, the area jump instruction is automatically compiled and generated, and the quality of the jump instruction generated by compiling is improved, the execution performance of the jump instruction on the virtual machine is optimized.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
Fig. 4 is a block diagram illustrating a structure of an electronic device 700 for instruction installation according to an example embodiment. For example, the electronic device 700 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, an exercise device, a personal digital assistant, and the like.
Referring to fig. 4, electronic device 700 may include one or more of the following components: a processing component 702, a memory 704, a power component 706, a multimedia component 708, an audio component 710, an input/output (I/O) interface 712, a sensor component 714, and a communication component 716.
The processing component 702 generally controls overall operation of the electronic device 700, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing element 702 may include one or more processors 720 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 702 may include one or more modules that facilitate interaction between the processing component 702 and other components. For example, the processing component 702 can include a multimedia module to facilitate interaction between the multimedia component 708 and the processing component 702.
The memory 704 is configured to store various types of data to support operation at the device 700. Examples of such data include instructions for any application or method operating on the electronic device 700, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 704 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The power component 704 provides power to the various components of the electronic device 700. Power components 704 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for electronic device 700.
The multimedia component 708 includes a screen that provides an output interface between the electronic device 700 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the electronic device 700 is in an operation mode, such as a photographing mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 710 is configured to output and/or input audio signals. For example, the audio component 710 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 700 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal may further be stored in the memory 704 or transmitted via the communication component 716. In some embodiments, audio component 710 also includes a speaker for outputting audio signals.
The I/O interface 712 provides an interface between the processing component 702 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor assembly 714 includes one or more sensors for providing various aspects of status assessment for the electronic device 700. For example, the sensor assembly 714 may detect an open/closed state of the device 700, the relative positioning of components, such as a display and keypad of the electronic device 700, the sensor assembly 714 may also detect a change in the position of the electronic device 700 or a component of the electronic device 700, the presence or absence of user contact with the electronic device 700, orientation or acceleration/deceleration of the electronic device 700, and a change in the temperature of the electronic device 700. The sensor assembly 714 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 716 is configured to facilitate wired or wireless communication between the electronic device 700 and other devices. The electronic device 700 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 714 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 714 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 700 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described methods.
In an exemplary embodiment, a non-transitory computer readable storage medium comprising instructions, such as the memory 704 comprising instructions, executable by the processor 720 of the electronic device 700 to perform the above-described method is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
A non-transitory computer readable storage medium in which instructions, when executed by a processor of a terminal, enable the terminal to perform a method of instruction installation, the method comprising:
allocating at least one fixed area from a memory address space as a buffer according to a comparison result of the maximum value of the fixed area of the processor and the size of the buffer for storing the local instruction sequence in the virtual machine;
compiling a target jump instruction in a virtual machine instruction sequence into a region jump instruction in a local instruction sequence;
and installing the local instruction sequence into a target fixed area of the buffer area, so that the jump instruction address and the jump target address of the area jump instruction are positioned in the same fixed area.
Optionally, the allocating at least one fixed region from the memory address space as a buffer according to a comparison result between a maximum value of the fixed region of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence includes:
and if the size of the buffer area does not exceed the maximum value of the fixed area, randomly selecting an available fixed area from the memory address space as the buffer area.
Optionally, the allocating at least one fixed region from the memory address space as a buffer according to a comparison result between a maximum value of the fixed region of the processor and a size of a buffer in the virtual machine for storing the native instruction sequence includes:
and if the size of the buffer area exceeds the maximum value of the fixed area, selecting a plurality of continuous fixed areas from the memory address space as the buffer area.
Optionally, the target jump instruction includes an inter-sequence jump instruction, and the compiling the target jump instruction in the virtual machine instruction sequence into a region jump instruction in the native instruction sequence includes:
judging whether a jump instruction address and a jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area or not;
and if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area, compiling the inter-sequence jump instruction into an area jump instruction.
Optionally, the buffer includes a plurality of fixed regions, and the installing the native instruction sequence into a target fixed region of the buffer such that a jump instruction address and a jump target address of the region jump instruction are located in the same fixed region includes:
selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the occupied space of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction;
installing the native instruction sequence into a target fixed region of the buffer.
Optionally, the method further comprises:
and if the target fixed area with enough space for storing the local instruction sequence cannot be selected from the plurality of fixed areas of the buffer area, informing the virtual machine to close the dynamic compilation.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The instruction installation method and the instruction installation device provided by the invention are described in detail, specific examples are applied in the description to explain the principle and the implementation mode of the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (14)
1. An instruction installation method, comprising:
allocating at least one fixed area from a memory address space as a buffer according to a comparison result of the maximum value of the fixed area of the processor and the size of the buffer for storing the local instruction sequence in the virtual machine;
compiling a target jump instruction in a virtual machine instruction sequence into a region jump instruction in a local instruction sequence;
and installing the local instruction sequence into a target fixed area of the buffer area, so that the jump instruction address and the jump target address of the area jump instruction are positioned in the same fixed area.
2. The method of claim 1, wherein allocating at least one fixed region from the memory address space as a buffer based on a comparison of a maximum fixed region of the processor and a size of a buffer in the virtual machine in which native instruction sequences are stored comprises:
and if the size of the buffer area does not exceed the maximum value of the fixed area, randomly selecting an available fixed area from the memory address space as the buffer area.
3. The method of claim 1, wherein allocating at least one fixed region from the memory address space as a buffer based on a comparison of a maximum fixed region of the processor and a size of a buffer in the virtual machine in which native instruction sequences are stored comprises:
and if the size of the buffer area exceeds the maximum value of the fixed area, selecting a plurality of continuous fixed areas from the memory address space as the buffer area.
4. The method of claim 3, wherein the target jump instruction comprises an inter-sequence jump instruction, and wherein compiling the target jump instruction in the virtual machine instruction sequence into a region jump instruction in the native instruction sequence comprises:
judging whether a jump instruction address and a jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area or not;
and if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed area, compiling the inter-sequence jump instruction into an area jump instruction.
5. The method of any of claims 1-4, wherein the buffer includes a plurality of fixed regions, and wherein installing the native instruction sequence into a target fixed region of the buffer such that a jump instruction address and a jump target address of the local jump instruction are located within the same fixed region comprises:
selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the occupied space of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction;
installing the native instruction sequence into a target fixed region of the buffer.
6. The method of claim 5, further comprising:
and if the target fixed area with enough space for storing the local instruction sequence cannot be selected from the plurality of fixed areas of the buffer area, informing the virtual machine to close the dynamic compilation.
7. An instruction installation apparatus, comprising:
the buffer area distribution module is used for distributing at least one fixed area from the memory address space as a buffer area according to the comparison result of the maximum value of the fixed area of the processor and the size of the buffer area for storing the local instruction sequence in the virtual machine;
the instruction compiling module is used for compiling the target jump instruction in the virtual machine instruction sequence into the region jump instruction in the local instruction sequence;
and the sequence installation module is used for installing the local instruction sequence into a target fixed area of the buffer area, so that the jump instruction address and the jump target address of the area jump instruction are positioned in the same fixed area.
8. The apparatus of claim 7, wherein the buffer allocation module comprises:
and the first selection submodule is used for selecting an available fixed area from the memory address space as the buffer area if the size of the buffer area does not exceed the maximum value of the fixed area.
9. The apparatus of claim 7, wherein the buffer allocation module comprises:
and the second selection submodule is used for selecting a plurality of continuous fixed areas from the memory address space as the buffer area if the size of the buffer area exceeds the maximum value of the fixed area.
10. The apparatus of claim 9, wherein the target jump instruction comprises an inter-sequence jump instruction, and wherein the instruction compiling module comprises:
the judging submodule is used for judging whether the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being positioned in the same fixed area or not;
and the compiling submodule is used for compiling the inter-sequence jump instruction into a region jump instruction if the jump instruction address and the jump target address corresponding to the inter-sequence jump instruction have the condition of being located in the same fixed region.
11. The apparatus of any of claims 7-10, wherein the buffer comprises a plurality of fixed regions, and wherein the sequence installation module comprises:
the area selection submodule is used for selecting a target fixed area with enough space for storing the local instruction sequence from a plurality of fixed areas of the buffer area according to the space occupation size of the local instruction sequence and the jump instruction address and the jump target address of the area jump instruction;
and the installation submodule is used for installing the local instruction sequence into a target fixed area of the buffer area.
12. The apparatus of claim 11, further comprising:
and the notification module is used for notifying the virtual machine to close the dynamic compilation if a target fixed area with enough space for storing the local instruction sequence cannot be selected from the plurality of fixed areas of the buffer.
13. An electronic device comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors the one or more programs including instructions for:
allocating at least one fixed area from a memory address space as a buffer according to a comparison result of the maximum value of the fixed area of the processor and the size of the buffer for storing the local instruction sequence in the virtual machine;
compiling a target jump instruction in a virtual machine instruction sequence into a region jump instruction in a local instruction sequence;
and installing the local instruction sequence into a target fixed area of the buffer area, so that the jump instruction address and the jump target address of the area jump instruction are positioned in the same fixed area.
14. A readable storage medium, characterized in that the instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the instruction installation method according to one or more of the method claims 1-6.
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| US7747989B1 (en) * | 2002-08-12 | 2010-06-29 | Mips Technologies, Inc. | Virtual machine coprocessor facilitating dynamic compilation |
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