CN102385524B - Method for replacing compiling chain order based on mixed-compiling order set - Google Patents
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Abstract
The invention discloses a method for replacing a compiling chain order based on a mixed-compiling order set, which comprises the following steps: 1) designing more than one replacing order or a replacing order sequence with identical functions and different skip ranges and capable of enabling a processor program counter to overlook useless space according to a replaced order; 2) calculating address distance between the replaced order and a skip target, choosing a corresponding replacing order or a replacing order sequence according to a choice rule and replacing the replaced order, wherein the useless space refers to unused target document space generated after the replaced order is replaced, and the replaced order is a skip order or/and a branch order. The choice rule in step 2) is that the address distance between the replaced order and the skip target is within the skip range and time cost with order performance is the least. In an assembling process, when the address distance between the replaced order and the skip target in step 2) can not be calculated, a maximum space is reserved in the target document and relocation information A, B and C are generated for a linker. In a link process, the address distance is re-calculated, and the order is replaced according to the choice rule. The relocation information A is used for an assembler to analyze local symbols, the relocation information B is used for analyzing a target symbol by means of a constant in the link process, and the relocation information C is used for performing order replacement in the link process. The maximum space refers to the total amount of space occupied by an order or an order sequence with the largest skip range.
Description
Technical field
The present invention relates to variable-length instruction in assembler and linker and rely on the optimization method of the instruction of constant pool, relate in particular to the compiling chain instruction replacement method based on shuffling instruction set.
Background technology
Computer processor instruction, or be called for short machine instruction, be the basic input of processor work running.The set of all instructions of a processor is called instruction set, instruction length, can be divided into: elongated (taking X86-based as example), fixed length (as only having 32 bit instructions), shuffling (as 32 bit instructions and 16 bit instructions exist simultaneously).In addition, some instructions also depend on some data (as indirect jump instruction needs an address constant) in the time of operation, thereby in the time that processor is worked, complete the needed instruction length of function of this instruction, can think different from other instructions.In a set of instruction set, for some function, be always to have a series of different instructions or instruction sequence (packing of orders use), as for using any instruction or instruction sequence, main considering processor is carried out their speed, also to take into account in addition can performance objective file size.The user of computing machine, does not use machine instruction direct organization program conventionally, but uses higher level lanquage, under a few cases, can use assembly language.First most higher level lanquages are converted into assembly language by compiler, or this aspect of assembly language.Afterwards, no matter generated by compiler, or by computer user hand-coding, all generate final executable file by assembler and linker.
Assembly process is converted to a file destination a source file.Link process is combined as a new file destination multiple file destinations.Due to link process be in whole compilation process for the first time the different piece program combine, so be the best opportunity that whole program is optimized in instruction-level.But link process is very time-consuming, especially for a large-scale program.But for some reason, the speed of link process is difficult to improve always, under certain writes situation, becomes the bottleneck in compiling chain.Instruction length optimization and instruction essence of replacing this optimization of equal value is: one (or one group) completes the instruction of certain function (sequence), in the situation that some condition is satisfied, can replace with another one (or a group) and can complete the instruction of said function (sequence).After replacement, different as the case may be, can improve travelling speed, or reduce program volume.Whether above-mentioned " some condition " refers to, in the assembly phase, in all instructions, to only have sub-fraction, can calculate condition and set up, thereby whether can determine to need optimizes; But in most of situation, only have and while by the time link, just can obtain these conditions.
The algorithm of present instruction optimization is divided into the trial on two opportunitys.Be the stage of compilation Single document first opportunity.When the first stage is resolved assembly language text, in internal memory, preserve the information that may need the instruction changing by some data structures.Then, so text resolution is complete by the time, more repeatedly process those data of previously having preserved.In this processing procedure, algorithm can be optimized the instruction that only relates to this file as much as possible.The relevant information of a lot of unascertainable instructions, is kept in file destination as a reorientation item respectively.Be the stage of all file destinations of link second opportunity.Linker reads all reorientation items and all symbol tables, judge one by one: residing address when calculating the value of the symbol quoted of reorientation or this symbol as a label, thereby according to instruction Substitution Rules, determine whether can be optimized.In the time can optimizing, generally all can make the length of this original (or one group) instruction change, and then need to revise other all relocation information, i.e. algorithm complex O (n
2).Meanwhile, the increase and decrease of each instruction length, also needs file content below move or move forward after all, and its time loss is unthinkable.If intensive data together in the end only while thinking to link at every turn, that just needs a very complicated Data Structure and Algorithm go to preserve and safeguard the information that move these positions, but still has a lot of disk operating, and speed is still beyond affordability.Due to these problems, when being all chosen in link, the rear end code of a lot of linkers do not optimize.
The compiling link method of " program global optimization " or " increment type compiling ", has exceeded the scope of assembler linker.Because this method need to, in the time that the preliminary stage of compiling retains abundant information for link, could complete the optimization of optimizing instruction effectively, ensure higher link speed simultaneously.Use this scheme to need the front end (before assembly code) of Compile toolchain to make a series of changes (increasing some functions).Doing is like this to have changed another one software module, and workload is very big.So, in assembler and this scope of linker, wanting to improve compilation linking speed, just can not adopt in this way.
In traditional linker treatment scheme, optimization and relocation process are the separate stages.The former is using program segment content, data segment content, relocation table and the symbol table etc. of file destination as input, and the result of optimization is revised file destination exactly, and effect is that the former has reduced file destination volume, has reduced program runtime.The latter, calculates and processes the routine of reorientation item, is a necessary process of linker, is not optimized, and is only used to ensure the correctness of file destination.By analyzing, can sum up the following similarities and differences:
(1) input and output of these two functional modules are basic coincideing.
(2) calculation procedure of these two functional modules has a lot of similar parts, merges these two program circuits and can reduce the calculating of a lot of repetitions.
(3) complexity of the algorithm of relocatable program is O (n); Optimization algorithm, owing to need to revise other entries in the time changing present instruction length, needs O (n
2) algorithm of complexity.
(4) the optimization stage need to change mobile follow-up instruction sequence according to the space length of every instruction; Relocation phase only need to be changed relocation information item, does not need mobile a large amount of file destination contents.
Merge two processing modules, just there is no this step of subsequent instructions in moving target file, will produce a series of bad consequences, as: produced invalid " wasted space ", program correctness is difficult to ensure.
For general elongated or fixed length instruction set, assembler linker optimization meeting replaces with the instruction of certain length (sequence) instruction (sequence) of different length, thereby produces the file destination space not used, and can become " wasted space ".At this moment fill these untapped spaces by the instruction having no side effect (after execution not reprogramming operation result) of inserting length-specific.In an instruction set, can find much this " having no side effect " instructions, we can choose a wherein the fastest instruction of operation.An original instruction (sequence) is replaced with to another instruction (sequence) and the instruction that has no side effect, normally can accomplish what processor execution speed improved.But in this case, processor has additionally moved these unnecessary instructions in the time of operation, and these instructions are not need operation, so this scheme could not improve the travelling speed of program to greatest extent.
Summary of the invention
The present invention is just more to development amount in the optimization method of existing assembler linker, compilation linking is slow, the shortcomings such as program operation speed is slow, utilize the feature of shuffling instruction set, realize the function of optimization module is incorporated to relocation process module, development amount is few, and compiling link is fast, and program operation speed is fast.
In order to solve the problems of the technologies described above, technical scheme of the present invention is as follows:
A compiling chain instruction replacement method based on shuffling instruction set, comprises the steps:
1) for being replaced instruction, design at least more than one function identical, but there are different jump range and can allow processor program counter ignore replacement instruction or the replacement instruction sequence of wasted space;
2) be replaced the address distance between instruction and jump target described in calculating, select corresponding replacement instruction or replacement instruction sequence and be replaced instruction and replace described according to selective rule;
Described wasted space refers to the described file destination space not used producing after instruction is replaced that is replaced; It is described that to be replaced instruction be that jump instruction is or/and branch instruction; Described step 2) in the time cost minimum that selective rule is replaced address distance between instruction and jump target described in being within described jump range and and instruction is carried out.Work as the assembly phase, described step 2) in reserved maximum space for linker generates relocation information A, relocation information B, relocation information C in file destination when being replaced address between instruction and jump target distance and can not calculating, in the time of link, recalculate again described address apart from and carry out instruction replacement according to described selective rule; Described relocation information A resolves local symbol for assembler; When described relocation information B is used for linking, constant pool is resolved object symbol; Described relocation information C carries out instruction and replaces while being used for linking; Described maximum space refers to the instruction of jump range maximum or the spatial summation that instruction sequence takies.
As possibility, when described link, recalculate again described address distance and carry out the step of instruction replacement according to described selective rule as follows:
31) linker is gone through all over relocation information;
32) calculate and reset place value;
33) judge whether to need instruction to replace according to the place value that resets calculating;
34) replace as needs instruction, will reset place value as address distance, and carry out instruction replacement according to described selective rule;
35) modify target file;
Write operation when described modify target file refers to calculate the ending of reorientation functional module.
Beneficial effect of the present invention is:
(1) before link, in file destination, reserve suitable space, while making optimization, do not need a large amount of Mobile datas, greatly accelerated link speed.
(2) this algorithm has utilized the flow process of linker conventional processing reorientation, does not increase the time complexity of intrinsic flow process, makes the optimizing process of assembler linker compared with classic method, does not almost increase the time of compilation linking.
(3), after instruction (sequence) is replaced, can too much not cause effect of optimization not obvious because of inserting " instruction has no side effect ".
(4) this algorithm has utilized the flow process of linker conventional processing reorientation, and code is write easily, and workload is few.
Brief description of the drawings
The program circuit of the original linker relocation process of Fig. 1 and optimization;
The program circuit of optimization is carried out in the improved linker reorientation of Fig. 2 simultaneously;
The binary format of Fig. 3 BSR16 instruction;
The binary format of Fig. 4 BSR32 instruction;
The binary format of Fig. 5 JSRI16 instruction.
Embodiment
Below by the present invention is described further with specific embodiment with reference to the accompanying drawings.
Here taking one group of jump instruction that can realize said function as example, implementation method is described.One of them case study on implementation, include instruction design, Substitution Rules design, three parts of compilation linking program design.
One, instruction design
Suppose to have pseudoinstruction JBSR, form is that JBSR Label effect is to link and jump to subroutine, the return address of subroutine (PC of next instruction, i.e. current PC+2) are kept in link register R15, and program jump is carried out to Label place.
Corresponding this pseudoinstruction, needs processor to have following machine instruction:
The BSR instruction of (1) 16 bit length, relevant information is as follows:
BSR16---jump to subroutine instruction
Order format: as shown in Figure 3
Time cost: 1
Operation:
Link and jump to subroutine:
R15?←?PC?+?2
PC ← PC+sign_extend (offset << 1) (offset is moved to left after 1 and carries out sign extended)
Grammer: bsr16 label
Illustrate: subroutine redirect, the return address of subroutine (PC of next instruction, i.e. current PC+2) are kept in link register R15, program jump is carried out to label place.Label adds by present procedure PC 10 relative displacements of 1 of moving to left, and has the value after sign extended to 32 to obtain.The jump range of BSR16 instruction is ± 1KB address space.
(2) 32 is the BSR instruction of length, and relevant information is as follows:
BSR32---jump to subroutine instruction
Order format: as shown in Figure 4
Time cost: 1
Operation:
Link and jump to subroutine:
R15?←?PC+4
PC?←?PC?+?sign_extend(offset?<<?1)
Grammer: bsr label
Illustrate: subroutine redirect, the return address of subroutine (PC of next instruction, i.e. current PC+4) are kept in link register R15, program jump is carried out to label place.Label adds by present procedure PC 26 relative displacements of 1 of moving to left, and has the value after sign extended to 32 to obtain.The jump range of BSR instruction is ± 64MB address space.
The JSRI instruction of (3) 16, relevant information is as follows:
JSRI16---indirectly jump to subroutine instruction
Order format: as shown in Figure 5
Time cost: 3
Operation:
Program jumps to the subroutine position that storer is specified
R15?←?PC?+?2,PC?←?MEM[(PC?+?unsign_extend(offset?<<?2))?&?0xfffffffc]
Grammer: jsri16 label
Illustrate: the indirect redirect of subroutine, by the return address of the subroutine (PC of next instruction, be current PC+2) be kept in link register R15, program jumps to the position at label place and carries out, and label is loaded and is obtained by storer.Storage address adds according to PC 10 relative displacements of 2 of moving to left, and obtains without the value after sign extended to 32.The jump range of JSRI16 instruction is whole 4GB address spaces.
Two, replace selective rule design
(1) calculate the address distance between this jump instruction and jump target: if the value of this distance, within ± 1KB scope, is used bsr16 instruction; Otherwise, if within the scope of ± 64MB, use bsr32 instruction; Otherwise, if within 4GB scope, use jsri16 instruction; Otherwise, go beyond the scope, report an error.
(2) if jump target can not be calculated (as having quoted derivation symbol) in the assembly phase, need in file destination, reserve maximum space (spatial summation that the instruction of jump range maximum or instruction sequence take) in the assembly phase: 16 bit spaces of JSRI16 add the address of 32, totally 48 (referring to form and the function declaration of jsri16 instruction), and be linker generation relocation information.Linker utilizes this information, replaces with same selective rule.Specifically can be referring to compilation linking programming procedure.
(3) in the time of link, recalculate this scope, as long as can meet its address jump range, all less a kind of scheme of access time cost and space cost.
For example, for JBSR instruction, the situation of " jump target can not be calculated in the assembly phase " is more, now: need to expend the file destination storage space of 48 for every JBSR, storage space expends and is not a lot.And for most programs, jump range is less, when operation, can adopt BSR16 or BSR32, time cost 1.For rare occasion, will select JSRI16 instruction, time cost 3.Compared with all using in this case the method for JSRI16 instruction in the past, obtain obvious speed and promoted.
Three, compilation linking program design
In the design of assembler and linker, use following method can realize optimization of the present invention:
(1), in the assembly phase, for a JBSR instruction, if " the address distance between this jump instruction and jump target " just can be calculated in the assembly phase, assembler utilizes this relocation information A to calculate this distance, and writes file destination.Now, unless use JSRI16 instruction (need to generate relocation information B), otherwise need to before compilation finishes, destroy relocation information B and relocation information C.
(2), in the assembly phase, for a JBSR instruction, if " the address distance between this jump instruction and jump target " can not resolve, need to generate 3 kinds of dissimilar reorientation: relocation information A, relocation information B, relocation information C.Relocation information A is for assembler, and assembler utilizes this information, after file been scanned and the whole parsings of symbol, recalculates " address distance ".Relocation information B, for linker, is bound to a constant in constant pool, the memory address of the symbol (Label) for parsing to be replaced, and assembler, in compilation final stage, is kept at this relocation information in file destination, for linker.In this example, " memory address " that in JSRI16 instruction, use is just kept in constant pool, but because destination address can only just can be calculated in linker, generates this reorientation therefore be required to be linker; Relocation information C, for linker, is bound to the position at JBSR instruction place.In the assembly phase, be resolved to this reorientation and represent that assembler need to recalculate " the address distance between this jump instruction and jump target ", then according to replacing selective rule strategy, carries out corresponding instruction and replaces.
(3) for the relocation process module of linker, do not adopt the program circuit of Fig. 1 in prior art, adopt the program circuit of Fig. 2.When wherein using the flow process of Fig. 2 to write code, in circulating treatment procedure each time: the position of optimization correlative code, before should being placed on the code of this step of modify target file.Here " modify target file " refers to the write operation while calculating the ending of reorientation functional module.Place like this code, relocation process letter and structure thereof while having utilized conventional link, do not increase additional cycles, and only need to add few code, and the optimization of each statement is also separately independently.
(4) in calculation optimization strategy, what newly calculate resets the foundation of place value as instruction jump range, meeting in this scope, selects the instruction of Executing Cost minimum, recalculates coding, writes original position, deletes this reorientation item simultaneously.
(5) the unnecessary relocation information producing in the assembly phase can not made Exception handling, because they are very little to the increase of file destination volume.Easily the implication of the reorientation type of Design assistant makes them only effective to those unnecessary headspaces, makes the processing of this type of reorientation item can not have influence on correct coding as calculated.
The present invention is equally applicable to branch instruction.
The difference of branch instruction and jump instruction is that, in the time not meeting redirect condition, processor will continue to carry out next instruction of this instruction.
Illustrate the implementation of branch instruction below.(while introducing instruction, relevant term explanation please refer to explanation above, and order format, owing to being similar to jump instruction, is omitted at this)
One, instruction design
There is jbt pseudoinstruction, expression redirect when the value of operand is genuine below.So, in the alternative of this pseudoinstruction, will relate to as given an order:
(1) BT16---C is 1 branch instruction
Operation:
if(C?==?1)
PC?←?PC?+?sign_extend(offset?<<?1)
else
PC?←?PC?+?2
Grammer: bt16 label
Illustrate: if condition flag bit C equals 1, program jump is carried out to label place; Otherwise program is carried out next instruction, i.e. PC ← PC+2.Label adds by present procedure PC 10 relative displacements of 1 of moving to left, and has the value after sign extended to 32 to obtain.The transfer scope of BT16 instruction is ± 1KB address space.
(2) BT---C is 1 branch instruction
Operation:
if(C?==?1)
PC?←?PC?+?sign_extend(offset?<<?1)
else
PC?←?PC?+?4
Grammer: bt label
Illustrate: if condition flag bit C equals 1, program jump is carried out to label place; Otherwise program is carried out next instruction, i.e. PC ← PC+4.Label adds by present procedure PC 16 relative displacements of 1 of moving to left, and has the value after sign extended to 32 to obtain.The transfer scope of BT instruction is ± 64KB address space.
(3) BF16---C is 0 branch instruction
Operation:
if(C==0)
PC?←?PC?+?sign_extend(offset?<<?1)
else
PC?←?PC?+?2
Grammer: bf16 label
Illustrate: if condition flag bit C equals 0, program jump is carried out to label place; Otherwise program is carried out next instruction, i.e. PC ← PC+2.Label adds by present procedure PC 10 relative displacements of 1 of moving to left, and has the value after sign extended to 32 to obtain.The transfer scope of BT16 instruction is ± 1KB address space.
(4) JMPI---jump instruction indirectly
Operation: program jumps to the position that storer is specified
PC?←?MEM[(PC?+?unsign_extend(offset?<<?2))?&?0xfffffffc]
Grammer: jmpi label
Illustrate: program jumps to the position at label place, label is loaded and is obtained by storer.Storage address adds according to PC 16 relative displacements of two of moving to left, and without after sign extended to 32, then forces zero clearings to obtain through minimum two.The jump range of JMPI instruction is whole 4GB address spaces.
Two, Substitution Rules design
(1) calculate the address distance between this jump instruction and jump target: if the value of this distance, within ± 1KB scope, is used bt16 instruction; Otherwise, if within the scope of ± 64KB, use bt32 instruction; Otherwise, if within 4GB scope, using bf16, jmpi, fills in the blanks, and the sequence of constant is denoted as " scheme 3 ", otherwise, go beyond the scope, report an error.In scheme 3, the effect filling in the blanks comprises: if constant is kept at after jmpi in (constant pool), the destination address that constant is taken out in this instruction must be 4 multiple (reason is shown in the explanation of jmpi instruction); Adjust bt16 instruction apart from the distance between the Article 1 instruction after this instruction sequence, it is certain digital multiple and cannot redirect that bf16 instruction can not met because of the address of Article 1 instruction after sequence.
(2) if jump target can not be calculated (as having quoted derivation symbol) in the assembly phase, (the whole instruction sums of this sequence comprise bf16 need to need in file destination, to reserve maximum space 96 bytes in the assembly phase, jmpi, fill in the blanks, the sequence of constant) and be linker generation relocation information.Linker utilizes this information, replace and (need to generate 3 kinds of dissimilar reorientation: relocation information A, relocation information B, relocation information C with same selective rule, each relocation information is already described in compilation linking program design, is here no longer describing in detail).
(3) in the time of link, recalculate this scope, as long as can meet its address jump range, all less a kind of scheme of access time cost and space cost.
(4) for most programs, jump range is less, when operation, can adopt the instruction little, execution speed is fast that takes up room.Can obtain obvious speed promotes.
Three, compilation linking program design
With the processing mode of jump instruction be similar, here no longer describe in detail.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, without departing from the inventive concept of the premise; can also make some improvements and modifications, these improvements and modifications also should be considered as in protection domain of the present invention.
Claims (1)
1. the compiling chain instruction replacement method based on shuffling instruction set, is characterized in that, comprises the steps:
1) for being replaced instruction, design at least more than one function identical, but there are different jump range and can allow processor program counter ignore replacement instruction or the replacement instruction sequence of wasted space;
2) be replaced the address distance between instruction and jump target described in calculating, select corresponding replacement instruction or replacement instruction sequence and be replaced instruction and replace described according to selective rule;
Described wasted space refers to the described file destination space not used producing after instruction is replaced that is replaced; It is described that to be replaced instruction be that jump instruction is or/and branch instruction; Described step 2) in the time cost minimum that selective rule is replaced address distance between instruction and jump target described in being within described jump range and instruction is carried out; Work as the assembly phase, described step 2) in reserved maximum space for linker generates relocation information A, relocation information B, relocation information C in file destination when being replaced address between instruction and jump target distance and can not calculating, in the time of link, recalculate again described address apart from and carry out instruction replacement according to described selective rule; Described relocation information A resolves local symbol for assembler; When described relocation information B is used for linking, constant pool is resolved object symbol; Described relocation information C carries out instruction and replaces while being used for linking; Described maximum space refers to the instruction of jump range maximum or the spatial summation that instruction sequence takies.
2. a kind of compiling chain instruction replacement method based on shuffling instruction set according to claim 1, is characterized in that, described when link is recalculated described address distance and carry out the step of instruction replacement according to described selective rule as follows again:
31) linker is gone through all over relocation information;
32) calculate and reset place value;
33) judge whether to need instruction to replace according to the place value that resets calculating;
34) replace as needs instruction, will reset place value as address distance, and carry out instruction replacement according to described selective rule;
35) modify target file;
Write operation when described modify target file refers to calculate the ending of reorientation functional module.
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| CN104216754B (en) * | 2014-09-23 | 2017-05-17 | 天津国芯科技有限公司 | Compiling method and compiler for generating assembly codes for fast outstacks |
| CN106155660B (en) * | 2015-04-14 | 2019-06-25 | 龙芯中科技术有限公司 | Random test program generation method and device |
| GB2540206B (en) * | 2015-07-10 | 2018-02-07 | Advanced Risc Mach Ltd | Apparatus and method for executing instruction using range information associated with a pointer |
| CN107526621B (en) * | 2017-08-07 | 2020-09-04 | 深圳芯邦科技股份有限公司 | External memory master control code compiling method and device |
| CN109918074B (en) * | 2017-12-08 | 2022-09-27 | 中标软件有限公司 | Compiling link optimization method |
| CN109918132B (en) * | 2019-03-26 | 2021-04-16 | 龙芯中科技术股份有限公司 | Instruction installation method and device, electronic equipment and storage medium |
| CN111309329B (en) * | 2020-01-19 | 2022-07-08 | 苏州浪潮智能科技有限公司 | Instruction address self-adaptive repositioning method and program compiling method |
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