CN107229413B

CN107229413B - Memory management method, memory control circuit unit and memory storage device

Info

Publication number: CN107229413B
Application number: CN201610167787.XA
Authority: CN
Inventors: 陈国荣
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2016-03-23
Filing date: 2016-03-23
Publication date: 2020-05-12
Anticipated expiration: 2036-03-23
Also published as: CN107229413A

Abstract

The invention provides a memory management method for a rewritable nonvolatile memory module, a memory control circuit unit and a memory storage device. The memory management method comprises the steps of using a first management mode to manage the rewritable nonvolatile memory module after the rewritable nonvolatile memory module is powered on; and if a shutdown command is received from the host system, managing the rewritable nonvolatile memory module by using a second management mode, wherein the second management mode is different from the first management mode, and the second management mode is to execute at least one mandatory processing program in a background. The invention can accelerate the starting speed of the system and further increase the working efficiency.

Description

Memory management method, memory control circuit unit and memory storage device

Technical Field

The present invention relates to a memory management method, and more particularly, to a memory management method, a memory control circuit unit and a memory storage device for a rewritable nonvolatile memory.

Background

Digital cameras, cellular phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for the electronic products. Therefore, the flash memory industry has become a relatively popular segment of the electronics industry in recent years. For example, an embedded multimedia Card (eMMC) widely used in mobile electronic devices is a storage device using a flash memory as a storage medium.

Generally, a flash memory of a flash memory device is divided into a plurality of physical units and the physical units are grouped into a data area (data area) and a spare area (spare area). The physical units classified as the data area store valid data written by the write command, and the physical units in the spare area are used to replace the physical units in the data area when the write command is executed. Specifically, when the flash memory storage device receives a write command from the host and writes a physical unit of the data area, the flash memory storage device extracts a physical unit from the spare area, writes valid old data and new data to be written in the physical unit to be written in the data area into the physical unit extracted from the spare area, associates the physical unit into which the new data has been written into the data area, and erases the physical unit of the original data area and associates the physical unit with the spare area. In order to enable the host to smoothly access the physical units storing data in an alternate manner, the flash memory device provides the host with a logical unit. That is, the flash memory device establishes a logical-to-physical mapping table (logical-to-logical mapping table) or a physical-to-logical mapping table (physical-to-logical mapping table), and records and updates the mapping relationship between the logical units and the physical units in the data area in the mapping table to reflect the replacement of the physical units, so that the host only needs to write in the provided logical units, and the flash memory device reads or writes data in the mapped physical units according to the logical-to-physical mapping table or the physical-to-logical mapping table.

However, as the design capacity and number of each physical unit increase with the progress of flash memory manufacturing, the size of the mapping table and the required update time increase accordingly. To overcome this problem, a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM) is currently provided as a cache Memory in the flash Memory device. In this architecture, the flash memory device temporarily stores the mapping table in the cache to improve the operation efficiency of the whole system.

Generally, if the storage device receives a shutdown (shut down) command from the host system, the storage device writes the mapping table or other system data/files for managing the storage device into the rewritable nonvolatile memory of the storage device. However, after the storage device receives the shutdown command, the storage device may need to process one or more write commands before the storage device is actually powered off. Therefore, the mapping table or the system data/file stored before cannot reflect the writing operation performed after the shutdown instruction, so that the mapping table and the system data/file stored before may be incorrect, and the storage device may enter the processing flow of abnormal power-off when the power is turned on next time, thereby increasing the time required for booting.

Disclosure of Invention

The invention provides a memory management method, a memory control circuit unit and a memory storage device for a rewritable nonvolatile memory module, which can accelerate the starting speed of a system and further increase the working efficiency.

An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module, which includes managing the rewritable non-volatile memory module using a first management mode after the rewritable non-volatile memory module is powered on; and if a shutdown command is received from the host system, managing the rewritable nonvolatile memory module by using a second management mode, wherein the second management mode is different from the first management mode, and the second management mode is to execute at least one mandatory processing program in a background.

In an embodiment of the invention, the at least one forcing handler includes forcing at least one first system data stored in a memory to be written into the rewritable non-volatile memory module if a clear instruction is received from the host system, wherein the clear instruction is used to instruct at least one user data temporarily stored in the memory to be written into the rewritable non-volatile memory module.

In an embodiment of the invention, the at least one first system data includes a mapping table.

In an embodiment of the invention, the step of managing the rewritable nonvolatile memory module using the first management mode includes not writing at least one first system data stored in a memory into the rewritable nonvolatile memory module if a clear command is received from the host system, where the clear command is used to instruct writing at least one user data temporarily stored in the memory into the rewritable nonvolatile memory module.

In an embodiment of the present invention, the at least one mandatory processing procedure includes adjusting a latency of executing at least one system instruction, wherein the at least one system instruction is used for instructing at least one system operation on the rewritable nonvolatile memory module in a background, and wherein the at least one system instruction is executed according to the latency.

In an embodiment of the present invention, the at least one system operation is a garbage collection operation.

In an embodiment of the invention, the step of adjusting the waiting time for executing the at least one system command includes adjusting the waiting time according to a time from when the host system receives the shutdown command to when the host system stops supplying power, so that the waiting time is greater than the time.

In an embodiment of the invention, the memory management method further includes writing at least one second system data to the rewritable nonvolatile memory module in response to the shutdown instruction.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device. The memory control circuit unit comprises a host interface, a memory interface and a memory management circuit. The host interface is electrically connected to the host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for managing the rewritable nonvolatile memory module by using a first management mode after the rewritable nonvolatile memory module is powered on. If a shutdown command is received from the host system, the memory management circuit is further configured to manage the rewritable non-volatile memory module using a second management mode, where the second management mode is different from the first management mode, and the second management mode is to execute at least one forced processing program in a background.

In an embodiment of the invention, the at least one forcing handler includes the memory management circuit forcing at least one first system data stored in the memory to be written into the rewritable non-volatile memory module if a clear instruction is received from the host system, wherein the clear instruction is used for instructing at least one user data temporarily stored in the memory to be written into the rewritable non-volatile memory module.

In an embodiment of the invention, in the operation of managing the rewritable nonvolatile memory module by using the first management mode, if a clear instruction is received from the host system, the memory management circuit does not write at least one first system data stored in a memory into the rewritable nonvolatile memory module, where the clear instruction is used to instruct at least one user data temporarily stored in the memory to be written into the rewritable nonvolatile memory module.

In an embodiment of the invention, the at least one enforcement handler includes the memory management circuit adjusting a latency of executing at least one system instruction, wherein the at least one system instruction is used for instructing at least one system operation on the rewritable non-volatile memory module in a background, and wherein the at least one system instruction is executed according to the latency.

In an embodiment of the invention, in the operation of the memory management circuit adjusting the waiting time for executing the at least one system command, the memory management circuit adjusts the waiting time according to a time from when the host system receives the shutdown command to when the host system stops supplying power, so that the waiting time is greater than the time.

In an embodiment of the invention, in response to the shutdown instruction, the memory management circuit writes at least one second system data into the rewritable nonvolatile memory module.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for managing the rewritable nonvolatile memory module by using a first management mode after the rewritable nonvolatile memory module is powered on. If a shutdown command is received from the host system, the memory control circuit unit is further configured to manage the rewritable nonvolatile memory module using a second management mode, where the second management mode is different from the first management mode, and the second management mode is to execute at least one forced processing program in a background.

In an embodiment of the invention, the at least one forcing processing program includes the memory control circuit unit forcing at least one first system data stored in the memory to be written into the rewritable non-volatile memory module if a clear instruction is received from the host system, wherein the clear instruction is used for instructing at least one user data temporarily stored in the memory to be written into the rewritable non-volatile memory module.

In an embodiment of the invention, in the operation of managing the rewritable nonvolatile memory module by using the first management mode, if a clear instruction is received from the host system, the memory control circuit unit does not write at least one first system data stored in a memory into the rewritable nonvolatile memory module, where the clear instruction is used to instruct at least one user data temporarily stored in the memory to be written into the rewritable nonvolatile memory module.

In an embodiment of the invention, the at least one enforcement handler includes the memory control circuit unit adjusting a latency of executing at least one system instruction, wherein the at least one system instruction is used for instructing at least one system operation on the rewritable nonvolatile memory module in a background, and the at least one system instruction is executed according to the latency.

In an embodiment of the invention, in the operation of adjusting the waiting time for executing the at least one system command by the memory control circuit unit, the memory control circuit unit adjusts the waiting time according to a time from when the host system receives the shutdown command to when the host system stops supplying power, so that the waiting time is greater than the time.

In an embodiment of the invention, in response to the shutdown instruction, the memory control circuit unit writes at least one second system data into the rewritable nonvolatile memory module.

Based on the above, the memory management method, the memory control circuit unit and the memory storage device for the rewritable nonvolatile memory module according to the exemplary embodiments of the present invention may manage the rewritable nonvolatile memory module using a special management mode corresponding to a shutdown instruction after receiving the shutdown instruction, so as to write the system data stored in the cache into the rewritable nonvolatile memory module in response to a flush instruction. Therefore, the processing procedure caused by incorrect system data when the system is started next time can be avoided, the system starting speed is accelerated, and the working efficiency is increased.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating memory control circuitry in accordance with an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating an apparatus for managing a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a diagram illustrating an apparatus for managing a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating a power-down operation of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 9 is a flowchart illustrating operation of a memory storage device in a power-down mode according to an exemplary embodiment of the present invention;

FIG. 10 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.

Reference numerals:

10: memory storage device

11: host system

110: system bus

111: processor with a memory having a plurality of memory cells

112: random access memory

113: read-only memory

114: data transmission interface

12: I/O device

20: main board

201: portable disc

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network adapter

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

211: mouse (Saggar)

30: memory storage device

31: host system

32: SD card

33: CF card

34: embedded storage device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

410(0) to 410 (N): physical erase unit

502: memory management circuit

504: host interface

506: memory interface

508: buffer memory

510: power management circuit

512: error checking and correcting circuit

602: data area

604: idle zone

606: system area

608: substitution zone

LBA (0), LBA (h): logic unit

T1, T2.1, T2.2, T2.3, T2.4, T3, T4: time of day

810: shutdown instruction

820. 821, 822, 823, 824: instructions

830: clear instruction

Step S901: the host system sends a shutdown command to the memory control circuit unit

Step S903: after receiving the shutdown instruction, the memory control circuit unit writes at least one piece of system data stored in the buffer memory into the rewritable nonvolatile memory module to respond to the shutdown instruction, and manages the rewritable nonvolatile memory module by using the second management mode.

Step S905: the memory control circuit unit receives at least one write command from the host system

Step S907: the memory control circuit unit writes user data into the rewritable nonvolatile memory module in response to the at least one write command

Step S908: the memory control circuit unit performs at least one corresponding system operation on the rewritable nonvolatile memory module according to at least one system instruction

Step S909: the host system sends a clear command to the memory control circuit unit

Step S911: the memory control circuit unit writes the user data stored in the buffer memory and the system data stored in the buffer memory into the rewritable nonvolatile memory module

Step S913: the memory control circuit unit may respond to the host system clear command being completed

Step S1001: managing the rewritable non-volatile memory module using a first management mode after powering up the rewritable non-volatile memory module

Step S1003: managing the rewritable non-volatile memory module using a second management mode if a shutdown command is received from a host system

Detailed Description

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another exemplary embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 can be electrically connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 can be, for example, a flash Drive 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) based on various wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and a mouse 211 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-chip package storage devices (eMCP) 342 to electrically connect the memory module directly to the embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the present exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-P Package) interface standard, the Multi-Media storage Card (Multi-Media) interface standard, the Multimedia storage Card (Multimedia storage Card, Embedded Multimedia Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each of the plurality of physical erase units has a plurality of physical program units, wherein the physical program units belonging to the same physical erase unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundant bit region is used for storing system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.

In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a multi-level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Single Level Cell (SLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 1 bit of data in one memory Cell), a Triple Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment.

Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504 and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations when the memory storage device 10 is in operation.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable nonvolatile memory module 406 (for example, a system area dedicated to storing system data in the memory module) by using a program code type. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the driver code segment to load the control command stored in the rewritable nonvolatile memory module 406 into the ram of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

The host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the present example embodiment, the host interface 504 is compatible with the eMMC standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the UFS standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the SATA standard, the CF standard, the IDE standard, or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The buffer memory 508 is, for example, a dynamic random access memory or a static random access memory or other memory module with faster access speed than the rewritable nonvolatile memory module 406.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.

FIG. 6 is a diagram illustrating an apparatus for managing a rewritable nonvolatile memory module according to a first exemplary embodiment.

It should be understood that the terms "select," "group," "partition," "associate," and the like are logical concepts when describing the operation of the rewritable non-volatile memory module 406. That is, the physical locations of the physical erase units of the rewritable nonvolatile memory module are not changed, but the physical erase units of the rewritable nonvolatile memory module are logically operated.

Referring to FIG. 6, the rewritable nonvolatile memory module 406 has a plurality of entity-erased cells 410(0) -410 (N), each of which has a plurality of entity-programmed cells. In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page or a physical fan (sector). If the physical programming units are physical pages, each physical programming unit generally includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region is used for storing system data (e.g., error correction codes or other data used by the system for management). On the other hand, the physically erased cell is the minimum unit of erase. That is, each physical erase cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block.

The memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410(0) -410 (N) of the rewritable nonvolatile memory module 406 into a data area 602, an idle area 604, a system area 606, and a replacement area 608.

The physical erase units logically belonging to the data area 602 and the idle area 604 are used to store data from the host system 11, and the physical erase units in the data area 602 and the idle area 604 can be mapped to a plurality of logical units of the host system 11 (e.g., the physical blocks of the data area 602 and the idle area 604 are mapped to the logical blocks of the host system 11). Specifically, the wear-leveling cells in the data area 602 are regarded as the wear-leveling cells storing data, and the wear-leveling cells in the idle area 604 are used to replace the wear-leveling cells in the data area 602. That is, it is assumed that the memory control circuit unit 404 (or the memory management circuit 502) receives a write command and data to be written corresponding to the write command from the host system 11. The write command indicates to store data to be written to at least one first logic unit. In response to the write command, the memory control circuit unit 404 (or the memory management circuit 502) stores the data to be written to at least one first physical erase unit of the rewritable nonvolatile memory module 406 mapped to at least one first logic unit. Alternatively, if the data area 602) does not have any physical erase unit mapped to the at least one first logic unit, the memory control circuit unit 404 (or the memory management circuit 502) selects at least one physical erase unit from the idle area 604 as the at least one first physical erase unit, and writes data into the selected at least one first physical erase unit to replace the physical erase unit of the data area 602.

The physical erase unit logically belonging to the system area 606 is used to record system data related to the rewritable nonvolatile memory module 406. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module 406, the number of memory dies to which the rewritable nonvolatile memory module 406 belongs, the number of physically erased units, the number of physically programmed units per physically erased unit, and so on.

The physically erased cells logically belonging to the replacement area 608 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 608 and the physically erased cells in the data area 602 are damaged, the memory control circuit unit 404 (or the memory management circuit 502) selects the normal physically erased cells from the replacement area 608 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 602, the idle area 604, the system area 606, and the replacement area 608 of the rewritable nonvolatile memory module 406 may vary according to different memory specifications. Moreover, it should be understood that during operation of the memory storage device 10, the grouping relationship of the physically erased cells associated with the data area 602, the idle area 604, the system area 606 and the replacement area 608 may dynamically change. For example, when the physically erased cells in the idle area 604 are damaged and replaced by the physically erased cells in the replacement area 608, the physically erased cells in the replacement area 608 are associated with the idle area 604. Alternatively, after selecting the physical erase unit from the idle area 604 to store the written data, the memory control circuit unit 404 (or the memory management circuit 502) associates the physical erase unit with the data area 602 and maps the logical unit corresponding to the written data to the physical erase unit.

FIG. 7 is a diagram illustrating an apparatus for managing a rewritable nonvolatile memory module according to a first exemplary embodiment. The following describes a management architecture of the device of the rewritable nonvolatile memory module with reference to fig. 6 and 7.

Referring to FIG. 7, it is assumed that the memory control circuit unit 404 (or the memory management circuit 502) has allocated the logic units LBA (0) -LBA (H) to map the physical erase units 410(0) -410 (F-1) of the data area 602, and the host system 11 accesses the data in the data area 602 through the logic units LBA (0) -LBA (H). Here, each of the logic units LBA (0) to LBA (h) may be composed of one or more logic addresses. For example, a logic cell may be a logic block (local), a logic page (local page), or a logic sector (local sector). A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasing units.

In the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) establishes a system data (e.g., mapping table) for managing the memory storage device 10, and stores the system data into the buffer memory for access. For example, the memory control circuit unit 404 (or the memory management circuit 502) establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record mapping relationships between logical units (e.g., logical blocks, logical pages, or logical sectors) and physical units (e.g., physical erase units, physical program units, physical sectors). In other words, the memory control circuit unit 404 (or the memory management circuit 502) can look up a physical unit mapped by a logical unit by the logical-to-physical address mapping table, and the memory control circuit unit 404 (or the memory management circuit 502) can look up a logical unit mapped by a physical unit by the physical-to-logical address mapping table. When the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a logical unit, the logical-to-physical address mapping table corresponding to the logical unit is loaded into the buffer memory to be updated. Similarly, the memory control circuit unit 404 also updates the physical-to-logical address mapping table accordingly.

In the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) can directly establish the mapping tables (e.g., the logical-to-physical address mapping table and the physical-to-logical address mapping table) in the buffer memory 508, or read the mapping tables from the rewritable nonvolatile memory module 406 and store the mapping tables in the buffer memory 508. As a result, the access speed of the buffer memory 508 is much higher than that of the rewritable nonvolatile memory module 406. Therefore, the efficiency of maintaining/updating/accessing the mapping table can be improved by storing the mapping table in the buffer memory 508. In another embodiment, the memory control circuit unit 404 (or the memory management circuit 502) may also store the mapping table in another suitable memory. In addition, in another embodiment, the memory control circuit unit 404 (or the memory management circuit 502) can also temporarily store other system data for managing the memory storage device 10 in the buffer memory 508, so as to improve the efficiency of maintaining/updating/accessing the system data stored in the buffer memory 508.

However, in general, data stored in the buffer memory 508 will disappear as the buffer memory 508 is powered down. Therefore, before the buffer 508 is powered off (e.g., the memory storage device 10 is powered off), the memory control circuit unit 404 (or the memory management circuit 502) writes the data stored in the buffer 508 (e.g., the user data from the host system 11 and the system data for managing the memory storage device 10) into the rewritable nonvolatile memory module 406. In this way, the system data stored in the rewritable nonvolatile memory module 406 can be loaded into the buffer memory 508 the next time the memory storage device 10 is powered on (e.g., when the memory storage device 10 is powered on). The memory management method related to the power-off operation of the memory storage device according to the present example embodiment will be described in detail with reference to fig. 8 and 9.

FIG. 8 is a diagram illustrating a power-down operation of a memory storage device according to an exemplary embodiment of the invention. FIG. 9 is a flowchart illustrating a power-down operation of a memory storage device according to an exemplary embodiment of the invention.

In the present exemplary embodiment, referring to fig. 8, for example, it is assumed that the memory control circuit unit 404 (or the memory management circuit 502) receives a shutdown command (shut down command)810, a command 821, a command 822, a command 823, a command 824 (also referred to as a command 820) and a clear command 830 from the host system according to the sequence of time T1, time T2.1, time T2.2, time T2.3, time T2.4 and time T3. It should be noted that the present invention is not limited to the number of instructions 820 received from the host system 11 after the shutdown instruction 810 is received. That is, the memory control circuitry 404 (or the memory management circuitry 502) may receive one or more instructions 820 from the host system after receiving the shutdown instruction 810. The time T4 is used to indicate the time point when the host system 11 stops supplying power to the memory storage device 10.

In the present exemplary embodiment, the shutdown instruction 810 is used to indicate that the memory storage device 10 can be powered off. For example, when the host system 11 performs a power-off operation or the host system 11 enters a specific power state (e.g., system hibernation, system sleep, etc.), the host system 11 will issue a power-off command 810 to the memory storage device 10. Thereafter, the host system 11 is ready to cut off power to the memory storage device 10.

As described above, data stored in the buffer memory 508 disappears as the buffer memory 508 is powered down. In the present exemplary embodiment, if the shutdown command 810 is received, the memory control circuit unit 404 (or the memory management circuit 502) writes the system data (also referred to as the second system data) stored in the buffer memory 508 into the rewritable nonvolatile memory module 406. It should be noted that the second system data stored in the rewritable nonvolatile memory module 406 in response to the shutdown command 810 includes the mapping tables (e.g., the logical-to-physical address mapping table and the physical-to-logical address mapping table) described above. However, the manufacturer may further store other suitable system data in the rewritable nonvolatile memory module 406 in response to the received shutdown command 810 according to the requirement.

In more detail, in the exemplary embodiment, if the shutdown command 810 is received from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) uses a special management mode (also called a second management mode) to manage the rewritable nonvolatile memory module 406. In contrast, after the host system 11 (or the external power supply) supplies power to the rewritable nonvolatile memory module 406 (or the memory storage device 10), the memory control circuit unit 404 (or the memory management circuit 502) manages the rewritable nonvolatile memory module 406 using a general management mode (also referred to as a first management mode) different from the special management mode. In other words, the memory control circuit unit 404 (or the memory management circuit 502) uses the first management mode to manage the rewritable nonvolatile memory module 406 in response to the power-on of the rewritable nonvolatile memory module 406 (or the memory storage device 10). The difference between the first management mode and the second management mode will be described below.

In the exemplary embodiment, the second management mode is different from the first management mode in that if the memory control circuit unit 404 (or the memory management circuit 502) manages the rewritable nonvolatile memory module 406 using a special management mode (also called the second management mode), the memory control circuit unit 404 (or the memory management circuit 502) executes at least one forced processing procedure in the background. In other words, the memory control circuit unit 404 (or the memory management circuit 502) does not execute the above-mentioned forced processing procedure corresponding to the second management mode during the period of using the first management mode to manage the rewritable non-volatile memory module 406.

For example, assume that after receiving the shutdown command 810, the memory control circuit unit 404 (or the memory management circuit 502) has used the second management mode to manage the rewritable nonvolatile memory module 406. In this case, if the memory control circuit unit 404 (or the memory management circuit 502) receives the clear command 830 from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) will "force" the system data (hereinafter, also referred to as the first system data) stored in the buffer memory 508 to be written into the rewritable nonvolatile memory module 406. It should be noted that, in the present exemplary embodiment, the flush command 830 is used to indicate that the data in the buffer memory 508 is to be flushed. Specifically, when the memory control circuit unit 404 (or the memory management circuit 502) receives the clear command 830 from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) writes the user data stored in the buffer memory 508 to the corresponding entity unit in the rewritable nonvolatile memory module 406, and updates the system data stored in the buffer memory 508 according to the written entity address (e.g., updates the logical-to-entity address mapping table or/and the physical-to-logical address mapping table).

That is, in the second management mode, if the memory control circuit unit 404 (or the memory management circuit 502) receives the clear command 830 from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) writes the (updated) first system data stored in the buffer memory 508 into the rewritable nonvolatile memory module 406 in addition to the user data and the updated system data (the first system data).

In contrast, in the first management mode, if the memory control circuit unit 404 (or the memory management circuit 502) receives the clear command 830 from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) writes the user data into the rewritable nonvolatile memory module 406 in response to the clear command, and updates the first system data stored in the buffer memory. However, the memory control circuit unit 404 (or the memory management circuit 502) does not write the (updated) first system data stored in the buffer memory 508 into the rewritable nonvolatile memory module 406.

More specifically, in the exemplary embodiment, if in the second management mode, after all the system data stored in the buffer 508 is updated in response to the clear command, the memory control circuit unit 404 (or the memory management circuit 502) writes the system data stored in the buffer 508 into the rewritable nonvolatile memory module 406. For example, the memory control circuit unit 404 (or the memory management circuit 502) writes all or specific (e.g., the first system data) system data into the physical erase units of the rewritable nonvolatile memory module 406 divided into the system area, or writes all or specific (e.g., the first system data) system data into a specific physical erase unit of the rewritable nonvolatile memory module 406, wherein the specific physical erase unit is a default physical erase unit for storing the system data.

It is noted that the first system data and the second system data may be mapping tables (e.g., updating logical to physical mapping tables or/and physical to logical mapping tables) as described above. However, the first system data is different from the second system data in that the second system data is system data stored in response to the shutdown instruction 810, and the first system data is system data stored in response to the clear instruction.

In the present exemplary embodiment, the instruction 820 is, for example, a write instruction, which is used to instruct to write user data into the memory storage device 10. The write command may include user data to be written and information indicating to store the user data (e.g., a logical address to store the user data).

However, in another example embodiment, the instructions 820 also include system instructions (e.g., garbage collection instructions) that are used to indicate in the background system operations on the rewritable non-volatile memory module 406. In other words, the instruction 820 can be further regarded as system instructions 821-824 executed on the rewritable nonvolatile memory module 406 at times T2.1-T2.4, respectively. In addition, the mapping relationship between the logical unit and the entity unit is changed due to the garbage collection operation performed on the rewritable nonvolatile memory module according to the garbage collection instruction. Therefore, the memory control circuit unit 404 (or the memory management circuit 502) will also update the mapping table or other corresponding system data temporarily stored in the buffer 508 according to the mapping relationship between the logical unit and the physical unit after the garbage collection operation is performed. In other words, in this alternative embodiment, the write command from the host system 11 or other system command from the memory control circuit unit 404 (or the memory management circuit 502) affects the mapping table stored in the buffer memory 508 or other system data corresponding to the system command. It should be noted that the number of the instructions 820 may be one or more, and the instructions 820 may include both the system instructions and the write instructions.

Further, in another example embodiment, assume that instruction 820 is a system instruction 820. The force handler is included in the second management mode, and the memory control circuitry 404 (or the memory management circuitry 502) adjusts the latency of executing the system instructions 820. In this further exemplary embodiment, the system instruction is executed according to the latency.

For example, assume that the system instruction is a garbage collection instruction that indicates to perform a garbage collection operation on the rewritable nonvolatile memory module 406 in the background. The memory control circuitry 404 (or the memory management circuitry 502) may execute the garbage collection instruction according to the latency of the corresponding garbage collection instruction. In more detail, the memory control circuit unit 404 (or the memory management circuit 502) executes the garbage collection instruction after the waiting time of the memory storage device 10 in the idle state (e.g., no operation) exceeds the waiting time.

For another example, in another exemplary embodiment, if the memory control circuit unit 404 (or the memory management circuit 502) determines to execute the garbage collection instruction, the memory control circuit unit 404 (or the memory management circuit 502) executes the garbage collection instruction after the waiting time elapses according to the current waiting time. It should be noted that the manufacturer may preset the length of the waiting time.

In addition, in the operation in which the memory control circuit unit 404 (or the memory management circuit 502) adjusts the waiting time for executing the system command 820, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the waiting time according to the time from the receiving of the shutdown command from the host system 11 to the stopping of the power supply of the host system 11, so that the waiting time is greater than the time.

In more detail, after receiving the power-off command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) identifies (or records) the time from the time point when the power-off command is received to the time point when the power supply of the host system 11 is actually stopped. And the memory control circuit unit 404 (or the memory management circuit 502) adjusts the waiting time according to the time. Specifically, the memory control circuit unit 404 (or the memory management circuit 502) adjusts the waiting time according to the time so that the waiting time is greater than the time (i.e., the time from the time point when the shutdown instruction is received to the time point when the power supply of the host system 11 is actually stopped). In this way, since the waiting time corresponding to the system command 820 is adjusted, the memory control circuit unit 404 (or the memory management circuit 502) will not execute the system command 820 during the period from the time the host system 11 receives the power-off command to the time the host system 11 actually stops supplying power. Thus, system data stored in cache 508 is not affected (updated) by the execution of system instructions 820. In other words, the system data (e.g., the second system data) stored in response to the received shutdown command 810 is not invalid (or expired) due to the system command 820 executed after the shutdown command 810, and the valid system data stored in the rewritable nonvolatile memory module 406 can be used next time the memory storage device 10 is powered on.

Referring to fig. 8 and fig. 9, for example, in operation S901, at time T1, the host system 11 sends a shutdown command 810 to the memory control circuit unit 404. In operation S903, after receiving the shutdown command 810, the memory control circuit unit 404 writes at least one system data (also referred to as a second system data) stored in the buffer memory 508 into the rewritable nonvolatile memory module 406 in response to the shutdown command 810, and manages the rewritable nonvolatile memory module 406 by using the second management mode.

Next, in operation S905, the memory control circuit unit 404 receives at least one write command (e.g., commands 821-824 corresponding to times T2.1-T2.4) from the host system 11. The write command 820 is used to instruct writing user data into the rewritable nonvolatile memory module 406. In operation S907, the memory control circuit unit 404 writes the user data corresponding to the at least one write command 820 into the rewritable nonvolatile memory module 406 in response to the at least one write command 820. In operation S908, the memory control circuit unit 404 performs at least one corresponding system operation on the rewritable nonvolatile memory module 406 according to at least one system instruction. It should be noted that the operations of step S905, step S907 and step S908 are optional, i.e. may not occur. In addition, the order of the operations of step S905, step S907, and step S908 may be interchanged with each other.

For example, the memory control circuit unit 404 first receives a write command from the host system 11 (step S905). Next, the memory control circuit unit 404 executes the system instruction (e.g., garbage collection instruction) (step S908), and after completing the system operation (e.g., garbage collection operation) corresponding to the system instruction, the memory control circuit unit 404 writes the user data corresponding to the write instruction into the rewritable nonvolatile memory module 406 (step S907). For another example, the memory control circuit unit 404 first performs operation S908, then performs operation S905, and then performs operation S907.

In operation S909, the host system 11 sends a clear command 830 to the memory control circuit unit 404. In operation S911, the memory control circuit unit 404 writes the user data stored in the buffer memory 508 and the system data stored in the buffer memory 508 into the rewritable nonvolatile memory module 406. After writing the user data and the system data into the rewritable nonvolatile memory module 406, in operation S913, the memory control circuit unit 404 may respond to the host system 11 that the clear command 830 is completed.

Referring to fig. 10, in step S1001, the memory control circuit unit 404 (or the memory management circuit 502) manages the rewritable nonvolatile memory module using a first management mode after supplying power to the rewritable nonvolatile memory module. In step S1003, if a shutdown command is received from the host system, the memory control circuit unit 404 (or the memory management circuit 502) uses the second management mode to manage the rewritable nonvolatile memory module.

In summary, the memory management method, the memory control circuit unit and the memory storage device for the rewritable nonvolatile memory module according to the exemplary embodiments of the present invention may manage the rewritable nonvolatile memory module using a special management mode corresponding to a shutdown instruction after receiving the shutdown instruction, so as to write the system data stored in the cache into the rewritable nonvolatile memory module in response to a flush instruction. Therefore, the processing procedure caused by incorrect system data when the system is started next time can be avoided, the system starting speed is accelerated, and the working efficiency is increased.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A memory management method for a rewritable nonvolatile memory module, the memory management method comprising:

managing the rewritable non-volatile memory module using a first management mode after the rewritable non-volatile memory module is powered on;

if a shutdown command is received from a host system, managing the rewritable nonvolatile memory module by using a second management mode, wherein the second management mode is different from the first management mode, and the second management mode is to execute at least one mandatory processing program in the background;

after receiving the shutdown command from the host system, receiving one or more write commands from the host system, and writing user data corresponding to the one or more write commands to the rewritable non-volatile memory module; and

after the user data is written to the rewritable non-volatile memory module, writing system data corresponding to the written user data in a memory to the rewritable non-volatile memory module.

2. The memory management method of claim 1, wherein the at least one enforcement handler comprises:

and if a clearing instruction is received from the host system, forcibly writing at least one first system data stored in a memory into the rewritable non-volatile memory module, wherein the clearing instruction is used for indicating that at least one user data temporarily stored in the memory is written into the rewritable non-volatile memory module.

3. The memory management method of claim 2, wherein the at least one first system data comprises a mapping table.

4. The memory management method of claim 1, wherein the step of managing the rewritable non-volatile memory module using the first management mode comprises:

and if a clearing instruction is received from the host system, not writing at least one first system data stored in a memory into the rewritable non-volatile memory module, wherein the clearing instruction is used for indicating that at least one user data temporarily stored in the memory is written into the rewritable non-volatile memory module.

5. The memory management method of claim 1, wherein the at least one enforcement handler comprises:

adjusting a latency of executing at least one system instruction, wherein the at least one system instruction is used for instructing at least one system operation on the rewritable non-volatile memory module in a background, and wherein the at least one system instruction is executed according to the latency.

6. The memory management method of claim 5, wherein the at least one system operation is a garbage collection operation.

7. The method of claim 5, wherein the step of adjusting a latency of executing at least one system instruction comprises:

and adjusting the waiting time according to the time from the receiving of the shutdown instruction from the host system to the stopping of the power supply of the host system, so that the waiting time is greater than the time.

8. The memory management method of claim 1, further comprising:

and writing at least one second system data into the rewritable nonvolatile memory module in response to the shutdown instruction.

9. A memory control circuit unit for controlling a memory storage device, the memory control circuit unit comprising:

a host interface electrically connected to a host system;

the memory interface is electrically connected to a rewritable nonvolatile memory module;

a memory management circuit electrically connected to the host interface and the memory interface, wherein the memory management circuit is configured to manage the rewritable non-volatile memory module using a first management mode after the rewritable non-volatile memory module is powered on,

wherein if a power-off command is received from the host system, the memory management circuit is further configured to manage the rewritable nonvolatile memory module using a second management mode, wherein the second management mode is different from the first management mode, and the second management mode is to execute at least one forced processing program in the background,

wherein after receiving the power-off command from the host system, the memory management circuit is further configured to receive one or more write commands from the host system and write user data corresponding to the one or more write commands to the rewritable non-volatile memory module,

after the user data is written into the rewritable nonvolatile memory module, the memory management circuit is further configured to write system data corresponding to the written user data in the memory into the rewritable nonvolatile memory module.

10. The memory control circuit unit of claim 9, wherein the at least one enforcement handler comprises:

if a clear command is received from the host system, the memory management circuit forces at least one first system data stored in a memory to be written into the rewritable nonvolatile memory module, wherein the clear command is used for indicating at least one user data temporarily stored in the memory to be written into the rewritable nonvolatile memory module.

11. The memory control circuit unit of claim 10, wherein the at least one first system data comprises a mapping table.

12. The memory control circuit unit of claim 9, wherein in the managing operation of the rewritable non-volatile memory module using the first management mode,

if a clear command is received from the host system, the memory management circuit does not write at least one first system data stored in a memory into the rewritable non-volatile memory module, wherein the clear command is used for indicating that at least one user data temporarily stored in the memory is written into the rewritable non-volatile memory module.

13. The memory control circuit unit of claim 9, wherein the at least one enforcement handler comprises:

the memory management circuit adjusts a latency time for executing at least one system instruction, wherein the at least one system instruction is used for instructing at least one system operation on the rewritable non-volatile memory module in a background, and the at least one system instruction is executed according to the latency time.

14. The memory control circuit unit of claim 13, wherein the at least one system operation is a garbage collection operation.

15. The memory control circuit unit of claim 13, wherein in the operation of the memory management circuit adjusting a latency of executing at least one system instruction,

the memory management circuit adjusts the waiting time according to a time from the receiving of a shutdown instruction from the host system to the stopping of the power supply of the host system, so that the waiting time is greater than the time.

16. The memory control circuit unit of claim 9, wherein in response to the shutdown command, the memory management circuit writes at least one second system data to the rewritable non-volatile memory module.

17. A memory storage device, comprising:

a connection interface unit for electrically connecting to a host system;

a rewritable nonvolatile memory module; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is used for managing the rewritable nonvolatile memory module by using a first management mode after the rewritable nonvolatile memory module is powered on,

wherein if a shutdown command is received from the host system, the memory control circuit unit is further configured to manage the rewritable nonvolatile memory module using a second management mode, wherein the second management mode is different from the first management mode, and the second management mode is to execute at least one forced processing program in the background,

wherein after receiving the shutdown command from the host system, the memory control circuit unit is further configured to receive one or more write commands from the host system and write user data corresponding to the one or more write commands to the rewritable non-volatile memory module,

after the user data is written into the rewritable nonvolatile memory module, the memory control circuit unit is further configured to write system data corresponding to the written user data in a memory into the rewritable nonvolatile memory module.

18. The memory storage device of claim 17, wherein the at least one enforcement process comprises:

if a clear command is received from the host system, the memory control circuit unit forcibly writes at least one first system data stored in a memory into the rewritable non-volatile memory module, wherein the clear command is used for indicating that at least one user data temporarily stored in the memory is written into the rewritable non-volatile memory module.

19. The memory storage device of claim 18, wherein the at least one first system data comprises a mapping table.

20. The memory storage device of claim 17, wherein in managing the operation of the rewritable non-volatile memory module using the first management mode,

if a clear command is received from the host system, the memory control circuit unit does not write at least one first system data stored in a memory into the rewritable non-volatile memory module, wherein the clear command is used for indicating that at least one user data temporarily stored in the memory is written into the rewritable non-volatile memory module.

21. The memory storage device of claim 17, wherein the at least one enforcement process comprises:

the memory control circuit unit adjusts a latency time for executing at least one system instruction, wherein the at least one system instruction is used for instructing to perform at least one system operation on the rewritable nonvolatile memory module in a background, and the at least one system instruction is executed according to the latency time.

22. The memory storage device of claim 21, wherein the at least one system operation is a garbage collection operation.

23. The memory storage device of claim 21, wherein in the operation of the memory control circuit unit adjusting a latency of executing at least one system instruction,

the memory control circuit unit adjusts the waiting time according to a time from the receiving of a shutdown instruction from the host system to the stopping of the power supply of the host system, so that the waiting time is greater than the time.

24. The memory storage device of claim 17, wherein in response to the shutdown command, the memory control circuit unit writes at least one second system data to the rewritable non-volatile memory module.