CN106951289B - Online upgrading method, DSP controller and upgrading system - Google Patents
Online upgrading method, DSP controller and upgrading system Download PDFInfo
- Publication number
- CN106951289B CN106951289B CN201710178931.4A CN201710178931A CN106951289B CN 106951289 B CN106951289 B CN 106951289B CN 201710178931 A CN201710178931 A CN 201710178931A CN 106951289 B CN106951289 B CN 106951289B
- Authority
- CN
- China
- Prior art keywords
- upgrading
- auxiliary chip
- program
- dsp controller
- online
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
Abstract
The embodiment of the invention discloses an online upgrading method, which comprises the steps of running a bootstrap program of a bootstrap address area in a DSP controller; operating an application program of an application address area in the DSP controller to initialize the DSP controller and copy an upgrading task program into an RAM of the DSP controller, wherein the upgrading task program is built in the application program, and the application address area is positioned in a FLASH storage area; the application program is operated to judge whether the auxiliary chip has an online upgrading mark, and the auxiliary chip displays the online upgrading mark after receiving an online upgrading command of an upper computer; if the auxiliary chip is judged to have the online upgrading mark, skipping to an RAM of a DSP controller to execute the upgrading task program; and running the upgrading task program to control the DSP controller to acquire the upgrading program through the auxiliary chip and write the upgrading program into the application address area. The embodiment of the invention also discloses a DSP controller and an upgrading system. The embodiment of the invention can simplify the upgrading operation and save the storage resources.
Description
Technical Field
The invention relates to the technical field of communication, in particular to an online upgrading method, a DSP controller and an upgrading system.
Background
Generally, a boot project and an application project are required for upgrading the DSP software, and the DSP software is upgraded by means of a simulator or a serial port, but the problems of complex operation and low safety exist no matter the upgrading mode of the simulator or the serial port is adopted. And a solidified guide project is burnt in a plurality of DSP chips, and when software of the DSP is upgraded, a traditional upgrading method is required to be adopted according to the solidified guide project, so that upgrading is not flexible enough, and the application range is limited.
In view of the above, there is a need for an online upgrade method, a DSP controller and an upgrade system that can simplify the upgrade operation and save memory resources.
Disclosure of Invention
In view of this, the embodiments of the present invention provide an online upgrade method, a DSP controller and an upgrade system that simplify upgrade operations and save storage resources.
In a first aspect, an embodiment of the present invention provides an online upgrade method, which is used to perform online program upgrade on a DSP controller, where the DSP controller is connected to an upper computer through an auxiliary chip, and the auxiliary chip is used to receive an upgrade program sent by the upper computer for the DSP controller to read, and the method includes: running a boot program of a boot address area in the DSP controller to initialize the DSP controller; operating an application program of an application address area in the DSP controller to initialize the DSP controller and copy an upgrading task program into an RAM of the DSP controller, wherein the upgrading task program is built in the application program, and the application address area is positioned in a FLASH storage area; the application program is operated to judge whether the auxiliary chip has an online upgrading mark, and the auxiliary chip displays the online upgrading mark after receiving an online upgrading command of the upper computer; if the auxiliary chip is judged to have the online upgrading mark, skipping to the RAM of the DSP controller to execute the upgrading task program; and running the upgrading task program to control the DSP controller to acquire the upgrading program through the auxiliary chip and write the upgrading program into the application address area.
Preferably, the auxiliary chip includes a status register, an online upgrade flag bit is set in the status register, and displaying the online upgrade flag after the auxiliary chip receives the online upgrade command from the upper computer specifically includes: after the auxiliary chip receives an online upgrading command of the upper computer, setting an online upgrading flag bit in the status register; if the auxiliary chip is judged to have the online upgrading mark, jumping to the RAM of the DSP controller to execute the upgrading task program specifically comprises the following steps: and if the on-line upgrading flag bit in the status register of the auxiliary chip is set, skipping to the RAM of the DSP controller to execute the upgrading task program.
Preferably, the running the application program to determine whether there is an online upgrade flag in the auxiliary chip specifically includes: reading the marking state of an online upgrading flag bit in a state register in the auxiliary chip according to a preset period; and judging whether an online upgrading mark exists in the auxiliary chip according to the read marking state of the online upgrading mark bit.
Preferably, a DSP ready flag bit, a data ready bit, and a DSP upgrade completion flag bit are further set in the status register of the auxiliary chip, and the running of the upgrade task program to control the DSP controller to obtain an upgrade program through the auxiliary chip and write the upgrade program into the application address area specifically includes: initializing the DSP controller and erasing the application program of the FLASH storage area; setting a DSP ready flag bit in a state register in the auxiliary chip; judging whether a data ready flag bit in a state register in the auxiliary chip is set, receiving frame data sent by an upper computer and setting the data ready flag bit after the DSP ready flag bit in the state register is set by the data register of the auxiliary chip, and receiving next frame data sent by the upper computer again when the DSP ready flag bit is not set after the data ready bit is cleared and the DSP upgrade completion flag bit is not set by the auxiliary chip; if the data is set, reading the frame data from a data register in the auxiliary chip and clearing a data ready zone bit in the state register; analyzing the read frame of data to obtain analysis information; judging whether the analysis information is an upgrade finish command; if the analysis information is not an upgrade completion command, writing the read frame data into the application address area according to the analysis information, and skipping to execute the step of judging whether a data ready flag bit in a status register in the auxiliary chip is set; and if the analysis information is an upgrade finish command, setting a DSP upgrade finish flag bit in a state register in the auxiliary chip.
Preferably, the auxiliary chip is an FPGA.
In a second aspect, an embodiment of the present invention provides a DSP controller, where the DSP controller is connected to an upper computer through an auxiliary chip, and the auxiliary chip is configured to receive an upgrade program sent by the upper computer for the DSP controller to read, and the DSP controller includes: the FLASH memory comprises a boot address area, an application address area and a RAM, wherein the application address area is located in a FLASH memory area, the boot address area is used for storing a solidified boot program, the application address area is used for storing an application program, an upgrading task program is arranged in the application program, the RAM is used for storing a copied upgrading task program, the upgrading task program is used for writing the upgrading program into the application address area, and the boot address area specifically comprises: the first initialization unit is used for initializing the DSP controller; the application address area specifically includes: the second initialization unit is used for initializing the DSP controller, and the upgrading task program is built in the application program; the copying unit is used for copying the upgrading task program to an RAM of the DSP controller; the first judgment unit is used for judging whether the auxiliary chip has an online upgrading mark or not, and the auxiliary chip displays the online upgrading mark after receiving an online upgrading command of the upper computer; the first skipping unit is used for skipping to the RAM of the DSP controller to execute the upgrading task program if the auxiliary chip is judged to have the online upgrading mark; the RAM specifically comprises: the acquisition unit is used for controlling the DSP controller to acquire an upgrading program through the auxiliary chip; and the writing unit is used for writing the acquired upgrading program into the application address area.
Preferably, the auxiliary chip includes a status register, an online upgrade flag bit is set in the status register, and when the auxiliary chip receives an online upgrade command from the upper computer, the online upgrade flag bit in the status register is set, and the first determining unit specifically includes: the first reading unit is used for reading the marking state of the online upgrading flag bit in the state register in the auxiliary chip according to a preset period; and the judging unit is used for judging whether an online upgrading mark exists in the auxiliary chip according to the read marking state of the online upgrading mark bit.
Preferably, a DSP ready flag bit, a data ready bit, and a DSP upgrade completion flag bit are further set in the status register of the auxiliary chip, and the obtaining unit specifically includes: the third initialization unit is used for carrying out upgrading initialization on the DSP controller; the erasing unit is used for erasing the application program of the FLASH storage area; the first setting unit is used for setting a DSP ready zone bit in a state register in the auxiliary chip; a second judging unit, configured to judge whether a data ready flag bit in a status register in the auxiliary chip is set, where the data register of the auxiliary chip receives and sets one frame of data sent by an upper computer after a DSP ready flag bit in the status register is set, and the auxiliary chip receives the next frame of data sent by the upper computer again after the data ready bit is cleared and the DSP update completion flag bit is not set; the second reading unit is used for reading the frame data from the data register in the auxiliary chip if the second reading unit is set; the clearing unit is used for clearing the data ready zone bit in the status register after the second reading unit reads the frame data; the writing unit specifically includes: the analysis unit is used for analyzing the read frame of data to obtain analysis information; a third judging unit, configured to judge whether the analysis information is an upgrade completion command; the burning unit is used for writing the read frame data into the application address area according to the analysis information if the analysis information is not the upgrading completion command; the second skipping unit is used for skipping to a second judging unit after the burning unit writes the frame data into the application address area so as to execute the step of judging whether a data ready flag bit in a state register in the auxiliary chip is set or not; the RAM further includes: and the second setting unit is used for setting a DSP upgrading completion flag bit in a status register in the auxiliary chip if the analysis information is an upgrading completion command.
Preferably, the auxiliary chip is an FPGA.
In a third aspect, an embodiment of the present invention further provides an upgrade system, where the upgrade system includes an upper computer, an auxiliary chip, and the DSP controller as described above, where the DSP controller and the auxiliary chip are in one-to-one correspondence and are in communication connection, and the auxiliary chip and the upper computer establish communication connection through a network; the DSP controller is used for acquiring an upgrading program from an upper computer through the auxiliary chip when an upgrading request exists and writing the upgrading program into an application address area to realize online upgrading.
The DSP controller in the embodiment of the invention is in communication connection with an upper computer through an auxiliary chip, and an upgrading task program is built in an application program in an application address area, when the DSP controller detects that an upgrading request exists, namely an upgrading mark exists in the auxiliary chip, the DSP controller jumps to an RAM from the application address area and executes the upgrading task program in the RAM, and the upgrading task program is operated to control the DSP controller to acquire the upgrading program through the auxiliary chip and write the upgrading program into a corresponding application address area, so that online upgrading is finished. By means of the built-in upgrading task program in the application program, the DSP controller can be upgraded remotely and online. Compared with the prior art, the DSP controller does not need to be electrically connected with the simulator or the serial port, so that the upgrading operation is simplified. Meanwhile, the upgrading task program is built in the application program in the application address area, so that an independent FLASH sector is not required to be occupied additionally, and FLASH storage resources are saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart of an online upgrade method provided by an embodiment of the present invention;
FIG. 2 is a sub-schematic flow chart of step S105 in FIG. 1;
FIG. 3 is a schematic block diagram of a DSP controller according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an upgrade system provided by an embodiment of the present invention;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 is a schematic flowchart of an online upgrade method according to an embodiment of the present invention. As shown in the figure, the online upgrading method comprises steps S101 to S105.
And S101, operating a boot program of a boot address area in the DSP controller to initialize the DSP controller.
Specifically, the DSP controller supports an IAP (application Programming in-line) function, and communicates with the upper computer through the auxiliary chip to realize the online program upgrade of the DSP controller. The auxiliary chip needs to have a storage function and a network communication function, and is embedded with a network data transceiver module and a data processing module. The network data transceiver module is used for receiving the upgrading program of the DSP controller and sending state information in the upgrading process; and the data processing module is used for interacting and processing data and state information with the DSP controller. In the embodiment of the present invention, the auxiliary chip may be an FPGA (Field-Programmable Gate Array), a ram (random access memory), an mcu (micro programmed Control unit), or the like, which is not limited herein. The auxiliary chip and the upper computer can be in network communication connection in a wired mode or a wireless mode.
After power-on or reset, the DSP controller runs a boot program in the boot address area to initialize the DSP controller, and after the boot program is executed, the DSP controller jumps to the application address area to execute the application program.
S102, operating an application program of an application address area in the DSP controller to initialize the DSP controller and copy an upgrading task program to an RAM of the DSP controller, wherein the upgrading task program is built in the application program.
The storage space of the DSP controller is divided into three areas, namely a boot address area, an application address area and a RAM. The guide address area and the application address area are not overlapped with each other, and the guide address area and the application address area are both positioned in the FLASH storage area. The boot address area is used for storing a solidified boot program; the application address area is used for storing an application program, and an upgrading task program is arranged in the application program; the RAM is used for storing copied upgrading task programs, and the upgrading task programs are used for writing the upgrading programs into the application address area. Because the DSP controller needs to erase the original application program in the application address area in the FLASH storage area when writing the upgrade program so as to write a new upgrade program, and because the upgrade task program is built in the application program, once the application program is erased, the upgrade task program is also erased, and in order to prevent the upgrade task program from being erased, the upgrade task program needs to be copied from the application address area to the RAM area when the application program is run each time. If the DSP controller includes a plurality of RAMs, one of the RAMs capable of storing the upgrade task program needs to be selected according to the size of the upgrade task program to copy the upgrade task program to the selected RAM.
In the embodiment of the invention, the upgrading task program comprises an API library function and an online upgrading function. When the upgrading task program is copied into the RAM, different instructions are needed to be used for copying the API library function and the online upgrading function separately. Before the copying of the API library functions, function definition needs to be carried out in a CMD file. The function definition in the CMD file includes a save sector specifying the API library function in the application address area, a start address of the API library function, an end address of the API library function, and a RAM run address. The specific definition is as follows:
MemCopy (& FLASH28_ API _ LoadStart, & FLASH28_ API _ LoadEnd, & FLASH28_ API _ RunStart); and then copied into RAM at power-up or reset initialization. The CMD file mainly plays a role in communicating a physical memory and a logical address.
When the online upgrade function is copied, a # pragma CODE _ session command needs to be used, which is specifically defined as follows: # pragma CODE _ session (function name, "segment name").
S103, the application program is operated to judge whether the auxiliary chip has an online upgrading mark, and the auxiliary chip displays the online upgrading mark after receiving an online upgrading command of the upper computer.
Specifically, the auxiliary chip is taken as an FPGA as an example for explanation. The data processing module in the FPGA comprises 1 32-bit status register and 18 32-bit data registers. The data register is used for registering upgrading program data received from the upper computer, and the state register is used for marking the state information of the upgrading process. For example, setting the status register data ready Bit (Bit2) when the data register has data, waiting for the DSP controller to read. The meaning of each flag bit of the status register is defined as the following table:
wherein setting is usually to set the corresponding flag to 0 or 1. The concrete description is as follows:
bit 0: and the FPGA judges whether an online upgrading command of the upper computer is received, and sets an upgrading flag Bit in the status register after the online upgrading command is received, namely Bit0 is set to be 1.
Bit 1: the FPGA initializes to perform reset operation on the data register and the status register, and simultaneously sets the FPGA ready flag Bit in the status register, namely Bit1 is set to 1.
Bit 2: the DSP ready zone Bit is valid, the data ready zone Bit is invalid, the FPGA receives frame data sent by the upper computer, and the data ready zone Bit in the state register is set after the frame data is received, namely Bit2 is set to be 1; after the DSP reads the data, the data ready flag is cleared, i.e., Bit2 is set to 0.
Bit 3-Bit 5: if an abnormality occurs in the upgrading process, corresponding fault codes are set to the Bit 3-Bit 5 according to the reason of the abnormality.
Bit 7: if the DSP controller reads the on-line upgrading completion command data, the DSP controller sets the completion flag Bit, namely Bit7 is set to 1.
Bit 8: after the DSP controller reads that the upgrading zone Bit in the status register is valid, the DSP controller sets the DSP ready zone Bit in the status register after completing online upgrading initialization, namely setting Bit8 to 1.
In the embodiment of the present invention, the determining whether the auxiliary chip has the online upgrade flag specifically includes: reading the marking state of an online upgrading flag bit in a state register in the auxiliary chip according to a preset period; and judging whether the online upgrading flag bit is set according to the read marking state of the online upgrading flag bit. And when the online upgrade flag bit in the status register is set, if the online upgrade flag bit is in the auxiliary chip, executing step S104, and if the online upgrade flag bit in the status register is not set, if the online upgrade flag bit is not in the auxiliary chip, continuing to execute step S103.
And S104, jumping to the RAM of the DSP controller to execute the upgrading task program.
Specifically, after detecting that the online upgrade flag bit exists in the secondary chip in step S103, the DSP controller jumps to the RAM to execute the copied upgrade task program.
And S105, operating the upgrading task program to control the DSP controller to acquire the upgrading program through the auxiliary chip and write the upgrading program into the application address area.
Specifically, the upgrade program is used for upgrading the application program in the DSP controller to further implement the function upgrade and improvement of the application program. In the embodiment of the present invention, referring to fig. 2, a sub-flow diagram of step S105 is shown. Step S105 specifically includes steps S201 to S208.
S201: and carrying out upgrading initialization on the DSP controller and erasing the application program of the FLASH storage area.
Specifically, the application program is stored in an application address area in the FLASH memory area, and in some embodiments, the FLASH memory area may be erased according to the number of sectors in the FLASH memory area occupied by the upgrade program, so as to obtain an address space matched with the upgrade program, where a sector is a basic erase unit in the FLASH memory area. And the upgrading program occupies a corresponding sector in the FLASH storage area for storage. Since the size of the upgrade program may not be a whole multiple of the size of the sector, in order to ensure that sufficient address space is provided for the upgrade program, it is preferable to perform address erasure on the FLASH memory area according to the number of sectors occupied by the upgrade program.
S202: and setting a DSP ready zone bit in a state register in the auxiliary chip.
Specifically, after the DSP controller reads the upgrade flag bit in the status register, the DSP controller writes the set flag in the status register to implement the setting of the DSP ready flag bit.
S203: and judging whether a data ready zone bit in a state register in the auxiliary chip is set or not, receiving frame data sent by an upper computer and setting the data ready zone bit after the DSP ready zone bit in the state register is set by the data register of the auxiliary chip, and receiving next frame data sent by the upper computer again when the DSP ready zone bit is not set after the data ready zone bit is cleared and the DSP upgrade completion zone bit is not set by the auxiliary chip.
Specifically, after the data register of the FPGA receives a frame of data sent by the upper computer, the data ready flag bit is set, the DSP controller periodically determines whether the data ready flag bit in the status register of the FPGA is set, and if the data ready flag bit is set, the step S204 is executed. If not, the step S203 is continued. It should be noted that, the auxiliary chip receives the next frame data sent by the upper computer again after the data ready bit is cleared and the DSP upgrade completion flag bit is not set.
S204: and reading the frame data from a data register in the auxiliary chip and clearing a data ready zone bit in the status register.
S205: and analyzing the read frame of data to obtain analysis information.
Specifically, when the upper computer performs the write operation of the upgrade program on the DSP controller through the FPGA, the upgrade program data is transmitted in a one-frame-data-at-a-time manner, that is, after the data register of the FPGA receives one frame of data sent by the upper computer each time, the DSP controller obtains the one frame of data from the data register in the FPGA and analyzes the one frame of data, so as to obtain the analysis information such as the first address, the offset address information, the data length, the data type, the end information, and the like of the one frame of data stored in the FLASH memory area.
S206: and judging whether the analysis information is an upgrade finishing command.
Specifically, if the analysis information is a data upgrade complete instruction, which indicates that the upgrade program has been received, step S208 is executed; if the analysis information is not the upgrade complete command, step S207 is executed.
S207: and writing the read frame data into the application address area according to the analysis information, and skipping to execute the step of judging whether the data ready flag bit in the status register in the auxiliary chip is set.
Specifically, if the analysis information is not the update completion command, which indicates that the DSP controller has not completed updating, the read frame data is written into the corresponding application address area according to the analysis information, and S203 is skipped to execute again to determine whether the data ready flag bit in the status register in the auxiliary chip is set, so as to wait for receiving the next frame data.
S208: and setting a DSP upgrading completion flag bit in a state register in the auxiliary chip.
It should be noted that, if an abnormality occurs in the upgrading process of the DSP controller, such as failure in erasing the FLASH memory area, timeout of waiting data, etc., the DSP controller may write a corresponding fault code into the status register, the DSP controller may perform upgrading initialization again to wait for upgrading again, the FPGA sends the fault information to the upper computer after receiving the fault information, and the upper computer processes the fault information and then issues upgrading program data again.
The DSP controller in the embodiment of the invention is in communication connection with an upper computer through an auxiliary chip, and an upgrading task program is built in an application program in an application address area, when the DSP controller detects that an upgrading request exists, namely an upgrading flag bit exists in the auxiliary chip, the DSP controller jumps to an RAM from the application address area and executes the upgrading task program in the RAM, and the upgrading task program is operated to control the DSP controller to acquire the upgrading program through the auxiliary chip and write the upgrading program into a corresponding application address area, so that online upgrading is finished. By means of the built-in upgrading task program in the application program, the DSP controller can be upgraded remotely and online. Compared with the prior art, the DSP controller does not need to be electrically connected with the simulator or the serial port, so that the upgrading operation is simplified. Meanwhile, the upgrading task program is built in the application program in the application address area, so that an independent FLASH sector is not required to be occupied additionally, and FLASH storage resources are saved.
Referring to fig. 3, a schematic block diagram of a DSP controller according to an embodiment of the present invention is shown. The DSP controller 30 in the present embodiment as shown in the figure includes a boot address area, an application address area, and a RAM, and the application address area is located in the FLASH memory area. The guide address area is preferably located in the FLASH memory area and does not overlap with the application address area. The boot address area is used for storing a solidified boot program, the application address area is used for storing an application program, an upgrading task program is arranged in the application program, the RAM is used for storing the copied upgrading task program, and the upgrading task program is used for writing the upgrading program into the application address area.
The boot address area specifically includes a first initialization unit 31, configured to initialize the DSP controller.
The application address area specifically includes a second initialization unit 32, a copy unit 33, a first judgment unit 34, and a jump unit 35.
A second initialization unit 32, configured to initialize the DSP controller.
And the copying unit 33 is used for copying the upgrading task program to the RAM of the DSP controller.
And the first judging unit 34 is used for judging whether the auxiliary chip has an online upgrading mark, and the auxiliary chip displays the online upgrading mark after receiving an online upgrading command of the upper computer.
And the first skipping unit 35 is configured to skip to the RAM of the DSP controller to execute the upgrade task program if it is determined that the auxiliary chip has the online upgrade flag.
Further, the auxiliary chip includes a status register, an online upgrade flag bit is set in the status register, and when the auxiliary chip receives an online upgrade command from the upper computer, the online upgrade flag bit in the status register is set, and the first determining unit 34 further includes a first reading unit 341 and a determining unit 342.
A first reading unit 341, configured to read a flag state of an online upgrade flag bit in a status register in the auxiliary chip according to a preset period;
the determining unit 342 is configured to determine whether the online upgrade flag bit is set according to the read flag state of the online upgrade flag bit.
The RAM specifically includes an acquisition unit 36 and a writing unit 37.
An obtaining unit 36, configured to control the DSP controller to obtain an upgrade program through the auxiliary chip;
a writing unit 37, configured to write the acquired upgrade program into the application address area.
Further, the obtaining unit 36 specifically includes: third initialization unit 361, erase unit 362, first set unit 363, second determination unit 364, second read unit 365, and clear unit 366.
A third initialization unit 361, configured to perform upgrade initialization on the DSP controller.
And the erasing unit 362 is used for erasing the application program of the FLASH storage area.
And the first setting unit 363 is configured to set a DSP ready flag bit in a status register in the auxiliary chip.
A second determining unit 364, configured to determine whether a data ready flag bit in a status register in the auxiliary chip is set, where the data register of the auxiliary chip receives and sets one frame of data sent by an upper computer after a DSP ready flag bit in the status register is set, and the auxiliary chip receives the next frame of data sent by the upper computer again after the data ready bit is cleared and the DSP upgrade completion flag bit is not set.
The second reading unit 365 is configured to read the frame data from the data register in the auxiliary chip if the frame data is set.
A clearing unit 366, configured to clear the data ready flag bit in the status register after the second reading unit reads the frame data.
Further, the writing unit 37 specifically includes an analyzing unit 371, a third determining unit 372, a burning unit 373, a second jumping unit 374, and a second setting unit 375.
The parsing unit 371 is configured to parse the read frame of data to obtain parsing information.
A third determining unit 372, configured to determine whether the analysis information is an upgrade complete command.
And a burning unit 373, configured to write the read frame data into the application address area according to the analysis information if the analysis information is not the update completion command.
A second skipping unit 374, configured to skip and execute the step of determining whether the data ready flag bit in the status register in the secondary chip is set after the burning unit writes the frame data into the application address area.
A second setting unit 375, configured to set a DSP upgrade complete flag bit in a status register in the auxiliary chip if the analysis information is an upgrade complete command.
The DSP controller in the embodiment of the invention is in communication connection with an upper computer through an auxiliary chip, and an upgrading task program is built in an application program in an application address area, when the DSP controller detects that an upgrading request exists, namely an upgrading flag bit exists in the auxiliary chip, the DSP controller jumps to an RAM from the application address area and executes the upgrading task program in the RAM, and the upgrading task program is operated to control the DSP controller to acquire the upgrading program through the auxiliary chip and write the upgrading program into a corresponding application address area, so that online upgrading is finished. By means of the built-in upgrading task program in the application program, the DSP controller can be upgraded remotely and online. Compared with the prior art, the DSP controller does not need to be electrically connected with the simulator or the serial port, so that the upgrading operation is simplified. Meanwhile, the upgrading task program is built in the application program in the application address area, so that an independent FLASH sector is not required to be occupied additionally, and FLASH storage resources are saved.
Fig. 4 is a schematic diagram of an upgrade system according to an embodiment of the present invention. As shown, the upgrade system 40 includes an auxiliary chip (not shown), a DSP controller (not shown), and an upper computer 42. The auxiliary chip and the DSP controller are in one-to-one correspondence and are in communication connection, and the auxiliary chip and the upper computer are in communication connection through a network. When the device is used, the auxiliary chip and the DSP controller are usually packaged into one terminal device 41, and the upper computer 42 can be in communication connection with one or more terminal devices 41. When the DSP controller is upgraded on line, the DSP controller obtains an upgrading program from an upper computer through the auxiliary chip and writes the upgrading program into an application address area to realize on-line upgrading.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the controller and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed controller and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, device apparatuses or units, and may also be an electrical, mechanical or other form of connection.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs.
The units in the controller of the embodiment of the invention can be merged, divided and deleted according to actual needs.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the first embodiment of the invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a controller, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above are preferred embodiments of the invention and are not intended to limit the invention in any way. Various equivalent changes and modifications can be made by those skilled in the art based on the above-described embodiments, and all equivalent changes and modifications within the scope of the claims should be considered as falling within the scope of the present invention.
Claims (7)
1. An online upgrade method is used for online program upgrade of a DSP controller, the DSP controller is connected with an upper computer through an auxiliary chip, and the auxiliary chip is used for receiving an upgrade program sent by the upper computer to be read by the DSP controller, and the online upgrade method is characterized by comprising the following steps:
running a boot program of a boot address area in the DSP controller to initialize the DSP controller;
operating an application program of an application address area in the DSP controller to initialize the DSP controller and copy an upgrading task program into an RAM of the DSP controller, wherein the upgrading task program is built in the application program, and the application address area is positioned in a FLASH storage area;
the application program is operated to judge whether the auxiliary chip has an online upgrading mark, and the auxiliary chip displays the online upgrading mark after receiving an online upgrading command of the upper computer;
if the auxiliary chip is judged to have the online upgrading mark, skipping to the RAM of the DSP controller to execute the upgrading task program;
running the upgrading task program to control the DSP controller to acquire an upgrading program through the auxiliary chip and write the upgrading program into the application address area;
the auxiliary chip includes a status register, a DSP ready flag bit, a data ready bit, and a DSP upgrade completion flag bit are set in the status register, and the running of the upgrade task program to control the DSP controller to obtain an upgrade program through the auxiliary chip and write the upgrade program into the application address area specifically includes:
initializing the DSP controller and erasing the application program of the FLASH storage area;
setting a DSP ready flag bit in a state register in the auxiliary chip;
judging whether a data ready flag bit in a state register in the auxiliary chip is set, receiving frame data sent by an upper computer and setting the data ready flag bit after the DSP ready flag bit in the state register is set by the data register of the auxiliary chip, and receiving next frame data sent by the upper computer again when the DSP ready flag bit is not set after the data ready bit is cleared and the DSP upgrade completion flag bit is not set by the auxiliary chip;
if the data is set, reading the frame data from a data register in the auxiliary chip and clearing a data ready zone bit in the state register;
analyzing the read frame of data to obtain analysis information;
judging whether the analysis information is an upgrade finish command;
if the analysis information is not an upgrade completion command, writing the read frame data into the application address area according to the analysis information, and skipping to execute the step of judging whether a data ready flag bit in a status register in the auxiliary chip is set;
if the analysis information is an upgrade finish command, setting a DSP upgrade finish flag bit in a status register in the auxiliary chip;
the status register is provided with an online upgrading flag bit, and the display of the online upgrading flag after the auxiliary chip receives the online upgrading command of the upper computer specifically comprises the following steps: after the auxiliary chip receives an online upgrading command of the upper computer, setting an online upgrading flag bit in the status register;
if the auxiliary chip is judged to have the online upgrading mark, jumping to the RAM of the DSP controller to execute the upgrading task program specifically comprises the following steps: and if the on-line upgrading flag bit in the status register of the auxiliary chip is set, skipping to the RAM of the DSP controller to execute the upgrading task program.
2. The method of claim 1, wherein the running the application program to determine whether the online upgrade flag bit in the status register in the companion chip is set specifically comprises:
reading the marking state of an online upgrading flag bit in a state register in the auxiliary chip according to a preset period;
and judging whether the online upgrading flag bit is set according to the read marking state of the online upgrading flag bit.
3. The method of any of claims 1-2, wherein the companion chip is an FPGA.
4. The utility model provides a DSP controller, DSP controller passes through auxiliary chip and is connected with the host computer, auxiliary chip is used for receiving the upgrading procedure that the host computer sent for the DSP controller reads, its characterized in that, DSP controller includes:
the system comprises a boot address area, an application address area and a RAM, wherein the application address area is positioned in a FLASH storage area, the boot address area is used for storing a solidified boot program, the application address area is used for storing an application program, an upgrading task program is arranged in the application program, the RAM is used for storing a copied upgrading task program, the upgrading task program is used for writing the upgrading program into the application address area, wherein,
the boot address area specifically includes:
the first initialization unit is used for initializing the DSP controller;
the application address area specifically includes:
the second initialization unit is used for initializing the DSP controller;
the copying unit is used for copying the upgrading task program to an RAM of the DSP controller;
the first judgment unit is used for judging whether the auxiliary chip has an online upgrading mark or not, and the auxiliary chip displays the online upgrading mark after receiving an online upgrading command of the upper computer;
the first skipping unit is used for skipping to the RAM of the DSP controller to execute the upgrading task program if the auxiliary chip is judged to have the online upgrading mark;
the RAM specifically comprises:
the acquisition unit is used for controlling the DSP controller to acquire an upgrading program through the auxiliary chip;
the writing unit is used for writing the obtained upgrading program into the application address area;
the auxiliary chip comprises a status register, wherein the status register is provided with a DSP ready zone bit, a data ready zone bit and a DSP upgrade completion zone bit,
the acquiring unit specifically includes:
the third initialization unit is used for carrying out upgrading initialization on the DSP controller;
the erasing unit is used for erasing the application program of the FLASH storage area;
the first setting unit is used for setting a DSP ready zone bit in a state register in the auxiliary chip;
a second judging unit, configured to judge whether a data ready flag bit in a status register in the auxiliary chip is set, where the data register of the auxiliary chip receives and sets one frame of data sent by an upper computer after a DSP ready flag bit in the status register is set, and the auxiliary chip receives the next frame of data sent by the upper computer again after the data ready bit is cleared and the DSP update completion flag bit is not set;
the second reading unit is used for reading the frame data from the data register in the auxiliary chip if the second reading unit is set;
the clearing unit is used for clearing the data ready zone bit in the status register after the second reading unit reads the frame data;
the writing unit specifically includes:
the analysis unit is used for analyzing the read frame of data to obtain analysis information;
a third judging unit, configured to judge whether the analysis information is an upgrade completion command;
the burning unit is used for writing the read frame data into the application address area according to the analysis information if the analysis information is not the upgrading completion command;
the second skipping unit is used for skipping to the second judging unit after the burning unit writes the frame data into the application address area so as to judge whether a data ready flag bit in a state register in the auxiliary chip is set or not;
and the second setting unit is used for setting a DSP upgrading completion flag bit in a status register in the auxiliary chip if the analysis information is an upgrading completion command.
5. The DSP controller according to claim 4, wherein the status register is provided with an online upgrade flag bit, and the auxiliary chip sets the online upgrade flag bit in the status register after receiving an online upgrade command from the upper computer, and the first determining unit specifically includes:
the first reading unit is used for reading the marking state of the online upgrading flag bit in the state register in the auxiliary chip according to a preset period;
and the judging unit is used for judging whether the online upgrading zone bit in the auxiliary chip is set according to the read marking state of the online upgrading zone bit.
6. The DSP controller according to any of claims 4 to 5, wherein the auxiliary chip is an FPGA.
7. An upgrading system, which is characterized by comprising an upper computer, an auxiliary chip and the DSP controller according to any one of claims 4 to 6, wherein the DSP controller is in one-to-one correspondence with the auxiliary chip and is in communication connection with the auxiliary chip, and the auxiliary chip is in communication connection with the upper computer through a network; the DSP controller is used for acquiring an upgrading program from an upper computer through the auxiliary chip when an upgrading request exists and writing the upgrading program into an application address area to realize online upgrading.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710178931.4A CN106951289B (en) | 2017-03-23 | 2017-03-23 | Online upgrading method, DSP controller and upgrading system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710178931.4A CN106951289B (en) | 2017-03-23 | 2017-03-23 | Online upgrading method, DSP controller and upgrading system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106951289A CN106951289A (en) | 2017-07-14 |
| CN106951289B true CN106951289B (en) | 2020-11-10 |
Family
ID=59473572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710178931.4A Active CN106951289B (en) | 2017-03-23 | 2017-03-23 | Online upgrading method, DSP controller and upgrading system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106951289B (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107748670A (en) * | 2017-09-13 | 2018-03-02 | 国电南瑞科技股份有限公司 | Electric automobile DC charging module controller program on-line upgrading system |
| CN107885523B (en) * | 2017-11-10 | 2021-08-31 | 航宇救生装备有限公司 | Rapid and stable serial port software upgrading method |
| CN108255538B (en) * | 2017-12-08 | 2021-02-09 | 中国航空工业集团公司成都飞机设计研究所 | Method for in-situ loading of second-level controller software on distributed heterogeneous system machine |
| CN110609691A (en) * | 2018-06-15 | 2019-12-24 | 株洲中车时代电气股份有限公司 | Method for remotely updating DSP program |
| CN109491648B (en) * | 2018-11-19 | 2022-05-17 | 上海新时达电气股份有限公司 | Method, system and equipment for realizing independent partition of library function in embedded software |
| CN109189461B (en) * | 2018-11-27 | 2022-01-18 | 上海辛格林纳新时达电机有限公司 | Procedure upgrading method for elevator control system, elevator control system and elevator equipment |
| CN109710291B (en) * | 2018-12-27 | 2021-02-12 | 中国科学院长春光学精密机械与物理研究所 | Remote upgrading method for aviation photoelectric load software configuration items |
| CN109683941A (en) * | 2018-12-27 | 2019-04-26 | 四川九洲空管科技有限责任公司 | A kind of answering machine method for upgrading software based on single-chip on-line loaded |
| CN109800007A (en) * | 2018-12-28 | 2019-05-24 | 航天信息股份有限公司 | Dsp chip online upgrading method and device |
| CN110659056B (en) * | 2019-09-28 | 2022-12-13 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | DSP program online updating circuit |
| CN112783519B (en) * | 2019-11-04 | 2023-10-20 | 航天科工惯性技术有限公司 | Application program updating method and system for measuring nipple |
| CN114112736B (en) * | 2020-08-28 | 2023-11-14 | 宝山钢铁股份有限公司 | Online measuring device and method for determining fracture elongation of low-carbon steel cold-rolled sheet |
| CN112199109B (en) * | 2020-10-16 | 2022-07-19 | 杭州觅睿科技股份有限公司 | Firmware upgrading method, device, equipment and medium |
| CN112363746B (en) * | 2020-11-20 | 2023-06-02 | 清能德创电气技术（北京）有限公司 | Dual-core DSP online upgrading method |
| CN112783531A (en) * | 2021-01-29 | 2021-05-11 | 湖北三江航天红峰控制有限公司 | Method for upgrading DSP (digital Signal processor) program through Ethernet under FPGA (field programmable Gate array) and DSP (digital Signal processor) framework |
| CN114281392A (en) * | 2022-03-04 | 2022-04-05 | 季华实验室 | Serial port upgrading method and system for multi-MCU slave station |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003114808A (en) * | 2001-10-04 | 2003-04-18 | Alps Electric Co Ltd | Transmitting and receiving unit for data transfer and method for updating program in the same |
| CN101131648A (en) * | 2006-08-25 | 2008-02-27 | 深圳迈瑞生物医疗电子股份有限公司 | On-line updating method for USB interface control panel |
| CN103136028A (en) * | 2013-03-11 | 2013-06-05 | 西北工业大学 | FLASH memorizer long-distance on-line upgrade method based on field programmable gate array (FPGA) |
| CN105808283A (en) * | 2014-12-31 | 2016-07-27 | 海洋王照明科技股份有限公司 | Program updating method and device applicable to intelligent illumination equipment |
| CN105867977B (en) * | 2016-04-01 | 2019-06-14 | 天津七所精密机电技术有限公司 | The upgrading of DSP user program and Flash method for down loading |
| CN106528203B (en) * | 2016-10-10 | 2019-10-18 | 上海无线电设备研究所 | A kind of automated procedures programming method of multi-DSP chip |
-
2017
- 2017-03-23 CN CN201710178931.4A patent/CN106951289B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN106951289A (en) | 2017-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106951289B (en) | Online upgrading method, DSP controller and upgrading system | |
| KR100448905B1 (en) | Computer system with nand flash memory for booting and storagement | |
| TWI220962B (en) | Firmware updating method and related apparatus for checking content of replacing firmware before firmware updating | |
| KR100988157B1 (en) | Method and apparatus for detecting memory device configuration, and computer readable medium containing instructions for performing method for detecting memory device configuration | |
| CN102623069B (en) | Random excitation flash model verification method | |
| CN101853692B (en) | Controller with flash memory test function, and storage system and test method thereof | |
| US20090198770A1 (en) | System and method of updating codes in controller | |
| CN104123153A (en) | Apparatus and method for firmware upgrade using USB | |
| US9158476B2 (en) | Method for switching operation mode, memory controller and memory storage apparatus | |
| CN103745167B (en) | The IAP method and device of single-chip microcomputer | |
| CN109445691B (en) | Method and device for improving FTL algorithm development and verification efficiency | |
| CN104077166A (en) | EPCS and EPCQ storer online upgrading method based on IP core in FPGA | |
| JP2010500682A (en) | Flash memory access circuit | |
| CN111737051B (en) | Trim data verification test method, device and system of SSD (solid State disk) | |
| JP2009252194A (en) | Data processor, hardware access method, and hardware access program | |
| CN107220065A (en) | A kind of Domestic Platform BIOS video driver methods based on X86 simulators | |
| CN107678770B (en) | Interface chip upgrading method and device, storage medium and processor | |
| CN102968319A (en) | VxWorks image loading method | |
| CN103577344A (en) | Data writing method, memory controller and memory storage device | |
| US20060224377A1 (en) | ROM emulator | |
| US20040194062A1 (en) | Data storage system and method for testing the same | |
| CN110825421A (en) | Firmware upgrading method and system and readable storage medium | |
| CN100498710C (en) | Method for reading and electing read only memory program code on self-storing mechanism | |
| CN101840520B (en) | Intelligent card and method for accessing flash memory of intelligent card | |
| CN112885403B (en) | Function test method, device and equipment of Flash controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |