CA1179024A - Suppressed clock extraction by a phase locked loop - Google Patents
Suppressed clock extraction by a phase locked loopInfo
- Publication number
- CA1179024A CA1179024A CA000400188A CA400188A CA1179024A CA 1179024 A CA1179024 A CA 1179024A CA 000400188 A CA000400188 A CA 000400188A CA 400188 A CA400188 A CA 400188A CA 1179024 A CA1179024 A CA 1179024A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- clock
- frequency
- output
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Abstract
ABSTRACT OF THE DISCLOSURE
A system for suppressed clock extraction by a phase locked loop is realized to extract clock signal from a digital suppressed clock modulation signal. The edge signal of the incoming data triggers a window generator's output high. The input signal is also delayed for a half clock period before applied to one input of a frequency/phase detector. The output of said window generator provides a control signal enabling an edge signal of feedback ?
through a sampling latch. This windowed feedback signal is routed to another input of the frequency/phase detector. The output of the detector is further filtered by a low pass filter before being applied to an input of a voltage controlled oscillator. The output of the voltage controlled oscillator is the extracted clock signal acting also as the feedback signal. Due to the window effect applied to the feedback signal, there will be phase comparison by the frequency/
phase detector only when input data edge signal is available.
A system for suppressed clock extraction by a phase locked loop is realized to extract clock signal from a digital suppressed clock modulation signal. The edge signal of the incoming data triggers a window generator's output high. The input signal is also delayed for a half clock period before applied to one input of a frequency/phase detector. The output of said window generator provides a control signal enabling an edge signal of feedback ?
through a sampling latch. This windowed feedback signal is routed to another input of the frequency/phase detector. The output of the detector is further filtered by a low pass filter before being applied to an input of a voltage controlled oscillator. The output of the voltage controlled oscillator is the extracted clock signal acting also as the feedback signal. Due to the window effect applied to the feedback signal, there will be phase comparison by the frequency/
phase detector only when input data edge signal is available.
Description
3~
SUPPRESSED C~O~K EXTRACTION BY A PHASE LOCKED L~OP
- BACKGROUND OF THæ INVENTION
This invention relates to a method of clock extraction throu~h a special arrangement o~ a phase locked loop.
For most baseband digital communications, data is usually transmitted in a form of suppressed carrier method to achieve maximum usage of the cha~nel's bandwidth. Bip~lar or binary (unipolar) are popular methods. Some data recording formats (such as ~, MFr~I~ r~FM and etc.) and NRZ can also be considered as modified suppressed clock modulations.
Phase locked loop is usually applied to regenerate the clock signal. For a narrow loop bandwi~dth design~ i~ usually requiras expensive voltage controlled c~ystal oscillator aue to stability proble~randd provides limited low frequency trac~ing ablility.
For a ~æ~ bandwidth design, phase and frequency of the clock generated will be degraded (drifted) if there is a long term of zero data input without transition.
The application of comparing a window signal and a feedback signal has been men-tioned in U.S. Pat. No. 4,218,771.
However, the stated reference cannot carry ou-t -the suppressed clock extraction as in my in~ention~s objective. ~urtn~rmore, if both delayed and advanced feedback signals are within -the ~window's limits, there is no error compensation signal generated to the voltage controlled phase shift even if there is phase error existing. Another reference cited with CAN. ~at. No.
1,051,528 relates to a data recovery system mainly for .~ ~q recording format. ~he stated invention may not stand for phase deviation as required by general baseband communication. A
,. ....
n 1l e n ~/v~ '~
feedback phase shi~t logic is no-t rny ~vn~t~D~ intention.
~urt~ermore, its phase tracking range is limited and with undefined regions which requires a leader signal of all unes to train and long time of acquisition.
SU~ ARY OF TXE I~ENTION
In this invention, a broad bandwidth phase locked loop can be applied to compare phases when there is a transition signal in the incoming data. When -the input signal~s data is zero during a particular clock time slot, the comparison of phases is disabled. At this time, the frequency/phase detector~output is off and the following 10W
pass ~ilter i~ kept idle. Thus the low pass filter la~ches the las~ filtered DC signal to control the ~oltage controlled oscillator. I~ the leakage o~ the ~ilter is low and the oscillator's dri~ting is small, the loop's oscillator will conti~ue to generate same ~requency as before and its phase position will be kept.
a~
When there is~transition edge of incoming signal available again, frequency/phase detector reacts again immediately to generate a compensation s,ignal o~ any phase/
frequency error. An expensive voltage controlled c~ys~al oscillator is not required because the phase error will be compensatad by the broad pass band low pass filter during transition comparison period. As a whole~ this invention provides an equivalen~ low noise band phase locked loop during zero da~a input while tracks the low ~requency jitter by the broad loop bandwid-th phase locked loop during ones da~a period.
BRIE~ DESCRIPTION OF ~HE DRAWINGS
A better un~erstanding o~ the inv-ention will be obtained by re~erence to ~he description below, in conjunction with the following drawings, in which:
Figure la is a block diagram of' a basic form of' the in~ention, Figure lb is a wa~eform diagram o~ t~e pre~erred embodiment of the invention, and Figure 2 is the schematic o~ a pre~erred ambodir.l~nt.
DE~AILE~ DESCRIPTION OF THE I~ENTIOM
Turning now to Figure la, a logical block diagram shows basic apparatus essential to an understandi.ng of the manner in which the in~ntion is implemented in more detailed apparatus to be explained later.
An input source of suppressed clock modulated signal with frequency and phase deviations which is intended to have data clock signal regenerated is applied to inputs of' delay device 1 and window generator 2. The output of delay device 1 is connected to one input of f'requency/phase detector 4. The output of the windo~ generator 2 prPvides a control signal enabling an edge signal of f'eedback clock through at the feedback clock sampling latch 3. This feedback clock is coming from voltage controllad oscillator 6. Output of feedback clock ~ampling latch 3 is connected to ano~her input of the frequency/phase detector 4 and -to an input of window generator 2 so as to reset it. Output o~ the frequ6ncy /phase detector 4 is filtered 'by a low pass filter 5. Filter's output is connected to input of voltage controll~d oscillator 6.
When the delayed input signal receeds the qampling latch 3's output, there i5 a positive pulse output from the frequency/phase detector ~ with the duration representing the p~ase di~ference. When the sampling latch~s output preceeds the delayed input, there is a negative pulse ouput from frequenc~/phase detector 4. Where there is no phase differe-nce or no phase comparison, ou~put o~ frequency/phase detector 4 is off. Detail action can be observed in Figure lb.
'F~rthermorè, detector 4 also provides a means to detect ~requency dif~erence between two inputs for a case of start-up or a sudden change of input!s ~requency.
The detector's output is smoothed by the low pass filter 5 before reaching the voltage controlled oscillator 6.
~he filter may be implemented in passive or active form.
Turning now to ~igure 2, a detailed logic diagram of the preferred form of the invention is shown.
The clock suppressed modulated input signal is applied to input terminal of hal~ clock period delay device 10 and clock C termianl of window generator flip flop 11. If the input signal's pulse duration is assumed to be about ~0 percentt the next opposite-edge of the signal can be used as the hal~ clock period'delayed signal. m that case, half clock period delay device 10 can be replaced by an in~erter.
`~~` The Q output of flip flop 11 is connected to ~Q D terminal of flip flop 12. The Q ou~put of flip flop 11 is connected to reset R terminal of flip flop 12. ~he Q output of flip flop 12 is connected to reset R terminal of flip flop 11 and an input o~ fr~quenc~/phase detector 13. The output terminal of delay device 10 is connec~ed to another input of frequency/
phase detector 13~ The output termi~al o~ frequency/phase detector 13 is connected to an input of a low pass filter 14.
The output terminal of the low pass filter 14 is connected to an input terminal of the voltage controlled oscillator 15.
Resistor 16 is used to control the maximum frequency generated by voltage controlled oscillator 15. rl~aximum frequency shoula be less than two times the average of the recovered data clock rate preventing locking to a higher harmonic frequency.
Resistor 18 is used to control the minimum ~requency generated by voltage con~rolled oscillator 15. Minimum ~requency should be more than half t~e average of t~e recovered data clock rate providing a start-up fast acquisition and preventing locking to lower harmonic frequenc~. ~he output terminal of voltage controlled oscillator 15 is connected to clock C terminal of sampling latch flip flop 12~ In a successful prototype, the frequency/phase detector 13 was CD4046B which included the charge-pump tri-state device and voltage controlled oscillator inside. Of course, other equivalent device or discrete logic can also be used. Flip flops ll and 12 are CD4013B.
In operation, the positive edge of input signal causes window generator flip flop 11 output high. The feed-back signal from voltage controlled oscillator 1~ sampling -r~
J
~7~
~`~`' this ~ P signal to cause the sampling latch 12 output high.
Thus this high transition is frequency/phase compared with the hal~ clock delayed positive edge of input signal by frequency/
phase detector 13. At the sametime, sampling latch 12 Q
output is fed to reset the window generator flip flop 11 and then the sampling latch 12 itself. ThUS there is a narrow pulse generated at latch 12 Q output for frequency/phase comparison. The reset of flip flop 11 using a narrow pulse is to provide the capability of tracking of an instant ~180 degrees phase step input. During transitions comparison period, the frequency/phase error signal is generated from the oub,put of detector 15 in order to charge or discharge the low pass ~ilter 14. ~he filtered signal is applied to input of voltage controlled oscillator 15 to cause its frequency output compensated. During zero data period, there is no transition applied to detector 15 and thus its output is off. And the low pass filter 14 will latch the last f;ltered DC output.
The output of voltage controlled oscillator 15 as the recovered data clock is also fed back to clock ~ input of sampling latch 12.
A suppressed clock extraction circuit applying a phase lco~d loop has been described. Various modifications may appear to those skilled in the art possible without departing from the spirit of the invention.
.~
SUPPRESSED C~O~K EXTRACTION BY A PHASE LOCKED L~OP
- BACKGROUND OF THæ INVENTION
This invention relates to a method of clock extraction throu~h a special arrangement o~ a phase locked loop.
For most baseband digital communications, data is usually transmitted in a form of suppressed carrier method to achieve maximum usage of the cha~nel's bandwidth. Bip~lar or binary (unipolar) are popular methods. Some data recording formats (such as ~, MFr~I~ r~FM and etc.) and NRZ can also be considered as modified suppressed clock modulations.
Phase locked loop is usually applied to regenerate the clock signal. For a narrow loop bandwi~dth design~ i~ usually requiras expensive voltage controlled c~ystal oscillator aue to stability proble~randd provides limited low frequency trac~ing ablility.
For a ~æ~ bandwidth design, phase and frequency of the clock generated will be degraded (drifted) if there is a long term of zero data input without transition.
The application of comparing a window signal and a feedback signal has been men-tioned in U.S. Pat. No. 4,218,771.
However, the stated reference cannot carry ou-t -the suppressed clock extraction as in my in~ention~s objective. ~urtn~rmore, if both delayed and advanced feedback signals are within -the ~window's limits, there is no error compensation signal generated to the voltage controlled phase shift even if there is phase error existing. Another reference cited with CAN. ~at. No.
1,051,528 relates to a data recovery system mainly for .~ ~q recording format. ~he stated invention may not stand for phase deviation as required by general baseband communication. A
,. ....
n 1l e n ~/v~ '~
feedback phase shi~t logic is no-t rny ~vn~t~D~ intention.
~urt~ermore, its phase tracking range is limited and with undefined regions which requires a leader signal of all unes to train and long time of acquisition.
SU~ ARY OF TXE I~ENTION
In this invention, a broad bandwidth phase locked loop can be applied to compare phases when there is a transition signal in the incoming data. When -the input signal~s data is zero during a particular clock time slot, the comparison of phases is disabled. At this time, the frequency/phase detector~output is off and the following 10W
pass ~ilter i~ kept idle. Thus the low pass filter la~ches the las~ filtered DC signal to control the ~oltage controlled oscillator. I~ the leakage o~ the ~ilter is low and the oscillator's dri~ting is small, the loop's oscillator will conti~ue to generate same ~requency as before and its phase position will be kept.
a~
When there is~transition edge of incoming signal available again, frequency/phase detector reacts again immediately to generate a compensation s,ignal o~ any phase/
frequency error. An expensive voltage controlled c~ys~al oscillator is not required because the phase error will be compensatad by the broad pass band low pass filter during transition comparison period. As a whole~ this invention provides an equivalen~ low noise band phase locked loop during zero da~a input while tracks the low ~requency jitter by the broad loop bandwid-th phase locked loop during ones da~a period.
BRIE~ DESCRIPTION OF ~HE DRAWINGS
A better un~erstanding o~ the inv-ention will be obtained by re~erence to ~he description below, in conjunction with the following drawings, in which:
Figure la is a block diagram of' a basic form of' the in~ention, Figure lb is a wa~eform diagram o~ t~e pre~erred embodiment of the invention, and Figure 2 is the schematic o~ a pre~erred ambodir.l~nt.
DE~AILE~ DESCRIPTION OF THE I~ENTIOM
Turning now to Figure la, a logical block diagram shows basic apparatus essential to an understandi.ng of the manner in which the in~ntion is implemented in more detailed apparatus to be explained later.
An input source of suppressed clock modulated signal with frequency and phase deviations which is intended to have data clock signal regenerated is applied to inputs of' delay device 1 and window generator 2. The output of delay device 1 is connected to one input of f'requency/phase detector 4. The output of the windo~ generator 2 prPvides a control signal enabling an edge signal of f'eedback clock through at the feedback clock sampling latch 3. This feedback clock is coming from voltage controllad oscillator 6. Output of feedback clock ~ampling latch 3 is connected to ano~her input of the frequency/phase detector 4 and -to an input of window generator 2 so as to reset it. Output o~ the frequ6ncy /phase detector 4 is filtered 'by a low pass filter 5. Filter's output is connected to input of voltage controll~d oscillator 6.
When the delayed input signal receeds the qampling latch 3's output, there i5 a positive pulse output from the frequency/phase detector ~ with the duration representing the p~ase di~ference. When the sampling latch~s output preceeds the delayed input, there is a negative pulse ouput from frequenc~/phase detector 4. Where there is no phase differe-nce or no phase comparison, ou~put o~ frequency/phase detector 4 is off. Detail action can be observed in Figure lb.
'F~rthermorè, detector 4 also provides a means to detect ~requency dif~erence between two inputs for a case of start-up or a sudden change of input!s ~requency.
The detector's output is smoothed by the low pass filter 5 before reaching the voltage controlled oscillator 6.
~he filter may be implemented in passive or active form.
Turning now to ~igure 2, a detailed logic diagram of the preferred form of the invention is shown.
The clock suppressed modulated input signal is applied to input terminal of hal~ clock period delay device 10 and clock C termianl of window generator flip flop 11. If the input signal's pulse duration is assumed to be about ~0 percentt the next opposite-edge of the signal can be used as the hal~ clock period'delayed signal. m that case, half clock period delay device 10 can be replaced by an in~erter.
`~~` The Q output of flip flop 11 is connected to ~Q D terminal of flip flop 12. The Q ou~put of flip flop 11 is connected to reset R terminal of flip flop 12. ~he Q output of flip flop 12 is connected to reset R terminal of flip flop 11 and an input o~ fr~quenc~/phase detector 13. The output terminal of delay device 10 is connec~ed to another input of frequency/
phase detector 13~ The output termi~al o~ frequency/phase detector 13 is connected to an input of a low pass filter 14.
The output terminal of the low pass filter 14 is connected to an input terminal of the voltage controlled oscillator 15.
Resistor 16 is used to control the maximum frequency generated by voltage controlled oscillator 15. rl~aximum frequency shoula be less than two times the average of the recovered data clock rate preventing locking to a higher harmonic frequency.
Resistor 18 is used to control the minimum ~requency generated by voltage con~rolled oscillator 15. Minimum ~requency should be more than half t~e average of t~e recovered data clock rate providing a start-up fast acquisition and preventing locking to lower harmonic frequenc~. ~he output terminal of voltage controlled oscillator 15 is connected to clock C terminal of sampling latch flip flop 12~ In a successful prototype, the frequency/phase detector 13 was CD4046B which included the charge-pump tri-state device and voltage controlled oscillator inside. Of course, other equivalent device or discrete logic can also be used. Flip flops ll and 12 are CD4013B.
In operation, the positive edge of input signal causes window generator flip flop 11 output high. The feed-back signal from voltage controlled oscillator 1~ sampling -r~
J
~7~
~`~`' this ~ P signal to cause the sampling latch 12 output high.
Thus this high transition is frequency/phase compared with the hal~ clock delayed positive edge of input signal by frequency/
phase detector 13. At the sametime, sampling latch 12 Q
output is fed to reset the window generator flip flop 11 and then the sampling latch 12 itself. ThUS there is a narrow pulse generated at latch 12 Q output for frequency/phase comparison. The reset of flip flop 11 using a narrow pulse is to provide the capability of tracking of an instant ~180 degrees phase step input. During transitions comparison period, the frequency/phase error signal is generated from the oub,put of detector 15 in order to charge or discharge the low pass ~ilter 14. ~he filtered signal is applied to input of voltage controlled oscillator 15 to cause its frequency output compensated. During zero data period, there is no transition applied to detector 15 and thus its output is off. And the low pass filter 14 will latch the last f;ltered DC output.
The output of voltage controlled oscillator 15 as the recovered data clock is also fed back to clock ~ input of sampling latch 12.
A suppressed clock extraction circuit applying a phase lco~d loop has been described. Various modifications may appear to those skilled in the art possible without departing from the spirit of the invention.
.~
Claims (4)
EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED BY ME ARE
DEFINED AS FOLLOWS:
1. A system for suppressed clock extraction by a phase locked loop comprising:
a) an input source of digital suppressed clock modulated signal with frequency and phase deviations, b) a half clock period delay device delaying inputing signal of hair a data clcok period, c) a window generator converting the said input source's edge signal to a level form signal, d) a sampling latch being enabled by the said level form signal from window generator permitting an edge signal of later defined feedback clock signal through, e) a frequency/phase detector circuit with a tri-state charge-pump device included comparing the said sampling latch output and the said delayed input signal for providing a frequency/phase difference error output, f) a low pass filter smoothing the said frequency/phase error output into a direct current signal, g) a voltage controlled oscillator receiving the said filtered error signal for providing a corresponding frequency output as the recovered data clock, and h) the said recovered data clock feeding back to an input of said sampling latch as the feedback clock signal.
a) an input source of digital suppressed clock modulated signal with frequency and phase deviations, b) a half clock period delay device delaying inputing signal of hair a data clcok period, c) a window generator converting the said input source's edge signal to a level form signal, d) a sampling latch being enabled by the said level form signal from window generator permitting an edge signal of later defined feedback clock signal through, e) a frequency/phase detector circuit with a tri-state charge-pump device included comparing the said sampling latch output and the said delayed input signal for providing a frequency/phase difference error output, f) a low pass filter smoothing the said frequency/phase error output into a direct current signal, g) a voltage controlled oscillator receiving the said filtered error signal for providing a corresponding frequency output as the recovered data clock, and h) the said recovered data clock feeding back to an input of said sampling latch as the feedback clock signal.
2. A system for suppressed clock extraction by a phase locked loop as defined in claim 1 wherein:
a) a short duration pulse is generated at the sampling latch output for every permitted edge signal of feedback clock, b) the said frequency/phase detector is disabled for phases comparison during input signal zero data period and providing an almost ? 180 degrees phase tracking range during ones data period, c) the said voltage controlled oscillator consisting of an adjustment means to limit its maximum frequency output within two times of average said recovered data clock for preventing locking to higher harmonic frequency, and d) the said voltage controlled oscillator consisting of an adjustment means to limit its minimum frequency output more than half of average said recovered data clock for providing fast acquisition and preventing locking to lower harmonic frequency.
a) a short duration pulse is generated at the sampling latch output for every permitted edge signal of feedback clock, b) the said frequency/phase detector is disabled for phases comparison during input signal zero data period and providing an almost ? 180 degrees phase tracking range during ones data period, c) the said voltage controlled oscillator consisting of an adjustment means to limit its maximum frequency output within two times of average said recovered data clock for preventing locking to higher harmonic frequency, and d) the said voltage controlled oscillator consisting of an adjustment means to limit its minimum frequency output more than half of average said recovered data clock for providing fast acquisition and preventing locking to lower harmonic frequency.
3. A system for suppressed clock extraction by a phase locked loop as defined in claim 1 or 2 wherein:
a) the window generator is reset by the presence of the sampling latch output, and b) the sampling latch is reset after the said window generator is reset.
a) the window generator is reset by the presence of the sampling latch output, and b) the sampling latch is reset after the said window generator is reset.
4. A method of extracting a suppressed clock signal from a digital clock signal from a digital modulated data stream with frequency and phase deviations, comprising:
providing a phase/frequency comparing through a detector to the input signal during ones data period with a regenerated data clock and a filter to smooth the detector's error output, floating said detector's output during zero data input and holding the previous latched error signal in said filter, compensating a limited range voltage controlled oscillator by said filter's output to generate the required data clock, and, limiting said oscillator's maximum frequency output less than twice the normal data clock rate and minimum frequency more than half the normal data rate to prevent locking to harmonic.
providing a phase/frequency comparing through a detector to the input signal during ones data period with a regenerated data clock and a filter to smooth the detector's error output, floating said detector's output during zero data input and holding the previous latched error signal in said filter, compensating a limited range voltage controlled oscillator by said filter's output to generate the required data clock, and, limiting said oscillator's maximum frequency output less than twice the normal data clock rate and minimum frequency more than half the normal data rate to prevent locking to harmonic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000400188A CA1179024A (en) | 1982-03-31 | 1982-03-31 | Suppressed clock extraction by a phase locked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000400188A CA1179024A (en) | 1982-03-31 | 1982-03-31 | Suppressed clock extraction by a phase locked loop |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1179024A true CA1179024A (en) | 1984-12-04 |
Family
ID=4122481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000400188A Expired CA1179024A (en) | 1982-03-31 | 1982-03-31 | Suppressed clock extraction by a phase locked loop |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1179024A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0429912A2 (en) * | 1989-11-15 | 1991-06-05 | National Semiconductor Corporation | Synchronisation with the edge transition insensitive delay line |
-
1982
- 1982-03-31 CA CA000400188A patent/CA1179024A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0429912A2 (en) * | 1989-11-15 | 1991-06-05 | National Semiconductor Corporation | Synchronisation with the edge transition insensitive delay line |
| EP0429912A3 (en) * | 1989-11-15 | 1992-04-29 | National Semiconductor Corporation | Synchronisation with the edge transition insensitive delay line |
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