KR100275919B1 - A signal clock recovery circuit and method for multi-level modulated signals - Google Patents

Abstract

PURPOSE: A symbol clock recovery circuit of a multi-level modulation signal and a method thereof are provided to overcome problems in early-late clock recovery and to simplify hardware by enabling a symbol clock recovery of a multi-level signal. CONSTITUTION: A signal input to a late sampler(11), an early sampler(13) and an on-time sampler(21) are output to a timing error detector(22). The output of the timing error detector(22) is input to a voltage control oscillator(17). The output of the voltage control oscillator(17) is input to an early-late-on-time clock generator(23). The output of the early-late-on-time clock generator(23) is input again to the late sampler(11), the early sampler(13) and the on-time sampler(21).

Description

Symbol Clock Recovery Circuit and Method for Multi-Level Modulated Signals

The present invention relates to a circuit and a method of restoring a symbol clock of a multi-level modulated signal.

In general, in order to synchronize the output side with respect to the multi-level input signal, it is preferable to control the input signal to be constantly input.

In the related art, a direction in which the difference is eliminated by using an energy difference between a rate sample and an early sample with respect to an input signal using a symbol clock recovery circuit as shown in the block diagram of FIG. Timing was controlled to restore the symbol clock.

In other words, the circuit is an example of a broadband synchronization circuit, and works well with binary modulation schemes, and can be used for multi-level modulation signals. Early Gate and Late Gate are Early and Rate values by T (symbol rate) / 4 amount based on the optimum point in each section of one symbol. Is sampled by the early sampler 13 and the rate sampler 11 and squared by the squarers 12 and 14, respectively, and the difference between them is obtained by the subtractor 15 to obtain a timing error. Filtering with the filter 16, and applying this signal to the input of the VCO (7), the clock is controlled by an amount corresponding to the timing error.

Then, using the output of the voltage-controlled oscillator 17, the early-rate timing extractor 18 uses a clock and on-time to select early samples and late samples. ) Generates a signal. If the Early Sampling value is greater than the Rate Sampling value, this means that the Recovered Clock is sampling later, and the Early Sampling value is the Rate Sampling. If it is smaller than the value, it means that the recovered clock is sampling early. If the early sampling value is larger than the rate sampling value, the recovered clock is sampled early. If the early sampling value is smaller than the rate sampling value, the sampling is adjusted to sample the recovered clock later.

However, in the conventional method, as shown in the signal operation waveform diagram of FIG. 3b, when only two slopes of the reference point are used, both slopes of +3 symbol and +1 symbol, and +1 symbol when it leads to +3 symbol When using, the timing is controlled by tracking in the opposite direction we want.

For example, ε _{k, sym} is the timing error at time k, y _{k, sym} is the symbol value at time k, y _{k + 1, sym} is the symbol value at time k + 1, y _{k-1 , sym} is called a symbol value at time k-1, where the symbol value is a Nyquist point for symbol decision, ε _{k, sym} = (y ² _{k + 1, sym-} y ² _{k-1, sym)} When the equation wherein d is also arbitrary values, _{3a y k + 1, sym =} 1.5, y k-1, sym = 2.5, wherein ^{_{ε k, sym = (1.5 2}} - 2.5 2) = - It becomes 4 and tracks correctly. On the other hand, in the Figure 3b a random value _{y k + 1, sym = 2.5} , y If _{k-1, sym} = 1.5 _{d, ε k, sym = (2.5} 2 - 1.5 2) = is the +4 track in the reverse direction (Tracking Sometimes, right and sometimes vice versa, there is an Adjust Error. In order to solve this problem, a modified early-late symbol clock recovery method using high-speed sampling (Sampling) per symbol and extracting peaks and then using left and right gradients has been proposed. The exact slope can be known only when a lot of sampling is performed per symbol. Furthermore, since the early samples are added around the peak value and the late samples are added, It is complicated and there is a problem that timing control is not performed at a point not a peak.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and includes a symbol such as Quadrature-Carrier Amplitude Modulation (QAM) or Multi-Level Frequency Shift Keying (FSK) signal. When this possible value is multi-level, more stable, faster synchronization is achieved, and hardware implementation is to provide a simple symbol clock recovery algorithm.

1 is a block diagram of a conventional basic early-late symbol recovery (ELCR) circuit.

2 is a circuit block diagram for a symbol clock recovery method according to the present invention.

3A is a first exemplary diagram of a 4-level signal operation waveform;

3B is a second exemplary diagram of a 4-level signal operation waveform;

3C is a third exemplary waveform diagram of a 4-level signal operation.

<Description of the code | symbol about the principal part of drawing>

11: Late Sampler

12, 14: squarer

13: Early Sampler

15: Subtracter

16: Low-pass filter (LPF)

17: voltage-controlled oscillator (VCO)

18: Early-Rate Timing Extractor

21: On-Time Sampler

22: Timing Error Detector

23: Early-Rate-Time Clock Generator

In order to achieve the above object, the method of the present invention basically uses a Nyquist point using not only a Rate Sample, an Early Sample, but also an On-Time Sample. By extracting the peak from the center, the sign of the on-time signal is differently determined according to whether it is a positive peak (PP) or a negative peak (NP), and the sign is changed. Timing Error is extracted by multiplying the On-Time signal by the difference between the Early Sample value and the Rate Sample value, and when the peak is not clear. Time signal is multiplied by the difference between the Early Sample value and the Rate Sample value to extract a timing error to control the clock to restore the symbol clock.

Meanwhile, in the circuit of the present invention, as shown in the block diagram of FIG. 2, the outputs of the rate sampler 11, the early sampler 13, and the on-time sampler 21 to which a signal is input are input to the timing error detector 22. The output of the timing error detector 22 is input to the low pass filter 16, the output of the low pass filter 16 is input to the voltage controlled oscillator 17, and the output of the voltage controlled oscillator 17 is Input to the early-rate-timed clock generator 23, and the output of the early-rate-timed clock generator 23 is input to the rate sampler 11, the early sampler 13 and the on-time sampler 21 again. It is composed. Here, instead of the early sampler 13, the rate sampler 11, and the on-time sampler 21, one sampler is used, and the output of the early-rate-timed clock generator 23 is used to generate an early sample ( Early Sample, Late Sample and On-Time Sample can be selected and used as the input of the timing error detector 22.

Hereinafter, the operation of the present invention having the configuration as described above.

First, when an input signal is input, the clock output from the voltage controlled oscillator 17 is transferred from the early-rate-time clock generator 23 to an early clock, a late clock, and an on-time clock. Is generated to sample the input signal from the early sampler 13, the rate sampler 11, and the on-time sampler 21 and input it to the timing error detector 22. Then, the timing error ε _{k, sym} is obtained, where the operation of the timing error detector 22 is as follows.

First, the slope is extracted around the Nyquist Point to determine whether the peak is a positive peak or a negative peak. here

SL (Left Slope) = (y _{k, sym} -y _{k-1, sym} )

SR (Right Slope) = (y _{k + 1, sym} -y _{k, sym} )

when,

PP (Positive Peak): (SL> 0) & (SR <0)

NP (Negative Peak): (SL <0) & (SR> 0)

to be.

Once the peak is determined as described above, the timing error ε _{k, sym} can be extracted using the sign of the peak _value.In this case, if the peak is not clear, early sampling is performed. Timing is always correctly controlled by the following logic by multiplying the difference between the rate sampling and the rate sampling by the sample value of the on-time sampling to extract the timing error ε _{k, sym} . can do.

First, in case of positive peak, that is, in case of [SL> 0] & [SR <0]

if y _{k, sym} > 0: ε _{k, sym} = y _{k, sym} (y _{k + 1, sym} -y _{k-1, sym} )

if y _{k, sym} <0: ε _{k, sym} = -y _{k, sym} (y _{k + 1, sym} -y _{k-1, sym} )

On the other hand, in case of negative peak, that is, in case of [SL <0] & [SR> 0],

if y _{k, sym} > 0: ε _{k, sym} = -y _{k, sym} (y _{k + 1, sym} -y _{k-1, sym} )

if y _{k, sym} <0: ε _{k, sym} = y _{k, sym} (y _{k + 1, sym} -y _{k-1, sym} )

On the other hand, if there is no peak

ε _{k, sym} = y _{k, sym} (y _{k + 1, sym} -y _{k-1, sym} )

The timing error signal ε _{k, sym is} then low-pass filtered by the low pass filter 16 and then controlled by the voltage controlled oscillator 17 to adjust the timing.

Therefore, according to the present invention, it is possible to overcome the problems caused by the early-late clock recovery method, and unlike the modified early-late clock recovery method, the peak is different. Even if it's not obvious, good timing control is possible, and timing recovery can be achieved with more than three samples per symbol, so quadrature-carrier amplitude modulation (QAM) or multi-level frequencies. It can be applied as a symbol clock recovery method of a multi-level signal, such as a frequency shift keying (FSK) modulated signal, and it can be implemented with relatively simple hardware.

Claims (3)

In the symbol clock recovery circuit of a multi-level modulation signal, a rate sampler 11, an early sampler 13, a timing sampler 21, a timing error detector 22, a low pass filter 16, a voltage controlled oscillator 17, And an output of the rate sampler 11, the early sampler 13, and the on-time sampler 21, to which the signal is input, to the timing error detector 22. The output of the timing error detector 22 is input to the low pass filter 16, the output of the low pass filter 16 is input to the voltage controlled oscillator 17, and the output of the voltage controlled oscillator 17 is early-rate. -Input to the on-time clock generator 23, and the output of the early-rate-time clock generator 23 is configured to be input to the rate sampler 11, the early sampler 13 and the on-time sampler 21 again. Symbol clock recovery circuit for multi-level modulation signals The output of the early-rate-time clock generator 23 according to claim 1, wherein one sampler is used in place of the early sampler 13, the rate sampler 11, and the on-time sampler 21. Symbol clock recovery of a multi-level modulated signal characterized in that early samples, late samples, and on-time samples are selected and used as inputs to the timing error detector 22 using Circuit In the symbol clock recovery method of a multi-level modulated signal, a peak is extracted around a Nyquist point to determine whether it is a positive peak or a negative peak. On-Time Signals are Differently Signed and On-Time Signals with Altered Signs are Multiplied by the Difference Between Early Sample and Late Sample Values ), And when the peak is not clear, Timing Error is extracted by multiplying the On-Time signal by the difference between the Early Sample value and the Rate Sample value. A symbol clock recovery method for a multilevel modulated signal characterized in that

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