JPS63178642A - Carrier extracting circuit - Google Patents

Abstract

PURPOSE:To attain the pullin setting at high speed by generating a sweeping signal digitally. CONSTITUTION:The counter of a controller 11 starts counting from a proper initial value. For example, a digital value at that time is sent sequentially at a proper time interval starting from a digital value corresponding to a low frequency or a digital value corresponding to a center frequency. The interval of the digital value and its generating interval are selected larger than the synchronizing signal interval and the sweeping width is selected to be nearly twice as much as the loop band. They are selected with no adjustment and high accuracy together with the sweeping speed. The interval of the digital value and its generating interval in the counting of the counter at the synchroniz ing state are selected smaller than those at the asynchronous state and the sweeping band is made narrower by a loop filter 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a carrier extraction circuit used in a demodulator for digital satellite communication, and particularly relates to an improvement of a carrier extraction circuit mainly composed of a phase-locked loop. .

(Prior Art) As a conventional carrier extraction circuit mainly composed of a phase-locked loop, the one shown in FIG. 2, for example, is known. This carrier extraction circuit includes mixers 1 and 2, low-pass filters 3 and 4, a phase detector 5, a loop filter 6, a voltage adder 7, a voltage-controlled oscillator 8, 90°
It basically consists of a shifter 9, a synchronization detector 10, and a sweeper 14.

A phase shift keying (PSK) modulation signal is applied to the input terminal T, and this PSK modulation signal becomes one input of mixers 1 and 2. The other input of mixer 1 is the output of voltage controlled oscillator 8, and the other input of mixer 2 is the output of 90° shifter 9, which phase shifts the output of voltage controlled oscillator 8 by 90°.

As a result, a baseband signal appears at the output of mixers 1 and 2, and this baseband signal is passed through the low-pass filter 3.
In step 4, waveform shaping and noise reduction are performed.

The outputs of the low-pass filters 3 and 4 are sent to a phase detector 5 and a synchronous detector 10. Note that the outputs of the low-pass filters 3 and 4 are also sent to the outside, and these are demodulated signals for demodulating and forming data during synchronization.

Phase detector 5 detects a phase error between the outputs of low-pass filters 3 and 4, and sends it to loop filter 6.

On the other hand, the synchronization detector 10 detects whether synchronization is achieved based on the outputs of the low-pass filters 3 and 4, and sends the result to the loop filter 10 and the sweeper 14 as a control signal.

Loop filter 6 provides an output voltage corresponding to the phase error signal output from phase detector 5 to one input of voltage adder 7 . It is well known that this loop filter changes its loop bandwidth to a narrower one when the output of the synchronization detector 10 indicates "synchronization detection".

The voltage adder 7 has the other input supplied with the sweep signal from the sweeper 14, and supplies the result of addition of both inputs to the voltage controlled oscillator 8 as a control voltage.

Here, the sweeper 14 is configured to establish synchronization early, considering that the difference between the input frequency and the output frequency of the voltage-controlled oscillator 8 is larger than the loop bandwidth due to the poor stability of the local oscillator on the satellite. It was established with the aim of

In addition, in satellite communications, there are situations where the input signal is "disconnected", and in order to avoid the waste of redoing the synchronization operation when it recovers, the sweep is sometimes stopped when synchronization is achieved. shows that.

A triangular wave voltage signal is used as the sweep signal, and the synchronous detector 1
This is applied to the other input of the voltage adder 7 during the period when the output of 0 indicates "synchronization not detected". Further, when the output of the synchronization detector 10 indicates "synchronization detection", the signal level value of the sweep signal at that time is held and applied to the other input of the voltage adder 7. For example, a sample and hold circuit is used as the holding means.

The carrier wave is extracted and regenerated from the input PSK modulated signal by the action of the phase-locked loop described above, that is, the voltage controlled oscillator 8
A regenerated carrier wave is obtained at the output of

Then, in mixers 1 and 2, a baseband demodulated signal is obtained from the input PSK modulated signal based on the recovered carrier wave, and this is sent to the outside via low-pass filters 3 and 4, and desired demodulated data is obtained. This will be obtained.

(Problem that the invention attempts to solve) Conventional carrier wave extraction circuits have the following problems.

First, since the inserter is designed to generate a triangular wave voltage signal, which is an analog signal, as a sweep signal, the content of the sweep is fixed and cannot be selected and set arbitrarily, and the sweep width and Setting the sweep speed with high precision requires a lot of adjustment time and is difficult.

Next, since the sweep signal is an analog signal, even if the signal level is held by a sample-and-hold circuit, the holding level fluctuates due to "discharge."

Therefore, it is difficult to maintain the frequency of the voltage controlled oscillator when the input signal is "cut off".

Furthermore, in conventional circuit configurations, a large loop gain is required to compress the error between the frequency of the input signal and the frequency of the voltage-controlled oscillator during synchronization, that is, the steady-state phase error, to a negligible level. If the error becomes very large, it may become impossible to achieve the required loop gain.

The present invention was devised in view of these conventional problems, and its purpose is to perform arbitrary sweeps, increase the accuracy of the sweep width and sweep speed without adjustment, and increase the loop gain. It is an object of the present invention to provide a carrier wave extraction circuit that can at least make the steady state consultation difference less than or equal to a predetermined value.

(Means for Solving the Problems) In order to achieve the above object, the carrier extraction circuit of the present invention has the following configuration.

That is, the carrier wave extraction circuit of the present invention is mainly configured with a phase-locked loop and is used in a demodulator for digital satellite communication to extract and reproduce a carrier wave for demodulating data from an input modulated signal from the input modulated signal. A sweep signal is generated in response to the output of a synchronization detector that detects whether or not synchronization is achieved based on the demodulated signal, and the control voltage of a voltage controlled oscillator that generates a regenerated carrier wave is connected to the sweep signal and the loop filter. a frequency deviation detector for detecting an input frequency deviation from the output voltage deviation of the loop filter; When the output of the synchronization detector indicates "synchronization detection," digital values for giving each level value of the sweep signal are generated at appropriate time intervals, and when the output of the synchronous detector indicates "synchronization detection," the frequency deviation detection a controller that generates a required digital value at an appropriate time interval different from the time interval based on the output of the controller; converting the output of the controller into an analog signal and transmitting it to the loop filter; A carrier wave extraction circuit is characterized by comprising: a digital-to-analog converter that generates a sweep signal to be added to the output voltage of the carrier wave extracting circuit.

(Function) Next, the function of the carrier wave extraction circuit of the present invention configured as described above will be explained.

During the synchronization pull-in process, the output of the synchronization detector indicates "synchronization not detected". Therefore, the controller generates digital values at appropriate time intervals to provide each level value of the extra signal.

A digital-to-analog converter converts each of these digital values into an analog signal, which becomes a sweep signal. At this time, the interval and generation interval of each digital value can be arbitrarily selected. Further, at the time of initial pull-in, an arbitrary sweeping method is possible, such as starting from any digital value or starting from a larger value toward a smaller value.

Furthermore, the sweep width can be made approximately twice the loop bandwidth, and the sweep width and sweep speed can be set to predetermined values with high accuracy without adjustment.

Therefore, the pull-in operation is performed at high speed in the synchronous pull-in process.

When synchronization is established, the output of the synchronization detector is "r period detection", so that the controller generates the required digital value at least at a time interval different from said time interval based on the output of the frequency deviation detector.

This becomes the sweep signal. During synchronization, the loop filter has a narrow band, so the loop bandwidth also becomes narrow.
Correspondingly, the sweep width can also be made smaller. In addition, the interval and generation interval of each digital value can be made smaller than in the above case, and the sweep method should be appropriate depending on the output state of the frequency deviation detector (deviation in the positive direction or negative direction, etc.). be able to.

Therefore, in this circuit, the loop gain does not need to be very large, so stable operation can be expected, and even if the deviation between the input frequency and the frequency of the voltage-controlled oscillator is large, the steady-state phase error will be larger than a certain value. Note that whether or not to stop the sweep at the time of synchronization is based on the system specifications, but in the present invention, the sweep signal is generated digitally, so it can be stably maintained when the sweep is stopped.

Therefore, synchronization can be performed at high speed when the input signal is cut off and then recovered.

As described above, according to the carrier wave extraction circuit of the present invention, since the sweep signal is generated digitally, arbitrary sweep can be performed, and if necessary, the sweep can be easily stopped, and its retention can be stabilized. Therefore, synchronization pull-in can be performed at high speed.

High accuracy can be achieved without adjusting the sweep width or sweep speed. Further, since the content of the sweep at the time of synchronization can be determined according to the input frequency deviation, the loop gain does not need to be so large, and stable operation can be expected. At this time, there is an advantage that even if the deviation between the input frequency and the frequency of the voltage-controlled oscillator is large, the steady-state consultation difference does not become larger than a certain value.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a carrier extraction circuit according to an embodiment of the present invention. Components that are the same as those of the conventional circuit shown in FIG.

This carrier extraction circuit includes a controller 11 that generates required digital values at appropriate time intervals, converts the output digital value of the controller 11 into an analog signal, and supplies it as a sweep signal to the other input of the voltage adder 7. Frequency deviation detection that detects the input frequency deviation from the output voltage deviation of the digital-to-analog converter 12 and the loop filter 6, and sends the detected contents to the controller 11 as, for example, two control signals a. A container 13 is provided. Note that two control signals C1 and d are inputted to the controller 11 from the synchronization detector 10. The control signal C is a signal indicating whether or not synchronization has been achieved, and is also input to the loop filter 6. The control signal d is a command signal for stopping and canceling the sweep, and for example, the input signal ``
A stop command is issued when the system is disconnected, and a release command is issued when the system recovers.

The controller 11 can be configured in various ways, but in this embodiment, it is mainly configured with a counter. This counter can freely count up and count down, and the count value of this counter is digital.
applied to analog converter 12;

At the initial pull-in, the content of control signal C is "synchronization not detected"
Therefore, the controller 11 ignores the output of the frequency shift detector 13 and performs the following operation.

That is, the counter of the controller 11 starts counting operation from an appropriate initial value. For example, starting from a digital value corresponding to a low frequency or a digital value corresponding to a center frequency, the counter starts counting from the current digital value at appropriate time intervals. are sent out sequentially. At this time, the interval between digital values and the interval between occurrences are made thicker than during synchronization, and the sweep width is approximately twice the loop band. It is clear that these can be done without adjustment and with high accuracy along with the sweep speed.

In this way, a quick pull-in operation is performed and a synchronized state is achieved. At the time of synchronization, the content of the control signal C indicates "synchronization detection", so the controller 11 changes the output state of the frequency deviation detector 13,
In other words, it operates as follows depending on the contents of the control signal a. That is, the contents of the control signal a are the same as those of the loop filter 6.
When the output voltage deviation is within a predetermined range, it becomes rl, OJ or "0°1," and when the output voltage deviation is in the positive direction, it becomes rl, IJ, and conversely, when the output voltage deviation is negative. It is assumed that a transition in the direction can be distinguished by ro and OJ.

Then, when the control signal a is "1°0" or ro, IJ, the counter holds and outputs the count value at that time, and when it is "rl, i", the counter outputs the count value at that time as the starting point. It counts, and conversely, in the case of ro or OJ, it counts down from the count value at that point in time.

In this way, the output voltage of the loop filter is controlled to always fall within a predetermined range. In other words, the loop gain does not need to be very large, the control system can easily operate stably, and even if the deviation between the input frequency and the output frequency of the voltage controlled oscillator 8 becomes large, the steady-state phase error will be less than a certain value. It also does not become large.

In addition, regarding the counting operation of the counter during synchronization, the interval of digital values and the interval of generation are smaller than those during non-synchronization, and the sweep width corresponds to the narrow band of the loop filter 6. shall be. As described above, these can be performed with high precision and without adjustment of the sweep speed.

Next, when the input signal becomes "off" during synchronization, the control signal C
indicates "synchronization not detected" and the control signal d indicates "sweep stop", so the counter of the controller 11 holds and outputs the count value at that time.

Since this held output can be performed stably for any time, the output frequency of the voltage controlled oscillator 8 can be stably held for any time. Then, when the input signal appears again, the control signal d indicates "release", so that the counter of the controller 11 can start counting from, for example, a slightly lower value than the held value.

In this way, the pull-in at the time of input signal recovery is performed at high speed.

(Effects of the Invention) As detailed above, according to the carrier wave extraction circuit of the present invention, since the sweep signal is generated digitally, arbitrary sweeping can be performed, and if necessary, sweeping can be easily stopped. Since this can be done and held stably, synchronization can be pulled in at high speed. High accuracy can be achieved without adjusting the t8 width or sweep speed. In addition, the content of the sweep during synchronization can be determined according to the input frequency deviation, so
The loop gain does not need to be very large, so
Stable operation can be expected. At this time, there is an advantage that even if the deviation between the input frequency and the frequency of the voltage-controlled oscillator is large, the steady-state phase error does not become larger than a certain value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a carrier extraction circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional carrier extraction circuit. 1.2...Mixer, 3,4...Low pass filter, 5...Phase detector, 6...
...Loop filter, 7...Voltage adder,
8...Voltage controlled oscillator, 9...9
0° deviation device, 10...Synchronization detector, 11.
...Controller, 12 ...Digital-to-analog converter, 13 ...Frequency deviation detector,
T...Input terminal. Agent Patent Attorney Yoshiyoshi Hachiman Hiromi's bald trimming and payment without payment - A great example of the withdrawal of repayments 1st figure 1
] (Column A, Figure 2)

Claims (1)

[Claims] A digital satellite communication demodulator mainly composed of a phase-locked loop is used to extract and reproduce a carrier wave for demodulating data from an input modulated signal from the input modulated signal, and is synchronized based on the demodulated signal. A sweep signal is generated in response to the output of a synchronous detector that detects whether or not the carrier wave is detected, and the control voltage of a voltage controlled oscillator that generates a regenerated carrier wave is formed by adding the sweep signal and the output voltage of the loop filter. In the carrier extraction circuit, the frequency deviation detector detects the input frequency deviation from the output voltage deviation of the loop filter; and when the output of the synchronization detector indicates "synchronization not detected", generating digital values for giving each level value at appropriate time intervals, and when the output of the synchronization detector indicates "synchronization detection", at least the time interval based on the output of the frequency deviation detector; a controller for generating a required digital value at appropriate time intervals different from the controller; converting the output of the controller into an analog signal and using it as a sweep signal to be added to the output voltage of the loop filter; A carrier extraction circuit comprising: a digital-to-analog converter for generating;