JPS63204837A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the lock time by adding simple circuits such as a crystal oscillator, an input signal detector and a selector to an APLL (analog PLL) circuit. CONSTITUTION:A crystal oscillator 6, a selector 7 and a carrier detection circuit 9 or the like are added to a conventional APLL (analog PLL) circuit. Receiving a reception signal 10, the carrier detection circuit 9 detects the start of reception to control the selector 7 thereby giving a synchronizing pulse obtained from a reception signal by means of a synchronizing pulse extraction circuit 8 to the phase comparator 1. In this case, the carrier detection circuit 9 retards the switching of the selector 7 for sometime until the reception signal is stabilized. In switching the selector 7, the PLL locking is started, but since the recovered clock is nearly equal to the transmission rate at a point of time when the switching is conducted, the phase of the recovered clock is matched to the phase of a reception signal quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a synchronization device that generates a signal that is synchronized in phase and frequency with an input signal.

[Prior Art] For example, when serially transmitting digital data, when the transmission rate is high, modulation is generally performed such as DMI modulation in which the data includes a synchronized clock, that is, digital modulation. Transmit. Figure 2 is DM
This is an example of an I-modulated signal.

On the receiving side, this digitally modulated signal is converted into raw data, that is, N K Z (No K
(eturn to 2ero), and a PLL circuit is generally used to recover a synchronization clock from the modulated signal during this demodulation.

PLL circuits are classified into two types. One is APLL (
One is DPLL (one digital PLL).

FIG. 3 shows a typical block diagram of an APLL circuit.

'The operation will be briefly explained.

The input signal and the regenerated clock, which is the output of the frequency divider, are input to the phase comparator 1, and the phase comparator 1 outputs a difference signal voltage according to the phase difference between the two inputs. When this PLL circuit is used for the data communication described above, the input signal is a synchronization pulse as shown in FIG. 4 obtained from the received signal.

The output difference signal voltage becomes an oscillation control voltage of a voltage controlled oscillator (VCO) 4 through a low-pass filter 2 and an amplifier 3, and the output of the VCO 4 is divided by a frequency divider 5.
It becomes a regenerated clock.

In this way, the APLL matches the phase of the input signal and the reproduced clock by controlling the oscillation frequency of the VCO4, but is this phase matching part completely digitalized using counters, shift registers, etc.? DP
It is LL.

Now, when performing data communication, when data arrives in bursts as in the case of packet communication, and there is a no-signal period or before and after the data as shown in Figure 5, if a PLL circuit is used, From the start of reception until the regenerated clock is synchronized with the received signal, that is, 2 of phase comparator l in Fig. 3.
The time it takes for the phases of two inputs to match (lock time)
becomes a problem.

When performing packet communication, a pattern for synchronization on the receiving side, a so-called preamble pattern, is added to the front of the data as shown in Figure 5. However, if the lock time of the PLL circuit on the receiving side is long, , a long preamble pattern is required, resulting in poor transmission efficiency.

Therefore, if the transmission rate is relatively low, a DPLL circuit with a short lock time is used, or a DPLL circuit operates with a clock that is several to ten times faster than the transmission rate, and the scale of the circuit becomes large. If used for high-rate signals, a large amount of high-speed ICs will be required, making them expensive.

Therefore, there are cases where APLL has to be used due to cost considerations, but in general, conventional APLL circuits have a long lock time, require a long preamble pattern, and have poor transmission efficiency.

[Purpose] The present invention has been made in view of the above points.
By improving the LL circuit, it has become possible to construct a PLL circuit that is inexpensive and has a short lock time.

[Example] The present invention will be explained in detail below.

FIG. 1 is an example of a block diagram of a PLL circuit according to the present invention. A crystal oscillator 6, a selector 7, a carrier detection circuit 9, etc. are added to the conventional APLL circuit shown in FIG.

First, the principle of the present invention will be explained.

One of the reasons for the long lock time of conventional APLL circuits is that the oscillation control voltage of vCO is unstable when there is no signal, so the frequency of the recovered clock deviates considerably from the transmission rate of the received signal. Therefore, after reception has started, the vCO is controlled, and it takes time for the frequency of the reproduced clock to become equal to the transmission rate, resulting in a long lock time.

Therefore, in the present invention, by using a crystal oscillator with an oscillation frequency that corresponds to the transmission rate, the frequency of the regenerated clock 11 is adjusted to the transmission rate even when there is no signal, so that it is quickly locked when reception starts. did.

The operation shown in FIG. 6 will be explained.

First, when there is no signal, the carrier detection circuit 9 detects
No signal is detected. Then, the carrier detection circuit controls the selector 7 and inputs the output of the crystal oscillator 6 to the phase comparator l. Since the oscillation frequency of the crystal oscillator 6 is matched to the transmission rate, the reproduced clock is stabilized at approximately the same frequency as the transmission rate.

Next, when the received signal 10 arrives, the carrier detection circuit 9
or detects the start of reception, controls selector 7,
The synchronization pulse extracted from the received signal by the synchronization pulse extraction circuit 8 is input to the phase comparator 1. At this time, the carrier detection circuit 9 delays the switching of the selector 7 a little until the received signal becomes stable.

When the selector 7 is switched, the locking operation of the PLL starts, but since the regenerated clock is almost equal to the transmission rate at the time of the switch, the phase of the regenerated clock can be quickly adjusted to match the received signal. It is possible to match the phase.

[Effects] As explained above, the lock time can be shortened simply by adding simple circuits such as a crystal oscillator, an input signal detector, and a selector to the conventional APLL circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a PLL circuit according to the present invention, Fig. 2 is a diagram showing a DMI modulation waveform, and Fig. 3 is a diagram of a conventional APLL circuit.
A block diagram of the circuit; FIG. 4 shows the synchronization pulse obtained from the DMI modulation waveform; FIG. 5 shows the flow of data in packet communication; and FIG. 6 shows the beginning of the transmission signal in packet communication. It is a figure showing an example of a part. 1 is a phase comparator, 2 is a low-pass filter, 3 is an amplifier,
4 is a voltage controlled oscillator (VCO), 5 is a period divider, 6 is a crystal oscillator, 7 is a selector, 8 is a synchronous pulse extraction circuit, 9 is an input signal detection circuit, IO is a received signal, and 11 is a reproduced clock. Part 8 Pa I Hong Figure 5

Claims (1)

[Claims] Comprising a phase comparator and a voltage controlled oscillator, the voltage controlled oscillator is controlled by a difference signal voltage according to the phase difference obtained from the phase comparator, and a signal whose phase and frequency are synchronized with the input signal is generated. The synchronous circuit includes an input signal detector, a crystal oscillator, and a selector, the input signal and the oscillation output of the crystal oscillator are input to the selector, and the selected output of the selector is input to the phase comparator. , the input signal detector selects the output of the selector, and in the selection, if the input signal is not present, selects the oscillation output of the crystal oscillator, and if the input signal is present, selects the oscillation output of the crystal oscillator. A synchronization device characterized in that it selects an input signal.