JPH07273648A - Pll circuit - Google Patents

Abstract

PURPOSE:To suppress frequency fluctuation in an output clock signal and phase/ frequency jump by providing a hold-over circuit for feeding back a feedback signal being either a count signal corresponding to a frequency division signal or a count signal corresponding to a hold signal to a phase comparator circuit to the PLL circuit. CONSTITUTION:The PLL circuit is provided with a phase comparator 1, a low pass filter 2 and a VCO 3 the same as those of a conventional PLL circuit and also a hold-over circuit 5 selecting by switchover either an error signal (c) or a hold signal (f) being an error signal (c) in the normal state to be latched corresponding respectively to the normal state or the intermitted state of an input signal (a), giving the selected signal to the low pass filter 2 as a signal Q and feeding back either an output signal B of a counter 6 or a count signal (g) of a counter 55 corresponding to the hold signal (f) to the phase comparation circuit as a feedback signal (b). Then the hold signal (f) being the error signal (c) just before the interruption of the input signal is generated and used to control the VCO 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit for bit synchronization of received data used in a digital transmission device of a synchronous transmission system.

[0002]

2. Description of the Related Art In a communication device for digital data transmission such as a digital transmission device, some bit synchronization must first be taken in order for the receiving side to correctly receive the data transmitted from the transmitting side. This synchronization method includes an asynchronous transmission method, which is also called a start-stop synchronization method, in which start and stop bits added to the beginning and end of each code are used as clues to synchronize with each other, and a change point between each bit of a data signal. There is a synchronization method in which a clock synchronized with the transmission side is generated by the reception side and detected. Except for small-scale data transmission such as a telemeter device, generally, a synchronous transmission method with high transmission efficiency is used. In the synchronous transmission method, a PLL circuit is used to generate the above-described clock signal for synchronization from the received data.

Referring to FIG. 3, which shows a block diagram of a known general first conventional PLL circuit, this conventional PLL circuit consists of an input signal a consisting of a pulse train and a divided signal b from a frequency divider 4. A phase comparator 1 that performs a phase comparison and outputs an error signal c, a low-pass filter 2 that outputs a smoothed signal d by removing high-frequency components of the error signal c, and a clock signal whose frequency is controlled by the signal d. A voltage controlled oscillator (VCO) 3 for generating e and a frequency divider 4 for dividing the clock signal e and outputting a feedback signal b are provided.

In operation, the phase comparator 1 compares the phase difference between the input signal a and the feedback signal b for comparison and outputs an error signal c corresponding to the phase difference. The low-pass filter 2 removes the high-frequency component of the error signal c and generates a smoothed signal d, which is supplied to the VCO 3. VCO 3 generates a frequency controlled clock signal e in response to the voltage level of signal d. This clock signal e is divided by the frequency divider 4 to generate a feedback signal b having the same frequency as the input signal a. The feedback signal b is fed back to the phase comparator 1 to form a closed loop, and the frequency of the output clock signal e is automatically adjusted.

In this first conventional PLL circuit, when the input signal a is interrupted due to a malfunction of the transmission line or the like, the PLL loop is released and the open loop state is established, so that the phase lock control becomes impossible and the output clock signal e. The frequency becomes unstable and becomes unstable. Further, when the input signal is restored, the PLL loop is closed and the initial synchronizing operation is performed again with respect to the input signal a from the above unstable state, so that a frequency jump in which the frequency of the VCO 3 largely fluctuates with this is caused, and the clock signal e The phase fluctuation becomes large.

In order to prevent the loss of synchronization when the input signal is interrupted and the frequency jump when the input signal is restored, some techniques have been conventionally proposed.

A second conventional method disclosed in Japanese Patent Application Laid-Open No. 4-29001 for solving a frequency jump when an input signal is restored.
The PLL circuit uses a double loop type PLL and
The N / 2 frequency-divided pulse of the oscillation frequency is used to hold the control voltage so that the oscillation frequency when the input signal is interrupted is near the center frequency.

Further, in the third conventional PLL circuit described in Japanese Patent Laid-Open No. 64-85426, when the input signal is lost, the output signal of the VCO or the feedback signal which is its frequency-divided signal is also dropped. Thus, the phase comparison operation of the phase comparator is stopped, and the error signal at that time is supplied to the VCO as a control signal to prevent the loss of synchronization.

Further, in the conventional fourth PLL circuit described in Japanese Patent Laid-Open No. 32720/1989, when the input pulse is lost, the VCO supplied to the phase comparator from that time point is supplied.
Counts the number of feedback pulses from 1 to a predetermined count value, holds the VCO control voltage from the loop filter until the input pulse returns, and when the number of input pulses at the time of return reaches the predetermined count value, By releasing the hold state, the large fluctuation of the VCO frequency is suppressed and the relocking time after the recovery is shortened.

[0010]

SUMMARY OF THE INVENTION The conventional PLL described above.
Regarding the circuit, first, the conventional first PLL circuit has a drawback that when the input signal is interrupted, the circuit becomes an open loop state and the phase lock control becomes impossible, so that the frequency of the output clock signal becomes unstable and becomes unstable. is there. Further, when the input signal is restored, the initial synchronization operation from the unstable state is performed by re-forming the closed loop,
Along with this, there is a drawback that a frequency jump in which the clock frequency fluctuates greatly occurs.

A second conventional P for eliminating the above-mentioned drawbacks
Since the LL circuit fixes the oscillation frequency of the VCO at approximately the center value of the frequency control range when the input signal is interrupted, when this center value is significantly different from the input signal frequency at the time of restoration,
The above drawbacks cannot be eliminated. Further, there is a drawback that it cannot be applied to general PLL circuits other than the double loop type.

Further, the third conventional PLL circuit is in an open loop state when the input signal is missing and controls the VCO by fixing it to the control signal when the input signal is missing. Therefore, the oscillation frequency of the VCO is the open loop state. There is a drawback that it is greatly affected by the temperature characteristics of the VCO and loop filter. Further, when the above-mentioned omission occurs for a long time, there is a drawback that the input frequency at the time of restoration does not always match the frequency of the VCO, as in the second conventional PLL.

Further, in the fourth conventional PLL circuit, when the input signal is missing, the PLL loop is formed with the error signal at the time point after the predetermined counting of the feedback pulse as a reference. The frequency change during the period of only the feedback pulse after the loss is large, and at the most, the number of pulses at the time of the loss can be up to about several, and the clock signal for synchronization from the received data in the synchronous transmission system which is the object of the present invention. Is unsuitable for the generation of.

[0014]

The PLL circuit of the present invention is
A phase comparator that outputs a phase error signal by comparing the phase of an input signal and a feedback signal composed of a pulse train of a predetermined frequency, a low-pass filter circuit that smoothes the phase error signal and generates a voltage control signal, A voltage-controlled oscillation circuit that outputs an oscillation signal of a predetermined oscillation frequency in response to the voltage control signal, and a first signal corresponding to the feedback signal that is supplied with the oscillation signal and is divided by a predetermined division ratio. In a PLL circuit including a frequency dividing circuit for generating the phase error signal, the phase error signal and the holding signal in which the phase error signal in the normal state immediately before the interruption is taken in and held corresponding to the normal time and the interruption of the input signal, respectively. One of them is selected and supplied to the low-pass filter, and one of the first signal and the second signal generated from the holding signal is used as the feedback signal for the phase comparison circuit. It is configured to include a holdover circuit to return to.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, which is a block diagram in which components common to those of FIG. 3 are designated by common reference characters / numerals, the PLL of this embodiment shown in FIG. The circuit includes a phase comparator 1 common to the conventional one, a low pass filter 2,
In addition to the VCO 3, the error signal c corresponding to the normal state and the interruption of the input signal a and the holding signal f which is the error signal c which is held in the normal state are switched to switch to the low frequency range as the signal Q. The holdover circuit 5 which supplies the output signal B of the counter 6 and the count signal g of the counter 55 corresponding to the hold signal f to the phase comparison circuit as the feedback signal b while being supplied to the filter 2 and the frequency divider 4. Instead, it is provided with a counter 6 for dividing the maximum count value N that divides the signal e to generate the signal B.

The holdover circuit 5 detects an interruption of the input signal a and generates an interruption signal h, and a control section which generates a control signal i in response to the supply of the interruption signal h and the signal l. 52, a data holding unit 53 that holds the error signal c and reads the held signal f in response to the supply of the control signal i, and compares the error signal c and the held signal f. In the case where j is a small signal c, a signal k is output when the signals c and f are equal to each other, and a comparator 54 which outputs a signal l, and up / down counting is performed in response to the supply of the signals j and k. A counter 55 having a maximum count value N for generating a count value signal g, and a selector for selecting and switching between the error signal c and the hold signal f in response to the supply of the control signal i and outputting the signal Q. 56,
The pulse generator 57 generates the feedback signal b which is a pulse signal only when the signals B and g are equal to each other.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 which is a time chart of the operation.
As shown in FIG. 2A, when the input signal a is normally supplied, the error signal c of the output of the phase comparator 1 is selected by the selection unit 56 and supplied as the signal Q to the low pass filter 2. The low-pass filter converts this signal Q into the conventional PLL described above.
Similarly, the smoothing is performed to generate the signal d to control the VCO 3. The clock signal e from the VCO 3 is output as an output signal and is also supplied to the counter 6. Counter 6
Counts the signal e and generates a signal B corresponding to the count value. This counter 6 is an ordinary binary counter, and the maximum count value N is equal to the frequency division number when dividing the frequency of the clock signal e to the frequency corresponding to the input signal a.
When the count value reaches N-1, it returns to the initial value at the next clock signal. On the other hand, the counter 55 has stopped its operation, and the count value M (0 ≦ M ≦ N−
1) is supplied to the pulse generator 57. Pulse generator 57
Compares the count value of the signal B with the value M of the signal g, and outputs the pulse feedback signal b when the count value of the signal B becomes equal to M.
Therefore, in response to the supply of N clock signals e, 1
Since only a single pulse feedback signal b is generated, the counter 6 and the pulse generator 57 perform the same operation as the frequency divider 4 in the conventional PLL.

As shown in FIG. 2 (b), when the input signal a is interrupted, the interrupt detector 51 detects interrupt and supplies the interrupt signal h to the controller 52. The control unit 52 supplies the control signal i to the selection unit 56 and the data holding unit 53 in response to the supply of the interruption signal h. The data holding unit 53 latches and holds the error signal c immediately before the interruption in response to the supply of the control signal i, and supplies the holding signal f obtained by reading the held data to the selection unit 56 and the comparison unit 54, respectively. To do. Such a circuit having the function of the data holding unit 53 can be realized by a combination of an A / D converter that A / D-converts the duty-corresponding DC voltage level of the error signal c and holds it as digital data, and a shift register. In response to the supply of the control signal i, the selection unit 56 selects the holding signal f output from the data holding unit 53 and supplies it as the signal Q to the low pass filter 2. The comparison unit 54 holds the holding signal f
Only the signal j is supplied and the other input, the error signal c, is interrupted, so that the signals j, k and l are not generated. Therefore, the counter 55 also remains in the operation stopped state, and the signal g remains the count value M at the time of the interruption. As a result, the pulse generator 57 generates the feedback signal b when the count value of the signal B is the count value M as in the normal case.

When the input signal a is restored, the control unit 52 receives the control signal i from the comparison unit 54 until it receives the comparison signal l indicating that the signals c and f are equal to each other.
To keep. As described above, the comparison unit 54 compares the error signal c with the holding signal f and generates the signals j, k, and 1 corresponding to the magnitude relation between these signals c, f.
The signals j and k are supplied to the counter 55, and the counter 55 counts up or down in response to the supply of the signals j and k, respectively, and increases or decreases the count value M of the signal g. Here, as shown in FIGS. 2C and 2D, when the count value of the signal g decreases to M−1, the pulse generator 57 outputs the feedback signal when the count value of the signal B is M−1. b
Is generated, that is, the phase of the clock signal e is adjusted to advance by one pulse. On the contrary, when the count value of the signal g increases to M + 1, the phase of the clock signal e becomes 1
Adjust so that it is delayed by the pulse. As a result, the error signal c which is the output of the phase comparator 1 changes. The comparator 54 again compares the signals c and f with each other and supplies new signals j and k to the counter 55.
The up / down operation corresponding to k is performed, and the above phase adjustment is repeated until the signals c and f coincide with each other and the signal 1 is generated. The control unit 52 stops the supply of the control signal i in response to the supply of the signal l, and the selection unit 56 selects the error signal c again in response to the stop of the supply of the control signal i and outputs it to the low-pass filter 2 as the signal Q. Supply. In this way, since the selector 56 switches to the error signal c after the signals c and f become equal to each other, the phase fluctuation of the VCO does not occur.

[0020]

As described above, the PLL circuit of the present invention selects either the phase error signal or the hold signal as the control signal of the VCO in correspondence with the normal state and the interrupted state of the input signal. By providing a holdover circuit that feeds back either the count signal corresponding to the frequency dividing signal or the count signal corresponding to the above holding signal as a feedback signal to the phase comparison circuit, when the input signal is interrupted, the phase comparison immediately before this interruption is performed. The error signal of the output device is held, the holding signal is generated, and the VCO is controlled by the holding signal to suppress the frequency fluctuation of the output clock signal, and when the input signal is restored, the error signal and the holding signal match. By controlling so that there is an effect that the phase / frequency jump of the output clock signal at the time of restoration can be significantly suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit of the present invention.

FIG. 2 is a time chart showing an example of the operation of the PLL circuit of this embodiment.

FIG. 3 is a block diagram showing an example of a conventional PLL circuit.

[Explanation of symbols]

 1 Phase Comparator 2 Low-pass Filter 3 VCO 4 Divider 5 Holdover Circuit 6,55 Counter 51 Interruption Detection Section 52 Control Section 53 Data Holding Section 54 Comparison Section 56 Selection Section 57 Pulse Generation Section

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H04L 25/40 C 9199-5K

Claims (2)

[Claims] 1. A phase comparator for phase-comparing an input signal composed of a pulse train of a predetermined frequency and a feedback signal and outputting a phase error signal, and a low-frequency comparator for smoothing the phase error signal to generate a voltage control signal. Band filter circuit, a voltage controlled oscillator circuit that outputs an oscillation signal of a predetermined oscillation frequency in response to the voltage control signal, and a supply of the oscillation signal and frequency division at a predetermined frequency division ratio to support the feedback signal And a frequency divider circuit for generating a first signal of 1), in which the phase error signal and the normal phase error signal immediately before the interruption are taken in and held corresponding to the normal time and the interruption of the input signal, respectively. One of the held signal is selected and supplied to the low-pass filter, and one of the first signal and the second signal generated from the held signal is used as the feedback signal. PLL circuit, characterized in that it comprises a holdover circuit for feeding back the serial phase comparator. 2. A hold detection circuit, wherein the holdover circuit detects a break in the input signal and generates a break signal, and a control signal generated in response to the supply of the break signal, and the control is performed by a first comparison signal. A control unit that stops the signal, and a data holding unit that holds the error data that is the digitized DC voltage corresponding to the phase error signal and that reads the held data that is the held error data in response to the supply of the control signal. And comparing the error data and the held data and comparing the error data and the held data with each other, the first comparison signal corresponding to the case where the error data is larger and the case where the error data is smaller. Corresponding second and third
Comparing unit for outputting the second comparison value signal, and for generating a second count value signal corresponding to the second signal by performing up or down counting respectively in response to the supply of the second and third comparison signals. The second counter having a predetermined maximum count value, and the low pass filter by selecting one of the phase error signal and a holding signal which is a DC voltage corresponding to the holding data in response to the supply of the control signal. And a pulse generator that generates the feedback signal only when the first and second count value signals are equal to each other, and the frequency dividing circuit counts the oscillation signal and outputs the feedback signal. 2. The PLL circuit according to claim 1, further comprising a first counter having the same maximum count value as the maximum count value for generating the first count value signal corresponding to one signal.