KR910009669B1 - Apparatus for eliminating jitter noise of telecommunication system - Google Patents

Abstract

A circuit is for eliminating the jitter component generating at the clock generation used for the data transmitting/receiving. The circuit comprises a crystal clock generating means (20) for producing the master clock, a phase compensation loop means (10) for revising the frequency of the frame pulse and for outputting the rectangular wave of the DS1 level, a driving and filtering means (30) for latching and filtering the output of the phase compensation loop means, a crystal iltering means (40) for producing an analog sine wave with eliminating the jitter component in the rectangular wave, an amplitude comparator (50) for converting the analog sine wave into the TTL level digital pulse.

Description

Jitter Removal Circuit

1 is an overall block diagram of the present invention.

2 is an internal configuration diagram of a phase compensation loop circuit portion.

3 is a waveform display of each step of the jitter removal process.

* Explanation of symbols for the main parts of the drawings

10: phase compensation loop circuit 20: modifier clock reference

30: drive and filter circuit portion 40: crystal filter circuit portion

50: amplitude comparison circuit section 11: frequency correction section

12: referral divided into eighties 13: 193 referral divided

14: phase comparison unit

The present invention relates to a circuit for the removal of jitter (components) generated when generating a clock required for data transmission and reception on a digital transmission system, in particular DS1 used in a transmission system using T1 carrier transmission, a North American digital transmission method. A circuit for removing jitter components that occurs when generating a level of 1.544 MHz clock.

The jitter component generated in the digital system itself in which data is transmitted in a frame configuration is used to reduce performance due to slip and transmission errors when the clock for data transmission and reception becomes asynchronous to the system clock. In addition to the increase, it has seriously affected the original digitally coated analog signal.

On the other hand, in order to improve the accumulated jitter due to the instantaneous fluctuations in which the Significant Instant of the digital signal does not accumulate away from the exact position in time, the significant moment of the clock is centered on the eye patterning of the data. In order to maximize the noise tolerance and to minimize the inter-symbol interference, there have been studies.

The jitter tolerance in the transmission device is characterized by the characteristics of the clock extraction circuit for signal reproduction, the frame type of the multiplexing device, the resulting stuff synchronization process, the number of buffer stages in the synchronizer / non-synchronizer, and the PLL transfer function. , PLL operating range, etc. are variables.

Accordingly, it is an object of the present invention to provide a circuit for removing a transient frequency variation component which is generated in excess of the above jitter tolerance in a digital circuit for a PLL using a universal phase detection scheme.

In order to achieve the above object, the present invention, the modifier clock generating means for generating a modifier clock (12.355MHz ± 100ppm) which is a master clock, connected to the modifier clock generating means from the outside and the modifier clock Phase compensating loop means for outputting 1.544 MHz square pulse of DS1 level while performing frequency correction by phase comparison of modifier clock with 8KHz (Pulse Width 244ns) divided by 1544 with input frame pulse as input, said phase compensation loop means A drive and filter means connected to the latching and primary filtering functions of the phase compensation loop means, and a 1.544 MHz rectangular pulse connected to the drive and filter means containing jitter components as outputs of the drive and filter means. A crystal filter means for outputting an analog sinusoidal signal of 1.544 MHz by removing jitter components, the analog filter being connected to the crystal filter means That is configured to amplitude comparator for changing the sinusoidal signal into a digital pulse of a TTL level is characterized.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram showing the overall configuration of the present invention. In the figure, reference numeral 10 denotes a phase compensation loop circuit portion, 20 a crystal clock generation circuit portion, 30 a driving and filtering circuit portion, 40 a crystal filtering circuit portion, and 50 an amplitude comparator.

The phase compensation loop circuit unit 10 is composed of a phase comparison circuit (PLL), a divider circuit, and a frequency correction circuit, and is a frame pulse that is a reference clock for dividing a T1 type frame (24channel, 193 bit) unit from the outside. Phase 9a is compared with a modifier clock of 12.355MHz ± 100ppm at 8KHz (Pulse Width 244ns, 3b) divided by 1544 to generate a 1.544MHz clock of DS1 level while performing frequency calibration.

In the present invention, the Motorola's MT8940 IC chip is implemented as a preferred embodiment of the phase-compensated loop circuit unit 10 that performs this function.

The modifier clock generation circuit unit 20 provides the phase compensation loop circuit unit 10 with a basic modifier clock (12.355 MHz ± 100 ppm) which is a master clock to be compared with the frame pulse which is the reference clock.

By the way, the phase of the phase compensation loop circuit 10 is phase-compared with the frame pulse inputted after being fed back and 193 divided by the 1.544 MHz clock output of the phase compensation loop circuit 10, in which the phase is locked to the active edge. In this case, a fixed in range of ± 1.04 MHz is maintained to satisfy the CCITT requirements, but there is a frequency variation of about 100 ns due to the instability of the phase compensation loop circuit 10 itself (Figure 3c). .

As a result, 1UI (Unit Interval) for 1.544MHz transmission is 648ns, and this accumulation of jitter causes slip and exists as a reason for duplication and loss in data transmission and reception.

The spherical pulse of 1.544 MHz, which is the output of the phase compensation loop circuit section 10 that includes the jitter component of a constant value and is output as described above, is latched by the driving and filtering circuit section 30, and is first filtered. It enters the input of the filter circuit part 40. Here, the driving and filtering circuit unit 30 is connected to a 74LS241 IC chip for latching and driving the rectangular pulse (1.544MHz) output from the phase compensation loop circuit unit 10, and is connected to a rear end of the 74LS241 IC chip, RC filter for first order filtering.

The 1.544 MHz square pulse containing the jitter component passed through the drive and filter circuit section 30 is input to the crystal filter circuit section 40 to be compensated to the correct clock level for the network synchronizer between switching stations. The internal configuration consists of a bidirectionally coupled transformer, a variable capacitor connected to the bidirectional transformer, and a crystal oscillator connected to the bidirectional transformer. According to the operation according to this, the input rectangular pulse is filtered by a transformer after the well-known filtering by the transformer coupling, the output signal of the crystal oscillator after passing the signal through the coupled transformer and the variable capacitor In synchronism, the jitter component is output as an accurate 1.544MHz analog sinusoidal output.

The crystal filter circuit unit 40 configured as described above has a center frequency of 1.544 MHz, a pass bandwidth of 200 Hz Min./3 dB, a ripple of 1.0 dB Max., And a stop bandwidth of ± 1.5 KHz Max. / 40dB, Insertion Loss 3.0dB Max, Termination Impedance 1.0Kohm / 1.0pF, Input Level 1dBm with temperature range of -20 ~ + 85degree.

The amplitude comparison circuit unit 50 is composed of a linear operational amplifier. The 1.544 MHz sine wave output through the quartz filter circuit 40 is compared with a reference voltage (zero level) of the linear operational amplifier to perform analog-to-digital conversion. As a result, the 1.544MHz square pulse with jitter removed is output at the TTL level.

Next, a detailed operation of the phase compensation loop circuit unit 10 of FIG. 1 will be described with reference to FIG. 2. FIG. 2 is an internal block diagram of the phase compensation loop circuit section (10 in FIG. 1), that is, the MT8940 IC chip.

In the drawing, reference numeral 11 denotes a frequency corrector, 12 denotes an eight-division circuit, 13 denotes a 193-division circuit, and 14 denotes a phase comparator.

The modifier clock (12.355 MHz ± 100 ppm) output from the modifier clock circuit section (20 in FIG. 1) passes through the frequency correcting section 11 and the eight division circuit section 12, and outputs a clock of 1.544 MHz. On the other hand, this output is fed back through the 193 division circuit unit 13 and converted to 8 KHz, and the phase comparison unit 14 compares the phase difference signal detected by phase comparing the output of the frame pulse and the 193 division circuit unit 13 with a frequency correction unit ( 11), the frequency corrector 11 adjusts the oscillation frequency of the crystal clock circuit (20 in FIG. 1) when a phase difference exists.

3 is a diagram showing waveforms for each step of the entire circuit.

Each waveform (a to e) is a waveform of each step point (a to e point) shown in FIG. 1 and FIG. 2, where (a) is a frame pulse and (b) is 8 divisions for phase comparison with the frame pulse. The frequency conversion of the 1.544 MHz output through the circuit section (12 in FIG. 2) to the 193 frequency divider circuit 13 is performed at 8 KHz and (c) shows the jitter component as an output of the phase compensation loop circuit section (10 in FIG. 1). The 1.544 MHz clock, (d) shows the 1.544 MHz analog sinusoidal waveform through the crystal filter circuit 40, and (e) shows the final output waveform with jitter removed through the amplitude comparator.

Therefore, the present invention, which is configured and operated as described above, has an application effect to completely remove the jitter component of the 1.544 MHz clock, which has been a difficulty in the North American digital transmission system, with a simple circuit configuration.

Claims (2)

In a circuit for removing jitter components generated during the generation of a clock required for data transmission and reception on a digital transmission system, a modifier clock generation means for generating a master clock (12.355 MHz ± 100 ppm) which is a master clock. (20) is connected to the modifier clock generation means 20 and inputs the modulator clock and a frame pulse input from the outside to compare the phase of the modifier clock with 8KHz (Pulse Width 244ns, 3b) divided by 1544; Phase compensation loop means 10 which outputs 1.544 MHz square pulse of DS1 level while performing frequency correction, and is connected to the phase compensation loop means 10 to latch and first filter the output of the phase compensation loop means 10. It is connected to the drive and filter means 30, the drive and filter means 30 that functions to remove the jitter component of the 1.544MHz spherical pulse containing the jitter component that is the output of the drive and filter means 1. A crystal comparator means 40 for outputting an analog sine wave signal of 544 MHz, and an amplitude comparator 50 connected to the crystal filter means 40 for converting the 1.544 MHz analog sine wave signal into a TTL level digital pulse. Jitter elimination circuit. 2. The frequency compensation means (11) according to claim 1, wherein said phase compensation loop means (10) is connected to said modifier clock generation means (20) to frequency correction means (11) and said frequency correction means (11) for frequency correcting a modifier clock. An 8-division circuit 12 connected to the 8-division circuit 12 to generate and output 1.544 MHz by dividing the modifier clock 8 output through the frequency correction means 11 connected to the 8-division circuit 12 A 193 frequency division circuit 13 for generating 8 KHz to be compared with the phase of the frame pulse by feeding back the output of 193; and receiving the frame pulse from the outside, and connected to the 193 frequency division circuit 13 and the frequency correcting means 11 Phase comparison means 14 for comparing the phase of the frame pulse and the output of the 193 frequency division circuit 13 to the frequency correction means 11 to output the jitter removal characterized in that to output the 1.544MHz phase-locked to the frame pulse Circuit.

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