ZA858310B - Bus broadcast method and apparatus - Google Patents

Bus broadcast method and apparatus

Info

Publication number
ZA858310B
ZA858310B ZA858310A ZA858310A ZA858310B ZA 858310 B ZA858310 B ZA 858310B ZA 858310 A ZA858310 A ZA 858310A ZA 858310 A ZA858310 A ZA 858310A ZA 858310 B ZA858310 B ZA 858310B
Authority
ZA
South Africa
Prior art keywords
broadcast method
bus broadcast
bus
broadcast
Prior art date
Application number
ZA858310A
Other languages
English (en)
Inventor
Jeffrey S Gilbert
Original Assignee
Spacelabs Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spacelabs Inc filed Critical Spacelabs Inc
Publication of ZA858310B publication Critical patent/ZA858310B/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
ZA858310A 1984-11-09 1985-10-29 Bus broadcast method and apparatus ZA858310B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US67019784A 1984-11-09 1984-11-09

Publications (1)

Publication Number Publication Date
ZA858310B true ZA858310B (en) 1986-06-25

Family

ID=24689410

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA858310A ZA858310B (en) 1984-11-09 1985-10-29 Bus broadcast method and apparatus

Country Status (5)

Country Link
EP (1) EP0181007A3 (zh)
JP (1) JPS61121150A (zh)
CN (1) CN85108393A (zh)
AU (1) AU4907285A (zh)
ZA (1) ZA858310B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3706734C1 (de) * 1987-03-02 1988-03-17 Force Computers Gmbh Verfahren zur UEbertragung von Daten sowie Computer
US4837735A (en) * 1987-06-09 1989-06-06 Martin Marietta Energy Systems, Inc. Parallel machine architecture for production rule systems
JPH02503121A (ja) * 1987-10-06 1990-09-27 ベル、コミュニケーションズ、リサーチ、インコーポレーテッド マルチプルプロセッサシステムにおける各プロセッサ用選択受信器
GB8814629D0 (en) * 1987-11-12 1988-07-27 Ibm Direct control facility for multiprocessor network
IT1223142B (it) * 1987-11-17 1990-09-12 Honeywell Bull Spa Sistema multiprocessore di elaborazione con multiplazione di dati globali
US4998245A (en) * 1987-12-17 1991-03-05 Matsushita Electric Industrial Co., Ltd. Information transmission system having collective data transmission and collection devices
GB9012970D0 (en) * 1989-09-22 1990-08-01 Ibm Apparatus and method for asynchronously delivering control elements with pipe interface
CA2021826A1 (en) * 1989-10-23 1991-04-24 Darryl Edmond Judice Delay logic for preventing cpu lockout from bus ownership
IT1239596B (it) * 1990-02-16 1993-11-10 Sincon Spa Sistemi Imformativi Rete di collegamento per la gestione di dati in elaborazioni parallele.
EP0537899B1 (en) * 1991-09-27 1999-12-15 Sun Microsystems, Inc. Bus arbitration architecture incorporating deadlock detection and masking

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5831637A (ja) * 1981-08-20 1983-02-24 Nec Corp 多重処理装置

Also Published As

Publication number Publication date
EP0181007A2 (en) 1986-05-14
CN85108393A (zh) 1986-08-27
EP0181007A3 (en) 1988-05-18
AU4907285A (en) 1986-05-15
JPS61121150A (ja) 1986-06-09

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