ZA202001262B - Cache-based trace recording using cache coherence protocol data - Google Patents

Cache-based trace recording using cache coherence protocol data

Info

Publication number
ZA202001262B
ZA202001262B ZA2020/01262A ZA202001262A ZA202001262B ZA 202001262 B ZA202001262 B ZA 202001262B ZA 2020/01262 A ZA2020/01262 A ZA 2020/01262A ZA 202001262 A ZA202001262 A ZA 202001262A ZA 202001262 B ZA202001262 B ZA 202001262B
Authority
ZA
South Africa
Prior art keywords
cache
protocol data
coherence protocol
trace recording
based trace
Prior art date
Application number
ZA2020/01262A
Other languages
English (en)
Inventor
Mola Jordi
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of ZA202001262B publication Critical patent/ZA202001262B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program
    • G06F11/364—Debugging of software by tracing the execution of the program tracing values on a bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3624—Debugging of software by performing operations on the source code, e.g. via a compiler
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3632—Debugging of software of specific synchronisation aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/3698—Environments for analysis, debugging or testing of software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/454—Vector or matrix data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
ZA2020/01262A 2017-09-18 2020-02-27 Cache-based trace recording using cache coherence protocol data ZA202001262B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762559780P 2017-09-18 2017-09-18
US15/915,930 US10459824B2 (en) 2017-09-18 2018-03-08 Cache-based trace recording using cache coherence protocol data
PCT/US2018/038875 WO2019055094A1 (en) 2017-09-18 2018-06-22 TRACE RECORDING USING CACHE MEMORY USING CACHE MEMORY COHERENCE PROTOCOL DATA

Publications (1)

Publication Number Publication Date
ZA202001262B true ZA202001262B (en) 2021-05-26

Family

ID=65721507

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA2020/01262A ZA202001262B (en) 2017-09-18 2020-02-27 Cache-based trace recording using cache coherence protocol data

Country Status (17)

Country Link
US (1) US10459824B2 (https=)
EP (1) EP3665575B1 (https=)
JP (1) JP7152474B2 (https=)
KR (1) KR102483506B1 (https=)
CN (1) CN111095222B (https=)
AU (1) AU2018334370B2 (https=)
BR (1) BR112020003342A2 (https=)
CL (1) CL2020000645A1 (https=)
CO (1) CO2020002932A2 (https=)
ES (1) ES2887195T3 (https=)
IL (1) IL272745B2 (https=)
MX (1) MX2020002865A (https=)
MY (1) MY203044A (https=)
PH (1) PH12020550109A1 (https=)
SG (1) SG11202001913RA (https=)
WO (1) WO2019055094A1 (https=)
ZA (1) ZA202001262B (https=)

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Publication number Publication date
CO2020002932A2 (es) 2020-04-13
BR112020003342A2 (pt) 2020-08-18
MY203044A (en) 2024-06-05
IL272745A (en) 2020-04-30
AU2018334370A1 (en) 2020-02-20
ES2887195T3 (es) 2021-12-22
SG11202001913RA (en) 2020-04-29
RU2020113601A3 (https=) 2022-01-31
RU2020113601A (ru) 2021-10-20
CN111095222A (zh) 2020-05-01
CN111095222B (zh) 2023-09-15
IL272745B2 (en) 2023-02-01
EP3665575A1 (en) 2020-06-17
JP7152474B2 (ja) 2022-10-12
PH12020550109A1 (en) 2020-12-07
CA3072872A1 (en) 2019-03-21
JP2020534589A (ja) 2020-11-26
EP3665575B1 (en) 2021-07-28
NZ761306A (en) 2023-10-27
AU2018334370B2 (en) 2022-12-22
KR102483506B1 (ko) 2022-12-30
MX2020002865A (es) 2020-07-24
US20190087305A1 (en) 2019-03-21
KR20200056430A (ko) 2020-05-22
IL272745B (en) 2022-10-01
CL2020000645A1 (es) 2020-09-11
WO2019055094A1 (en) 2019-03-21
US10459824B2 (en) 2019-10-29

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