CO2020002932A2 - Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché. - Google Patents

Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché.

Info

Publication number
CO2020002932A2
CO2020002932A2 CONC2020/0002932A CO2020002932A CO2020002932A2 CO 2020002932 A2 CO2020002932 A2 CO 2020002932A2 CO 2020002932 A CO2020002932 A CO 2020002932A CO 2020002932 A2 CO2020002932 A2 CO 2020002932A2
Authority
CO
Colombia
Prior art keywords
cache
data
trace log
consistency protocol
protocol data
Prior art date
Application number
CONC2020/0002932A
Other languages
English (en)
Inventor
Jordi Mola
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of CO2020002932A2 publication Critical patent/CO2020002932A2/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G06F11/364—Software debugging by tracing the execution of the program tracing values on a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3632—Software debugging of specific synchronisation aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3624—Software debugging by performing operations on the source code, e.g. via a compiler
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3664—Environments for testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/454—Vector or matrix data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

La ejecución de un registro de seguimiento con base en memoria caché utilizando los datos del protocolo de coherencia de memoria caché (CCP, por sus siglas en inglés). Las modalidades detectan que ha ocurrido una operación que provoca una interacción entre una línea de memoria caché y un almacenamiento de respaldo, que el registro se habilite para una unidad de procesamiento que provocó la operación, que la línea de memoria caché sea un participante en el registro y que el CCP indique que existen los datos que se registrarán en un seguimiento. Las modalidades entonces provocan que los datos se registren en el seguimiento, cuyos datos pueden utilizarse para reproducir la operación.
CONC2020/0002932A 2017-09-18 2020-03-12 Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché. CO2020002932A2 (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762559780P 2017-09-18 2017-09-18
US15/915,930 US10459824B2 (en) 2017-09-18 2018-03-08 Cache-based trace recording using cache coherence protocol data
PCT/US2018/038875 WO2019055094A1 (en) 2017-09-18 2018-06-22 TRACE RECORDING USING CACHE MEMORY USING CACHE MEMORY COHERENCE PROTOCOL DATA

Publications (1)

Publication Number Publication Date
CO2020002932A2 true CO2020002932A2 (es) 2020-04-13

Family

ID=65721507

Family Applications (1)

Application Number Title Priority Date Filing Date
CONC2020/0002932A CO2020002932A2 (es) 2017-09-18 2020-03-12 Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché.

Country Status (17)

Country Link
US (1) US10459824B2 (es)
EP (1) EP3665575B1 (es)
JP (1) JP7152474B2 (es)
KR (1) KR102483506B1 (es)
CN (1) CN111095222B (es)
AU (1) AU2018334370B2 (es)
BR (1) BR112020003342A2 (es)
CA (1) CA3072872A1 (es)
CL (1) CL2020000645A1 (es)
CO (1) CO2020002932A2 (es)
ES (1) ES2887195T3 (es)
IL (1) IL272745B2 (es)
MX (1) MX2020002865A (es)
PH (1) PH12020550109A1 (es)
SG (1) SG11202001913RA (es)
WO (1) WO2019055094A1 (es)
ZA (1) ZA202001262B (es)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9378560B2 (en) * 2011-06-17 2016-06-28 Advanced Micro Devices, Inc. Real time on-chip texture decompression using shader processors
US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10990504B2 (en) 2018-01-08 2021-04-27 Ozcode Ltd. Time travel source code debugger incorporating future prediction
US10558572B2 (en) * 2018-01-16 2020-02-11 Microsoft Technology Licensing, Llc Decoupling trace data streams using cache coherence protocol data
US10541042B2 (en) 2018-04-23 2020-01-21 Microsoft Technology Licensing, Llc Level-crossing memory trace inspection queries
US10592396B2 (en) * 2018-04-23 2020-03-17 Microsoft Technology Licensing, Llc Memory validity states in time-travel debugging
US11126537B2 (en) * 2019-05-02 2021-09-21 Microsoft Technology Licensing, Llc Coprocessor-based logging for time travel debugging
LU101769B1 (en) 2020-05-05 2021-11-08 Microsoft Technology Licensing Llc Omitting processor-based logging of separately obtainable memory values during program tracing
LU101768B1 (en) * 2020-05-05 2021-11-05 Microsoft Technology Licensing Llc Recording a cache coherency protocol trace for use with a separate memory value trace
LU101770B1 (en) * 2020-05-05 2021-11-05 Microsoft Technology Licensing Llc Memory page markings as logging cues for processor-based execution tracing
LU101767B1 (en) * 2020-05-05 2021-11-05 Microsoft Technology Licensing Llc Recording a memory value trace for use with a separate cache coherency protocol trace
US11360906B2 (en) 2020-08-14 2022-06-14 Alibaba Group Holding Limited Inter-device processing system with cache coherency
US11561896B2 (en) 2021-02-22 2023-01-24 Microsoft Technology Licensing, Llc Cache-based trace logging using tags in an upper-level cache
US20220269614A1 (en) * 2021-02-22 2022-08-25 Microsoft Technology Licensing, Llc Treating main memory as a collection of tagged cache lines for trace logging
EP4295234A1 (en) * 2021-02-22 2023-12-27 Microsoft Technology Licensing, LLC Cache-based trace logging using tags in an upper-level cache
US20220269615A1 (en) * 2021-02-22 2022-08-25 Microsoft Technology Licensing, Llc Cache-based trace logging using tags in system memory
LU500061B1 (en) * 2021-04-20 2022-10-20 Microsoft Technology Licensing Llc Processor support for using cache way- locking to simultaneously record plural execution contexts into independent execution traces
LU500060B1 (en) * 2021-04-20 2022-10-20 Microsoft Technology Licensing Llc Processor support for using memory page markings as logging cues to simultaneously record plural execution contexts into independent execution traces
WO2023181241A1 (ja) * 2022-03-24 2023-09-28 日本電気株式会社 監視サーバ装置、システム、方法、及びプログラム
CN114845132B (zh) * 2022-04-29 2023-05-12 厦门理工学院 基于哈希算法的低延迟直播缓存方法、装置、设备及介质

Family Cites Families (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4598364A (en) 1983-06-29 1986-07-01 International Business Machines Corporation Efficient trace method adaptable to multiprocessors
AU3776793A (en) 1992-02-27 1993-09-13 Intel Corporation Dynamic flow instruction cache memory
US5905855A (en) 1997-02-28 1999-05-18 Transmeta Corporation Method and apparatus for correcting errors in computer systems
US6009270A (en) 1997-04-08 1999-12-28 Advanced Micro Devices, Inc. Trace synchronization in a processor
US6167536A (en) 1997-04-08 2000-12-26 Advanced Micro Devices, Inc. Trace cache for a microprocessor-based device
US6094729A (en) 1997-04-08 2000-07-25 Advanced Micro Devices, Inc. Debug interface including a compact trace record storage
US5944841A (en) 1997-04-15 1999-08-31 Advanced Micro Devices, Inc. Microprocessor with built-in instruction tracing capability
US6101524A (en) 1997-10-23 2000-08-08 International Business Machines Corporation Deterministic replay of multithreaded applications
JP3239935B2 (ja) * 1997-11-28 2001-12-17 日本電気株式会社 密結合マルチプロセッサシステムの制御方法、密結合マルチプロセッサシステム及びその記録媒体
US6513155B1 (en) 1997-12-12 2003-01-28 International Business Machines Corporation Method and system for merging event-based data and sampled data into postprocessed trace output
US6351844B1 (en) 1998-11-05 2002-02-26 Hewlett-Packard Company Method for selecting active code traces for translation in a caching dynamic translator
JP3147876B2 (ja) * 1998-11-12 2001-03-19 日本電気株式会社 マルチプロセッサシステムで用いられるトレース方法及びトレース装置
US6854108B1 (en) 2000-05-11 2005-02-08 International Business Machines Corporation Method and apparatus for deterministic replay of java multithreaded programs on multiprocessors
US7448025B2 (en) 2000-12-29 2008-11-04 Intel Corporation Qualification of event detection by thread ID and thread privilege level
FR2820850B1 (fr) * 2001-02-15 2003-05-09 Bull Sa Controleur de coherence pour ensemble multiprocesseur, module et ensemble multiprocesseur a architecture multimodule integrant un tel controleur
US6634011B1 (en) 2001-02-15 2003-10-14 Silicon Graphics, Inc. Method and apparatus for recording program execution in a microprocessor based integrated circuit
US20020144101A1 (en) 2001-03-30 2002-10-03 Hong Wang Caching DAG traces
US7178133B1 (en) 2001-04-30 2007-02-13 Mips Technologies, Inc. Trace control based on a characteristic of a processor's operating state
US7185234B1 (en) 2001-04-30 2007-02-27 Mips Technologies, Inc. Trace control from hardware and software
US7181728B1 (en) 2001-04-30 2007-02-20 Mips Technologies, Inc. User controlled trace records
US20030079205A1 (en) 2001-10-22 2003-04-24 Takeshi Miyao System and method for managing operating systems
US7051239B2 (en) 2001-12-28 2006-05-23 Hewlett-Packard Development Company, L.P. Method and apparatus for efficiently implementing trace and/or logic analysis mechanisms on a processor chip
US7089400B1 (en) 2002-08-29 2006-08-08 Advanced Micro Devices, Inc. Data speculation based on stack-relative addressing patterns
US20040117690A1 (en) 2002-12-13 2004-06-17 Andersson Anders J. Method and apparatus for using a hardware disk controller for storing processor execution trace information on a storage device
US20040139305A1 (en) 2003-01-09 2004-07-15 International Business Machines Corporation Hardware-enabled instruction tracing
US7526757B2 (en) 2004-01-14 2009-04-28 International Business Machines Corporation Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program
US20050223364A1 (en) 2004-03-30 2005-10-06 Peri Ramesh V Method and apparatus to compact trace in a trace buffer
US8010337B2 (en) 2004-09-22 2011-08-30 Microsoft Corporation Predicting database system performance
US7447946B2 (en) 2004-11-05 2008-11-04 Arm Limited Storage of trace data within a data processing apparatus
JP4114879B2 (ja) 2005-01-21 2008-07-09 インターナショナル・ビジネス・マシーンズ・コーポレーション トレース情報収集システム、トレース情報収集方法、及びトレース情報収集プログラム
US7640539B2 (en) 2005-04-12 2009-12-29 International Business Machines Corporation Instruction profiling using multiple metrics
US8301868B2 (en) 2005-09-23 2012-10-30 Intel Corporation System to profile and optimize user software in a managed run-time environment
US7877630B1 (en) 2005-09-28 2011-01-25 Oracle America, Inc. Trace based rollback of a speculatively updated cache
US7984281B2 (en) 2005-10-18 2011-07-19 Qualcomm Incorporated Shared interrupt controller for a multi-threaded processor
US9268666B2 (en) 2005-10-21 2016-02-23 Undo Ltd. System and method for debugging of computer programs
US7620938B2 (en) 2005-10-31 2009-11-17 Microsoft Corporation Compressed program recording
US20070106827A1 (en) 2005-11-08 2007-05-10 Boatright Bryan D Centralized interrupt controller
US7461209B2 (en) 2005-12-06 2008-12-02 International Business Machines Corporation Transient cache storage with discard function for disposable data
US20070150881A1 (en) 2005-12-22 2007-06-28 Motorola, Inc. Method and system for run-time cache logging
US7543116B2 (en) * 2006-01-30 2009-06-02 International Business Machines Corporation Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains
US20070220361A1 (en) 2006-02-03 2007-09-20 International Business Machines Corporation Method and apparatus for guaranteeing memory bandwidth for trace data
US7958497B1 (en) 2006-06-07 2011-06-07 Replay Solutions, Inc. State synchronization in recording and replaying computer programs
US7676632B2 (en) 2006-07-18 2010-03-09 Via Technologies, Inc. Partial cache way locking
US7472218B2 (en) 2006-09-08 2008-12-30 International Business Machines Corporation Assisted trace facility to improve CPU cache performance
US20080114964A1 (en) 2006-11-14 2008-05-15 Davis Gordon T Apparatus and Method for Cache Maintenance
US20080250207A1 (en) 2006-11-14 2008-10-09 Davis Gordon T Design structure for cache maintenance
US8370806B2 (en) 2006-11-15 2013-02-05 Qualcomm Incorporated Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor
US8261130B2 (en) 2007-03-02 2012-09-04 Infineon Technologies Ag Program code trace signature
US8484516B2 (en) 2007-04-11 2013-07-09 Qualcomm Incorporated Inter-thread trace alignment method and system for a multi-threaded processor
US20090037886A1 (en) 2007-07-30 2009-02-05 Mips Technologies, Inc. Apparatus and method for evaluating a free-running trace stream
CN101446909B (zh) 2007-11-30 2011-12-28 国际商业机器公司 用于管理任务事件的方法和系统
US8078807B2 (en) 2007-12-27 2011-12-13 Intel Corporation Accelerating software lookups by using buffered or ephemeral stores
US8413122B2 (en) 2009-02-12 2013-04-02 International Business Machines Corporation System and method for demonstrating the correctness of an execution trace in concurrent processing environments
US8402318B2 (en) 2009-03-24 2013-03-19 The Trustees Of Columbia University In The City Of New York Systems and methods for recording and replaying application execution
US8589629B2 (en) 2009-03-27 2013-11-19 Advanced Micro Devices, Inc. Method for way allocation and way locking in a cache
US8140903B2 (en) 2009-04-16 2012-03-20 International Business Machines Corporation Hardware process trace facility
US8423965B2 (en) 2009-06-23 2013-04-16 Microsoft Corporation Tracing of data flow
JP2011013867A (ja) 2009-06-30 2011-01-20 Panasonic Corp データ処理装置、性能評価解析システム
US8392929B2 (en) * 2009-12-15 2013-03-05 Microsoft Corporation Leveraging memory isolation hardware technology to efficiently detect race conditions
US8719796B2 (en) 2010-01-26 2014-05-06 The Board Of Trustees Of The University Of Illinois Parametric trace slicing
US8468501B2 (en) 2010-04-21 2013-06-18 International Business Machines Corporation Partial recording of a computer program execution for replay
US9015441B2 (en) 2010-04-30 2015-04-21 Microsoft Technology Licensing, Llc Memory usage scanning
US8499200B2 (en) 2010-05-24 2013-07-30 Ncr Corporation Managing code-tracing data
US9448938B2 (en) * 2010-06-09 2016-09-20 Micron Technology, Inc. Cache coherence protocol for persistent memories
US20120042212A1 (en) 2010-08-10 2012-02-16 Gilbert Laurenti Mixed Mode Processor Tracing
US9645913B2 (en) 2011-08-03 2017-05-09 Daniel Geist Method and apparatus for debugging programs
US20130055033A1 (en) 2011-08-22 2013-02-28 International Business Machines Corporation Hardware-assisted program trace collection with selectable call-signature capture
US8584110B2 (en) 2011-09-30 2013-11-12 International Business Machines Corporation Execution trace truncation
US8612650B1 (en) 2012-03-13 2013-12-17 Western Digital Technologies, Inc. Virtual extension of buffer to reduce buffer overflow during tracing
WO2013147898A1 (en) 2012-03-30 2013-10-03 Intel Corporation Tracing mechanism for recording shared memory interleavings on multi-core processors
US9824009B2 (en) * 2012-12-21 2017-11-21 Nvidia Corporation Information coherency maintenance systems and methods
US9311241B2 (en) * 2012-12-29 2016-04-12 Intel Corporation Method and apparatus to write modified cache data to a backing store while retaining write permissions
US9304863B2 (en) 2013-03-15 2016-04-05 International Business Machines Corporation Transactions for checkpointing and reverse execution
US9058415B1 (en) 2013-03-15 2015-06-16 Google Inc. Counting events using hardware performance counters and annotated instructions
US9189360B2 (en) 2013-06-15 2015-11-17 Intel Corporation Processor that records tracing data in non contiguous system memory slices
US9086974B2 (en) 2013-09-26 2015-07-21 International Business Machines Corporation Centralized management of high-contention cache lines in multi-processor computing environments
US9336110B2 (en) 2014-01-29 2016-05-10 Red Hat, Inc. Identifying performance limiting internode data sharing on NUMA platforms
US9535815B2 (en) 2014-06-04 2017-01-03 Nvidia Corporation System, method, and computer program product for collecting execution statistics for graphics processing unit workloads
US9300320B2 (en) 2014-06-27 2016-03-29 Qualcomm Incorporated System and method for dictionary-based cache-line level code compression for on-chip memories using gradual bit removal
US9875173B2 (en) 2014-06-30 2018-01-23 Microsoft Technology Licensing, Llc Time travel debugging in managed runtime
US9361228B2 (en) 2014-08-05 2016-06-07 Qualcomm Incorporated Cache line compaction of compressed data segments
US9588870B2 (en) 2015-04-06 2017-03-07 Microsoft Technology Licensing, Llc Time travel debugging for browser components
WO2017028908A1 (en) 2015-08-18 2017-02-23 Telefonaktiebolaget Lm Ericsson (Publ) Method for observing software execution, debug host and debug target
US9767237B2 (en) 2015-11-13 2017-09-19 Mentor Graphics Corporation Target capture and replay in emulation
US9569338B1 (en) 2015-12-02 2017-02-14 International Business Machines Corporation Fingerprint-initiated trace extraction
US10031833B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10031834B2 (en) 2016-08-31 2018-07-24 Microsoft Technology Licensing, Llc Cache-based tracing for time travel debugging and analysis
US10489273B2 (en) * 2016-10-20 2019-11-26 Microsoft Technology Licensing, Llc Reuse of a related thread's cache while recording a trace file of code execution
US10310977B2 (en) * 2016-10-20 2019-06-04 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using a processor cache
US10324851B2 (en) * 2016-10-20 2019-06-18 Microsoft Technology Licensing, Llc Facilitating recording a trace file of code execution using way-locking in a set-associative processor cache
US10445211B2 (en) * 2017-08-28 2019-10-15 Microsoft Technology Licensing, Llc Logging trace data for program code execution at an instruction level

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RU2020113601A3 (es) 2022-01-31
CA3072872A1 (en) 2019-03-21
ZA202001262B (en) 2021-05-26
CN111095222A (zh) 2020-05-01
CL2020000645A1 (es) 2020-09-11
JP7152474B2 (ja) 2022-10-12
IL272745B2 (en) 2023-02-01
MX2020002865A (es) 2020-07-24
IL272745A (en) 2020-04-30
US10459824B2 (en) 2019-10-29
US20190087305A1 (en) 2019-03-21
BR112020003342A2 (pt) 2020-08-18
AU2018334370B2 (en) 2022-12-22
SG11202001913RA (en) 2020-04-29
KR102483506B1 (ko) 2022-12-30
IL272745B (en) 2022-10-01
ES2887195T3 (es) 2021-12-22
PH12020550109A1 (en) 2020-12-07
CN111095222B (zh) 2023-09-15
WO2019055094A1 (en) 2019-03-21
EP3665575B1 (en) 2021-07-28
KR20200056430A (ko) 2020-05-22
EP3665575A1 (en) 2020-06-17
AU2018334370A1 (en) 2020-02-20
JP2020534589A (ja) 2020-11-26
NZ761306A (en) 2023-10-27
RU2020113601A (ru) 2021-10-20

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