CO2020002932A2 - Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché. - Google Patents

Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché.

Info

Publication number
CO2020002932A2
CO2020002932A2 CONC2020/0002932A CO2020002932A CO2020002932A2 CO 2020002932 A2 CO2020002932 A2 CO 2020002932A2 CO 2020002932 A CO2020002932 A CO 2020002932A CO 2020002932 A2 CO2020002932 A2 CO 2020002932A2
Authority
CO
Colombia
Prior art keywords
cache
data
trace log
consistency protocol
protocol data
Prior art date
Application number
CONC2020/0002932A
Other languages
English (en)
Inventor
Jordi Mola
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of CO2020002932A2 publication Critical patent/CO2020002932A2/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G06F11/364—Software debugging by tracing the execution of the program tracing values on a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3632—Software debugging of specific synchronisation aspects
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3624—Software debugging by performing operations on the source code, e.g. via a compiler
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3664—Environments for testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/454—Vector or matrix data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

La ejecución de un registro de seguimiento con base en memoria caché utilizando los datos del protocolo de coherencia de memoria caché (CCP, por sus siglas en inglés). Las modalidades detectan que ha ocurrido una operación que provoca una interacción entre una línea de memoria caché y un almacenamiento de respaldo, que el registro se habilite para una unidad de procesamiento que provocó la operación, que la línea de memoria caché sea un participante en el registro y que el CCP indique que existen los datos que se registrarán en un seguimiento. Las modalidades entonces provocan que los datos se registren en el seguimiento, cuyos datos pueden utilizarse para reproducir la operación.
CONC2020/0002932A 2017-09-18 2020-03-12 Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché. CO2020002932A2 (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201762559780P 2017-09-18 2017-09-18
US15/915,930 US10459824B2 (en) 2017-09-18 2018-03-08 Cache-based trace recording using cache coherence protocol data
PCT/US2018/038875 WO2019055094A1 (en) 2017-09-18 2018-06-22 TRACE RECORDING USING CACHE MEMORY USING CACHE MEMORY COHERENCE PROTOCOL DATA

Publications (1)

Publication Number Publication Date
CO2020002932A2 true CO2020002932A2 (es) 2020-04-13

Family

ID=65721507

Family Applications (1)

Application Number Title Priority Date Filing Date
CONC2020/0002932A CO2020002932A2 (es) 2017-09-18 2020-03-12 Registro de seguimiento con base en memoria caché utilizando datos de protocolo de coherencia de memoria caché.

Country Status (17)

Country Link
US (1) US10459824B2 (es)
EP (1) EP3665575B1 (es)
JP (1) JP7152474B2 (es)
KR (1) KR102483506B1 (es)
CN (1) CN111095222B (es)
AU (1) AU2018334370B2 (es)
BR (1) BR112020003342A2 (es)
CA (1) CA3072872A1 (es)
CL (1) CL2020000645A1 (es)
CO (1) CO2020002932A2 (es)
ES (1) ES2887195T3 (es)
IL (1) IL272745B2 (es)
MX (1) MX2020002865A (es)
PH (1) PH12020550109A1 (es)
SG (1) SG11202001913RA (es)
WO (1) WO2019055094A1 (es)
ZA (1) ZA202001262B (es)

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CN111095222A (zh) 2020-05-01
SG11202001913RA (en) 2020-04-29
JP2020534589A (ja) 2020-11-26
RU2020113601A (ru) 2021-10-20
US20190087305A1 (en) 2019-03-21
KR20200056430A (ko) 2020-05-22
ES2887195T3 (es) 2021-12-22
IL272745B (en) 2022-10-01
NZ761306A (en) 2023-10-27
ZA202001262B (en) 2021-05-26
BR112020003342A2 (pt) 2020-08-18
AU2018334370A1 (en) 2020-02-20
CL2020000645A1 (es) 2020-09-11
AU2018334370B2 (en) 2022-12-22
PH12020550109A1 (en) 2020-12-07
CN111095222B (zh) 2023-09-15
CA3072872A1 (en) 2019-03-21
US10459824B2 (en) 2019-10-29
IL272745B2 (en) 2023-02-01
EP3665575B1 (en) 2021-07-28
RU2020113601A3 (es) 2022-01-31
KR102483506B1 (ko) 2022-12-30
EP3665575A1 (en) 2020-06-17
JP7152474B2 (ja) 2022-10-12
MX2020002865A (es) 2020-07-24
WO2019055094A1 (en) 2019-03-21
IL272745A (en) 2020-04-30

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