WO2026026331A1 - 信号传输电路及信号传输系统、电控系统、车辆 - Google Patents

信号传输电路及信号传输系统、电控系统、车辆

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Publication number
WO2026026331A1
WO2026026331A1 PCT/CN2025/103646 CN2025103646W WO2026026331A1 WO 2026026331 A1 WO2026026331 A1 WO 2026026331A1 CN 2025103646 W CN2025103646 W CN 2025103646W WO 2026026331 A1 WO2026026331 A1 WO 2026026331A1
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WO
WIPO (PCT)
Prior art keywords
signal
circuit
terminal
output
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/103646
Other languages
English (en)
French (fr)
Inventor
宋平
陈强强
王文情
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BYD Co Ltd
Original Assignee
BYD Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BYD Co Ltd filed Critical BYD Co Ltd
Publication of WO2026026331A1 publication Critical patent/WO2026026331A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

Definitions

  • This application relates to the field of capacitor isolation technology, and in particular to a signal transmission circuit and signal transmission system, an electronic control system, and a vehicle.
  • the current architecture for using capacitor isolators is as follows: the input signal is transmitted to the secondary side via the capacitor isolator, and the signal is then output from the secondary side. This architecture suffers from poor signal transmission performance.
  • the purpose of this application is to provide a signal transmission circuit and signal transmission system, an electronic control system, and a vehicle, for improving the signal transmission effect of a capacitor isolator.
  • the signal receiving circuit has its input terminal connected to the output terminal of the isolation module, and is used to process the second differential signal and output a third differential signal.
  • the signal output device has its input terminal connected to the output terminal of the signal receiving circuit, and is used to combine the third differential signal and output a single signal.
  • this application discloses a signal transmission system, including the signal transmission circuit as described in the first aspect, and further including: a controller, a drive module and a power device;
  • the output terminal of the controller is connected to the input terminal of the signal transmission circuit
  • the input terminal of the drive module is connected to the output terminal of the signal transmission circuit
  • the input terminal of the power device is connected to the output terminal of the drive module
  • the driving module is used to boost the signal output from the signal transmission circuit and then output it to the power device to drive the power device to operate.
  • this application provides a vehicle including the electronic control system of the vehicle as described in the third aspect.
  • the signal transmission circuit disclosed in this application includes an isolation module and a receiving module.
  • the receiving module includes a signal receiving circuit and a signal output device.
  • the isolation module receives a first differential signal and, after electrically isolating the first differential signal, outputs a second differential signal.
  • the signal receiving circuit with its input terminal connected to the output terminal of the isolation module, processes the second differential signal and outputs a third differential signal.
  • the signal output device with its input terminal connected to the output terminal of the signal receiving circuit, combines the third differential signal and outputs a single signal.
  • the signal transmission circuit provided in this embodiment can achieve the functionality of multiple secondary components in a traditional capacitor isolator architecture using only a single signal output unit. This reduces the number of secondary components and simplifies the circuit structure of the secondary side (the receiving module) of the isolation module. The more secondary components and the more complex the circuit structure, the worse the signal transmission performance. Conversely, fewer secondary components and a simpler circuit structure result in fewer factors affecting signal interference and less signal loss, leading to better signal transmission quality and performance. Therefore, the signal transmission circuit provided in this embodiment can improve the signal transmission performance of capacitor isolators.
  • Figure 1 is a schematic diagram of the signal transmission circuit provided in some embodiments of this application.
  • Figure 2 is a schematic diagram of the signal transmission circuit provided in some embodiments of this application.
  • FIG. 3 is a schematic diagram of the signal transmission circuit provided in some embodiments of this application.
  • Figure 4 is a schematic diagram of the differential amplifier circuit in the signal transmission circuit provided in some embodiments of this application.
  • Figure 5 is a schematic diagram of the circuit used to generate trigger levels in the signal transmission circuit provided in some embodiments of this application;
  • Figure 6 is a schematic diagram of the signal transmission circuit provided in some embodiments of this application.
  • Figure 7 is a schematic diagram of the clamping module in the signal transmission circuit provided in some embodiments of this application.
  • Figure 8 is a schematic diagram of the clamping module in the signal transmission circuit provided in some embodiments of this application.
  • Figure 9 is a schematic diagram of the signal transmission circuit provided in some embodiments of this application.
  • Figure 10 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 11 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 12 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 13 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 14 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 15 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 16 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 17 is a partial structural schematic diagram of the front-stage differential amplifier in a signal transmission circuit provided in some embodiments of this application;
  • Figure 18 is a schematic diagram of the structure of the input module in the signal transmission circuit provided in some embodiments of this application.
  • Figure 19 is a schematic diagram of the input signal in the signal transmission circuit provided in some embodiments of this application.
  • Figure 20 is a schematic diagram of the oscillator signal in the signal transmission circuit provided in some embodiments of this application.
  • Figure 21 is a schematic diagram of the first differential signal in a signal transmission circuit provided in some embodiments of this application.
  • Figure 22 is a schematic diagram of the structure of a signal transmission circuit provided in some embodiments of this application.
  • Figure 23 is a schematic diagram of the structure of the filter circuit in the signal transmission circuit provided in some embodiments of this application.
  • Figure 24 is a schematic diagram of the signal transmission circuit provided in some embodiments of this application.
  • Figure 25 is a schematic diagram of the structure of a signal transmission system provided in some embodiments of this application.
  • Figure 26 is a schematic diagram of the structure of an electronic control system provided in some embodiments of this application.
  • Figure 27 is a schematic diagram of the structure of a vehicle provided in some embodiments of this application.
  • 10 Signal transmission circuit; 20 - Isolation Module; 30 - Clamping module; 31 - Trigger circuit; 32 - Discharge circuit; 40 - Receiver module; 41 - Signal receiving circuit; 42 - Signal output device; 43 - Pre-amplifier differential amplifier circuit; 44 - Filtering circuit; 45 - Signal combining circuit; 46 - Signal inverting circuit; 47 - Delay circuit; 50 - Input module; 51 - Oscillator; 52 - Logic circuit; 53 - Driver circuit; 60 - Signal transmission system; 61 - Controller; 62 - Drive module; 63 - Power device; 70 - Electrical control system; 71 - Load; 310 - First voltage divider circuit; 320 - Second voltage divider circuit; 411-First amplifier circuit; 412-Second amplifier circuit; 413-First stage sub-circuit; 414-Second stage sub-circuit; 415- Third-level sub-circuit
  • Capacitor isolators are primarily used to isolate high-voltage and low-voltage domains, achieving "ground" isolation between different power domains. They are commonly used for signal transmission between chips or systems located in different power domains.
  • the architecture of capacitor isolators is as follows: the input signal is transmitted to the secondary side via the capacitor isolator, and the signal is output from the secondary side.
  • This type of architecture has high circuit complexity, resulting in poor signal transmission performance.
  • this application provides a signal transmission circuit and signal transmission system, an electronic control system, and a vehicle.
  • the signal transmission circuit includes an isolation module and a receiving module.
  • the receiving module includes a signal receiving circuit and a signal output device.
  • the isolation module receives a first differential signal, electrically isolates it, and outputs a second differential signal.
  • the signal receiving circuit with its input connected to the output of the isolation module, processes the second differential signal and outputs a third differential signal.
  • the signal output device with its input connected to the output of the signal receiving circuit, combines the third differential signal and outputs a single signal.
  • the signal transmission circuit provided in this application can achieve the functionality of multiple secondary components in a traditional capacitor isolator architecture using only a single signal output unit. This reduces the number of secondary components and simplifies the circuit structure of the secondary side (the receiving module) of the isolation module. The more secondary components and the more complex the circuit structure, the worse the signal transmission performance. Conversely, fewer secondary components and a simpler circuit structure result in fewer factors affecting signal interference and less signal loss, leading to better signal transmission quality and performance. Therefore, the signal transmission circuit provided in this application can improve the signal transmission performance of capacitor isolators.
  • One embodiment of this application provides a signal transmission circuit 10, including an isolation module 20 and a receiving module 40.
  • the isolation module 20 is described as follows:
  • the isolation module 20 is used to receive the first differential signal and output the second differential signal. Specifically, the isolation module 20 is used to electrically isolate the first differential signal before outputting the second differential signal.
  • the first differential signal is output by the input module.
  • the pulse signal output from the chip to the input module is processed into the first differential signal.
  • the first differential signal can also be output by other modules; there are no restrictions here.
  • the first differential signal includes a first positive signal (OUT+) and a first negative signal (OUT-).
  • the isolation module 20 receives the first positive signal and outputs a second positive signal (INPUT+), and receives the first negative signal and outputs a second negative signal (INPUT-).
  • the isolation module 20 is a capacitor isolation module 20, which includes an isolation capacitor, which may be a high-voltage isolation capacitor.
  • At least one high-voltage isolation capacitor can be provided, and two high-voltage isolation capacitors connected in series can be provided.
  • the second positive signal (OUT-) at least one high-voltage isolation capacitor can be provided, and two high-voltage isolation capacitors connected in series can be provided.
  • the number of high-voltage isolation capacitors set for the first positive signal and the second positive signal must be the same. For example, if two high-voltage isolation capacitors are set in series for the first positive signal, then two high-voltage isolation capacitors in series must also be set for the second positive signal.
  • the receiving module 40 is described as follows:
  • the receiving module 40 is used to demodulate the second differential signal and then output it. This demodulation process may involve amplifying the second differential signal and then fusing it.
  • the receiving module 40 includes a signal receiving circuit 41 and a signal output device 42.
  • the input terminal of the signal receiving circuit 41 is connected to the output terminal of the isolation module 20.
  • the signal receiving circuit 41 processes the second differential signal and outputs a third differential signal.
  • the signal receiving circuit 41 can perform amplification, filtering, and other processing on the second differential signal.
  • the amplification process can include single-stage amplification or multi-stage amplification.
  • the filtering process can include single-stage filtering or multiple-stage filtering.
  • the input terminal of the signal output device 42 is connected to the output terminal of the signal receiving circuit 41.
  • the signal output device 42 is used to combine the third differential signal and output a single signal. This single signal is almost identical to the pulse signal output to the input module by the chip described above.
  • the signal output device 42 can be composed of resistors, capacitors, etc., and the circuit structure is simple.
  • the signal output device 42 can also differentially amplify the third differential signal and then invert and combine them into a single signal. It is understood that in the actual use of the signal transmission circuit 10, the output terminal of the secondary device is connected to the input terminal of the power device. When the power device switches, due to the large parasitic capacitance of the isolation module 20 to ground, the signal output by the isolation module 20 carries a common-mode level. If the common-mode level is too high, it will damage the secondary device. When the signal output device 42 amplifies the third differential signal, it performs differential amplification based on the voltage amplitude of the third differential signal, which can effectively suppress the common-mode level. Furthermore, the greater the amplification factor of the third differential signal by the signal output device 42, the stronger its common-mode interference immunity.
  • the signal transmission circuit 10 includes an isolation module 20 and a receiving module 40.
  • the receiving module 40 includes a signal receiving circuit 41 and a signal output device 42.
  • the isolation module 20 is used to receive a first differential signal and output a second differential signal after electrically isolating the first differential signal.
  • the signal receiving circuit 41 has its input terminal connected to the output terminal of the isolation module 20 and is used to process the second differential signal and output a third differential signal.
  • the signal output device 42 has its input terminal connected to the output terminal of the signal receiving circuit 41 and is used to combine the third differential signal and output a single signal.
  • the signal transmission circuit 10 provided in this embodiment can achieve the functionality of multiple secondary components in a traditional capacitor isolator architecture using only a single signal output unit 42. This reduces the number of secondary components and simplifies the circuit structure of the secondary side (receiving module 40) of the isolation module 20. The more secondary components and the more complex the circuit structure, the worse the signal transmission performance. Conversely, fewer secondary components and a simpler circuit structure result in fewer factors affecting signal interference and less signal loss, leading to better signal transmission quality and performance. Therefore, the signal transmission circuit 10 provided in this embodiment can improve the signal transmission performance of the capacitor isolator.
  • the signal output device 42 includes a signal merging circuit 45 and a signal inverting circuit 46.
  • the input terminal of the signal combining circuit 45 is connected to the output terminal of the signal receiving circuit 41, and is used to invert and combine the third differential signal into an initial signal.
  • the signal combining circuit 45 can also differentially amplify the third differential signal, and then invert and combine the amplified third differential signal into an initial signal.
  • the input terminal of the signal inverting circuit 46 is connected to the output terminal of the signal combining circuit 45, and is used to invert the initial signal and output a signal.
  • the initial signal output by the signal combining circuit 45 is out of phase with the pulse signal received by the input module as described above.
  • the signal inverting circuit 46 needs to invert the initial signal output by the signal combining circuit 45 to output a new signal.
  • the signal output device 42 includes a signal combining circuit 45 and a signal inverting circuit 46.
  • the input terminal of the signal combining circuit 45 is connected to the output terminal of the signal receiving circuit 41, and is used to invert and combine the third differential signal into an initial signal.
  • the input terminal of the signal inverting circuit 46 is connected to the output terminal of the signal combining circuit 45, and is used to invert the initial signal and output a signal.
  • the signal inverting circuit 46 outputs a signal to the power device on the secondary side. The output signal is almost identical to the pulse signal received by the input module, thereby completing the signal transmission.
  • the signal combining circuit 45 includes a differential amplifier circuit 440 and a combining sub-circuit 450.
  • the input terminal of the differential amplifier circuit 440 is connected to the output terminal of the signal receiving circuit 41, and is used to amplify the third differential signal and output the fourth differential signal.
  • the signal merging circuit 45 first performs differential amplification on the third differential signal based on the differential amplifier circuit 440, and then merges the differential signal after differential amplification (i.e., the fourth differential signal).
  • the differential amplifier circuit 440 may include a metal-oxide-semiconductor (MOS) transistor.
  • MOS metal-oxide-semiconductor
  • a MOS transistor is also called a transistor.
  • the third differential signal is amplified through the amplification effect of the transistor.
  • Other devices capable of amplifying differential signals may also be included in the differential amplifier circuit 440; this embodiment is not limited to any particular type.
  • the differential amplifier circuit 440 may include a single-stage amplifier circuit or a multi-stage amplifier circuit; this embodiment does not impose any limitations.
  • the amplification factor of the differential amplifier circuit 440 can be increased by applying a voltage level.
  • the input terminal of the merging sub-circuit 450 is connected to the output terminal of the differential amplifier circuit 440, and is used to invert and merge the fourth differential signal into the initial signal.
  • the merging sub-circuit 450 can be equipped with a switch that periodically turns on under the control of the fourth differential signal. This switch can be a transistor or a similar type of switch, as long as it can periodically turn on under the control of the differential signal.
  • the signal combining circuit 45 provided in this embodiment includes a differential amplifier circuit 440 and a combining sub-circuit 450.
  • the input terminal of the differential amplifier circuit 440 is connected to the output terminal of the signal receiving circuit 41, and is used to differentially amplify the third differential signal and output a fourth differential signal.
  • the input terminal of the combining sub-circuit 450 is connected to the output terminal of the differential amplifier circuit 440, and is used to invert and combine the fourth differential signal into the initial signal.
  • the larger the amplification factor of the differential amplifier circuit 440 the stronger the common-mode interference immunity of the signal combining circuit 45 and the signal output device 42, which can further improve the signal transmission effect of the signal transmission circuit 10.
  • the differential amplifier circuit 440 includes a first signal input circuit 441 and a second signal input circuit 442.
  • the third differential signal includes a third positive signal (OUTA+ as shown in Figure 4) and a third negative signal (OUTA- as shown in Figure 4).
  • the first signal input circuit 441 receives the third positive signal and the positive trigger level, outputs the fourth positive signal to the merging sub-circuit 450 based on the voltage difference between the third positive signal and the positive trigger level, and outputs a first composite signal of the third positive signal and the positive trigger level to the merging sub-circuit 450.
  • the second signal input circuit 442 receives the third negative signal and the negative trigger level, outputs the fourth negative signal to the merging sub-circuit 450 based on the voltage difference between the third negative signal and the negative trigger level, and outputs a second composite signal of the third negative signal and the negative trigger level to the merging sub-circuit 450.
  • the positive trigger level and the negative trigger level are common-mode levels; the larger the absolute values of the positive trigger level and the negative trigger level, the greater the amplification factor of the differential amplifier circuit 440.
  • the first signal input circuit 441 includes a capacitor CC1, a transistor MC2, and a current source AC1.
  • One end of capacitor CC1 receives the third positive signal, and the other end is connected to the control terminal of transistor MC2.
  • the second end of transistor MC2 is connected to one end of current source AC1.
  • the other end of current source AC1 is connected to a first power supply terminal (VSS as shown in Figure 4). This first power supply terminal is ground or a low-voltage power supply terminal.
  • the first end of transistor MC2 is connected to the first end of transistor MC1.
  • the second end of transistor MC1 is connected to the power supply terminal (VCC as shown in Figure 4).
  • Transistor MC1 forms a pull-up circuit; the pull-up circuit may also include other components, which are not limited in this embodiment.
  • the capacitor CC1 is used to transmit the voltage amplitude of the third positive signal to the positive trigger level (VB+ as shown in Figure 4).
  • the signal input to the control terminal of the transistor MC2 is a first composite signal of the third positive signal and the positive trigger level.
  • the second terminal of the transistor MC2 outputs the fourth positive signal.
  • the second signal input circuit 442 includes a capacitor CC2, a transistor MC3, and a current source AC2.
  • One end of capacitor CC2 receives the third negative signal, and the other end is connected to the control terminal of transistor MC3.
  • the second end of transistor MC3 is connected to one end of current source AC2.
  • the other end of current source AC2 is connected to the first power supply terminal (VSS as shown in Figure 4).
  • the first end of transistor MC3 is connected to the first end of transistor MC1.
  • the second end of transistor MC1 is connected to the power supply terminal (VCC as shown in Figure 4).
  • Transistor MC1 constitutes a pull-up circuit; the pull-up circuit may also include other components, which are not limited in this embodiment.
  • the capacitor CC2 is used to transmit the voltage amplitude of the third negative signal to the negative trigger level (VB- as shown in Figure 4).
  • the signal input to the control terminal of the transistor MC3 is a second composite signal of the third negative signal and the negative trigger level.
  • the second terminal of the transistor MC3 outputs the fourth negative signal.
  • Transistor MC1 can be a PMOS transistor as shown in Figure 4, with the gate as the control terminal, the drain as the first terminal, and the source as the second terminal.
  • Transistor MC2 can be an NMOS transistor as shown in Figure 4, with the gate as the control terminal, the drain as the first terminal, and the source as the second terminal.
  • Transistor MC3 can be an NMOS transistor as shown in Figure 4, with the gate as the control terminal, the drain as the first terminal, and the source as the second terminal.
  • Transistors MC2 and MC3 must be of the same type, such as both being NMOS transistors or both being PMOS transistors.
  • the differential amplifier circuit 440 also includes a circuit for generating a trigger level.
  • This circuit generates common-mode levels such as the positive trigger level and the negative trigger level.
  • the circuit may include transistor MC9, resistors RC3, RC4, and RC5, and current source AC4, as shown in Figure 5.
  • the second terminal of transistor MC9 is connected to the power supply terminal (VCC as shown in Figure 5).
  • the control terminal of transistor MC9 is connected to the first terminal.
  • the first terminal of transistor MC9 is connected to the first terminal of resistor RC3.
  • the second terminal of resistor RC3 is connected to the first terminals of resistors RC4 and RC5.
  • the first terminals of resistors RC4 and RC5 are both connected to the first terminal of current source AC4.
  • the second terminal of current source AC4 is connected to the first power supply terminal.
  • the second terminal of resistor RC4 outputs the positive trigger level.
  • the second terminal of resistor RC5 outputs the negative trigger level.
  • the magnitudes of the positive and negative trigger levels can be adjusted by adjusting the value of resistor R3. The larger the absolute values of the positive and negative trigger levels, the greater the amplification factor of the differential amplifier circuit 440, and correspondingly, the stronger the common-mode interference immunity of the signal output unit 42.
  • the differential amplifier circuit 440 includes a first signal input circuit 441 and a second signal input circuit 442.
  • the first signal input circuit 441 receives the third positive signal and a positive trigger level, outputs the fourth positive signal to the merging sub-circuit 450 based on the third positive signal and the positive trigger level, and outputs a first composite signal of the third positive signal and the positive trigger level to the merging sub-circuit 450.
  • the second signal input circuit 442 receives the third negative signal and a negative trigger level, outputs the fourth negative signal to the merging sub-circuit 450 based on the third negative signal and the negative trigger level, and outputs a second composite signal of the third negative signal and the negative trigger level to the merging sub-circuit 450.
  • the positive trigger level and the negative trigger level are common-mode levels; the larger the absolute values of the positive trigger level and the negative trigger level, the greater the amplification factor of the differential amplifier circuit 440.
  • the amplification factor of the differential amplifier circuit 440 can be adjusted, thereby improving the common-mode interference immunity of the signal output device 42 and further enhancing the signal transmission effect.
  • the differential amplifier circuit 440 has a simple structure, requiring only a few transistors to amplify the signal, reducing the complexity of secondary components in the signal transmission architecture and improving the signal transmission effect.
  • the merging sub-circuit 450 includes a first switching circuit 451, a second switching circuit 452, and a merging unit 453.
  • the input terminal of the first switch circuit 451 is connected to the output terminal of the first signal input circuit 441. When the circuit is turned on under the control of the first synthesized signal, it outputs a first signal to be merged based on the first synthesized signal and the fourth positive signal.
  • the input terminal of the second switch is connected to the output terminal of the second signal input circuit 442. When the circuit is turned on under the control of the second synthesized signal, it outputs a second signal to be merged based on the second synthesized signal and the fourth negative signal.
  • the first switch circuit 451 and the second switch circuit 452 are not turned on or off simultaneously.
  • the first switching circuit 451 may include transistor MC5 as shown in FIG. 4, and may also include resistor RC1 as shown in FIG. 4, where RC1 acts as a load.
  • the control terminal of transistor MC5 receives the first synthesized signal.
  • the first terminal of resistor RC1 is connected to the second terminal of transistor MC2, and the second terminal of resistor RC1 is connected to the second terminal of transistor MC5.
  • the second terminal of transistor MC5 is connected to the second terminal of transistor MC4.
  • the first terminal of transistor MC4 is connected to the power supply terminal (VCC as shown in FIG. 4).
  • the control terminal of transistor MC4 is connected to the control terminal of transistor MC1.
  • Transistor MC4 and transistor MC1 form a current mirror, used to replicate the current of transistor MC1 to transistor MC4.
  • the fourth positive signal output by transistor MC2 is transmitted to transistor MC5 via resistor RC1.
  • Transistor MC5 is turned on or off under the control of the fourth positive signal and the first combined signal. When transistor MC5 is on, it outputs a signal to the second terminal of transistor MC4.
  • the second switching circuit 452 may include transistor MC6 as shown in FIG. 4, and may also include resistor RC2 as shown in FIG. 4, where RC2 acts as a load.
  • the control terminal of transistor MC6 receives the second composite signal.
  • the first terminal of resistor RC2 is connected to the second terminal of transistor MC3, and the second terminal of resistor RC2 is connected to the second terminal of transistor MC6.
  • the second terminal of transistor MC6 is connected to the second terminal of transistor MC4.
  • the fourth negative signal output by transistor MC3 is transmitted to transistor MC6 via resistor RC2.
  • Transistor MC6 is turned on or off under the control of the fourth negative signal and the second combined signal. When transistor MC6 is on, it outputs a signal to the second terminal of transistor MC4.
  • transistor MC5 when transistor MC5 is turned on, transistor MC6 is turned off, and when transistor MC6 is turned off, transistor MC5 is turned on.
  • Transistors MC5 and MC6 can be NMOS transistors as shown in Figure 4.
  • the control terminal of transistor MC5 is the gate, the first terminal is the drain, and the second terminal is the source.
  • the control terminal of transistor MC6 is the gate, the first terminal is the drain, and the second terminal is the source.
  • Transistor MC4 can be a PMOS transistor as shown in Figure 4.
  • the control terminal of transistor MC4 is the gate, the first terminal is the source, and the second terminal is the drain.
  • Transistors MC4 and MC1 form a current mirror.
  • the input terminal of the merging unit 453 is connected to the output terminals of the first switching circuit 451 and the second switching circuit 452, and is used to merge the first signal to be merged and the second signal to be merged into a single initial signal.
  • the merging unit 453 may include the transistor MC4 described above.
  • the merging unit 453 may also include other devices, as long as they can achieve the corresponding functions.
  • the merging sub-circuit 450 includes a first switching circuit 451, a second switching circuit 452, and a merging unit 453.
  • the first switching circuit 451 when turned on under the control of the first synthesized signal, outputs a first signal to be merged based on the first synthesized signal and the fourth positive signal.
  • the merging unit 453 is used to invert and merge the first and second signals to be merged into a single initial signal.
  • the initial signal output by the merging unit 453 is an inverted signal compared to the pulse signal input by the input module as described above. After processing by the signal inversion circuit 46, it can output a signal almost identical to the pulse signal, thereby completing signal transmission.
  • the merging sub-circuit 450 provided in this embodiment has a simple structure, requiring only a few transistors to achieve signal merging, reducing the complexity of secondary devices in the signal transmission architecture and improving the signal transmission effect.
  • the signal inverting circuit 46 includes an inverting unit 460 and a control unit 461.
  • the input terminal of the inverting unit 460 is connected to the output terminal of the merging unit 453, and is used to invert the initial signal and output a signal under the control of the control unit 461.
  • the inverting unit 460 can be an inverter or other device with inverting function.
  • the inverter unit 460 may include transistors MC7 and MC8 as shown in FIG. 4.
  • the control terminals of transistors MC7 and MC8 are connected.
  • a first terminal of transistor MC7 is connected to the power supply terminal (VCC as shown in FIG. 4), and a second terminal is connected to the control terminal.
  • the second terminal is also connected to the second terminal of transistor MC4, the first terminal of transistor MC5, and the first terminal of transistor MC6.
  • the initial signal formed by the second terminal of transistor MC4 is transmitted to the second terminal of transistor MC7.
  • the first terminal of transistor MC8 is connected to the power supply terminal (VCC as shown in FIG. 4), and the second terminal outputs the signal.
  • the control unit 461 may include a current source AC3 as shown in FIG4.
  • the first terminal of the current source AC3 is connected to the second terminal of the transistor MC8, and the second terminal is connected to the first power supply terminal (VSS or low voltage power supply terminal as shown in FIG4).
  • This inverter inverts the initial signal and outputs the corresponding signal (OUTP as shown in Figure 4). At this point, the output signal is almost identical to the pulse signal described above, thus completing the signal transmission.
  • Transistors MC7 and MC8 can be PMOS transistors as shown in Figure 4.
  • the control terminal of transistor MC7 is the gate, the first terminal is the source, and the second terminal is the drain.
  • the control terminal of transistor MC8 is the gate, the first terminal is the source, and the second terminal is the drain.
  • Transistors MC7 and MC8 can also be other types of MOS transistors, but they must meet the condition of forming a current mirror.
  • the signal inverting circuit 46 provided in this embodiment includes an inverting unit 460 and a control unit 461.
  • the inverting unit 460 under the control of the control unit 461, inverts an initial signal and outputs a new signal.
  • the inverting unit 460 and the control unit 461 are simple in construction, requiring only some transistors and current sources to achieve signal inversion, reducing the complexity of secondary devices in the signal transmission architecture and improving the signal transmission effect.
  • the second differential signal includes a second positive signal and a second negative signal.
  • the signal transmission circuit 10 also includes a clamping module 30.
  • the clamping module 30 is connected to the output of the isolation module 20 and is used to clamp the common-mode level of the second positive signal and the second negative signal according to the second positive signal and the second negative signal.
  • the reason for clamping the common-mode level is that transient interference caused during the switching of devices on the 10th side of the signal transmission circuit can lead to a difference between the ground on the main side and the ground on the secondary side. This difference in ground causes the absolute value of the common-mode level (positive or negative) of the second differential signal output by the isolation module 20 to increase.
  • the devices on the secondary side can be understood as power devices.
  • the magnitude of the common-mode level is affected by the operating voltage and switching time of the power devices; the higher the operating voltage and the shorter the switching time, the higher the common-mode level.
  • the devices inside the receiving module 40 have limited withstand voltage. To prevent damage to the devices inside the receiving module 40 due to excessively high common-mode levels, the clamping module 30 clamps the common-mode level below the withstand voltage of the devices inside the receiving module 40 when the common-mode level is too high.
  • the clamping module 30 can be equipped with a circuit for discharging common-mode levels. This circuit can discharge both positive and negative common-mode levels. One end of the circuit receives the second differential signal, and the other end can be connected to a power supply with a lower voltage. When discharging a positive common-mode level, the positive common-mode level is discharged to the power supply with a lower voltage. When discharging a negative common-mode level, the power supply charges the output of the isolation module 20.
  • the clamping circuit needs to be set between the output of the isolation module 20 and the input of the receiving module 40 to clamp the common-mode level of the second differential signal before the second differential signal enters the receiving module 40, thus preventing the common-mode level from damaging the devices in the receiving module 40.
  • the signal transmission circuit 10 provided in this embodiment also includes a clamping module 30.
  • the common-mode level is adjusted based on the second positive signal and the second negative signal.
  • the common-mode level carried by the second positive signal and the common-mode level carried by the second negative signal are clamped equally, improving the clamping effect. More importantly, it prevents the signal transmitted from the main side from having an excessively high common-mode level due to the difference between the main and secondary sides, which could damage the devices on the secondary side.
  • clamping the common-mode level also reduces the risk of signal anomalies from the main side to the secondary side.
  • the clamping module 30 is used to adjust the common-mode level of the second positive signal and the second negative signal when the absolute value of the common-mode level of the second positive signal and the second negative signal is greater than a preset level threshold.
  • the preset level threshold can be less than or equal to the withstand voltage value of the device in the receiving module 40. When there are multiple devices in the receiving module 40, the preset level threshold is less than or equal to the withstand voltage value of the self-test with the worst withstand voltage performance.
  • the common-mode levels of the second positive signal and the second negative signal are adjusted to be less than or equal to the preset threshold. This ensures that the devices in the receiving module 40 are not damaged by the common-mode level, and also ensures that the signals received and output by the receiving module 40 are normal.
  • the clamping module 30 is configured to adjust the common-mode level clamping amount based on the second positive signal and the second negative signal, and to adjust the common-mode level of the second positive signal and the second negative signal based on the common-mode level clamping amount.
  • the clamping amount is determined based on the second positive signal and the second negative signal.
  • the smaller the absolute value of the common-mode level carried by the second positive signal and the second negative signal the smaller the clamping amount can be.
  • Adjusting the common-mode level of the second positive and second negative signals according to the clamping amount means reducing the absolute value of the common-mode level according to the clamping amount.
  • the clamping amount can be understood as a voltage value; for a positive common-mode level, the voltage value is negative, and for a negative common-mode level, the voltage value is positive.
  • the clamping module 30 includes a trigger circuit 31 and a discharge circuit 32.
  • the first input terminal of the trigger circuit 31 receives a second positive signal
  • the second input terminal of the trigger circuit 31 receives a second negative signal
  • the trigger circuit 31 is used to output a trigger signal.
  • the control terminal of the discharge circuit 32 is connected to the output terminal of the trigger circuit 31.
  • the first terminal of the discharge circuit 32 receives the second positive signal
  • the second terminal of the discharge circuit 32 receives the second negative signal
  • the third terminal of the discharge circuit 32 is connected to the first power supply terminal.
  • the first power supply terminal can be ground (VSS shown in Figure 7) or a low-voltage power supply terminal. Low voltage means that when the common-mode level is positive, it is lower than the common-mode level voltage.
  • the second positive signal can be discharged from either the discharge path formed from the first terminal to the third terminal of the discharge circuit 32, or from the discharge path formed from the third terminal to the first terminal of the discharge circuit 32.
  • the discharge circuit 32 controls the amount of charge discharged between its first and third terminals according to the trigger signal.
  • the second negative signal can be discharged from either the discharge path formed from the second terminal to the third terminal of the discharge circuit 32, or from the discharge path formed from the third terminal to the second terminal of the discharge circuit 32.
  • the discharge circuit 32 controls the amount of charge discharged between its second and third terminals according to the trigger signal.
  • both the second positive signal and the second negative signal carry a positive common-mode level
  • the second positive signal is discharged from the discharge path formed from the first terminal to the third terminal of the discharge circuit 32
  • the second negative signal is discharged from the discharge path formed from the second terminal to the third terminal of the discharge circuit 32.
  • both the second positive signal and the second negative signal carry a negative common-mode level
  • the second positive signal is discharged from the discharge path formed by the third terminal to the first terminal of the discharge circuit 32
  • the second negative signal is discharged from the discharge path formed by the third terminal to the second terminal of the discharge circuit 32.
  • the trigger signal is generated when the second positive signal and the second negative signal are input, and is positively correlated with the absolute value of the common-mode level carried by the second positive signal and the second negative signal.
  • This trigger signal is used to trigger the discharge circuit 32 to discharge the common-mode level.
  • the lower the absolute value of the common-mode level the lower the level of the trigger signal, and the smaller the charge discharge between the first and third terminals of the discharge circuit 32, and the smaller the charge discharge between the second and third terminals of the discharge circuit 32.
  • the devices between the first and third ends may be configured to have the same structure as the devices between the second and third ends.
  • the charge discharge amount corresponding to the discharge path from the first to the third terminal is the same as the charge discharge amount corresponding to the discharge path from the second to the third terminal. Furthermore, because they are simultaneously controlled by the trigger signal, the discharge paths from the first and second terminals are formed simultaneously. In this way, the positive common-mode level carried by the second positive signal and the positive common-mode level carried by the second negative signal can be clamped simultaneously and by the same amount.
  • the charge discharge amount corresponding to the discharge path from the third terminal to the first terminal is the same as the charge discharge amount corresponding to the discharge path from the third terminal to the second terminal. Furthermore, because they are simultaneously controlled by the trigger signal, the discharge paths from the third terminal to the first terminal and the third terminal to the second terminal are formed simultaneously. Thus, the negative common-mode level carried by the second positive signal and the negative common-mode level carried by the second negative signal can be clamped simultaneously and by the same amount.
  • the clamping module 30 receives a second positive signal and a second negative signal through the trigger circuit 31, and outputs a trigger signal to the discharge circuit 32.
  • the discharge circuit 32 controls the charge discharge amount according to the trigger signal, and discharges the common-mode level of the second positive signal and the second negative signal based on the charge discharge amount.
  • the problem of excessive absolute value of the common-mode level is effectively suppressed, preventing damage to the devices in the receiving circuit.
  • the same trigger signal is used to control the discharge of the common-mode level of the second positive signal and the second negative signal, the common-mode level carried by the second positive signal and the common-mode level carried by the second negative signal are clamped at the same time and in equal amounts.
  • the bleeder circuit 32 forms a bleeder path from the first terminal to the third terminal.
  • the common-mode level flows from the first terminal to the third terminal. Since the third terminal is connected to the first power supply terminal, which is a low-voltage terminal (e.g., ground), the common-mode level can flow to the low-voltage terminal (e.g., ground), thereby bleeding the common-mode level and achieving the effect of clamping the common-mode level.
  • the discharge circuit 32 When a positive common-mode level is generated, the discharge circuit 32 also forms a discharge path from the second terminal to the third terminal. Correspondingly, the common-mode level flows from the second terminal to the third terminal. Since the third terminal is connected to the first power supply terminal, which is a low-voltage terminal (e.g., ground), the common-mode level can flow to the low-voltage terminal (e.g., ground), thereby discharging the common-mode level and achieving the effect of clamping the common-mode level.
  • the first power supply terminal which is a low-voltage terminal (e.g., ground)
  • the bleeder circuit 32 when a negative common-mode level is formed, that is, when the common-mode level of the second positive signal and the second negative signal is less than the voltage of the first power supply terminal, the bleeder circuit 32 forms a bleedering path from the third terminal to the first terminal.
  • the common-mode level flows from the third terminal connected to the first power supply terminal to the first terminal, that is, from the low-voltage terminal (e.g., ground terminal) to the output terminal of the isolation module 20, thereby suppressing the negative common-mode level.
  • the common-mode level After the common-mode level is bleedered, it flows into the second positive signal, achieving the effect of clamping the common-mode level.
  • the discharge circuit 32 When a negative common-mode level is generated, the discharge circuit 32 also forms a discharge path from the third terminal to the second terminal.
  • the common-mode level flows from the third terminal connected to the first power supply terminal to the second terminal, that is, from the low voltage terminal (e.g., ground terminal) to the output terminal of the isolation module 20, thereby suppressing the negative common-mode level.
  • the common-mode level After the common-mode level is discharged, it flows into the second negative signal, achieving the effect of clamping the common-mode level.
  • the discharge circuit 32 includes a first transistor MA1 and a second transistor MA2.
  • the first transistor MA1 and the second transistor MA2 can be metal-oxide-semiconductor (MOS) transistors as shown in Figure 8.
  • MOS metal-oxide-semiconductor
  • the control terminal of the first transistor MA1 is connected to the control terminal of the second transistor MA2.
  • the gate of the first transistor MA1 is connected to the gate of the second transistor MA2, and the gate is the control terminal.
  • Both the first transistor MA1 and the second transistor MA2 shown in the figure are NMOS transistors, but in actual use they can be replaced with PMOS transistors, as long as common-mode discharge can be achieved. However, it is important to emphasize that the first transistor MA1 and the second transistor MA2 have the same dimensions to ensure that the charge discharge amounts of the first transistor MA1 and the second transistor MA2 are the same.
  • the control terminals of both the first transistor MA1 and the second transistor MA2 receive the trigger signal.
  • the gates of the first transistor MA1 and the second transistor MA2 simultaneously receive the trigger signal, and both transistors MA1 and MA2 are simultaneously triggered to conduct, while the common-mode levels carried by the second positive signal and the second negative signal are simultaneously discharged.
  • the first terminal of the first transistor MA1 is the first terminal of the discharge circuit 32, that is, the first terminal of the first transistor MA1 receives the second positive signal (INPUT+).
  • the second terminal of the first transistor MA1 is connected to the first power supply terminal, which is VSS as shown in Figure 8.
  • the first terminal of the first transistor MA1 is the drain, and the second terminal of the first transistor MA1 is the source.
  • the first transistor MA1 is turned on, and the positive common-mode level flows into the first power supply terminal, achieving the effect of clamping the common-mode level.
  • the first terminal of the first transistor MA1 is the source, and the second terminal of the first transistor MA1 is the drain.
  • the first transistor MA1 is turned on, and the negative common-mode level flows from the first power supply terminal into the output terminal of the isolation module 20, achieving the effect of clamping the common-mode level.
  • the first terminal of the second transistor MA2 is the second terminal of the discharge circuit 32, that is, the second terminal of the second transistor MA2 receives the second negative signal (INPUT-).
  • the second terminal of the second transistor MA2 is connected to the first power supply terminal, which is VSS as shown in Figure 8.
  • VSS voltage supply terminal
  • the first terminal of the second transistor MA2 is the drain, and the second terminal is the source.
  • the second transistor MA2 is turned on, and the positive common-mode level flows into the first power supply terminal, achieving the effect of clamping the common-mode level.
  • a negative common-mode level is formed, the first terminal of the first transistor MA1 is the source, and the second terminal is the drain.
  • the second transistor MA2 is turned on, and the negative common-mode level flows from the first power supply terminal into the second negative signal, achieving the effect of clamping the common-mode level.
  • first transistor MA1 and the second transistor MA2 have the same conduction conditions, the same conduction time, and the same charge discharge amount.
  • the discharge circuit 32 provided in this embodiment allows common-mode levels to be discharged by using transistors that can switch between source and drain. Specifically, the trigger signal controls the first transistor MA1 and the second transistor MA2 to be turned on simultaneously, and the common-mode levels carried by the second positive signal and the second negative signal are discharged simultaneously. This achieves the effect of clamping the common-mode level for both positive and negative common-mode levels.
  • the first transistor MA1 and the second transistor MA2 are formed on the same substrate. This is done to allow either the first transistor MA1 or the second transistor MA2 to switch between its source and drain.
  • the first transistor MA1 can switch from its current source to its drain, and vice versa.
  • the second transistor MA2 can switch from its current source to its drain, and vice versa.
  • the trigger circuit 31 includes a first voltage divider circuit 310 and a second voltage divider circuit 320.
  • the first terminal of the first voltage divider circuit 310 receives the second positive signal, and the second terminal of the first voltage divider circuit 310 is connected to the second terminal of the second voltage divider circuit 320.
  • the second terminal of the first voltage divider circuit 310 is used to output the trigger signal.
  • the third terminal of the first voltage divider circuit 310 is connected to the first power supply terminal.
  • the first terminal of the second voltage divider circuit 320 receives the second negative signal, and the third terminal of the second voltage divider circuit 320 is connected to the first power supply terminal.
  • the first voltage divider circuit 310 is used to divide the second positive signal
  • the second voltage divider circuit 320 is used to divide the second negative signal.
  • the trigger signal is formed when the first voltage divider circuit 310 divides the second positive signal and the second voltage divider circuit 320 divides the second negative signal.
  • the second positive signal and the second negative signal are input simultaneously, and the trigger signal is formed when the second positive signal and the second negative signal are divided after input.
  • the first voltage divider circuit 310 and the second voltage divider circuit 320 have the same voltage dividing capability. Voltage dividing resistors or other voltage dividing devices may be provided in the first voltage divider circuit 310 and the second voltage divider circuit 320, and the provided voltage dividing resistors or other voltage dividing devices should ensure that the voltage dividing capability of the first voltage divider circuit 310 and the second voltage divider circuit 320 is the same.
  • the first voltage divider circuit 310 includes a first resistor RA1 and a second resistor RA2.
  • the second voltage divider circuit 320 includes a third resistor RA3 and a fourth resistor RA4.
  • the first terminal of the first resistor RA1 is the first terminal of the first voltage divider circuit 310, and the second terminal of the first resistor RA1 is connected to the first terminal of the second resistor RA2.
  • the second terminal of the first resistor RA1 is the second terminal of the first voltage divider circuit 310.
  • the second terminal of the second resistor RA2 is the third terminal of the first voltage divider circuit 310. As shown in Figure 8, the first terminal of the first resistor RA1 receives the second positive signal, and the second terminal of the second resistor RA2 is connected to the first power supply terminal.
  • the first terminal of the third resistor RA3 is the first terminal of the second voltage divider circuit 320.
  • the second terminal of the third resistor RA3 is connected to the first terminal of the fourth resistor RA4.
  • the second terminal of the third resistor RA3 is the second terminal of the second voltage divider circuit 320, and the second terminal of the fourth resistor RA4 is the third terminal of the second voltage divider circuit 320.
  • the first terminal of the third resistor RA3 receives the second negative signal, and the second terminal of the fourth resistor RA4 is connected to the first power supply terminal.
  • the resistance values of the first resistor RA1 and the second resistor RA2 can be different.
  • the resistance values of the third resistor RA3 and the fourth resistor RA4 can be different.
  • the first resistor RA1 and the third resistor RA3 should be the same, and the second resistor RA2 and the fourth resistor RA4 should be the same.
  • the first resistor RA1 and the second resistor RA2 divide the voltage
  • the third resistor RA3 and the fourth resistor RA4 divide the voltage, causing the gate voltage of the first transistor MA1 and the gate voltage of the second transistor MA2 to rise.
  • the common-mode current corresponding to the common-mode level flows to the first power supply terminal (e.g., ground terminal) to clamp the common-mode level.
  • the original source of the first transistor MA1 switches to the drain, and the original drain switches to the source.
  • the common-mode current corresponding to the common-mode level flows from the first power supply terminal (e.g., ground) to the second positive signal.
  • the original source of the second transistor MA2 switches to the drain, and the original drain switches to the source.
  • the common-mode current corresponding to the common-mode level flows from the first power supply terminal (e.g., ground) to the second negative signal.
  • the first voltage divider circuit 310 may be further equipped with a resistor
  • the second voltage divider circuit 320 may be further equipped with a resistor. If a resistor is added to the first voltage divider circuit 310, a resistor must also be added to the second voltage divider circuit 320, and the resistance values of the added resistors in the first voltage divider circuit 310 and the second voltage divider circuit 320 should be the same. In addition, the connection positions of the added resistors should be corresponding.
  • connection positions of the added resistors are corresponding. For example, if a resistor is added to the first voltage divider circuit 310, the first end of the added resistor is connected to the first end of the first resistor RA1, and the second end of the added resistor receives the second positive signal. Then, if a resistor of the same value is added to the second voltage divider circuit 320, the first end of the added resistor is connected to the first end of the third resistor RA3, and the second end of the added resistor receives the second negative signal.
  • the voltage divider circuit provided in this embodiment includes a first voltage divider circuit 310 and a second voltage divider circuit 320.
  • the first voltage divider circuit 310 includes a first resistor RA1 and a second resistor RA2
  • the second voltage divider circuit 320 includes a third resistor RA1 and a fourth resistor RA4.
  • the signal receiving circuit 41 includes a pre-stage differential amplifier circuit 43.
  • the input terminal of the pre-stage differential amplifier circuit 43 is connected to the output terminal of the isolation module 20, and is used to amplify the second differential signal and output a third differential signal.
  • the reason why the signal receiving circuit 41 amplifies the first differential signal is that, due to the influence of the isolation module 20 and related parasitic parameters (such as the parasitic parameters of the isolation capacitor, the parasitic parameters of the power device, etc.), the amplitude of the second differential signal output by the isolation module 20 after the first differential signal at the input terminal is transmitted to the output terminal is significantly attenuated, which may prevent it from being processed properly in the next step. Therefore, the attenuated second differential signal can be amplified first so that subsequent devices can recognize it.
  • parasitic parameters such as the parasitic parameters of the isolation capacitor, the parasitic parameters of the power device, etc.
  • the preamplifier circuit 43 compares the voltage differences of the differential signal, thereby reducing the interference of common-mode level on the signal.
  • the preamplifier circuit 43 may include a transistor, which amplifies the second differential signal using the transistor's amplification function.
  • the signal receiving circuit 41 provided in this embodiment includes a pre-stage differential amplifier circuit 43, which is used to differentially amplify the second differential signal, that is, to amplify the differential signal transmitted from the isolation module 20, so that the differential signal can be recognized by subsequent circuits, thereby further improving the signal transmission effect.
  • the pre-amplifier circuit 43 includes a first amplifier circuit 411 shown in Figure 10 and a second amplifier circuit 412 shown in Figure 14.
  • the first amplifier circuit 411 outputs a third positive signal
  • the second amplifier circuit 412 outputs a third negative signal.
  • IN+ shown in Figures 10 and 14 represents the second positive signal after common-mode level clamping
  • IN- represents the second negative signal after common-mode level clamping.
  • the first input terminal of the first amplifier circuit 411 receives the second negative signal (IN- as shown in Figure 10), and the second input terminal of the first amplifier circuit 411 receives the second positive signal (IN+ as shown in Figure 10).
  • the first amplifier circuit 411 is used to generate a third positive signal (OUTA+ as shown in Figure 10) based on the difference between the second negative signal and the second positive signal.
  • the first input terminal of the second amplifier circuit 412 receives the second positive signal (IN+ as shown in Figure 14), and the second input terminal of the second amplifier circuit 412 receives the second negative signal (IN- as shown in Figure 14).
  • the second amplifier circuit 412 is used to generate a third negative signal (OUTA- as shown in Figure 14) based on the difference between the second positive signal and the second negative signal.
  • the first amplifier circuit 411 and the second amplifier circuit 412 have the same structure.
  • the first amplifier circuit 411 is described in detail below.
  • the first amplifier circuit 411 can be configured with a single-stage amplifier sub-circuit or multiple-stage amplifier sub-circuits.
  • the second amplifier circuit 412 can be configured with a single-stage amplifier sub-circuit or multiple-stage amplifier sub-circuits.
  • the amplification levels of the first amplifier circuit 411 and the second amplifier circuit 412 must be the same.
  • the first amplifier circuit 411 includes a first-stage sub-circuit 413.
  • a first input terminal of the first-stage sub-circuit 413 receives the second positive signal
  • a second input terminal of the first-stage sub-circuit 413 receives the second negative signal.
  • the first-stage sub-circuit 413 generates a third positive signal based on the second positive signal and the second negative signal; specifically, the third positive signal is generated based on the difference between the second positive signal and the second negative signal.
  • the first amplifier circuit 411 may also include more stages of sub-circuits, which can be specifically set according to the actual signal amplification requirements.
  • the second amplifier circuit 412 is described in detail below.
  • the second amplifier circuit 412 can be configured with a single-stage amplifier sub-circuit or multiple-stage amplifier sub-circuits. However, the amplification levels of the first amplifier circuit 411 and the second amplifier circuit 412 must be the same.
  • the second amplifier circuit 412 includes a first-stage sub-circuit 413.
  • a first input terminal of the first-stage sub-circuit 413 receives the second positive signal, and a second input terminal of the first-stage sub-circuit 413 receives the second negative signal.
  • the first-stage sub-circuit 413 generates a third negative signal based on the second positive signal and the second negative signal; specifically, it generates the third negative signal based on the voltage difference between the second positive signal and the second negative signal.
  • the first amplifier circuit 411 may also include more stages of sub-circuits, which can be specifically set according to the actual signal amplification requirements.
  • the preamplifier circuit 43 provided in this embodiment includes a first amplifier circuit 411 and a second amplifier circuit 412.
  • the first amplifier circuit 411 generates a third positive signal based on the voltage difference between the second negative signal and the second positive signal.
  • the second amplifier circuit 412 generates a third negative signal based on the voltage difference between the second positive signal and the second negative signal.
  • the third differential signal output by the preamplifier circuit 43 includes a third positive signal and a third negative signal.
  • the following provides a detailed description of cases where the first amplifier circuit 411 includes different numbers of sub-circuits.
  • the first case The first amplifier circuit 411 only contains the first stage sub-circuit 413.
  • the first-stage sub-circuit 413 may include a third pull-up circuit 423 and a third pull-down circuit 424.
  • the first end of the third pull-up circuit 423 is connected to the power supply terminal (VCC as shown in Figure 10), and the second end of the third pull-up circuit 423 is connected to the first end of the third pull-down circuit 424.
  • the control terminal of the third pull-down circuit 424 receives the second negative signal, and the second terminal of the third pull-down circuit 424 receives the second positive signal.
  • the first terminal of the third pull-down circuit 424 outputs the third positive signal.
  • the third pull-down circuit 424 adjusts the downward driving capability of the second positive signal to the first terminal of the third pull-down circuit 424 under the control of the second negative signal.
  • the third pull-up circuit 423 is used to amplify the voltage difference signal output by the third pull-down circuit 424.
  • the voltage difference signal output by the third pull-down circuit 424 is the amplified signal of the voltage difference between the second negative signal and the second positive signal.
  • the third pull-down circuit 424 includes a first capacitor CB1 and a third transistor MB1.
  • the first terminal of the first capacitor CB1 receives the second negative signal, and the second terminal is connected to the control terminal of the third transistor MB1.
  • the first terminal of the first capacitor CB1 is also the first terminal of the third pull-down circuit 424.
  • the first terminal of the third transistor MB1 is connected to the second terminal of the third pull-up circuit 423.
  • the second terminal of the third transistor MB1 receives a second positive signal.
  • the control terminal of the third transistor MB1 is connected to the second terminal of the first capacitor CB1.
  • the third transistor MB1 can be an NMOS transistor as shown in Figure 10.
  • the gate (control terminal) of the third transistor MB1 is connected to the second terminal of the first capacitor CB1, the source receives the second positive signal, and the drain is connected to the second terminal of the third pull-up circuit 423.
  • the third transistor MB1 When the third transistor MB1 is turned on, it outputs the difference between the second negative signal and the second positive signal.
  • the third pull-up circuit 423 includes a transistor (MB2 as shown in Figure 10) and a capacitor (CB2 as shown in Figure 10).
  • the first terminal of the capacitor is connected to the power supply terminal, and the second terminal is connected to the control terminal of the transistor.
  • the first terminal of the transistor is connected to both the power supply terminal and the first terminal of the capacitor, and the second terminal of the transistor is connected to the first terminal of the third transistor MB1.
  • the transistor can be a PMOS transistor as shown in Figure 10, with the first terminal being the source and the second terminal being the drain.
  • the third pull-up circuit 423 After the transistor is turned on, the third pull-up circuit 423 outputs a stable voltage signal, which is used to amplify the voltage difference signal output by the third transistor MB1.
  • the third pull-up circuit 423 can also be equipped with a resistor RB1 as shown in Figure 10.
  • RB1 acts as a load, which further enhances the amplification effect of the voltage difference signal.
  • the third pull-down circuit 424 also includes a second capacitor CB3 and a fourth transistor MB3.
  • the first terminal of the second capacitor CB3 receives the second negative signal, and the second terminal is connected to the control terminal of the fourth transistor MB3.
  • the first terminal of the fourth transistor MB3 is connected to the first terminal of the third transistor MB1, and the second terminal receives the second positive signal.
  • the fourth transistor MB3 After the fourth transistor MB3 is turned on, the voltage difference signal between the second negative signal and the second positive signal is amplified by the fourth transistor MB3 and then input to the first terminal of the third transistor MB1. After the third transistor MB1 is turned on, it outputs the voltage difference signal between the second negative signal and the voltage difference signal output by the fourth transistor MB3, and the third transistor MB1 further amplifies the voltage difference signal.
  • the second capacitor CB3 and the fourth transistor MB3 provided in this embodiment can further improve the amplification effect of the voltage difference signal.
  • the third transistor MB1 and the fourth transistor MB3 can both be NMOS transistors.
  • the control terminal of the fourth transistor MB3 is the gate, the first terminal is the drain, and the second terminal is the source.
  • the first-stage sub-circuit 413 further includes a preset voltage circuit 419.
  • the first terminal of the preset voltage circuit 419 receives the second negative signal, and the second terminal of the preset voltage circuit 419 is connected to the control terminal of the third pull-down circuit 424.
  • the control terminal of the third pull-down circuit 424 is the control terminal of the fourth transistor MB3.
  • the preset voltage circuit 419 generates a preset voltage at the control terminal of the third pull-down circuit 424 based on the second negative signal.
  • the preset voltage output by the preset voltage circuit 419 is input to the gate of the fourth transistor MB3 to further enhance the amplification effect of the voltage difference signal.
  • the preset voltage circuit 419 may include a fifth transistor MB4 and a sixth transistor MB5 (as shown in Figure 12).
  • the control terminal of the fifth transistor MB4 is connected to the other end of the second capacitor CB3, the first end of which receives the second negative signal, and the second end of which is connected to the first end of the sixth transistor MB5.
  • the control terminal of the sixth transistor MB5 is connected to the other end of the first capacitor CB1, and the second end of which is connected to the control terminal of the fourth transistor MB3.
  • the fifth transistor MB4 and the sixth transistor MB5 can both be NMOS transistors.
  • the gate of the fifth transistor MB4 is connected to the second terminal of the second capacitor CB3, its source receives the second negative signal, and its drain is connected to the source of the sixth transistor MB5.
  • the gate of the sixth transistor MB5 is connected to the second terminal of the first capacitor CB1, and its drain is connected to the gate of the fourth transistor MB3.
  • the preset voltage circuit 419 may further include a resistor RB2 and a current source A1 as shown in FIG. 12, where the current source A1 provides the required electrical energy to the resistor RB2.
  • the current source A1 draws power from the power supply terminal VCC.
  • the first end of the resistor RB2 is connected to the current source A1, and the second end is connected to the control terminal of the fourth transistor MB3.
  • the signal input to the fourth transistor MB3 includes the signal output from the second end of the first capacitor CB1 and the signal output from the second end of the resistor RB2.
  • the design of the preset voltage circuit 419 provided in this embodiment can further improve the amplification effect of the voltage difference signal.
  • the first amplifier circuit 411 includes a first-stage sub-circuit 413 and a second-stage sub-circuit 414.
  • the specific structure of the first amplifier circuit 411 can be any of the structures shown above or a variation thereof; this embodiment is not limited.
  • the first amplifier circuit 411 is used to output an intermediate signal
  • the second-stage sub-circuit 414 is used to amplify the intermediate signal and output a third positive signal.
  • the input terminal of the second-stage sub-circuit 414 is connected to the output terminal of the first-stage sub-circuit 413.
  • the second-stage sub-circuit 414 is used to amplify the signal output by the first-stage sub-circuit 413 and output the third positive signal.
  • the second-stage sub-circuit 414 includes a second pull-up circuit 421 and a second pull-down circuit 422.
  • the first terminal of the second pull-up circuit 421 is connected to the power supply terminal (VSS as shown in Figure 13), and the second terminal of the second pull-up circuit 421 is connected to the first terminal of the third pull-down circuit 424.
  • the second terminal of the second pull-down circuit 422 is connected to the second power supply terminal (A3 as shown in Figure 13).
  • the control terminal of the second pull-down circuit 422 receives the signal output by the first-stage sub-circuit 413.
  • the first terminal of the second pull-down circuit 422 outputs a third positive signal.
  • the second pull-down circuit 422 adjusts the downward driving capability of the second power supply terminal to the second terminal of the second pull-down circuit 422, and the first terminal of the second pull-down circuit 422 outputs the third positive signal.
  • the second pull-down circuit 422 includes a seventh transistor MB6.
  • the second pull-up circuit 421 includes an eighth transistor MB7 and a third capacitor CB4.
  • the control terminal of the seventh transistor MB6 is the control terminal of the second pull-down circuit 422, receiving the signal output from the first-stage sub-circuit 413.
  • the first terminal of the seventh transistor MB6 is connected to the second power supply terminal, and the second terminal is connected to the first terminal of the eighth transistor MB7.
  • the control terminal of the eighth transistor MB7 is connected to the first terminal of the third capacitor CB4, and the second terminal is connected to the power supply terminal.
  • the second terminal of the third capacitor CB4 is also connected to the power supply terminal.
  • the seventh transistor MB6 can be an NMOS transistor as shown in Figure 13, with the gate as the control terminal, the source as the second terminal, and the drain as the second terminal.
  • the eighth transistor MB7 can be a PMOS transistor as shown in Figure 13, with the gate as the control terminal, the drain as the first terminal, and the source as the second terminal.
  • the first amplification circuit 411 provided in this embodiment includes a first-stage sub-circuit 413 and a second-stage sub-circuit 414
  • the voltage difference signal between the second positive signal and the second negative signal is amplified once by the first-stage sub-circuit 413
  • the voltage difference signal amplified by the first-stage sub-circuit 413 is amplified again by the second-stage sub-circuit 414, thereby further improving the amplification effect of the voltage difference signal.
  • the following provides a detailed description of the second amplifier circuit 412, which includes different numbers of sub-circuits.
  • the second amplifier circuit 412 only contains the third stage sub-circuit 415.
  • the third-level sub-circuit 415 may include a fourth pull-up circuit 425 and a fourth pull-down circuit 426.
  • the first end of the fourth pull-up circuit 425 is connected to the power supply terminal (VCC as shown in Figure 14), and the second end of the fourth pull-up circuit 425 is connected to the first end of the fourth pull-down circuit 426.
  • the control terminal of the fourth pull-down circuit 426 receives the second positive signal, and the second terminal of the fourth pull-down circuit 426 receives the second negative signal.
  • the first terminal of the fourth pull-down circuit 426 outputs the third negative signal.
  • the fourth pull-down circuit 426 adjusts the downward driving capability of the second positive signal to the first terminal of the fourth pull-down circuit 426 under the control of the second negative signal.
  • the fourth pull-up circuit 425 is used to amplify the voltage difference signal output by the fourth pull-down circuit 426.
  • the voltage difference signal output by the fourth pull-down circuit 426 is the voltage difference signal of the second positive signal minus the second negative signal.
  • the fourth pull-down circuit 426 includes a fourth capacitor CB5 and a ninth transistor MB8.
  • the first terminal of the fourth capacitor CB5 receives the second positive signal, and the second terminal is connected to the control terminal of the ninth transistor MB8.
  • the first terminal of the fourth capacitor CB5 is also the first terminal of the fourth pull-down circuit 426.
  • the first terminal of the ninth transistor MB8 is connected to the second terminal of the fourth pull-up circuit 425.
  • the second terminal of the ninth transistor MB8 receives a second positive signal.
  • the control terminal of the ninth transistor MB8 is connected to the second terminal of the fourth capacitor CB5.
  • the ninth transistor MB8 can be an NMOS transistor as shown in Figure 14, with its gate (control terminal) connected to the second terminal of the fourth capacitor CB5, its source receiving the second positive signal, and its drain connected to the second terminal of the fourth pull-up circuit 425.
  • the ninth transistor MB8 When the ninth transistor MB8 is turned on, it outputs the voltage difference between the second negative signal and the second positive signal.
  • the fourth pull-up circuit 425 includes a transistor MB9 and a capacitor CB6.
  • the first terminal of the capacitor CB6 is connected to the power supply terminal, and the second terminal is connected to the control terminal of the transistor MB9.
  • the first terminal of the transistor MB9 is connected to both the power supply terminal and the first terminal of the capacitor CB6, and the second terminal of the transistor MB9 is connected to the first terminal of the third transistor MB1.
  • the transistor MB9 can be a PMOS transistor as shown in Figure 14.
  • the first terminal of the transistor MB9 is the source, and the second terminal of the transistor MB9 is the drain.
  • the fourth pull-up circuit 425 After the transistor MB9 is turned on, the fourth pull-up circuit 425 outputs a stable voltage signal, which is used to amplify the voltage difference signal output by the ninth transistor MB8.
  • the fourth pull-up circuit 425 can also be equipped with a resistor RB4 as shown in Figure 14.
  • RB4 acts as a load, which further enhances the amplification effect of the voltage difference signal.
  • the fourth pull-down circuit 426 also includes a fifth capacitor CB7 and a tenth transistor MB10.
  • the first terminal of the fifth capacitor CB7 receives the second negative signal, and the second terminal is connected to the control terminal of the tenth transistor MB10.
  • the first terminal of the tenth transistor MB10 is connected to the first terminal of the ninth transistor MB8, and the second terminal receives the second positive signal.
  • the voltage difference signal between the second negative signal and the second positive signal is amplified by the tenth transistor MB10 and then input to the first terminal of the ninth transistor MB8.
  • the ninth transistor MB8 After the ninth transistor MB8 is turned on, it outputs the voltage difference signal between the second negative signal and the voltage difference signal output by the tenth transistor MB10, and the ninth transistor MB8 further amplifies the voltage difference signal.
  • the fifth capacitor CB7 and the tenth transistor MB10 provided in this embodiment can further improve the amplification effect of the voltage difference signal.
  • the ninth transistor MB8 and the tenth transistor MB10 can both be NMOS transistors.
  • the control terminal of the tenth transistor MB10 is the gate, the first terminal is the drain, and the second terminal is the source.
  • the third-level sub-circuit 415 also includes another preset voltage circuit 430.
  • the first terminal of the other preset voltage circuit 430 receives the second positive signal, and the second terminal of the other preset voltage circuit 430 is connected to the control terminal of the third pull-down circuit 424.
  • the control terminal of the third pull-down circuit 424 is the control terminal of the tenth transistor MB10.
  • the other preset voltage circuit 430 is used to generate a preset voltage at the control terminal of the third pull-down circuit 424 based on the second positive signal.
  • the preset voltage output by the other preset voltage circuit 430 is input to the gate of the tenth transistor MB10 to further enhance the amplification effect of the voltage difference signal.
  • the other preset voltage circuit 430 may include an eleventh transistor MB11 and a twelfth transistor MB12.
  • the control terminal of the eleventh transistor MB11 is connected to the other end of the fifth capacitor CB7, the first end of which receives a second positive signal, and the second end of which is connected to the first end of the eleventh transistor MB12.
  • the control terminal of the eleventh transistor MB12 is connected to the other end of the fourth capacitor CB5, and the second end of which is connected to the control terminal of the tenth transistor MB10.
  • Both eleventh transistors MB11 and MB12 can be NMOS transistors.
  • the gate of eleventh transistor MB11 is connected to the second terminal of the fifth capacitor CB7, its source receives the second negative signal, and its drain is connected to the source of eleventh transistor MB12.
  • the gate of eleventh transistor MB12 is connected to the second terminal of the fourth capacitor CB5, and its drain is connected to the gate of the tenth transistor MB10.
  • a resistor RB5 and a current source A2 can also be provided.
  • Current source A2 provides the necessary power to the branch containing resistor RB5.
  • Current source A2 draws power from the power supply terminal VCC.
  • the first end of resistor RB5 is connected to current source A2, and the second end is connected to the control terminal of the tenth transistor MB10.
  • the signal input to the tenth transistor MB10 includes the signal output from the second terminal of the first capacitor CB1 and the signal output from the second terminal of resistor RB5.
  • the resistor RB5 is used to amplify the voltage difference signal.
  • the design of the other preset voltage circuit 430 provided in this embodiment can further improve the amplification effect of the voltage difference signal.
  • the second amplifier circuit 412 includes a third-stage sub-circuit 415 and a fourth-stage sub-circuit 416.
  • the specific structure of the second amplifier circuit 412 can be any of the structures shown above or a variation thereof; this embodiment is not limited to any particular structure.
  • the signal output by the second amplifier circuit 412 is not the third negative signal, and the fourth-stage sub-circuit 416 outputs the third negative signal.
  • the input terminal of the fourth-stage sub-circuit 416 is connected to the output terminal of the third-stage sub-circuit 415.
  • the fourth-stage sub-circuit 416 is used to amplify the signal output by the third-stage sub-circuit 415 and output the third positive signal.
  • the fourth-stage sub-circuit 416 includes a fifth pull-up circuit 427 and a fifth pull-down circuit 428.
  • the first terminal of the fifth pull-up circuit 427 is connected to a power supply terminal (VSS as shown in Figure 17), and the second terminal of the fifth pull-up circuit 427 is connected to the first terminal of the fifth pull-down circuit 428.
  • the second terminal of the fifth pull-down circuit 428 is connected to a second power supply terminal (A3 as shown in Figure 17). This second power supply terminal is used to make the voltage difference signal more differential.
  • the control terminal of the fifth pull-down circuit 428 receives the signal output from the third-stage sub-circuit 415.
  • the first terminal of the fifth pull-down circuit 428 outputs a third positive signal.
  • the fifth pull-down circuit 428 adjusts the downward driving capability of the second power supply terminal to the second terminal of the fifth pull-down circuit 428 under the control of the second positive signal, and the first terminal of the fifth pull-down circuit 428 outputs the third negative signal.
  • the fifth pull-down circuit 428 includes a thirteenth transistor MB13.
  • the fifth pull-up circuit 427 includes a fourteenth transistor MB14 and a sixth capacitor CB8.
  • the control terminal of the thirteenth transistor MB13 is the control terminal of the fifth pull-down circuit 428, receiving the signal output from the third-stage sub-circuit 415.
  • the first terminal of the thirteenth transistor MB13 is connected to the second power supply terminal, and the second terminal is connected to the first terminal of the fourteenth transistor MB14.
  • the control terminal of the fourteenth transistor MB14 is connected to the first terminal of the sixth capacitor CB8, and the second terminal is connected to the power supply terminal.
  • the second terminal of the sixth capacitor CB8 is connected to the power supply terminal.
  • the thirteenth transistor MB13 can be an NMOS transistor as shown in Figure 17, with the gate as the control terminal, the source as the second terminal, and the drain as the second terminal.
  • the fourteenth transistor MB14 can be a PMOS transistor as shown in Figure 17, with the gate as the control terminal, the drain as the first terminal, and the source as the second terminal.
  • the second amplifier circuit 412 provided in this embodiment includes a third-stage sub-circuit 415 and a fourth-stage sub-circuit 416
  • the voltage difference signal between the second positive signal and the second negative signal is amplified once by the third-stage sub-circuit 415, and then the voltage difference signal amplified by the third-stage sub-circuit 415 is amplified again by the fourth-stage sub-circuit 416, thereby further improving the amplification effect of the voltage difference signal.
  • One embodiment of the signal transmission circuit 10 provided in this application also includes an input module 50.
  • the input terminal of the input module 50 receives the input signal, and the output terminal of the input module 50 is connected to the isolation module 20. After modulating the input signal, the first differential signal is output.
  • the input signal can be a square wave pulse signal as shown in Figure 19.
  • the input module 50 can include an oscillator 51 and a logic circuit 52 as shown in Figure 18.
  • the oscillator 51 is used to output a continuous and high-frequency oscillation signal as shown in Figure 20.
  • the oscillator 51 can be of various types, such as a ring oscillator.
  • the signal frequency of the oscillator 51 can be adjusted according to internal resistors and capacitors.
  • the signal frequency of the input signal must be lower than the signal frequency of the oscillator 51 signal, and the pulse width must be at least two cycles of the oscillator 51 signal to ensure signal transmission.
  • the logic circuit 52 includes AND gates and NOT gates. After the input signal and the oscillation signal enter the logic circuit 52, one signal is output through the AND gate, and another signal is output through the NOT gate. The two signals are differential, and are differential high-frequency signals with similar pulse widths.
  • the logic circuit 52 outputs the differential signal shown in Figure 21.
  • the differential signal shown in Figure 21 is the aforementioned first differential signal. This first differential signal is input to the isolation module 20.
  • the input module 50 may further include a driving circuit 53 as shown in FIG18, in which case the driving circuit 53 outputs the first differential signal.
  • the waveform of the first differential signal output by the driving circuit 53 is approximately the same as that of the signal output by the logic circuit 52, the main difference being the enhanced driving capability.
  • the driving circuit 53 is used to further enhance the strength of the differential signal output by the logic circuit 52.
  • the high-voltage isolation capacitor in the isolation module 20 achieves extremely high withstand voltage, thus preventing transient interference from the secondary side from being transmitted to the primary side and protecting the circuitry in the input module 50 from damage. Furthermore, the input module 50 processes the input signal into a differential signal and sends it to the isolation module 20 in differential form, which reduces common-mode interference.
  • the signal transmission circuit further includes a filter circuit 44 as shown in Figure 22.
  • the filter circuit 44 is used to filter the second differential signal output by the isolation module 20.
  • the filter circuit 44 can be a high-pass filter. As shown in Figure 23, the filter circuit 44 includes resistors R1 and R2. The first terminal of resistor R1 receives the second positive signal, and the second terminal is grounded. The first terminal of resistor R2 receives the second negative signal, and the second terminal is grounded. Resistors R1 and R2, together with the isolation capacitor in the isolation module 20, form a high-pass filter, which can greatly attenuate interference from low-frequency signals.
  • the filter circuit 44 connected to the input terminal of the receiving module 40 must be matched between the two signal channels to prevent signal failure.
  • the filter circuit 44 can be set between the isolation module 20 and the clamping module 30, or it can be set in other positions according to actual needs. This embodiment does not limit it.
  • the filter circuit 44 provided in this embodiment can also be other filters, as long as they can attenuate interference from low-frequency signals.
  • the receiving module 40 further includes a delay circuit 47.
  • the input of the delay circuit 47 is connected to the output of the signal output device 42.
  • the delay circuit 47 is used to filter out abnormal signals in one of the signals output by the signal outputter 42 and then output another signal.
  • the delay circuit 47 can be a transistor delay circuit or other types of delay circuits, which can be selected according to actual needs. This embodiment does not limit the choice.
  • the delay circuit 47 provided in this embodiment can improve the accuracy of the output signal of the signal transmission circuit and also improve the anti-interference capability of the signal transmission circuit to a certain extent.
  • Some embodiments of this application also provide a signal transmission system 60.
  • the signal transmission system 60 includes a signal transmission circuit 10 as provided in any of the above embodiments, and also includes a controller 61, a drive module 62, and a power device 63.
  • the output terminal of the controller 61 is connected to the input terminal of the signal transmission circuit 10.
  • the controller 61 can be a microcontroller unit (MCU).
  • the output signal of the controller 61 is a square wave pulse signal.
  • the input terminal of the drive module 62 is connected to the output terminal of the signal transmission circuit 10, receiving the single-channel signal output by the signal transmission circuit 10.
  • the single-channel signal output by the signal transmission circuit 10 is a square wave pulse signal.
  • the drive module 62 is used to boost the signal output by the signal transmission circuit 10 before outputting it to the power device 63 to drive the power device 63. That is, the drive module 62 is used to further drive the square wave pulse signal to meet the usage requirements of the power device 63.
  • the power device 63 is, for example, a silicon carbide power device, an insulated-gate bipolar transistor (IGBT).
  • IGBT insulated-gate bipolar transistor
  • the signal transmission system 60 provided in this embodiment clamps the transient interference generated by the switching of the power device 63 by the signal transmission circuit 10, thus preventing damage to the signal transmission circuit 10. Compared with existing signal transmission systems 60, it offers higher security and greater practicality.
  • an electronic control system 70 for a vehicle which includes the signal transmission system 60 as provided in any of the preceding embodiments, and may further include a load 71.
  • the load 71 is, for example, a motor.
  • the power device 63 can be an IGBT as shown in Figure 26, and the IGBT is connected to the motor on the vehicle.
  • Some embodiments of this application also provide a vehicle, as shown in FIG27, the vehicle 100 including the electronic control system 70 of the vehicle as described above.
  • the vehicle may also be equipped with other functions, such as head-up display function, adaptive cruise function, active braking function, etc., which are not limited in this embodiment.
  • the vehicle 100 further includes a battery 102 and a charger 101.
  • An electronic control system 70 is connected to the charger 101 and the battery 102, and the charger 101 is connected to the battery 102.
  • the electronic control system 70 can monitor the state of the battery 102 and control the charging parameters of the charger 101 according to the state of the battery 102.
  • the charger 101 charges the battery 102 according to the charging parameters.
  • the electronic control system 70 may include a battery management system (BMS) for monitoring the state of the battery 101, such as voltage, current, temperature, and charging status.
  • BMS battery management system
  • the battery management system may also communicate with the charger 101 to enable the charger 101 to adjust charging parameters.
  • the electronic control system may also include a vehicle control unit (VCU), which is responsible for the overall management and coordination of the vehicle, including powertrain control, energy management, regenerative braking, and thermal management. It may also include a motor controller, which controls the operation of the drive motors, including regulating current and voltage to control the motor's speed and torque.
  • VCU vehicle control unit
  • motor controller which controls the operation of the drive motors, including regulating current and voltage to control the motor's speed and torque.

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Abstract

本申请属于电容隔离技术领域，提供一种信号传输电路及信号传输系统、电控系统、车辆。信号传输电路包括：隔离模块和接收模块，所述接收模块包括信号接收电路和信号输出器；所述隔离模块，用于接收第一差分信号，并对所述第一差分信号进行电气隔离后输出第二差分信号；所述信号接收电路，输入端与所述隔离模块的输出端连接，用于对所述第二差分信号进行处理后输出第三差分信号；所述信号输出器，输入端与所述信号接收电路的输出端连接，用于将所述第三差分信号合并后输出一路信号。本申请可以提升电容隔离器的信号传输效果。

Description

信号传输电路及信号传输系统、电控系统、车辆
本申请要求于2024年07月30日提交中国专利局、申请号为：202411038834.1、申请名称为“信号传输电路及信号传输系统、电控系统、车辆”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电容隔离技术领域，尤其涉及一种信号传输电路及信号传输系统、电控系统、车辆。
背景技术
电容隔离器主要用于隔离高压域和低压域，用以实现不同电源域之间的“地”隔离，常用在处于不同电源域的芯片或系统之间的信号传输。
目前电容隔离器的使用架构是：电容隔离器的主边输入信号，通过电容隔离器传递信号到次边，由次边输出信号。这种使用架构存在信号传输效果差的问题。
如何提升电容隔离器的信号传输效果，仍然是亟待解决的。
发明内容
本申请的目的在于提供一种信号传输电路及信号传输系统、电控系统、车辆，用于提升电容隔离器的信号传输效果。
第一方面，本申请公开了一种信号传输电路，包括：隔离模块和接收模块，所述接收模块包括信号接收电路和信号输出器；
所述隔离模块，用于接收第一差分信号，并对所述第一差分信号进行电气隔离后输出第二差分信号；
所述信号接收电路，输入端与所述隔离模块的输出端连接，用于对所述第二差分信号进行处理后输出第三差分信号；
所述信号输出器，输入端与所述信号接收电路的输出端连接，用于将所述第三差分信号合并后输出一路信号。
第二方面，本申请公开了一种信号传输系统，包括如第一方面所述的信号传输电路，还包括：控制器、驱动模块和功率器件；
所述控制器的输出端与所述信号传输电路的输入端连接；
所述驱动模块的输入端与所述信号传输电路的输出端连接；
所述功率器件的输入端与所述驱动模块的输出端连接；
所述驱动模块用于对所述信号传输电路输出的信号进行升压处理后输出至所述功率器件，以驱动所述功率器件运行。
第三方面，本申请提供一种车辆的电控系统，包括如第二方面所述的信号传输系统。
第四方面，本申请提供一种车辆，包括如第三方面所述的车辆的电控系统。
结合上述技术方案，本申请公开的信号传输电路包括隔离模块和接收模块，该接收模块包括信号接收电路和信号输出器。所述隔离模块，用于接收第一差分信号，并对所述第一差分信号进行电气隔离后输出第二差分信号。所述信号接收电路，输入端与所述隔离模块的输出端连接，用于对所述第二差分信号进行处理后输出第三差分信号。所述信号输出器，输入端与所述信号接收电路的输出端连接，用于将所述第三差分信号合并后输出一路信号。
相比于次边器件数量多、使用架构复杂度高的传统电容隔离器使用架构，本实施例提供的信号传输电路，用一个信号输出器就可以实现传统电容隔离器使用架构中多个次边器件的功能，减少次边器件的数量，且简化了隔离模块次边(该接收模块)的电路结构。次边器件越多、次边的电路结构越复杂，则信号传输效果越差。相反的，若次边器件越少，次边的电路结构越简单，则信号受干扰的因素越少，信号的损耗也更少，所以信号传输质量和传输效果更佳。因此，本实施例提供的信号传输电路可以提升电容隔离器的信号传输效果。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一些实施例提供的信号传输电路的结构示意图；
图2为本申请一些实施例提供的信号传输电路的结构示意图；
图3为本申请一些实施例提供的信号传输电路的结构示意图；
图4为本申请一些实施例提供的信号传输电路中差分放大电路的结构示意图；
图5为本申请一些实施例提供的信号传输电路中用于产生触发电平的电路的结构示意图；
图6为本申请一些实施例中提供的信号传输电路的结构示意图；
图7为本申请一些实施例提供的信号传输电路中钳位模块的结构示意图；
图8为本申请一些实施例提供的信号传输电路中钳位模块的结构示意图；
图9为本申请一些实施例提供的信号传输电路的结构示意图；
图10为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图11为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图12为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图13为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图14为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图15为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图16为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图17为本申请一些实施例提供的信号传输电路中前级差分放大器的部分结构示意图；
图18为本申请一些实施例提供的信号传输电路中输入模块的结构示意图；
图19为本申请一些实施例提供的信号传输电路中输入信号的示意图；
图20为本申请一些实施例提供的信号传输电路中振荡器信号的示意图；
图21为本申请一些实施例提供的信号传输电路中第一差分信号的示意图；
图22为本申请一些实施例提供的信号传输电路中的结构示意图；
图23为本申请一些实施例提供的信号传输电路中滤波电路的结构示意图；
图24为本申请一些实施例提供的信号传输电路的结构示意图；
图25为本申请一些实施例提供的信号传输系统的结构示意图；
图26为本申请一些实施例提供的电控系统的结构示意图；
图27为本申请一些实施例提供的车辆的结构示意图。
附图标记说明：
10-信号传输电路；
20-隔离模块；
30-钳位模块；31-触发电路；32-泄放电路；
40-接收模块；41-信号接收电路；42-信号输出器；43-前级差分放大电路；44-滤波电
路；45-信号合并电路；46-信号反相电路；47-延时电路；
50-输入模块；51-振荡器；52-逻辑电路；53-驱动电路；
60-信号传输系统；61-控制器；62-驱动模块；63-功率器件；
70-电控系统；71-负载；
310-第一分压电路；320-第二分压电路；
411-第一放大电路；412-第二放大电路；413-第一级子电路；414-第二级子电路；415-
第三级子电路；416-第四级子电路；419-预置电压电路；421-第二上拉电路；422-第二下拉电路；423-第三上拉电路；424-第三下拉电路；425-第四上拉电路；426-第四下拉电路；427-第五上拉电路；428-第五下拉电路；430-另一预置电压电路；
440-差分放大电路；441-第一信号输入电路；442-第二信号输入电路；
450-合并子电路；451-第一开关电路；452-第二开关电路；453-合并单元；
460-反相单元；461-控制单元。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应作广义理解，例如，可以使固定连接，也可以是通过中间媒介间接相连，可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或者位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或者暗示所指的装置或者元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。
此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或维护工具不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或维护工具固有的其它步骤或单元。
电容隔离器主要用于隔离高压域和低压域，用以实现不同电源域之间的“地”隔离，常用在处于不同电源域的芯片或系统之间的信号传输。目前电容隔离器的使用架构是：电容隔离器的主边输入信号，通过电容隔离器传递信号到次边，由次边输出信号。
这种使用架构电路复杂度高，导致信号传输效果差。
基于此，本申请提供一种信号传输电路及信号传输系统、电控系统、车辆。
其中，该信号传输电路包括隔离模块和接收模块，该接收模块包括信号接收电路和信号输出器。该隔离模块，用于接收第一差分信号，并对该第一差分信号进行电气隔离后输出第二差分信号。该信号接收电路，输入端与该隔离模块的输出端连接，用于对该第二差分信号进行处理后输出第三差分信号。该信号输出器，输入端与该信号接收电路的输出端连接，用于将该第三差分信号合并后输出一路信号。
相比于次边器件数量多、使用架构复杂度高的传统电容隔离器使用架构，本申请提供的信号传输电路，用一个信号输出器就可以实现传统电容隔离器使用架构中多个次边器件的功能，减少次边器件的数量，且简化了隔离模块次边(该接收模块)的电路结构。次边器件越多、次边的电路结构越复杂，则信号传输效果越差。相反的，若次边器件越少，次边的电路结构越简单，则信号受干扰的因素越少，信号的损耗也更少，所以信号传输质量和传输效果更佳。因此，本申请提供的信号传输电路可以提升电容隔离器的信号传输效果。
请参见图1，本申请的一个实施例提供一种信号传输电路10，包括隔离模块20和接收模块40。
针对该隔离模块20的描述如下：
该隔离模块20用于接收第一差分信号，并输出第二差分信号。具体的，该隔离模块20用于对该第一差分信号进行电气隔离后输出该第二差分信号。
其中，该第一差分信号由输入模块输出。输入模块连接芯片时，将该芯片输出到输入模块的脉冲信号处理为第一差分信号。第一差分信号也可以是其他模块输出，此处不做限制。
如图1所示的，第一差分信号包括第一正向信号(OUT+)和第一负向信号(OUT-)。该隔离模块20接收第一正向信号后输出第二正向信号(INPUT+)，接收第一负向信号后输出第二负向信号(INPUT-)。
一些可选的实施例中，该隔离模块20为电容隔离模块20，包含隔离电容，该隔离电容可以是高压隔离电容。
示例的，针对第一正向信号(OUT+)可以设置至少一个高压隔离电容，可以设置两个相互串联的高压隔离电容。对应的，针对第二正向信号(OUT-)可以设置至少一个高压隔离电容，设置两个相互串联的高压隔离电容。
需要说明的是，针对第一正向信号和第二正向信号，所设置的高压隔离电容的数量需要一致，譬如针对第一正向信号设置了两个相互串联的高压隔离电容，则针对第二正向信号也需要设置两个相互串联的高压隔离电容。
针对该接收模块40的描述如下：
该接收模块40用于对该第二差分信号进行解调处理后输出。该解调处理，可以是对该第二差分信号进行放大后再融合。
该接收模块40包括信号接收电路41和信号输出器42。
其中，该信号接收电路41的输入端与该隔离模块20的输出端连接。该信号接收电路41用于对该第二差分信号进行处理后输出第三差分信号。该信号接收电路41可以对该第二差分信号进行放大处理、滤波处理等。该放大处理可以包括一级放大处理、多级放大处理。该滤波处理可以包括一次滤波处理、多次滤波处理。
其中，该信号输出器42的输入端与该信号接收电路41的输出端连接。该信号输出器42用于将该第三差分信号合并后输出一路信号。该一路信号与以上描述的该芯片输出到输入模块的脉冲信号几乎相同。
该信号输出器42可以由电阻、电容等构成，电路结构简单。
可选的，该信号输出器42还可以对该第三差分信号进行差分放大后再反相合并为一路信号。可以理解的是，该信号传输电路10的实际使用中，次边器件的输出端连接功率器件的输入端，功率器件开关时，由于隔离模块20对地的寄生电容较大，而造成隔离模块20输出的信号携带共模电平，共模电平过大时就会损坏次边器件。该信号输出器42对该第三差分信号进行放到处理时，基于该第三差分信号的电压幅度进行差分放大，可以有效抑制共模电平。进一步的，该信号输出器42对该第三差分信号的放大倍数越大，该信号输出器42的抗共模干扰能力就越强。
综上，本实施例提供的该信号传输电路10包括隔离模块20和接收模块40，该接收模块40包括信号接收电路41和信号输出器42。该隔离模块20，用于接收第一差分信号，并对该第一差分信号进行电气隔离后输出第二差分信号。该信号接收电路41，输入端与该隔离模块20的输出端连接，用于对该第二差分信号进行处理后输出第三差分信号。该信号输出器42，输入端与该信号接收电路41的输出端连接，用于将该第三差分信号合并后输出一路信号。
相比于次边器件数量多、使用架构复杂度高的传统电容隔离器使用架构，本实施例提供的信号传输电路10，用一个信号输出器42就可以实现传统电容隔离器使用架构中多个次边器件的功能，减少次边器件的数量，且简化了隔离模块20次边(该接收模块40)的电路结构。次边器件越多、次边的电路结构越复杂，则信号传输效果越差。相反的，若次边器件越少，次边的电路结构越简单，则信号受干扰的因素越少，信号的损耗也更少，所以信号传输质量和传输效果更佳。因此，本实施例提供的信号传输电路10可以提升电容隔离器的信号传输效果。
请参见图2，本申请的一些实施例中，该信号输出器42包括：信号合并电路45和信号反相电路46。
其中，该信号合并电路45的输入端与该信号接收电路41的输出端连接，用于将该第三差分信号反相合并为一路初始信号。可选的，该信号合并电路45还可以对该第三差分信号进行差分放大后，再将差分放大后的该第三差分信号反相合并为一路初始信号。
其中，该信号反相电路46的输入端与该信号合并电路45的输出端连接，用于将该一路初始信号反相后输出一路信号。
需要说明的是，该信号合并电路45输出的该一路初始信号，是与如上所描述的输入模块接收的脉冲信号反相的。为了使最终输出的信号与输入模块接收的脉冲信号几乎相同，需要由该信号反相电路46对该信号合并电路45输出的一路初始信号进行反相后输出一路信号。
本实施例提供的信号传输电路10中，该信号输出器42包括信号合并电路45和信号反相电路46。该信号合并电路45的输入端与该信号接收电路41的输出端连接，用于将该第三差分信号反相合并为一路初始信号。该信号反相电路46的输入端与该信号合并电路45的输出端连接，用于将该一路初始信号反相后输出一路信号。该信号反相电路46输出一路信号至次边的功率器件，输出的一路信号与输入模块接收的脉冲信号几乎相同，由此完成信号的传输。
请参见图3，本申请的一些实施例中，该信号合并电路45包括：差分放大电路440和合并子电路450。
其中，该差分放大电路440的输入端与该信号接收电路41的输出端连接，用于对该第三差分信号进行放大处理后输出第四差分信号。
也就是说，该信号合并电路45先基于该差分放大电路440对该第三差分信号先进行差分放大处理，再对差分放大处理后的差分信号(即该第四差分信号)进行合并。
可选的，该差分放大电路440中可以设置金属-氧化物-半导体(Metal-Oxide-Semiconductor，简称MOS)管等。MOS管也称为晶体管。通过晶体管的放大作用，对该第三差分信号进行放大。该差分放大电路440中还可以设置其他可以对差分信号进行放大的器件，本实施例不做限定。
该差分放大电路440可以包含一级放大电路或多级放大电路，本实施例不做限定。
如上所描述的，该信号输出器42对该第三差分信号的放大倍数越大，该信号输出器42的抗共模干扰能力就越强。也就是说，该差分放大电路440的放大倍数越大，该信号输出器42的抗共模干扰能力越强。可选的，可以通过施加电平的方式提升该差分放大电路440的放大倍数。
其中，该合并子电路450的输入端与该差分放大电路440的输出端连接，用于将该第四差分信号反相合并为该一路初始信号。该合并子电路450中可以设置在该第四差分信号的控制下周期性导通的开关，该开关可以是晶体管，或者是类型的开关，只要能够在差分信号的控制下周期性导通即可。
本实施例提供的该信号合并电路45包括差分放大电路440和合并子电路450。该差分放大电路440的输入端与该信号接收电路41的输出端连接，用于对该第三差分信号进行差分放大处理后输出第四差分信号。该合并子电路450的输入端与该差分放大电路440的输出端连接，用于将该第四差分信号反相合并为该一路初始信号。该差分放大电路440的放大倍数越大，该信号合并电路45以及该信号输出器42的抗共模干扰能力越强，能够进一步提升该信号传输电路10的信号传输效果。
请参见图4，本申请的一些实施例中，该差分放大电路440包括第一信号输入电路441和第二信号输入电路442。该第三差分信号包括第三正向信号(如图4所示的OUTA+)和该第三负向信号(如图4所示的OUTA-)。
该第一信号输入电路441用于接收该第三正向信号和正向触发电平，根据该第三正向信号和该正向触发电平的电压差输出该第四正向信号至该合并子电路450，以及将该第三正向信号和该正向触发电平的第一合成信号输出至该合并子电路450。该第二信号输入电路442用于接收该第三负向信号和负向触发电平，根据该第三负向信号和该负向触发电平的电压差输出该第四负向信号至该合并子电路450，以及将该第三负向信号和该负向触发电平的第二合成信号输出至该合并子电路450。其中，该正向触发电平和该负向触发电平为共模电平，该正向触发电平的绝对值和该负向触发电平的绝对值越大，该差分放大电路440的放大倍数越大。
如图4所示的示例，该第一信号输入电路441包含电容CC1、晶体管MC2和电流源AC1。其中，电容CC1的一端接收该第三正向信号，另一端与该晶体管MC2的控制端连接。该晶体管MC2的第二端与该电流源AC1的一端连接。该电流源AC1的另一端连接第一电源端(如图4所示的VSS)。该第一电源端为地端或者低压电源端。该晶体管MC2的第一端与晶体管MC1的第一端连接。晶体管MC1的第二端与电源端(如图4所示的VCC)连接。晶体管MC1构成上拉电路，上拉电路还可以包含其他器件，本实施例不做限定。
该电容CC1用于将该第三正向信号的电压幅度传输到正向触发电平(如图4所示的VB+)上。该晶体管MC2的控制端输入的信号是该第三正向信号和该正向触发电平的第一合成信号。该晶体管MC2的第二端输出该第四正向信号。
如图4所示的示例，该第二信号输入电路442包含电容CC2、晶体管MC3和电流源AC2。其中，电容CC2的一端接收该第三负向信号，另一端与该晶体管MC3的控制端连接。该晶体管MC3的第二端与该电流源AC2的一端连接。该电流源AC2的另一端连接该第一电源端(如图4所示的VSS)。该晶体管MC3的第一端与该晶体管MC1的第一端连接。该晶体管MC1的第二端与电源端(如图4所示的VCC)连接。该晶体管MC1构成上拉电路，上拉电路还可以包含其他器件，本实施例不做限定。
该电容CC2用于将该第三负向信号的电压幅度传输到负向触发电平(如图4所示的VB-)上。该晶体管MC3的控制端输入的信号是该第三负向信号和该负向触发电平的第二合成信号。该晶体管MC3的第二端输出该第四负向信号。
该晶体管MC1可以是如图4所示的PMOS管，该晶体管MC1的控制端为栅极，第一端为漏极，第二端为源极。该晶体管MC2可以是如图4所示的NMOS管，该晶体管MC2的控制端为栅极，第一端为漏极，第二端为源极。该晶体管MC3可以是如图4所示的NMOS管，该晶体管MC3的控制端为栅极，第一端为漏极，第二端为源极。该晶体管MC2与该晶体管MC3需为同类型的晶体管，比如都是NMOS管或都是PMOS管。
请参见图5，该差分放大电路440还包括用于产生触发电平的电路。该电路用于产生该正向触发电平和该负向电平这样的共模电平。该电路可以包括如图5所示的晶体管MC9、电阻RC3、电阻RC4、电阻RC5和电流源AC4。其中，晶体管MC9的第二端连接电源端(如图5所示的VCC)。晶体管MC9的控制端与第一端连接。晶体管MC9的第一端与电阻RC3的第一端连接。电阻RC3的第二端与电阻RC4的第一端和电阻RC5的第一端连接。电阻RC4的第一端和电阻RC5的第一端均与电流源AC4的第一端连接。电流源AC4的第二端连接该第一电源端。
电阻RC4的第二端输出该正向触发电平。电阻RC5的第二端输出该负向触发电平。可以通过调节电阻R3的大小来调节该正向触发电平和该负向触发电平的大小。该正向触发电平的绝对值和该负向触发电平的绝对值越大，该差分放大电路440的放大倍数越大，对应的，该信号输出器42的抗共模干扰能力越强。
本实施例提供的信号传输电路10中，该差分放大电路440包括第一信号输入电路441和第二信号输入电路442。该第一信号输入电路441用于接收该第三正向信号和正向触发电平，根据该第三正向信号和该正向触发电平输出该第四正向信号至该合并子电路450，以及将该第三正向信号和该正向触发电平的第一合成信号输出至该合并子电路450。该第二信号输入电路442用于接收该第三负向信号和负向触发电平，根据该第三负向信号和该负向触发电平输出该第四负向信号至该合并子电路450，以及将该第三负向信号和该负向触发电平的第二合成信号输出至该合并子电路450。该正向触发电平和该负向触发电平为共模电平，该正向触发电平的绝对值和该负向触发电平的绝对值越大，该差分放大电路440的放大倍数越大。
也就是说，通过该正向触发电平和该负向触发电平，可以调整该差分放大电路440的放大倍数，从而提高该信号输出器42的抗共模干扰能力，进一步提升信号传输效果。除此之外，该差分放大电路440的构造简单，只需要一些晶体管就可以实现信号的放大，降低了信号传输架构中次边器件的复杂度，提升了信号传输的效果。
还请参见图4，本申请的一些实施例中，该合并子电路450包括第一开关电路451、第二开关电路452和合并单元453。
该第一开关电路451的输入端与该第一信号输入电路441的输出端连接，用于在该第一合成信号的控制下导通时，基于该第一合成信号和该第四正向信号，输出第一路待合并信号。该第二开关的输入端与该第二信号输入电路442的输出端连接，用于在该第二合成信号的控制下导通时，基于该第二合成信号和该第四负向信号，输出第二路待合并信号。该第一开关电路451和该第二开关电路452不同时导通或关断。
该第一开关电路451可以包括如图4所示的晶体管MC5，还可以包含如图4所示的电阻RC1，RC1相当于负载。该晶体管MC5的控制端接收该第一合成信号。电阻RC1的第一端与该晶体管MC2的第二端连接，电阻RC1的第二端与该晶体管MC5的第二端连接。晶体管MC5的第二端与晶体管MC4的第二端连接。晶体管MC4的第一端连接电源端(如图4所示的VCC)。晶体管MC4的控制端与晶体管MC1的控制端连接。
晶体管MC4与晶体管MC1构成电流镜，用于将晶体管MC1的电流复制到晶体管MC4。
该晶体管MC2输出的该第四正向信号经电阻RC1传输至晶体管MC5。晶体管MC5在该第四正向信号和该第一合成信号的控制下导通或关断。晶体管MC5导通时输出信号至晶体管MC4的第二端。
该第二开关电路452可以包括如图4所示的晶体管MC6，还可以包含如图4所示的电阻RC2，RC2相当于负载。该晶体管MC6的控制端接收该第二合成信号。电阻RC2的第一端与晶体管MC3的第二端连接，电阻RC2的第二端与该晶体管MC6的第二端连接。晶体管MC6的第二端与该晶体管MC4的第二端连接。
该晶体管MC3输出的该第四负向信号经电阻RC2传输至晶体管MC6。晶体管MC6在该第四负向信号和该第二合成信号的控制下导通或关断。晶体管MC6导通时输出信号至晶体管MC4的第二端。
需要说明的是，由于该第三正向信号和该第三负向信号是相互反相的周期性变化的信号，晶体管MC5导通时，晶体管MC6关闭，晶体管MC6关闭时，晶体管MC5导通。
晶体管MC5和晶体管MC6可以是如图4所示的NMOS管。晶体管MC5的控制端为栅极，第一端为漏极，第二端为源极。晶体管MC6的控制端为栅极，第一端为漏极，第二端为源极。晶体管MC4可以是如图4所示的PMOS管，晶体管MC4的控制端为栅极，第一端为源极，第二端为漏极。晶体管MC4和晶体管MC1构成电流镜。
该第一开关电路451和该第二开关电路452中还可以增设其他开关器件、电阻等，只要该第一开关电路451和该第二开关电路452能够实现如上所描述的功能即可。
该合并单元453的输入端与该第一开关电路451的输出端和该第二开关电路452的输出端连接，用于将该第一路待合并信号和该第二路待合并信号合并为一路初始信号。该合并单元453可以包括以上描述的晶体管MC4。该合并单元453还可以包含其他器件，只要能实现相对应的功能即可。
本实施例提供的该信号传输电路10中，该合并子电路450包括第一开关电路451、第二开关电路452和合并单元453。该第一开关电路451用于在该第一合成信号的控制下导通时，基于该第一合成信号和该第四正向信号，输出第一路待合并信号。该第二开关电路452用于在该第二合成信号的控制下导通时，基于该第二合成信号和该第四负向信号，输出第二路待合并信号。该合并单元453用于将该第一路待合并信号和该第二路待合并信号反相合并为一路初始信号。该合并单元453输出的该一路初始信号是与如上所描述的输入模块输入的脉冲信号反相的信号，通过该信号反相电路46的处理后可以输出与该脉冲信号几乎相同的信号，从而完成信号的传输。本实施例提供的该合并子电路450构造简单，只需要一些晶体管就可以实现信号的合并，降低了信号传输架构中次边器件的复杂度，提升了信号传输的效果。
还请参见图4，本申请的一些实施例中，该信号反相电路46包括反相单元460和控制单元461。
该反相单元460的输入端与该合并单元453的输出端连接，用于在该控制单元461的控制下将该一路初始信号反相后输出一路信号。
该反相单元460可以是反相器，或者是具有反相功能的其他器件。
该反相单元460可以包括如图4所示的晶体管MC7和晶体管MC8。晶体管MC7和晶体管MC8的控制端连接。晶体管MC7的第一端与电源端(如图4所示的VCC)连接，第二端和控制端连接。第二端还与晶体管MC4的第二端、晶体管MC5的第一端和晶体管MC6的第一端连接。晶体管MC4第二端形成的该一路初始信号传输至该晶体管MC7的第二端。晶体管MC8的第一端与电源端(如图4所示的VCC)连接，第二端输出该一路信号。
该控制单元461可以包括如图4所示的电流源AC3。该电流源AC3的第一端与该晶体管MC8的第二端连接，第二端连接第一电源端(如图4所示的VSS或低电压电源端)。
该晶体管MC7、该晶体管MC8和该电流源AC3构成一个模拟的反相器，将该一路初始信号反相后输出该一路信号(如图4所示的OUTP)。此时，该一路信号与如上所描述的该脉冲信号几乎相同，完成了信号传输。
该晶体管MC7和该晶体管MC8可以是如图4所示的PMOS管。该晶体管MC7的控制端为栅极，第一端为源极，第二端为漏极。该晶体管MC8的控制端为栅极，第一端为源极，第二端为漏极。该晶体管MC7和该晶体管MC8也可以是其他类型的MOS管，但满足能够构成电流镜的条件。
本实施例提供的该信号反相电路46包括反相单元460和控制单元461。该反相单元460用于在该控制单元461的控制下将该一路初始信号反相后输出一路信号。该反相单元460和该控制单元461构造简单，只需要一些晶体管和电流源就可以实现信号的反相，降低了信号传输架构中次边器件的复杂度，提升了信号传输的效果。
请参见图6，本申请的一些实施例中，该第二差分信号包括第二正向信号和第二负向信号。该信号传输电路10还包括钳位模块30。
该钳位模块30与该隔离模块20的输出端连接，用于根据该第二正向信号和该第二负向信号钳位该第二正向信号和该第二负向信号的共模电平。
需要将共模电平钳位的原因是：在该信号传输电路10次边的器件开关期间引起的瞬态干扰会导致主边的地与次边的地不同，不同的地会导致该隔离模块20输出的第二差分信号的共模电平(正的共模电平或负的共模电平)的绝对值升高。次边的器件可以理解为功率器件，共模电平的大小受功率器件的工作电压和开关时间影响，工作电压越大，开关时间越短，共模电平越大。该接收模块40内部的器件具备有限的耐压值，为防止共模电平过大损坏该接收模块40内部的器件，该钳位模块30在共模电平过大时，将共模电平钳位到该接收模块40内部的器件的耐压以下。
该钳位模块30中可以设置用于泄放共模电平的电路，该电路能够泄放正的共模电平和泄放负的共模电平。该电路的一端接收该第二差分信号，另一端可以连接具有较低电压的电源端。在泄放正的共模电平时，将正的共模电平泄放到具有较低电压的电源端，在泄放负的共模电平时，由电源端向隔离模块20的输出端进行充电。
需要说明的是，该钳位电路需要设置在该隔离模块20的输出端与该接收模块40的输入端之间，以在该第二差分信号进入该接收模块40之前，对该第二差分信号的共模电平进行钳位。防止该共模电平损坏该接收模块40中的器件。
本实施例提供的该信号传输电路10还包括钳位模块30，采用与隔离模块20输出端连接的钳位模块30，对隔离模块20传输过来的高频信号(即第二正向信号和第二负向信号)进行钳位。在钳位时，基于第二正向信号和第二负向信号一起调节共模电平，该第二正向信号携带的共模电平和第二负向信号携带的共模电平等时等量钳位，提高钳位效果。更重要的是，防止从主边传输过来的信号由于主次边不同地，引起的共模电平过大，从而对次边的器件造成损坏。除此之外，通过钳位共模电平，还降低了主边传输到次边的信号发生异常的风险。
一些实施例中，该钳位模块30用于，在该第二正向信号和该第二负向信号的共模电平的绝对值大于预设电平阈值时，调整该第二正向信号和该第二负向信号的共模电平。
该预设电平阈值可以小于或等于该接收模块40中器件的耐压值，该接收模块40中有多个器件时，该预设电平阈值小于或等于耐压性能最差的自检的耐压值。
无论该共模电平是正的共模电平还是负的共模电平，在该共模电平的绝对值大于该预设电平阈值时，都调整该第二正向信号和该第二负向信号的共模电平小于或等于该预设电平阈值。如此，可以保障该接收模块40中的器件不会因为该共模电平而受损，也可以保障该接收模块40接收的信号和输出的信号都无异常。
一些实施例中，该钳位模块30用于，根据该第二正向信号和该第二负向信号调整共模电平钳位量，并根据该共模电平钳位量调整该第二正向信号和该第二负向信号的共模电平。
也就是说，钳位量是根据该第二正向信号和该第二负向信号确定的。当该第二正向信号和该第二负向信号携带的共模电平的绝对值越大时，钳位量可以越大。当该第二正向信号和该第二负向信号携带的共模电平的绝对值越小时，钳位量可以越小。
根据该钳位量调整该第二正向信号和该第二负向信号的共模电平，指的是根据该钳位量降低该共模电平的绝对值。该钳位量可以理解为电压值，对于正的共模电平，该电压值为负。对于负的共模电平，该电压值为正。
请参见图7，本申请的一个实施例中，该钳位模块30包括触发电路31和泄放电路32。
该触发电路31的第一输入端接收第二正向信号，该触发电路31的第二输入端接收第二负向信号，该触发电路31用于输出触发信号。
该泄放电路32的控制端连接该触发电路31的输出端，该泄放电路32的第一端接收该第二正向信号，该泄放电路32的第二端接收第二负向信号，该泄放电路32的第三端连接第一电源端。该第一电源端可以是地端(图7所示的VSS)，也可以是低电压的电源端，低电压指的是在共模电平为正电压时，小于共模电平电压。
该第二正向信号可以从该泄放电路32的第一端至第三端形成的泄放路径泄放，也可以从该泄放电路32的第三端至第一端形成的泄放路径泄放。该泄放电路32根据该触发信号控制该泄放电路32的第一端和第三端之间电荷泄放量。
该第二负向信号可以从该泄放电路32的第二端至第三端形成的泄放路径泄放，也可以从该泄放电路32的第三端至第二端形成的泄放路径泄放。该泄放电路32根据该触发信号控制该泄放电路32的第二端和第三端之间电荷泄放量。
具体的，该第二正向信号和该第二负向信号都携带正的共模电平时，该第二正向信号从该泄放电路32的第一端至第三端形成的泄放路径泄放，该第二负向信号从该泄放电路32的第二端至第三端形成的泄放路径泄放。
具体的，该第二正向信号和该第二负向信号都携带负的共模电平时，该第二正向信号从该泄放电路32的第三端至第一端形成的泄放路径泄放，该第二负向信号从该泄放电路32的第三端至第二端形成的泄放路径泄放。
该触发信号是在该第二正向信号和该第二负向信号输入时产生，与该第二正向信号和该第二负向信号携带的共模电平的绝对值正相关。该触发信号用于触发该泄放电路32泄放共模电平。该共模电平的绝对值越高，该触发信号的电平越高，该泄放电路32的第一端和第三端之间的电荷泄放量越大，该泄放电路32的第二端和第三端之间的电荷泄放量越大。该共模电平的绝对值越小，该触发信号的电平越低，该泄放电路32的第一端和第三端之间的电荷泄放量越小，该泄放电路32的第二端和第三端之间的电荷泄放量越小。
在一些实施例中，可以设置第一端到第三端之间的器件和第二端到第三端之间的器件结构相同。
如此，针对正的共模电平，由于第一端到第三端之间的器件和第二端到第三端之间的器件结构相同，第一端至第三端的泄放路径对应的电荷泄放量，与第二端至第三端的泄放路径对应的电荷泄放量相同。且由于同时受触发信号控制，第一端至第三端的泄放路径和第二端至第三端的泄放路径同时形成。如此，能够对第二正向信号携带的正的共模电平和第二负向信号携带的正的共模电平等时等量钳位。
针对负的共模电平，由于第一端到第三端之间的器件和第二端到第三端之间的器件结构相同，第三端至第一端的泄放路径对应的电荷泄放量，与第三端至第二端的泄放路径对应的电荷泄放量相同。且由于同时受触发信号控制，第三端至第一端的泄放路径和第三端至第二端的泄放路径同时形成。如此，能够对该第二正向信号携带的负的共模电平和第二负向信号携带的负的共模电平等时等量钳位。
本实施例提供的该钳位模块30，通过该触发电路31接收第二正向信号和第二负向信号，并输出触发信号至该泄放电路32。该泄放电路32根据该触发信号控制电荷泄放量，基于电荷泄放量对该第二正向信号和该第二负向信号的共模电平进行泄放。通过该泄放电路32对该共模电平进行泄放，有效抑制了共模电平的绝对值过大的问题，防止该接收电路中的器件受损，并且由于使用同一触发信号控制对第二正向信号和该第二负向信号的共模电平进行泄放，该第二正向信号携带的共模电平和第二负向信号携带的共模电平等时等量钳位。
一些实施例中，当形成正的共模电平，也就是在该第二正向信号和该第二负向信号的共模电平大于该第一电源端的电压时，该泄放电路32形成第一端到第三端的泄放路径。对应的，共模电平从第一端流至第三端。由于第三端连接第一电源端，第一电源端是低电压端(例如地端)，因此可以将共模电平流到低电压端(例如地端)，从而泄放该共模电平，达到钳位该共模电平的效果。
当形成正的共模电平时，该泄放电路32还形成第二端到第三端的泄放路径。对应的，共模电平从第二端流至第三端。由于第三端连接第一电源端，第一电源端是低电压端(例如地端)，因此可以将共模电平流到低电压端(例如地端)，从而泄放该共模电平，达到钳位该共模电平的效果。
一些实施例中，当形成负的共模电平，也就是在该第二正向信号和该第二负向信号的共模电平小于该第一电源端的电压时，该泄放电路32形成第三端到第一端的泄放路径。对应的，共模电平从连接第一电源端的第三端流至第一端，也就是从低电压端(例如地端)流至隔离模块20的输出端，从而抑制负的共模电平。共模电平被泄放后流入该第二正向信号，达到钳位该共模电平的效果。
当形成负的共模电平时，该泄放电路32还形成第三端到第二端的泄放路径，对应的，共模电平从连接第一电源端的第三端流至第二端，也就是从低电压端(例如地端)流至隔离模块20的输出端，从而抑制负的共模电平。共模电平被泄放后流入该第二负向信号，达到钳位该共模电平的效果。
请参见图8，本申请的一个实施例中，该泄放电路32包括第一晶体管MA1和第二晶体管MA2。该第一晶体管MA1和该第二晶体管MA2可以是如图8所示的金属-氧化物-半导体(Metal-Oxide-Semiconducto，简称MOS)管。
该第一晶体管MA1的控制端连接该第二晶体管MA2的控制端。如图8所示的，该第一晶体管MA1的栅极与该第二晶体管MA2的栅极连接，栅极为控制端。图中所示的第一晶体管MA1和第二晶体管MA2均为NMOS管，实际使用中也可以替换为PMOS管，只要能够实现共模电平的泄放即可。但需强调的是，第一晶体管MA1和该第二晶体管MA2的尺寸相同，如此保证该第一晶体管MA1和该第二晶体管MA2的电荷泄放量需相同。
该第一晶体管MA1的控制端和该第二晶体管MA2的控制端均接收该触发信号。如图8所示的，该第一晶体管MA1的栅极与该第二晶体管MA2的栅极同时接收到该触发信号，该第一晶体管MA1和该第二晶体管MA2同时被触发导通，第二正向信号和第二负向信号携带的共模电平同时被泄放。
该第一晶体管MA1的第一端为该泄放电路32的第一端，即该第一晶体管MA1的第一端接收该第二正向信号(INPUT+)。该第一晶体管MA1的第二端连接该第一电源端，该第一电源端如图8所示的VSS。在形成正的共模电平时，如图8所示，该第一晶体管MA1的第一端为漏极，该第一晶体管MA1的第二端为源极。正的共模电平形成时，该第一晶体管MA1导通，正的共模电平流入该第一电源端，达到钳位共模电平的效果。在形成负的共模电平时，该第一晶体管MA1的第一端为源极，该第一晶体管MA1的第二端为漏极。负的共模电平形成时，该第一晶体管MA1导通，负的共模电平从第一电源端流入隔离模块20的输出端，达到钳位共模电平的效果。
该第二晶体管MA2的第一端为该泄放电路32的第二端，即该第二晶体管MA2的第二端接收该第二负向信号(INPUT-)。该第二晶体管MA2的第二端均连接该第一电源端，该第一电源端如图8所示的VSS。在形成正的共模电平时，如图8所示，该第二晶体管MA2的第一端为漏极，该第二晶体管MA2的第二端为源极。正的共模电平形成时，该第二晶体管MA2导通，正的共模电平流入该第一电源端，达到钳位共模电平的效果。在形成负的共模电平时，该第一晶体管MA1的第一端为源极，该第一晶体管MA1的第二端为漏极。负的共模电平形成时，该第二晶体管MA2导通，负的共模电平从第一电源端流入该第二负向信号，达到钳位共模电平的效果。
需要强调的是，该第一晶体管MA1和该第二晶体管MA2的导通条件相同，该第一晶体管MA1和该第二晶体管MA2的导通时间相同，且电荷泄放量也相同。
本实施例提供的该泄放电路32，通过设置可以切换源极和漏极的晶体管，使共模电平能够被泄放。具体的，该触发信号控制该第一晶体管MA1和该第二晶体管MA2同时导通，第二正向信号和第二负向信号携带的共模电平同时被泄放。针对正的共模电平和负的共模电平，都能达到钳位共模电平的效果。
还请参见图8，一些实施例中，该第一晶体管MA1和该第二晶体管MA2基于同一衬底形成。这样做的目的是为了支持该第一晶体管MA1或该第二晶体管MA2可以切换源极和漏极。第一晶体管MA1可以将当前的源极切换为漏极，将当前的漏极切换为源极。同理，第二晶体管MA2可以将当前的源极切换为漏极，将当前的漏极切换为源极。
一些实施例中，请参见图8的示例，该触发电路31包括第一分压电路310和第二分压电路320。
该第一分压电路310的第一端接收该第二正向信号，该第一分压电路310的第二端连接该第二分压电路320的第二端。该第一分压电路310的第二端用于输出该触发信号。该第一分压电路310的第三端连接该第一电源端。
该第二分压电路320的第一端接收该第二负向信号，该第二分压电路320的第三端连接该第一电源端。
该第一分压电路310用于对该第二正向信号进行分压后，该第二分压电路320用于对该第二负向信号进行分压。该触发信号形成于该第一分压电路310分压该第二正向信号和该第二分压电路320分压该第二负向信号。该第二正向信号和该第二负向信号同时输入，该触发信号在该第二正向信号和该第二负向信号输入后被分压时即形成。
该第一分压电路310和该第二分压电路320的分压能力相同。该第一分压电路310和该第二分压电路320中可以设置分压电阻或其他分压器件，所设置的分压电阻或其他分压器件应该满足使改第一分压电路310和该第二分压电路320的分压能力相同。
一些实施例中，还请参见图8，该第一分压电路310包括第一电阻RA1和第二电阻RA2。该第二分压电路320包括第三电阻RA3和第四电阻RA4。
该第一电阻RA1的第一端为该第一分压电路310的第一端，该第一电阻RA1的第二端连接该第二电阻RA2的第一端。该第一电阻RA1的第二端为该第一分压电路310的第二端。该第二电阻RA2的第二端为该第一分压电路310的第三端。如图8所示的，该第一电阻RA1的第一端接收第二正向信号，该第二电阻RA2的第二端连接该第一电源端。
该第三电阻RA3的第一端为该第二分压电路320的第一端，该第三电阻RA3的第二端连接该第四电阻RA4的第一端，该第三电阻RA3的第二端为该第二分压电路320的第二端，该第四电阻RA4的第二端为该第二分压电路320的第三端。如图8所示的，该第三电阻RA3的第一端接收第二负向信号，该第四电阻RA4的第二端连接该第一电源端。
该第一电阻RA1和该第二电阻RA2的阻值可以不同。该第三电阻RA3和第四电阻RA4的阻值可以不同。
在该第一晶体管MA1和该第二晶体管MA2相同时，该第一电阻RA1和该第三电阻RA3应该相同，该第二电阻RA2和该第四电阻RA4应该相同。
当正的共模电平产生时，该第一电阻RA1和该第二电阻RA2分压，该第三电阻RA3和该第四电阻RA4分压，使得该第一晶体管MA1的栅极电压和该第二晶体管MA2的栅极电压均上升，此时共模电平对应的共模电流流到第一电源端(例如地端)，将共模电平钳位。
当负的共模电平产生时，该第一晶体管MA1原始的源极切换为漏极，原始的漏极切换为源极，此时共模电平对应的共模电流从第一电源端(例如地端)流到第二正向信号。同样的，该第二晶体管MA2原始的源极切换为漏极，原始的漏极切换为源极，此时共模电平对应的共模电流从第一电源端(例如地端)流到第二负向信号。
一些可选的实施例中，该第一分压电路310还可以再增设电阻，同样的，该第二分压电路320还可以再增设电阻。若该第一分压电路310增设电阻，该第二分压电路320也需增设电阻，且该第一分压电路310和该第二分压电路320所增设电阻的阻值应该相同，除此之外，所增设电阻的连接位置应该相应。
所增设电阻的连接位置相应，例如，在第一分压电路310中增设电阻，所增设电阻的第一端连接第一电阻RA1的第一端，所增设电阻的第二端接收第二正向信号。则，在第二分压电路320中增设相同阻值的电阻，所增设电阻的第一端连接第三电阻RA3的第一端，所增设电阻的第二端接收第二负向信号。
本实施例提供的该分压电路包括该第一分压电路310和该第二分压电路320。该第一分压电路310包括第一电阻RA1和第二电阻RA2，该第二分压电路320包括第三电路和第四电阻RA4第四电阻RA4。当正的共模电平产生时，共模电平对应的共模电流通过该第一晶体管MA1和该第二晶体管MA2流到该第一电源端，达到共模电平钳位的效果。当负的共模电平产生时，通过该第一晶体管MA1和该第二晶体管MA2流到隔离模块20的输出端，达到共模电平钳位的效果。
一些实施例中，请参见图9，该信号接收电路41包括前级差分放大电路43。该前级差分放大电路43的输入端与该隔离模块20的输出端连接，用于对该第二差分信号进行放大处理后输出第三差分信号。
该信号接收电路41对该第一差分信号放大的原因是，由于隔离模块20和相关寄生参数(如隔离电容寄生参数、功率器件寄生参数等)的影响，隔离模块20输入端的第一差分信号传输到输出端后，其所输出的第二差分信号的幅度被大幅度衰减，可能无法正常进行下一步处理。因此，衰减的第二差分信号可以先进行放大，使得后续的器件能够识别。
该前级差分放大电路43对差分信号的电压不同进行比较，从而减少共模电平对信号的干扰。
该前级差分放大电路43可以包括晶体管，利用晶体管的放大功能对该第二差分信号进行放大。
本实施例提供的该信号接收电路41包括前级差分放大电路43，该前级差分放大电路43用于对该第二差分信号进行差分放大，即对该隔离模块20传输过来的差分信号进行放大，使得差分信号能够被后续电路识别，进一步提升信号的传输效果。
一些实施例中，请参见图10和图14，该前级差分放大电路43包括图10所示的第一放大电路411和图14所示的第二放大电路412。该第一放大电路411输出第三正向信号，第二放大电路412输出第三负向信号。需要说明的是，图10和图14所示的IN+代表的是经过共模电平钳位后的第二正向信号，IN-代表的是经过共模电平钳位后的第二负向信号。
具体的，该第一放大电路411的第一输入端接收该第二负向信号(如图10所示的IN-)，该第一放大电路411的第二输入端接收该第二正向信号(如图10所示的IN+)。该第一放大电路411用于根据该第二负向信号和该第二正向信号的差值生成第三正向信号(如图10所示的OUTA+)。
具体的，该第二放大电路412的第一输入端接收该第二正向信号(如图14所示的IN+)，该第二放大电路412的第二输入端接收该第二负向信号(如图14所示的IN-)。该第二放大电路412用于根据该第二正向信号和该第二负向信号的差值生成第三负向信号(如图14所示的OUTA-)。
示例的，该第一放大电路411和该第二放大电路412的结构相同。
以下详细针对该第一放大电路411进行描述。
该第一放大电路411可以设置一级放大子电路或多级放大子电路，同样的，该第二放大电路412可以设置一级放大子电路或多级放大子电路。但是该第一放大电路411和该第二放大电路412的放大程度需相同。
一些实施例中，该第一放大电路411包括第一级子电路413。该第一级子电路413的第一输入端接收该第二正向信号，该第一级子电路413的第二输入端接收该第二负向信号。该第一级子电路413根据该第二正向信号和该第二负向信号生成第三正向信号，具体的，根据该第二正向信号和该第二负向信号的差值生成该第三正向信号。
一些实施例中，该第一放大电路411还可以包括更多级的子电路，具体可以根据实际的信号放大需求设置。
以下详细针对该第二放大电路412进行描述。
该第二放大电路412可以设置一级放大子电路或多级放大子电路。但是该第一放大电路411和该第二放大电路412的放大程度需相同。
一些实施例中，该第二放大电路412包括第一级子电路413。第一级子电路413的第一输入端接收该第二正向信号，该第一级子电路413的第二输入端接收该第二负向信号。该第一级子电路413根据该第二正向信号和该第二负向信号生成第三负向信号，具体的，根据该第二正向信号和该第二负向信号的电压差生成第三负向信号。
一些实施例中，该第一放大电路411还可以包括更多级的子电路，具体可以根据实际的信号放大需求设置。
以上，本实施例提供的该前级差分放大电路43包括第一放大电路411和第二放大电路412。第一放大电路411用于根据第二负向信号和第二正向信号的电压差生成第三正向信号。第二放大电路412用于根据第二正向信号和第二负向信号的电压差生成第三负向信号。该前级差分放大电路43输出的第三差分信号包括第三正向信号和第三负向信号。通过该前级差分放大电路43对该第二差分信号进行放大，可以有效提升信号强度，使得差分信号可以被后续电路识别。
以下针对该第一放大电路411包含不同数量的子电路的情况进行详细说明。
第一种情况：该第一放大电路411仅包含第一级子电路413。
请参见图10，此时，该第一级子电路413可以包括第三上拉电路423和第三下拉电路424。
该第三上拉电路423的第一端连接电源端(如图10所示的VCC)，该第三上拉电路423的第二端连接该第三下拉电路424的第一端。
该第三下拉电路424的控制端接收该第二负向信号，该第三下拉电路424的第二端接收该第二正向信号。该第三下拉电路424的第一端输出该第三正向信号。
该第三下拉电路424在该第二负向信号的控制下调整该第二正向信号对该第三下拉电路424的第一端的向下驱动能力。
该第三上拉电路423用于对该第三下拉电路424输出的电压差信号进行放大，该第三下拉电路424输出的电压差信号是第二负向信号减去第二正向信号的电压差的放大后的信号。
如图10所示，该第三下拉电路424包括第一电容CB1和第三晶体管MB1。
该第一电容CB1的第一端接收第二负向信号，第二端连接该第三晶体管MB1的控制端。第一电容CB1的第一端为该第三下拉电路424的第一端。
该第三晶体管MB1的第一端为该第三上拉电路423的第二端连接。该第三晶体管MB1的第二端接收第二正向信号。该第三晶体管MB1的控制端与该第一电容CB1的第二端连接。该第三晶体管MB1可以是如图10所示的NMOS管，该第三晶体管MB1的栅极(控制端)与该第一电容CB1的第二端连接，源极接收第二正向信号，漏极与该第三上拉电路423的第二端连接。
该第三晶体管MB1导通后输出第二负向信号和第二正向信号的差值。
还请参见图10，该第三上拉电路423包括晶体管(如图10所示的MB2)和电容(如图10所示的CB2)。该电容的第一端连接电源端，第二端连接该晶体管的控制端。该晶体管的第一端连接电源端和该电容的第一端，该晶体管的第二端连接该第三晶体管MB1的第一端。
该晶体管可以是如图10所示的PMOS管，该晶体管的第一端为源极，该晶体管的第二端为漏极。
该晶体管导通后，该第三上拉电路423输出稳定的电压信号，所输出的电压信号用于对该第三晶体管MB1输出的电压差信号进行放大。
该第三上拉电路423还可以设置如图10所示的电阻RB1，此处的RB1充当负载作用，效果是进一步提升电压差信号的放大效果。
请参见图11，一些实施例中，该第三下拉电路424还包括第二电容CB3和第四晶体管MB3。
第二电容CB3的第一端接收第二负向信号，第二端连接第四晶体管MB3的控制端。第四晶体管MB3的第一端与第三晶体管MB1的第一端连接，第二端接收第二正向信号。
第四晶体管MB3导通后，第二负向信号和第二正向信号的电压差信号经过第四晶体管MB3放大后输入到第三晶体管MB1的第一端。第三晶体管MB1导通后，输出第二负向信号和第四晶体管MB3输出的电压差信号之间的电压差信号，第三晶体管MB1进一步放大电压差信号。也就是说，本实施例提供的该第二电容CB3和该第四晶体管MB3可以进一步提升电压差信号的放大效果。
该第三晶体管MB1和该第四晶体管MB3可以都是NMOS管。该第四晶体管MB3的控制端是栅极，第一端是漏极，第二端是源极。
请参见图12，一些实施例中，该第一级子电路413还包括预置电压电路419。
该预置电压电路419的第一端接收该第二负向信号，该预置电压电路419的第二端连接该第三下拉电路424的控制端。该第三下拉电路424的控制端即该第四晶体管MB3的控制端。
该预置电压电路419用于根据第二负向信号在该第三下拉电路424的控制端产生预置电压。该预置电压电路419输出的该预置电压输入到该第四晶体管MB3的栅极，用以进一步提升电压差信号的放大效果。
该预置电压电路419可以包括第五晶体管MB4和第六晶体管MB5(如图12所示的晶体管MB5)。第五晶体管MB4的控制端连接第二电容CB3的另一端，第一端接收第二负向信号，第二端连接第六晶体管MB5的第一端。第六晶体管MB5的控制端连接第一电容CB1的另一端，第二端连接第四晶体管MB3的控制端。
第五晶体管MB4和第六晶体管MB5可以都是NMOS管。第五晶体管MB4的栅极与该第二电容CB3的第二端连接，源极接收第二负向信号，漏极连接第六晶体管MB5的源极。第六晶体管MB5的栅极与该第一电容CB1的第二端连接，漏极与该第四晶体管MB3的栅极连接。
一些可选的实施例中，预置电压电路419还可以包括如图12所示的电阻RB2和电流源A1，图中的电流源A1为电阻RB2提供所需的电能。电流源A1从电源端VCC取电。电阻RB2的第一端连接电流源A1，第二端连接该第四晶体管MB3的控制端。此时，该第四晶体管MB3输入的信号包含该第一电容CB1的第二端输出的信号和电阻RB2的第二端输出的信号。
本实施例提供的该预置电压电路419的设计可以进一步提升电压差信号的放大效果。
第二种情况：请参见图13，该第一放大电路411包含第一级子电路413和第二级子电路414。该第一放大电路411的具体结构可以是以上所示的结构中的任一种结构或任一种结构的变形，本实施例不做限定。此时，该第一放大电路411用于输出中间信号，第二级子电路414用于对中间信号进行放大后输出第三正向信号。
请参见图13，该第二级子电路414的输入端连接该第一级子电路413的输出端，该第二级子电路414用于对该第一级子电路413输出的信号进行放大后输出该第三正向信号。
该第二级子电路414包括第二上拉电路421和第二下拉电路422。该第二上拉电路421的第一端连接电源端(如图13所示的VSS)，该第二上拉电路421的第二端连接该第三下拉电路424的第一端。该第二下拉电路422的第二端连接第二电源端(如图13所示的A3)。
该第二下拉电路422的控制端接收该第一级子电路413输出的信号。该第二下拉电路422的第一端输出第三正向信号。
该第二下拉电路422在该第二负向信号的控制下调整该第二电源端对该第二下拉电路422的第二端的向下驱动能力，该第二下拉电路422的第一端输出该第三正向信号。
一些实施例中，该第二下拉电路422包括第七晶体管MB6。该第二上拉电路421包括第八晶体管MB7和第三电容CB4。第七晶体管MB6的控制端为该第二下拉电路422的控制端，接收该第一级子电路413输出的信号，第七晶体管MB6的第一端连接第二电源端，第二端连接第八晶体管MB7的第一端。第八晶体管MB7的控制端与第三电容CB4的第一端连接，第二端与电源端连接。第三电容CB4的第二端与电源端连接。
该第七晶体管MB6可以是如图13所示的NMOS管，栅极为控制端，源极为第二端，漏极为第二端。该第八晶体管MB7可以是如图13所示的PMOS管，栅极为控制端，漏极为第一端，源极为第二端。
还可以设置如图13所示的电阻RB3，以进一步提升压差信号的放大效果。
本实施例提供的该第一放大电路411包含第一级子电路413和第二级子电路414时，通过该第一级子电路413对该第二正向信号和该第二负向信号之间的电压差信号进行一次放大，再通过该第二级子电路414对该第一级子电路413放大输出的电压差信号再进行放大，进一步提升电压差信号的放大效果。
以下详细针对该第二放大电路412包含不同数量的子电路的情况进行详细说明。
第一种情况：请参见图14，该第二放大电路412仅包含第三级子电路415。
请参见图14，此时，该第三级子电路415可以包括第四上拉电路425和第四下拉电路426。
该第四上拉电路425的第一端连接电源端(如图14所示的VCC)，该第四上拉电路425的第二端连接该第四下拉电路426的第一端。
该第四下拉电路426的控制端接收该第二正向信号，该第四下拉电路426的第二端接收该第二负向信号。该第四下拉电路426的第一端输出该第三负向信号。
该第四下拉电路426在该第二负向信号的控制下调整该第二正向信号对该第四下拉电路426的第一端的向下驱动能力。
该第四上拉电路425用于对该第四下拉电路426输出的电压差信号进行放大，该第四下拉电路426输出的电压差信号是第二正向信号减去第二负向信号的电压差信号。
如图14所示，该第四下拉电路426包括第四电容CB5和第九晶体管MB8。
该第四电容CB5的第一端接收第二正向信号，第二端连接该第九晶体管MB8的控制端。第四电容CB5的第一端为该第四下拉电路426的第一端。
该第九晶体管MB8的第一端与该第四上拉电路425的第二端连接。该第九晶体管MB8的第二端接收第二正向信号。该第九晶体管MB8的控制端与该第四电容CB5的第二端连接。该第九晶体管MB8可以是如图14所示的NMOS管，该第九晶体管MB8的栅极(控制端)与该第四电容CB5的第二端连接，源极接收第二正向信号，漏极与该第四上拉电路425的第二端连接。
该第九晶体管MB8导通后输出第二负向信号和第二正向信号的电压差。
还请参见图14，该第四上拉电路425包括晶体管MB9和电容CB6。该电容CB6的第一端连接电源端，第二端连接该晶体管MB9的控制端。该晶体管MB9的第一端连接电源端和该电容CB6的第一端，该晶体管MB9的第二端连接该第三晶体管MB1的第一端。
该晶体管MB9可以是如图14所示的PMOS管，该晶体管MB9的第一端为源极，该晶体管MB9的第二端为漏极。
该晶体管MB9导通后，该第四上拉电路425输出稳定的电压信号，所输出的电压信号用于对该第九晶体管MB8输出的电压差信号进行放大。
该第四上拉电路425还可以设置如图14所示的电阻RB4，此处的RB4充当负载作用，效果是进一步提升电压差信号的放大效果。
请参见图15，一些实施例中，该第四下拉电路426还包括第五电容CB7和第十晶体管MB10。
第五电容CB7的第一端接收第二负向信号，第二端连接第十晶体管MB10的控制端。第十晶体管MB10的第一端与第九晶体管MB8的第一端连接，第二端接收第二正向信号。
第十晶体管MB10导通后，第二负向信号和第二正向信号的电压差信号经过第十晶体管MB10放大后输入到第九晶体管MB8的第一端。第九晶体管MB8导通后，输出第二负向信号和第十晶体管MB10输出的电压差信号之间的电压差信号，第九晶体管MB8进一步放大电压差信号。也就是说，本实施例提供的该第五电容CB7和该第十晶体管MB10可以进一步提升电压差信号的放大效果。
该第九晶体管MB8和该第十晶体管MB10可以都是NMOS管。该第十晶体管MB10的控制端是栅极，第一端是漏极，第二端是源极。
请参见图16，一些实施例中，该第三级子电路415还包括另一预置电压电路430。
该另一预置电压电路430的第一端接收该第二正向信号，该另一预置电压电路430的第二端连接该第三下拉电路424的控制端。该第三下拉电路424的控制端即该第十晶体管MB10的控制端。
该另一预置电压电路430用于根据第二正向信号在该第三下拉电路424的控制端产生预置电压。该另一预置电压电路430输出的该预置电压输入到该第十晶体管MB10的栅极，用以进一步提升电压差信号的放大效果。
该另一预置电压电路430可以包括第十一晶体管MB11和第十二晶体管MB12。第十一晶体管MB11的控制端连接第五电容CB7的另一端，第一端接收第二正向信号，第二端连接第十一晶体管MB12的第一端。第十一晶体管MB12的控制端连接第四电容CB5的另一端，第二端连接第十晶体管MB10的控制端。
第十一晶体管MB11和第十一晶体管MB12可以都是NMOS管。第十一晶体管MB11的栅极与该第五电容CB7的第二端连接，源极接收第二负向信号，漏极连接第十一晶体管MB12的源极。第十一晶体管MB12的栅极与该第四电容CB5的第二端连接，漏极与该第十晶体管MB10的栅极连接。
一些可选的实施例中，还可以设置如图16所示的电阻RB5和电流源A2，图中的电流源A2为电阻RB5所在的支路提供所需的电能。电流源A2从电源端VCC取电。电阻RB5的第一端连接电流源A2，第二端连接该第十晶体管MB10的控制端。此时，该第十晶体管MB10输入的信号包含该第一电容CB1的第二端输出的信号和电阻RB5的第二端输出的信号。电阻RB5的设置用于放大电压差信号的放大倍数。
本实施例提供的该另一预置电压电路430的设计可以进一步提升电压差信号的放大效果。
第二种情况：该第二放大电路412包含第三级子电路415和第四级子电路416。该第二放大电路412的具体结构可以是以上所示的结构中的任一种结构或任一种结构的变形，本实施例不做限定。此时，该第二放大电路412输出的信号不是第三负向信号，第四级子电路416输出第三负向信号。
请参见图17，该第四级子电路416的输入端连接该第三级子电路415的输出端，该第四级子电路416用于对该第三级子电路415输出的信号进行放大后输出该第三正向信号。
该第四级子电路416包括第五上拉电路427和第五下拉电路428。该第五上拉电路427的第一端连接电源端(如图17所示的VSS)，该第五上拉电路427的第二端连接该第五下拉电路428的第一端。该第五下拉电路428的第二端连接第二电源端(如图17所示的A3)。该第二电源端用于使电压差信号更加差分。
该第五下拉电路428的控制端接收该第三级子电路415输出的信号。该第五下拉电路428的第一端输出第三正向信号。
该第五下拉电路428在该第二正向信号的控制下调整该第二电源端对该第五下拉电路428的第二端的向下驱动能力，该第五下拉电路428的第一端输出该第三负向信号。
一些实施例中，该第五下拉电路428包括第十三晶体管MB13。该第五上拉电路427包括第十四晶体管MB14和第六电容CB8。第十三晶体管MB13的控制端为该第五下拉电路428的控制端，接收该第三级子电路415输出的信号，第十三晶体管MB13的第一端连接第二电源端，第二端连接第十四晶体管MB14的第一端。第十四晶体管MB14的控制端与第六电容CB8的第一端连接，第二端与电源端连接。第六电容CB8的第二端与电源端连接。
该第十三晶体管MB13可以是如图17所示的NMOS管，栅极为控制端，源极为第二端，漏极为第二端。该第十四晶体管MB14可以是如图17所示的PMOS管，栅极为控制端，漏极为第一端，源极为第二端。
还可以设置如图17所示的电阻RB6，以进一步提升压差信号的放大效果。
本实施例提供的该第二放大电路412包含第三级子电路415和第四级子电路416时，通过该第三级子电路415对该第二正向信号和该第二负向信号之间的电压差信号进行一次放大，再通过该第四级子电路416对该第三级子电路415放大输出的电压差信号再进行放大，进一步提升电压差信号的放大效果。
请参见图18，本申请的一个实施例提供的信号传输电路10还包括输入模块50。
该输入模块50的输入端接收输入信号，该输入模块50的输出端连接该隔离模块20，并对该输入信号进行调制后输出该第一差分信号。
其中，该输入信号可以是如图19所示的方波脉冲信号。该输入模块50可以包含如图18所示的振荡器51、逻辑电路52。
若该输入信号是如图19所示的方波脉冲信号，该振荡器51用于输出如图20所示的连续且高频的振荡信号。该振荡器51的类型有环形振荡器51等形式。该振荡器51的信号频率可以根据内部的电阻和电容等进行调节。该输入信号的信号频率低于该振荡器51信号的信号频率，且脉宽至少是振荡器51信号的2个周期以上，才能保证信号的传输。
该逻辑电路52包含逻辑与门电路和逻辑非门电路。该输入信号和该振荡信号进入该逻辑电路52后，通过逻辑与门电路输出一路信号，通过逻辑非门电路输出一路信号，两路信号互为差分，是脉宽接近的差分高频信号。该逻辑电路52输出如图21所示的差分信号。图21所示的差分信号即前述的该第一差分信号。该第一差分信号输入至该隔离模块20。
一些可选的实施例中，该输入模块50还可以包含如图18所示的驱动电路53，此时该驱动电路53输出该第一差分信号。该驱动电路53输出的第一差分信号与该逻辑电路52输出的信号的波形近似一致，主要区别在于驱动能力的增强。该驱动电路53用于进一步提升逻辑电路52输出的差分信号的强度。
需要说明的是，该隔离模块20中设计高压隔离电容时，高压隔离电容能够实现极高的耐压，因此可以防止次边的瞬态干扰传输至主边，可以保护该输入模块50中电路不受损。除此之外，该输入模块50将输入信号处理为差分信号，采用差分信号的形式发送至给隔离模块20，可以降低共模电平的干扰。
请参见图22和图23，本申请的一些实施例中，该信号传输电路还包括如图22所示的滤波电路44。
该滤波电路44用于对该隔离模块20输出的第二差分信号进行滤波处理。
该滤波电路44可以是高通滤波器。如图23所示，该滤波电路44包含电阻R1和电阻R2。电阻R1的第一端接收第二正向信号，第二端接地。电阻R2的第一端接收第二负向信号，第二端接地。电阻R1、电阻R2与该隔离模块20中的隔离电容形成高通滤波器，可以极大程度衰减低频信号的干扰。
需要说明的是，与该接收模块40输入端连接的滤波电路44必须两个信号通道匹配，防止信号的失效。
该滤波电路44可以设置在该隔离模块20和该钳位模块30之间，也可以根据实际需要设置在其他位置，本实施例不做限定。
本实施例提供的该滤波电路44还可以是其他滤波器，只要能衰减低频信号的干扰即可。
请参见图24，一些实施例中，该接收模块40还包括延时电路47。该延时电路47的输入端与该信号输出器42的输出端连接。
该延时电路47用于滤除该信号输出器42输出的一路信号中的异常信号后输出一路信号。该延时电路47可以是晶体管延时电路，也可以是其他类型的延时电路，具体可以根据实际需要选择，本实施例不做限定。
本实施例提供的该延时电路47，可以提高该信号传输电路输出信号的正确率，也可以在一定程度上提高该信号传输电路的抗干扰能力。
请参见图25，本申请的一些实施例还提供一种信号传输系统60。
该信号传输系统60包括如上任一项实施例提供的信号传输电路10，还包括控制器61、驱动模块62和功率器件63。
该控制器61的输出端与该信号传输电路10的输入端连接。该控制器61可以是单片机(Microcontroller Unit，简称MCU)。该控制器61输出信号为方波脉冲信号。
该驱动模块62的输入端与该信号传输电路10的输出端连接，接收该信号传输电路10输出的单路信号。请参考以上对于该接收模块40输出的单路信号的描述，则该信号传输电路10输出的单路信号是方波脉冲信号。该驱动模块62用于对该信号传输电路10输出的信号进行升压处理后输出至该功率器件63，以驱动该功率器件63运行。即，该驱动模块62用于进一步驱动该方波脉冲信号，以满足该功率器件63的使用要求。
该功率器件63例如碳化硅功率元器件、绝缘栅双极晶体管(Insulate-Gate Bipolar Transistor，简称IGBT)。
本实施例提供的信号传输系统60，该功率器件63的开关瞬间产生的瞬态干扰被该信号传输电路10钳位，因此不会损坏该信号传输电路10。相比于现有的信号传输系统60，安全性更高，实用性更强。
请参见图26，本申请的一些实施例还提供一种车辆的电控系统70，该电控系统70包括如上任一项实施例提供的该信号传输系统60，还可以包括负载71。负载71例如电机。
如图26所示，该功率器件63可以是如图26所示的IGBT，IGBT连接车辆上的电机。
本申请的一些实施例还提供一种车辆，如图27所示，该车辆100包括如上所描述的车辆的该电控系统70。该车辆还可以设置其他功能，例如抬头显示功能、自适应巡航功能、主动刹车功能等，本实施例不做限定。
根据本申请的一些实施例，参考图27所示，车辆100还包括电池102和充电机101，电控系统70连接充电机101和电池102，充电机101连接电池102。电控系统70可以监控电池102的状态，并根据电池102的状态控制充电机101的充电参数，充电机101根据充电参数对电池102充电。
示例地，电控系统70可以包括电池管理系统(Battery Management System，BMS)，电池管理系统用于监控电池101的状态，例如，电压、电流、温度、充电状态等，电池管理系统还可以与充电机101通信，以使充电机101调整充电参数。
电控系统还可以包括整车控制器(Vehicle Control Unit，VCU)，整车控制器负责整体车辆的管理和协调，包括动力系统的控制、能量管理、再生制动、热管理等。还可以包括电机控制器，电机控制器控制驱动电机的运行，包括调节电流和电压以控制电机的转速和扭矩。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (32)

  1. 一种信号传输电路，其中，包括：隔离模块(20)和接收模块(40)，所述接收模块(40)包括信号接收电路(41)和信号输出器(42)；
    所述隔离模块(20)，用于接收第一差分信号，并对所述第一差分信号进行电气隔离后输出第二差分信号；
    所述信号接收电路(41)，输入端与所述隔离模块(20)的输出端连接，用于对所述第二差分信号进行处理后输出第三差分信号；
    所述信号输出器(42)，输入端与所述信号接收电路(41)的输出端连接，用于将所述第三差分信号合并后输出一路信号。
  2. 根据权利要求1所述的信号传输电路，其中，所述信号输出器(42)包括：信号合并电路(45)和信号反相电路(46)；
    所述信号合并电路(45)的输入端与所述信号接收电路(41)的输出端连接，用于将所述第三差分信号反相合并为一路初始信号；
    所述信号反相电路(46)的输入端与所述信号合并电路(45)的输出端连接，用于将所述一路初始信号反相后输出一路信号。
  3. 根据权利要求2所述的信号传输电路，其中，所述信号合并电路(45)包括：差分放大电路(440)和合并子电路(450)；
    所述差分放大电路(440)的输入端与所述信号接收电路(41)的输出端连接，用于对所述第三差分信号进行差分放大处理后输出第四差分信号；
    所述合并子电路(450)的输入端与该差分放大电路(440)的输出端连接，用于将所述第四差分信号反相合并为所述一路初始信号。
  4. 根据权利要求3所述的信号传输电路，其中，所述第三差分信号包括第三正向信号和第三负向信号，所述第四差分信号包括第四正向信号和第四负向信号，所述差分放大电路(440)包括：第一信号输入电路(441)和第二信号输入电路(442)；
    所述第一信号输入电路(441)用于接收所述第三正向信号和正向触发电平，根据所述第三正向信号和所述正向触发电平输出所述第四正向信号至所述合并子电路(450)，以及将所述第三正向信号和所述正向触发电平的第一合成信号输出至所述合并子电路(450)；
    所述第二信号输入电路(442)用于接收所述第三负向信号和负向触发电平，根据所述第三负向信号和所述负向触发电平输出所述第四负向信号至所述合并子电路(450)，以及将所述第三负向信号和所述负向触发电平的第二合成信号输出至所述合并子电路(450)。
  5. 根据权利要求4所述的信号传输电路，其中，所述正向触发电平和所述负向触发电平为共模电平。
  6. 根据权利要求4或5所述的信号传输电路，其中，所述合并子电路(450)包括：第一开关电路(451)、第二开关电路(452)和合并单元(453)；
    所述第一开关电路(451)的输入端与所述第一信号输入电路(441)的输出端连接，用于在所述第一合成信号的控制下导通时，基于所述第一合成信号和所述第四正向信号，输出第一路待合并信号；
    所述第二开关电路(452)的输入端与所述第二信号输入电路(442)的输出端连接，用于在所述第二合成信号的控制下导通时，基于所述第二合成信号和所述第四负向信号，输出第二路待合并信号；
    所述合并单元(453)的输入端与所述第一开关电路(451)的输出端和所述第二开关电路(452)的输出端连接，用于将所述第一路待合并信号和所述第二路待合并信号反相合并为一路初始信号；
    其中，所述第一开关电路(451)和所述第二开关电路(452)不同时导通或关断。
  7. 根据权利要求6所述的信号传输电路，其中，所述信号反相电路(46)包括：反相单元(460)和控制单元(461)；
    所述反相单元(460)的输入端与所述合并单元(453)的输出端连接，用于在所述控制单元(461)的控制下将所述一路初始信号反相后输出一路信号。
  8. 根据权利要求1-7任一项所述的信号传输电路，其中，所述第二差分信号包括第二正向信号和第二负向信号，所述信号传输电路(10)还包括：
    钳位模块(30)，与所述隔离模块(20)的输出端连接，用于根据所述第二正向信号和所述第二负向信号钳位所述第二正向信号和所述第二负向信号的共模电平。
  9. 根据权利要求8所述的信号传输电路，其中，所述钳位模块(30)用于，在所述第二正向信号和所述第二负向信号的共模电平的绝对值大于预设电平阈值时，调整所述第二正向信号和所述第二负向信号的共模电平。
  10. 根据权利要求8或9所述的信号传输电路，其中，所述钳位模块(30)用于，根据所述第二正向信号和所述第二负向信号调整共模电平钳位量，并根据所述共模电平钳位量调整所述第二正向信号和所述第二负向信号的共模电平。
  11. 根据权利要求8-10中任一项所述的信号传输电路，其中，所述钳位模块(30)包括触发电路(31)和泄放电路(32)；
    所述触发电路(31)的第一输入端接收第二正向信号，所述触发电路(31)的第二输入端接收第二负向信号，所述触发电路(31)用于输出触发信号；
    所述泄放电路(32)的控制端连接所述触发电路(31)的输出端，所述泄放电路(32)的第一端接收所述第二正向信号，所述泄放电路(32)的第二端接收第二负向信号，所述泄放电路(32)的第三端连接第一电源端，所述泄放电路(32)根据所述触发信号控制所述泄放电路(32)的第一端和第三端之间电荷泄放量，并根据所述触发信号控制所述泄放电路(32)的第二端和第三端之间电荷泄放量。
  12. 根据权利要求11所述的信号传输电路，其中，所述泄放电路(32)包括第一晶体管和第二晶体管；
    所述第一晶体管的控制端连接所述第二晶体管的控制端，所述第一晶体管的控制端和所述第二晶体管的控制端均接收所述触发信号，所述第一晶体管的第一端为所述泄放电路(32)的第一端，所述第二晶体管的第一端为所述泄放电路(32)的第二端，所述第一晶体管的第二端和所述第二晶体管的第二端均连接所述第一电源端。
  13. 根据权利要求11或12所述的信号传输电路，其中，所述第一晶体管和所述第二晶体管基于同一衬底形成。
  14. 根据权利要求11-13中任一项所述的信号传输电路，其中，所述触发电路(31)包括第一分压电路(310)和第二分压电路(320)；
    所述第一分压电路(310)的第一端接收所述第二正向信号，所述第一分压电路(310)的第二端连接所述第二分压电路(320)的第二端，所述第一分压电路(310)的第二端用于输出所述触发信号；所述第一分压电路(310)的第三端连接所述第一电源端；
    所述第二分压电路(320)的第一端接收所述第二负向信号，所述第二分压电路(320)的第三端连接所述第一电源端。
  15. 根据权利要求14所述的信号传输电路，其中，所述第一分压电路(310)包括第一电阻和第二电阻；
    所述第一电阻的第一端为所述第一分压电路(310)的第一端，所述第一电阻的第二端连接所述第二电阻的第一端，所述第一电阻的第二端为所述第一分压电路(310)的第二端，所述第二电阻的第二端为所述第一分压电路(310)的第三端。
  16. 根据权利要求14或15所述的信号传输电路，其中，所述第二分压电路(320)包括第三电阻和第四电阻；
    所述第三电阻的第一端为所述第二分压电路(320)的第一端，所述第三电阻的第二端连接所述第四电阻的第一端，所述第三电阻的第二端为所述第二分压电路(320)的第三端，所述第四电阻的第二端为所述第二分压电路(320)的第三端。
  17. 根据权利要求1-16任一项所述的信号传输电路，其中，所述信号接收电路(41)包括：前级差分放大电路(43)；
    所述前级差分放大电路(43)的输入端与所述隔离模块(20)的输出端连接，用于对所述第二差分信号进行放大处理后输出第三差分信号。
  18. 根据权利要求17所述的信号传输电路，其中，所述第三差分信号包括第三正向信号和第三负向信号，所述前级差分放大电路(43)包括第一放大电路(411)和第二放大电路(412)。
  19. 根据权利要求18所述的信号传输电路，其中，所述第一放大电路(411)的第一输入端接收第二负向信号，所述第一放大电路(411)的第二输入端接收第二正向信号，所述第一放大电路(411)用于根据所述第二负向信号和所述第二正向信号的差值生成所述第三正向信号；
    所述第二放大电路(412)的第一输入端接收所述第二正向信号，所述第二放大电路(412)的第二输入端接收所述第二负向信号，所述第二放大电路(412)用于根据所述第二正向信号和所述第二负向信号的差值生成所述第三负向信号。
  20. 根据权利要求18或19所述的信号传输电路，其中，所述第一放大电路(411)和所述第二放大电路(412)的结构相同。
  21. 根据权利要求19所述的信号传输电路，其中，所述第一放大电路(411)包括第一级子电路(413)；
    所述第一级子电路(413)的第一输入端接收所述第二正向信号，所述第一级子电路(413)的第二输入端接收所述第二负向信号，并根据所述第二正向信号和所述第二负向信号生成第三正向信号。
  22. 根据权利要求21所述的信号传输电路，其中，所述第一级子电路(413)包括第三上拉电路(423)和第三下拉电路(424)，所述第三上拉电路(423)的第一端连接电源端，所述第三上拉电路(423)的第二端连接所述第三下拉电路(424)的第一端，所述第三下拉电路(424)的控制端接收所述第二负向信号，所述第三下拉电路(424)的第二端接收所述第二正向信号；所述第三下拉电路(424)在所述第二负向信号的控制下调整所述第二正向信号对所述第三下拉电路(424)的第一端的向下驱动能力，所述第三下拉电路(424)的第一端输出所述第三正向信号。
  23. 根据权利要求22所述的信号传输电路，其中，所述第一级子电路(413)还包括预置电压电路(419)，所述预置电压电路(419)的第一端接收所述第二负向信号，所述预置电压电路(419)的第二端连接所述第三下拉电路(424)的控制端，所述预置电压电路(419)用于根据第二负向信号在所述第三下拉电路(424)的控制端产生预置电压。
  24. 根据权利要求21-23中任一项所述的信号传输电路，其中，所述第一放大电路(411)还包括第二级子电路(414)；
    所述第二级子电路(414)的输入端连接所述第一级子电路(413)的输出端，所述第二级子电路(414)用于对所述第一级子电路(413)输出的信号进行放大后输出所述第三正向信号。
  25. 根据权利要求24所述的信号传输电路，其中，所述第二级子电路(414)包括第二上拉电路(421)和第二下拉电路(422)，所述第二上拉电路(421)的第一端连接电源端，所述第二下拉电路(422)的第二端连接所述第二下拉电路(422)的第一端，所述第二下拉电路(422)的第二端连接第二电源端，所述第二下拉电路(422)的控制端接收所述第一级子电路(413)输出的信号；所述第二下拉电路(422)在所述第二负向信号的控制下调整所述第二电源端对所述第二下拉电路(422)的第二端的向下驱动能力，所述第二下拉电路(422)的第一端输出所述第三正向信号。
  26. 根据权利要求1-25任一项所述的信号传输电路，其中，所述信号传输电路(10)还包括输入模块(50)；
    所述输入模块(50)的输入端接收输入信号，所述输入模块(50)的输出端连接所述隔离模块(20)，并对所述输入信号进行调制后输出所述第一差分信号；
    所述信号输出器(42)输出的一路信号与所述输入模块(50)接收的输入信号同相。
  27. 根据权利要求1-26任一项所述的信号传输电路，其中，所述隔离模块(20)为电容隔离模块(20)。
  28. 根据权利要求1-27任一项所述的信号传输电路，其中，所述接收模块(40)还包括：
    延时电路(47)，输入端与所述信号输出器(42)的输出端连接，用于滤除所述信号输出器(42)输出的一路信号中的异常信号后输出一路信号。
  29. 一种信号传输系统(60)，其中，包括如权利要求1-28任一项所述的信号传输电路、控制器(61)、驱动模块(62)和功率器件(63)；
    所述控制器(61)的输出端与所述信号传输电路(10)的输入端连接；
    所述驱动模块(62)的输入端与所述信号传输电路(10)的输出端连接；
    所述功率器件(63)的输入端与所述驱动模块(62)的输出端连接；
    所述驱动模块(62)用于对所述信号传输电路(10)输出的信号进行升压处理后输出至所述功率器件(63)，以驱动所述功率器件(63)运行。
  30. 根据权利要求29所述的信号传输系统(60)，其中，所述控制器(61)输出信号为方波脉冲信号。
  31. 一种车辆的电控系统(70)，其中，包括如权利要求29或30所述的信号传输系统(60)。
  32. 一种车辆(100)，其中，包括如权利要求31所述的车辆的电控系统(70)。
PCT/CN2025/103646 2024-07-30 2025-06-25 信号传输电路及信号传输系统、电控系统、车辆 Pending WO2026026331A1 (zh)

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CN114050818A (zh) * 2021-10-11 2022-02-15 北京芯可鉴科技有限公司 数字隔离器及芯片
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