WO2026016178A1 - 一种基于半导体异质结的光电存算一体器件及其制备方法 - Google Patents

一种基于半导体异质结的光电存算一体器件及其制备方法

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Publication number
WO2026016178A1
WO2026016178A1 PCT/CN2024/106494 CN2024106494W WO2026016178A1 WO 2026016178 A1 WO2026016178 A1 WO 2026016178A1 CN 2024106494 W CN2024106494 W CN 2024106494W WO 2026016178 A1 WO2026016178 A1 WO 2026016178A1
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Prior art keywords
layer
charge
metal
semiconductor layer
heterojunction
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PCT/CN2024/106494
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English (en)
French (fr)
Inventor
孟佳琳
王天宇
陈琳
孙清清
张卫
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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Fudan University
Shanghai IC Manufacturing Innovation Center Co Ltd
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Priority to PCT/CN2024/106494 priority Critical patent/WO2026016178A1/zh
Publication of WO2026016178A1 publication Critical patent/WO2026016178A1/zh
Pending legal-status Critical Current
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/067—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using optical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/10—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising heterojunctions between organic semiconductors and inorganic semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/60—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors
    • H10K30/65—Light-sensitive field-effect devices, e.g. phototransistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • This invention relates to the field of semiconductor technology, and in particular to an optoelectronic in-memory computing device based on a semiconductor heterojunction and its fabrication method.
  • the purpose of this invention is to overcome the above-mentioned defects in the prior art and provide an optoelectronic in-memory computing device based on a semiconductor heterojunction and its fabrication method.
  • This invention provides an optoelectronic in-memory computing device based on a semiconductor heterojunction, comprising:
  • a charge blocking layer, a charge trapping layer, a charge tunneling layer, and a channel layer are sequentially disposed on the surface of a substrate, and source and drain electrodes are disposed at both ends of the channel layer.
  • the channel layer includes a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end to form a heterojunction, and the source and drain electrodes are respectively disposed on the two-dimensional semiconductor layer and the organic semiconductor layer;
  • the heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer simultaneously realizes carrier regulation and photoelectric signal response, as well as band matching regulation, and works in conjunction with the charge trapping layer to complete in-situ calculation and storage of information.
  • the charge blocking layer material comprises a ternary metal high-k oxide formed by a first metal element, a second metal element, and an oxygen element;
  • the charge trapping layer material comprises a binary metal oxide formed by a second metal element and an oxygen element;
  • the charge tunneling layer material comprises a binary metal high-k oxide formed by a first metal element and an oxygen element.
  • the first metal element includes Hf
  • the second metal element includes Al, La, Ti or Zr
  • the charge blocking layer includes an HfAlO x layer, an HfLaO x layer, an HfTiO x layer or an HfZrO x layer
  • the charge trapping layer includes an Al 2O 3 layer, a La 2O 3 layer, a TiO 2 layer or a ZrO 2 layer
  • the charge tunneling layer includes an HfO 2 layer
  • the thickness of the charge blocking layer is 20-50 nm
  • the thickness of the charge trapping layer is 10-20 nm
  • the thickness of the charge tunneling layer is 3-12 nm.
  • the two-dimensional semiconductor layer is n-type, the organic semiconductor layer is p-type, and the organic semiconductor layer forms a pn junction with the two-dimensional semiconductor layer.
  • the material of the two-dimensional semiconductor layer includes MoS2 , MoSe2 , or WS2 , and the material of the organic semiconductor layer includes... C8-BTBT, DNTT, pentacene, or P3HT, and/or, wherein the thickness of the two-dimensional semiconductor layer is 1–10 nm, and the thickness of the organic semiconductor layer is 20–50 nm.
  • the substrate includes a highly doped silicon wafer, which also serves as a back gate electrode; and/or, the source/drain electrodes include stacked metal electrodes, the stacked metal electrodes including a third metal layer and a fourth metal layer stacked together, the third metal layer being made of Cr or Ti, the fourth metal layer being made of Au, Pt, or Pd, the thickness of the third metal layer being 5–15 nm, and the thickness of the fourth metal layer being 30–100 nm.
  • This invention also provides a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction, comprising:
  • a charge blocking layer, a charge trapping layer, a charge tunneling layer, and a channel layer are sequentially formed on the surface of the substrate, and source and drain electrodes are formed at both ends of the channel layer.
  • the channel layer comprises a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end to form a heterojunction, and the source and drain electrodes are respectively disposed on the two-dimensional semiconductor layer and the organic semiconductor layer.
  • the heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer simultaneously realizes carrier regulation and photoelectric signal response, as well as band matching regulation, and works in conjunction with the charge trapping layer to complete in-situ calculation and storage of information.
  • the method for forming the charge blocking layer, the charge trapping layer, and the charge tunneling layer specifically includes:
  • a highly doped silicon wafer is used as the substrate and back gate electrode;
  • a thin film layer of ternary metal high-k oxide formed of a first metal element, a second metal element and an oxygen element is formed on the surface of the highly doped silicon wafer as a charge blocking layer.
  • a thin film layer of binary metal oxide formed of a second metal element and an oxygen element is formed on the surface of the charge blocking layer as a charge trapping layer;
  • a thin film layer of binary metal high-k oxide formed of a first metal element and an oxygen element is formed on the surface of the charge trapping layer as a charge tunneling layer.
  • the first metallic element includes Hf
  • the second metallic element includes Al, La, Ti, or Zr; wherein:
  • Atomic layer deposition technology is used to grow HfAlO x layer, HfLaO x layer, HfTiO x layer or HfZrO x layer with a thickness of 20-50 nm on the surface of the highly doped silicon wafer to form the charge barrier layer;
  • a physical vapor deposition technique is used to grow an Al2O3 layer, La2O3 layer, TiO2 layer , or ZrO2 layer with a thickness of 10–20 nm on the surface of the charge -blocking layer to form the charge-trapping layer.
  • the substrate is heated to a temperature of 80–150°C, and an HfO2 layer with a thickness of 3–12 nm is grown on the surface of the charge trapping layer to form the charge tunneling layer.
  • the method for forming the channel layer specifically includes:
  • Oxygen plasma treatment technology is used to treat the surface of the charge tunneling layer with oxygen plasma.
  • the treatment power is 100-200W and the treatment time is 20-120s.
  • a MoS2 layer, MoSe2 layer, or WS2 layer with a thickness of 1–10 nm is transferred to the surface of the charge tunneling layer to form an n-type two-dimensional semiconductor layer.
  • Electron beam lithography is used as a mask, and an organic evaporation method is used to grow a C8-BTBT layer, a DNTT layer, a pentacene layer, or a P3HT layer on one end of an n-type two-dimensional semiconductor layer.
  • This forms a p-type organic semiconductor layer with a thickness of 20-50 nm that is connected to one end of the n-type two-dimensional semiconductor layer.
  • a channel layer based on a pn junction of organic semiconductor and two-dimensional semiconductor is formed on the surface of the charge tunneling layer.
  • the method for forming the source and drain electrodes specifically includes:
  • Electron beam evaporation technology is used to form stacked metal electrodes on opposite ends of a two-dimensional semiconductor layer and an organic semiconductor layer.
  • the stacked metal electrodes include a lower third metal layer and an upper fourth metal layer stacked together to form source and drain electrodes.
  • the material of the third metal layer includes Cr or Ti, and the material of the fourth metal layer includes Au, Pt or Pd.
  • the thickness of the third metal layer is 5-15 nm, and the thickness of the fourth metal layer is 30-100 nm.
  • this invention constructs a nanoscale charge-trapping memory device by designing a novel scheme for a neuromorphic optoelectronic memory device based on a pn junction of n-type two-dimensional semiconductors and p-type organic semiconductors. Leveraging the excellent carrier manipulation capabilities of two-dimensional semiconductor and organic semiconductor materials, it achieves efficient charge storage under optical field control, realizing a memory-computing integrated optoelectronic memory device with neuromorphic computing capabilities.
  • This invention has the following advantages:
  • Two-dimensional semiconductor materials have atomic-level thickness, which can greatly improve the miniaturization capability of devices and enable applications of new electronic devices in the post-Moore era. Function.
  • Figure 1 is a schematic diagram of the structure of a preferred embodiment of the present invention, which is an optoelectronic in-memory computing device based on a semiconductor heterojunction.
  • Figures 2-7 are schematic diagrams of the process flow of a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction according to a preferred embodiment of the present invention.
  • Figure 8 is a schematic diagram illustrating the working principle of an optoelectronic in-memory computing device based on a semiconductor heterojunction according to a preferred embodiment of the present invention.
  • This invention relates to a heterostructure channel material (forming a channel layer) using a two-dimensional material (forming a two-dimensional semiconductor layer) and an organic material (forming an organic semiconductor layer) to form a neuromorphic electronic device with photoelectric storage effect, suitable for photoelectric neuromorphic computing and applications.
  • Traditional silicon-based semiconductor memories are made of silicon-based materials. As their size shrinks, they gradually approach their physical limits, and problems such as leakage current become increasingly apparent, making it difficult to meet the ever-increasing demand for high-density storage. In addition, traditional silicon-based semiconductor memories can only achieve storage through electrical signals, making it difficult to achieve multi-dimensional signal control.
  • Two-dimensional (2D) materials as novel semiconductor materials with atomically thin profiles, exhibit significant size reduction advantages in the post-Moore's Law era, demonstrating potential applications in novel memory devices.
  • 2D materials can serve as channels for floating-gate memories, simultaneously enabling carrier modulation and photoelectric signal response.
  • bandgap matching modulation can be achieved, further enhancing the storage performance of devices under photoelectric stimulation and providing new insights for novel memory devices.
  • neuromorphic computing characteristics can be realized using the designed storage device, and signal processing and computation can be completed in the storage device. This is of great significance for building a new type of storage and computing integrated storage device, and provides a core device unit for breaking the von Neumann computing paradigm.
  • an optoelectronic in-memory computing device based on a semiconductor heterojunction includes a charge blocking layer 11, a charge trapping layer 12, a charge tunneling layer 13 and a channel layer 15 sequentially disposed on the surface of a substrate 10, and source/drain electrodes 14 disposed at both ends of the channel layer 15.
  • the channel layer 15 includes a two-dimensional semiconductor layer 152 and an organic semiconductor layer 151 simultaneously disposed on the surface of the charge tunneling layer 13.
  • the two-dimensional semiconductor layer 152 and the organic semiconductor layer 151 are connected at one end to form a heterojunction.
  • Source and drain electrodes 14 are respectively disposed on the two-dimensional semiconductor layer 152 and the organic semiconductor layer 151.
  • the heterojunction formed by the two-dimensional semiconductor layer 152 and the organic semiconductor layer 151 As the channel layer 15, it simultaneously realizes carrier control and photoelectric signal response, as well as band matching control, and works in conjunction with the charge trapping layer 12 to complete in-situ calculation and storage of information.
  • the charge blocking layer 11 material comprises a ternary metal high-k oxide formed of a first metal element, a second metal element, and an oxygen element, i.e., the charge blocking layer 11 comprises a ternary metal high-k oxide layer.
  • the charge trapping layer 12 material includes a binary metal oxide formed from a second metal element and an oxygen element, that is, the charge trapping layer 12 includes a binary metal oxide layer.
  • the charge tunneling layer 13 material includes a binary metal high-k oxide formed from a first metal element and an oxygen element, that is, the charge tunneling layer 13 includes a binary metal high-k oxide layer.
  • the first metal element includes Hf
  • the second metal element includes Al, La, Ti, or Zr.
  • the charge blocking layer 11 includes an HfAlO x layer 111, an HfLaO x layer, an HfTiO x layer, or an HfZrO x layer. That is, the material of the charge blocking layer 11 includes HfAlO x , HfLaO x , HfTiO x , or HfZrO x .
  • the charge trapping layer 12 includes an Al2O3 layer 121, a La2O3 layer , a TiO2 layer, or a ZrO2 layer. That is , the material of the charge trapping layer 12 includes Al2O3 , La2O3 , TiO2 , or ZrO2 .
  • the charge tunneling layer 13 includes an HfO2 layer 131. That is, the material of the charge tunneling layer 13 includes HfO2 .
  • the thickness of the charge blocking layer 11 is 20–50 nm. Preferably, the thickness of the charge blocking layer 11 is approximately 30 nm.
  • the thickness of the charge trapping layer 12 is 10–20 nm. Preferably, the thickness of the charge trapping layer 12 is... The optimal nanometer size is around 15nm.
  • the thickness of the charge tunneling layer 13 is 3–12 nm. Preferably, the thickness of the charge tunneling layer 13 is about 7 nm.
  • the two-dimensional semiconductor layer 152 is n-type
  • the organic semiconductor layer 151 is p-type
  • the organic semiconductor layer 151 and the two-dimensional semiconductor layer 152 form a pn junction.
  • the material of the two-dimensional semiconductor layer 152 includes MoS2 , MoSe2 or WS2 , that is, the n-type two-dimensional semiconductor layer 152 includes an n-type MoS2 layer 1521, an n-type MoSe2 layer or an n-type WS2 layer.
  • the organic semiconductor layer 151 material includes C8-BTBT, DNTT, pentacene, or P3HT, that is, the p-type organic semiconductor layer 151 material includes p-type C8-BTBT layer 1511, p-type DNTT layer, p-type pentacene layer, or p-type P3HT layer.
  • the thickness of the two-dimensional semiconductor layer 152 is 1–10 nm. Preferably, the thickness of the two-dimensional semiconductor layer 152 is approximately 3 nm.
  • the thickness of the organic semiconductor layer 151 is 20–50 nm. Preferably, the thickness of the organic semiconductor layer 151 is about 30 nm.
  • the substrate 10 includes a highly doped silicon wafer 101. Furthermore, the highly doped silicon wafer 101 also serves as a back gate electrode (connected to the V gate ).
  • the source/drain electrodes 14 include a source electrode disposed at one end of the channel layer 15 and a drain electrode disposed at the other end of the channel layer 15.
  • the source electrode 141 (connected to V S ) is disposed on the outer end (right end shown in the figure) surface of the organic semiconductor layer 151 and grounded;
  • a drain electrode 142 (connected to V D ) is disposed on the outer end (left end shown in the figure) surface of the two-dimensional semiconductor layer 152, thereby forming an optoelectronic memory device.
  • the source and drain electrodes 14 include a multilayer metal electrode, which includes a third metal layer and a fourth metal layer stacked on top of each other.
  • the third metal layer is in contact with the surface of the channel layer 15, and the fourth metal layer is stacked on the surface of the third metal layer.
  • the third metal layer material includes Cr or Ti
  • the fourth metal layer material includes Au, Pt, or Pd.
  • the thickness of the third metal layer is 5–15 nm. Preferably, the thickness of the third metal layer is approximately 10 nm.
  • the thickness of the fourth metal layer is 30–100 nm. Preferably, the thickness of the fourth metal layer is about 50 nm.
  • the aforementioned two-dimensional semiconductor materials can significantly improve the miniaturization capability of devices, enabling applications in novel electronic devices for the post-Moore's Law era.
  • Constructing semiconductor heterojunctions using two-dimensional and organic semiconductor materials can greatly improve the electron-hole separation efficiency under photoelectric excitation, enhancing the device's photoelectric storage capacity.
  • Utilizing photoelectric storage devices for neuromorphic computing can significantly improve the device's in-memory computing efficiency, breaking through the traditional bottleneck of separating storage and computation, and achieving in-situ computation and storage of information, which is of great significance for constructing novel in-memory computing architectures.
  • the present invention discloses a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction, comprising:
  • a charge blocking layer, a charge trapping layer, a charge tunneling layer, and a channel layer are sequentially formed on the surface of the substrate, and source and drain electrodes are formed at both ends of the channel layer.
  • the channel layer comprises a two-dimensional semiconductor layer and an organic semiconductor layer connected at one end to form a heterojunction, and the source and drain electrodes are respectively disposed on the two-dimensional semiconductor layer and the organic semiconductor layer.
  • the heterojunction formed by the two-dimensional semiconductor layer and the organic semiconductor layer can simultaneously achieve carrier control and photoelectric signal response, as well as band matching control, and cooperate with the charge trapping layer to complete in-situ calculation and storage of information.
  • a method for fabricating an optoelectronic in-memory computing device based on a semiconductor heterojunction includes the following steps:
  • Step S1 Form a charge blocking layer 11 on the surface of substrate 10.
  • a highly doped silicon wafer 101 is used as the substrate 10 and the back gate electrode.
  • a ternary high-k oxide ternary metal layer composed of a first metal element, a second metal element, and an oxygen element, is formed on the surface of a highly doped silicon wafer 101 as a charge blocking layer 11. Further, the first metal element includes Hf, and the second metal element includes Al, La, Ti, or Zr.
  • atomic layer deposition technology is used to grow HfAlO x layer 111, HfLaO x layer, HfTiO x layer or HfZrO x layer with a thickness of 20 to 50 nm on the surface of highly doped silicon wafer 101 as charge blocking layer 11.
  • atomic layer deposition technology is used to grow a ternary metal high-k oxide HfAlOx layer 111 with a thickness of about 30 nm on the surface of a highly doped silicon wafer 101 to form a charge blocking layer 11.
  • Step S2 Form a charge trapping layer 12 on the surface of the charge blocking layer 11.
  • a thin film layer of binary metal oxide formed by a second metal element (Al, La, Ti or Zr) and an oxygen element is then formed on the surface of the charge blocking layer 11 as the charge trapping layer 12.
  • a 10-20 nm thick Al2O3 layer 121, La2O3 layer, TiO2 layer, or ZrO2 layer is grown on the surface of the charge-blocking layer 11 using physical vapor deposition (PVD) as the charge-trapping layer 12.
  • PVD physical vapor deposition
  • the elements in the charge-trapping layer 12 material must be consistent with the remaining elements in the ternary high-k oxide of the charge-blocking layer 11 after removing the first metal element to achieve high-quality interface growth.
  • the charge-blocking layer 11 material is HfAlO2x
  • the charge-trapping layer 12 material is correspondingly Al2O3
  • the charge-blocking layer 11 material is HfLaO2x
  • the charge-trapping layer 12 material is correspondingly La2O3
  • the charge-blocking layer 11 material is HfTiO2x
  • the charge-trapping layer 12 material is correspondingly TiO2
  • the charge-blocking layer 11 material is HfZrO2x
  • the charge-trapping layer 12 material is correspondingly ZrO2 .
  • a binary metal oxide Al2O3 layer 121 with a thickness of about 15 nm is grown on the surface of the HfAlO2x charge blocking layer 11 using physical vapor deposition at room temperature to form a charge trapping layer 12.
  • Step S3 Form a charge tunneling layer 13 on the surface of the charge trapping layer 12.
  • a first metal is formed on the surface of the charge trapping layer 12.
  • a thin film of a binary metal high-k oxide formed by element and oxygen element serves as a charge tunneling layer 13.
  • the substrate 10 is heated using a tray-heated physical vapor deposition technique, with the heating temperature set to 80–150°C, to grow an HfO2 layer 131 with a thickness of 3–12 nm on the surface of the charge trapping layer 12, forming a charge tunneling layer 13.
  • the substrate 10 is heated using a tray-heated physical vapor deposition technique.
  • the heating temperature is set to 100°C, and a binary metal high-k oxide HfO2 layer 131 with a thickness of about 7 nm is grown on the surface of the Al2O3 charge trapping layer 12 to form a charge tunneling layer 13.
  • Step S4 Form an n-type two-dimensional semiconductor layer 152 on the surface of the charge tunneling layer 13.
  • the surface of the charge tunneling layer 13 can be treated to improve the interface quality of the charge tunneling layer 13.
  • oxygen plasma treatment technology is used to treat the surface of the charge tunneling layer 13 with oxygen plasma.
  • the treatment power during oxygen plasma treatment is 100–200 W, and the treatment duration is 20–120 s.
  • a mechanical peeling method is used to transfer a MoS2 layer 1521, MoSe2 layer or WS2 layer with a thickness of 1 to 10 nm as an n-type semiconductor material in the channel onto the surface of the charge tunneling layer 13 to form an n-type two-dimensional semiconductor layer 152.
  • the HfO2 charge tunneling layer 13 is treated with oxygen plasma formed from oxygen at a power of 150W for approximately 40 seconds. Then, a MoS2 layer 1521 with a thickness of approximately 3nm is transferred onto the surface of the HfO2 charge tunneling layer 13 using a mechanical exfoliation method. On top, an n-type two-dimensional semiconductor layer 152 is formed.
  • Step S5 A p-type organic semiconductor layer 151 is formed on one end of the n-type two-dimensional semiconductor layer 152 to form a channel layer 15.
  • electron beam lithography is used as a mask to define the working area of the pn junction.
  • a photoresist protection method is employed, and an organic vapor deposition method is used to grow a C8-BTBT layer 1511, a DNTT layer, a pentacene layer, or a P3HT layer on one end of the n-type two-dimensional semiconductor layer 152.
  • This forms a p-type organic semiconductor layer 151 with a thickness of 20–50 nm, connected at one end to the n-type two-dimensional semiconductor layer 152.
  • the p-type organic semiconductor layer 151 is also simultaneously formed on the surface of the charge tunneling layer 13.
  • a channel layer 15 based on the pn junction of the organic semiconductor and the two-dimensional semiconductor is formed on the surface of the charge tunneling layer 13.
  • the p-type organic semiconductor layer 151 is disposed along the length extension direction of the n-type two-dimensional semiconductor layer 152 and is connected to one end of the n-type two-dimensional semiconductor layer 152.
  • electron beam lithography is used to define the working area of the pn junction.
  • Photoresist protection is used to grow p-type organic semiconductor material C8 -BTBT on the surface of HfO2 charge tunneling layer 13 and one end of n-type MoS2 two-dimensional semiconductor layer 152 using organic evaporation equipment. The thickness is controlled at about 30nm to form C8-BTBT layer 1511, which serves as p-type organic semiconductor layer 151, thus constructing a pn junction channel based on n-type two-dimensional material and p-type organic material.
  • Step S6 Prepare source and drain electrodes 14.
  • electron beam evaporation technology is used to form stacked metal electrodes on the left and right ends of the n-type two-dimensional semiconductor layer 152 and the p-type organic semiconductor layer 151, which are opposite to each other.
  • the stacked metal electrodes include a lower third metal layer and an upper fourth metal layer, forming source and drain electrodes 14.
  • the material of the third metal layer includes Cr or Ti, and the material of the fourth metal layer includes Au, Pt, or Pd.
  • the thickness of the third metal layer is 5-15 nm, and the thickness of the fourth metal layer is 30-100 nm.
  • electron beam evaporation technology is used to grow Cr/Au stacked metal electrodes on the left and right surfaces of the n-type MoS2 two-dimensional semiconductor layer 152 and the p-type C8-BTBT organic semiconductor layer 151, which are opposite to each other.
  • a source electrode 141 is formed on the surface of the p-type C8-BTBT organic semiconductor layer 151, and a drain electrode 142 is formed on the surface of the n-type MoS2 two-dimensional semiconductor layer 152.
  • the source electrode 141 and the drain electrode 142 together form the source-drain electrode 14.
  • the thickness of the Cr third metal layer is about 10 nm
  • the thickness of the Au fourth metal layer is about 50 nm.
  • the method for fabricating a semiconductor heterojunction-based opto-in-memory computing device according to the present invention described above can be used to fabricate, for example, the semiconductor heterojunction-based opto-in-memory computing device shown in FIG1.
  • the semiconductor heterojunction-based opto-in-memory computing device shown in FIG1 can be fabricated using the method for fabricating a semiconductor heterojunction-based opto-in-memory computing device according to the present invention described above, for example, in FIG2-7.
  • V ⁇ sub> gate ⁇ /sub> voltage gate voltage
  • V ⁇ sub>D ⁇ /sub> voltage drain voltage
  • the source electrode 141 is grounded (source voltage VS is ground), forming a memory-in-memory optoelectronic storage device with neuromorphic computing capabilities.
  • this invention constructs a nanoscale charge-trapping memory device by designing a novel scheme for a neuromorphic optoelectronic memory device based on a pn junction of an n-type two-dimensional semiconductor and a p-type organic semiconductor.

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Abstract

本发明公开了一种基于半导体异质结的光电存算一体器件及其制备方法，包括：依次设于衬底表面上的电荷阻挡层、电荷俘获层、电荷隧穿层和沟道层，以及设于所述沟道层的两端上的源漏电极；所述沟道层包括以一端相连并形成异质结的二维半导体层和有机半导体层，所述源漏电极分设于所述二维半导体层和所述有机半导体层上；其中，通过所述二维半导体层和所述有机半导体层形成的异质结，同时实现载流子调控和光电信号响应，以及实现能带匹配调控，并与所述电荷俘获层配合，以完成信息的原位计算与存储。本发明利用二维材料与有机材料的异质结构建沟道材料，制备具有光电存储效果的神经形态电子器件，适合于光电神经形态计算与应用。

Description

一种基于半导体异质结的光电存算一体器件及其制备方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种基于半导体异质结的光电存算一体器件及其制备方法。
背景技术
作为信息化时代中核心的信息记录单元，存储器在集成电路中扮演着重要角色。传统的半导体硅基存储器组成于硅基材料，在尺寸微缩的过程中逐渐接近物理极限，漏电等问题逐渐明显，难以满足日益增加的高密度存储需求。此外，传统的半导体硅基存储器仅能通过电信号实现“0”和“1”的信号存储，无法满足存算一体的计算需求，从而难以实现多维度的信号调控。
因此，有必要提供一种新型的光电存算一体器件以解决现有技术中存在的上述问题。
发明内容
本发明的目的在于克服现有技术存在的上述缺陷，提供一种基于半导体异质结的光电存算一体器件及其制备方法。
为实现上述目的，本发明的技术方案如下：
本发明提供一种基于半导体异质结的光电存算一体器件，包括：
依次设于衬底表面上的电荷阻挡层、电荷俘获层、电荷隧穿层和沟道层，以及设于所述沟道层的两端上的源漏电极；
所述沟道层包括以一端相连并形成异质结的二维半导体层和有机半导体层，所述源漏电极分设于所述二维半导体层和所述有机半导体层上；
其中，通过所述二维半导体层和所述有机半导体层形成的异质结，同时实现载流子调控和光电信号响应，以及实现能带匹配调控，并与所述电荷俘获层配合，以完成信息的原位计算与存储。
进一步地，所述电荷阻挡层材料包括由第一金属元素、第二金属元素和氧元素形成的三元金属高k氧化物，所述电荷俘获层材料包括由第二金属元素和氧元素形成的二元金属氧化物，所述电荷隧穿层材料包括由第一金属元素和氧元素形成的二元金属高k氧化物。
进一步地，所述第一金属元素包括Hf，所述第二金属元素包括Al、La、Ti或Zr，所述电荷阻挡层包括HfAlOx层、HfLaOx层、HfTiOx层或HfZrOx层，所述电荷俘获层包括Al2O3层、La2O3层、TiO2层或ZrO2层，所述电荷隧穿层包括HfO2层，和/或，所述电荷阻挡层的厚度为20～50nm，所述电荷俘获层的厚度为10～20nm，所述电荷隧穿层的厚度为3～12nm。
进一步地，所述二维半导体层为n型，所述有机半导体层为p型，所述有机半导体层与所述二维半导体层形成pn结，所述二维半导体层材料包括MoS2、MoSe2或WS2，所述有机半导体层材料包括 C8-BTBT、DNTT、并五苯或P3HT，和/或，所述二维半导体层的厚度为1～10nm，所述有机半导体层的厚度为20～50nm。
进一步地，所述衬底包括高掺杂硅片，所述高掺杂硅片还作为背栅电极；和/或，所述源漏电极包括叠层金属电极，所述叠层金属电极包括相叠设的第三金属层和第四金属层，所述第三金属层材料包括Cr或Ti，所述第四金属层材料包括Au、Pt或Pd，所述第三金属层的厚度为5～15nm，所述第四金属层的厚度为30～100nm。
本发明还提供一种基于半导体异质结的光电存算一体器件的制备方法，包括：
提供衬底；
在所述衬底的表面上依次形成电荷阻挡层、电荷俘获层、电荷隧穿层和沟道层，以及在所述沟道层的两端上形成源漏电极；
其中，使所述沟道层包括以一端相连并形成异质结的二维半导体层和有机半导体层，并使所述源漏电极分设于所述二维半导体层和所述有机半导体层上；
其中，通过所述二维半导体层和所述有机半导体层形成的异质结，同时实现载流子调控和光电信号响应，以及实现能带匹配调控，并与所述电荷俘获层配合，以完成信息的原位计算与存储。
进一步地，形成所述电荷阻挡层、所述电荷俘获层和所述电荷隧穿层的方法，具体包括：
采用高掺杂硅片作为衬底和背栅电极；
在所述高掺杂硅片的表面上形成由第一金属元素、第二金属元素和氧元素形成的三元金属高k氧化物的薄膜层，作为电荷阻挡层；
在所述电荷阻挡层的表面上形成由第二金属元素和氧元素形成的二元金属氧化物的薄膜层，作为电荷俘获层；
在所述电荷俘获层的表面上形成由第一金属元素和氧元素形成的二元金属高k氧化物的薄膜层，作为电荷隧穿层。
进一步地，所述第一金属元素包括Hf，所述第二金属元素包括Al、La、Ti或Zr；其中：
采用原子层沉积技术，在所述高掺杂硅片的表面上生长厚度为20～50nm的HfAlOx层、HfLaOx层、HfTiOx层或HfZrOx层，形成所述电荷阻挡层；
在室温的环境下，采用物理气相沉积技术，在所述电荷阻挡层的表面上生长厚度为10～20nm的Al2O3层、La2O3层、TiO2层或ZrO2层，形成所述电荷俘获层；
利用托盘加热型物理气相沉积技术，对所述衬底进行加热，加热温度为80～150℃，在所述电荷俘获层的表面上生长厚度为3～12nm的HfO2层，形成所述电荷隧穿层。
进一步地，形成所述沟道层的方法，具体包括：
采用氧等离子体处理技术，利用氧等离子体对所述电荷隧穿层的表面进行处理，处理功率为100～200W，处理时长为20～120s；
采用机械剥离方法，将厚度为1～10nm的MoS2层、MoSe2层或WS2层转移在所述电荷隧穿层的表面上，形成n型二维半导体层；
采用电子束光刻作为掩膜，并采用有机蒸镀方法，在n型二维半导体层的一端上生长C8-BTBT层、DNTT层、并五苯层或P3HT层，形成通过一端连接在n型二维半导体层的一端上的厚度为20～50nm的p型有机半导体层，从而在所述电荷隧穿层的表面上形成基于有机半导体与二维半导体的pn结的沟道层。
进一步地，形成所述源漏电极的方法，具体包括：
采用电子束蒸发技术，在二维半导体层和有机半导体层相背离的两端上分别形成叠层金属电极，使所述叠层金属电极包括相叠设的下层第三金属层和上层第四金属层，形成源漏电极；其中，所述第三金属层材料包括Cr或Ti，所述第四金属层材料包括Au、Pt或Pd，所述第三金属层的厚度为5～15nm，所述第四金属层的厚度为30～100nm。
由上述技术方案可以看出，本发明通过设计基于n型二维半导体与p型有机半导体的pn结的神经形态光电存储器件的新方案，构建纳米级尺度的电荷俘获型存储器件，借助二维半导体材料与有机半导体材料的优异载流子调控功能，实现光场调控下的高效电荷存储，实现具有神经形态计算功能的存算一体型光电存储器件。本发明具有以下优点：
(1)二维半导体材料具有原子层级的厚度，可以极大程度地提高器件的尺寸微缩能力，具有面向后摩尔时代的新型电子器件的应用 功能。
(2)创新地采用二维半导体材料与有机半导体材料构建半导体异质结，极大程度地提高器件在光电激励下的电子-空穴分离效率，提升器件的光电存储能力。
(3)利用光电存储器件实现神经形态计算，极大程度地提高器件的存算效率，打破传统的存储与计算分离瓶颈，完成信息的原位计算与存储，对于构建新型存算一体架构具有重要意义。
附图说明
图1为本发明一较佳实施例的一种基于半导体异质结的光电存算一体器件的结构示意图。
图2-图7为本发明一较佳实施例的一种基于半导体异质结的光电存算一体器件的制备方法的工艺流程示意图。
图8为本发明一较佳实施例的一种基于半导体异质结的光电存算一体器件的工作原理示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。除非另外定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技 能的人士所理解的通常意义。本文中使用的“包括”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本发明涉及一种利用二维材料(形成二维半导体层)与有机材料(形成有机半导体层)的异质结构建沟道材料(形成沟道层)，形成具有光电存储效果的神经形态电子器件，适合于光电神经形态计算与应用。
传统的半导体硅基存储器组成于硅基材料，在尺寸微缩的过程中逐渐接近物理极限，漏电等问题逐渐明显，难以满足日益增加的高密度存储需求。此外，传统的半导体硅基存储器仅能通过电信号实现存储，难以实现多维度的信号调控。
二维材料作为一种原子级厚度的新型半导体材料，在后摩尔时代展现出巨大的尺寸微缩优势，具有应用于新型存储器的潜力。作为一种新型的半导体沟道材料，二维材料可以作为浮栅存储器的沟道，同时实现载流子调控以及光电信号响应。另一方面，通过二维材料与有机半导体材料的异质结构建，可以实现能带匹配调控，进一步增强器件在光电刺激下的存储效果，为新型存储器件提供了新的思路。
传统的存储器仅仅能实现“0”和“1”的信号存储，无法满足存算一体的计算需求。受到人脑的启发，可以开发具有类脑计算功能的存储器件，在同一器件完成存储与计算两种功能，极大程度促进了计算效率的提升。同时，借助器件的神经形态特性，可以在存储的同时 实现神经形态计算等智能计算任务，打破传统的冯·诺依曼式架构瓶颈。
传统的半导体pn结构，需对硅采用不同掺杂工艺实现。我们借助二维材料与有机材料优异的载流子调控能力，利用n型二维半导体材料与p型有机半导体材料构建优异光电响应的异质结沟道，在纳米尺寸完成高性能光电存储器件的搭建，将存储器件的信号调控模式从纯电调控拓展至光调控，为面向尺寸微缩的新型光电存储器件提供了新的思路。
此外，通过对存储的电荷俘获层的设计，可以利用设计的存储器件实现类脑计算特性，在存储器件完成信号的处理计算，对于构建存算一体的新型存储器件具有重要意义，为打破冯·诺依曼式计算范式提供了核心器件单元。
以下结合附图，对本发明的具体实施方式作进一步的详细说明。
参考图1。本发明的一种基于半导体异质结的光电存算一体器件，包括依次设于衬底10表面上的电荷阻挡层11、电荷俘获层12、电荷隧穿层13和沟道层15，以及设于沟道层15的两端上的源漏电极14。
其中，沟道层15包括同时设于电荷隧穿层13表面上的二维半导体层152和有机半导体层151。并且，二维半导体层152和有机半导体层151以各自的一端相连，形成异质结。源漏电极14分设于二维半导体层152和有机半导体层151上。
从而，通过二维半导体层152和有机半导体层151形成的异质结 作为沟道层15，同时实现载流子调控和光电信号响应，以及实现能带匹配调控，并与电荷俘获层12配合，以完成信息的原位计算与存储。
参考图1。在一些实施例中，电荷阻挡层11材料包括由第一金属元素、第二金属元素和氧元素形成的三元金属高k氧化物，即电荷阻挡层11包括三元金属高k氧化物层。
电荷俘获层12材料包括由第二金属元素和氧元素形成的二元金属氧化物，即电荷俘获层12包括二元金属氧化物层。
电荷隧穿层13材料包括由第一金属元素和氧元素形成的二元金属高k氧化物，即电荷隧穿层13包括二元金属高k氧化物层。
在一些实施例中，第一金属元素包括Hf，第二金属元素包括Al、La、Ti或Zr。
在一些实施例中，电荷阻挡层11包括HfAlOx层111、HfLaOx层、HfTiOx层或HfZrOx层。即电荷阻挡层11材料包括HfAlOx、HfLaOx、HfTiOx或HfZrOx。
电荷俘获层12包括Al2O3层121、La2O3层、TiO2层或ZrO2层。即电荷俘获层12材料包括Al2O3、La2O3、TiO2或ZrO2。
电荷隧穿层13包括HfO2层131。即电荷隧穿层13材料包括HfO2。
在一些实施例中，电荷阻挡层11的厚度为20～50nm。较佳地，电荷阻挡层11的厚度优选为30nm左右。
电荷俘获层12的厚度为10～20nm。较佳地，电荷俘获层12的厚 度优选为15nm左右。
电荷隧穿层13的厚度为3～12nm。较佳地，电荷隧穿层13的厚度优选为7nm左右。
参考图1。在一些实施例中，二维半导体层152为n型，有机半导体层151为p型，有机半导体层151与二维半导体层152形成pn结。
在一些实施例中，二维半导体层152材料包括MoS2、MoSe2或WS2，即n型二维半导体层152包括n型MoS2层1521、n型MoSe2层或n型WS2层。
有机半导体层151材料包括C8-BTBT、DNTT、并五苯或P3HT，即p型有机半导体层151材料包括p型C8-BTBT层1511、p型DNTT层、p型并五苯(Pentacene)层或p型P3HT层。
在一些实施例中，二维半导体层152的厚度为1～10nm。较佳地，二维半导体层152的厚度优选为3nm左右。
有机半导体层151的厚度为20～50nm。较佳地，有机半导体层151的厚度优选为30nm左右。
参考图1。在一些实施例中，衬底10包括高掺杂硅片101。并且，高掺杂硅片101还作为背栅电极(接Vgate)。
在一些实施例中，源漏电极14包括设于沟道层15的一端上的源电极，和设于沟道层15的另一端上的漏电极。例如，源电极141(接VS)设于有机半导体层151的外端(图示为右端)表面上，并接地； 漏电极142(接VD)设于二维半导体层152的外端(图示为左端)表面上。从而形成光电存储器件。
在一些实施例中，源漏电极14(源电极141和漏电极142)包括叠层金属电极，叠层金属电极包括相叠设的第三金属层和第四金属层。其中，第三金属层与沟道层15的表面相接触，第四金属层叠设于第三金属层的表面上。
在一些实施例中，第三金属层材料包括Cr或Ti，第四金属层材料包括Au、Pt或Pd。
在一些实施例中，第三金属层的厚度为5～15nm。较佳地，第三金属层的厚度优选为10nm左右。
第四金属层的厚度为30～100nm。较佳地，第四金属层的厚度优选为50nm左右。
上述采用的二维半导体材料具有原子层级的厚度，可以极大程度地提高器件的尺寸微缩能力，具有面向后摩尔时代的新型电子器件的应用功能。采用二维半导体材料与有机半导体材料构建半导体异质结，能够极大程度地提高器件在光电激励下的电子-空穴分离效率，提升器件的光电存储能力。利用光电存储器件实现神经形态计算，能够极大程度地提高器件的存算效率，打破传统的存储与计算分离瓶颈，完成信息的原位计算与存储，对于构建新型存算一体架构具有重要意义。
以下通过具体实施方式并结合附图，对本发明的一种基于半导体异质结的光电存算一体器件的制备方法作进一步的详细说明。
本发明的一种基于半导体异质结的光电存算一体器件的制备方法，包括：
提供衬底；
在衬底的表面上依次形成电荷阻挡层、电荷俘获层、电荷隧穿层和沟道层，以及在沟道层的两端上形成源漏电极；
其中，使沟道层包括以一端相连并形成异质结的二维半导体层和有机半导体层，并使源漏电极分设于二维半导体层和有机半导体层上；
其中，通过二维半导体层和有机半导体层形成的异质结，同时实现载流子调控和光电信号响应，以及实现能带匹配调控，并与电荷俘获层配合，以完成信息的原位计算与存储。
参考图2-图7。在一些实施例中，本发明的一种基于半导体异质结的光电存算一体器件的制备方法，包括以下步骤：
步骤S1：在衬底10的表面上形成电荷阻挡层11。
如图2所示，采用高掺杂硅片101作为衬底10和背栅电极。
在高掺杂硅片101的表面上形成由第一金属元素、第二金属元素和氧元素形成的三元金属高k氧化物的薄膜层，作为电荷阻挡层11。进一步地，第一金属元素包括Hf，第二金属元素包括Al、La、Ti或Zr。
在一些实施例中，采用原子层沉积技术，在高掺杂硅片101的表面上生长厚度为20～50nm的HfAlOx层111、HfLaOx层、HfTiOx层或HfZrOx层，作为电荷阻挡层11。
本实施例中，采用原子层沉积技术，在高掺杂硅片101的表面上生长厚度为30nm左右的三元金属高k氧化物HfAlOx层111，形成电荷阻挡层11。
步骤S2：在电荷阻挡层11的表面上形成电荷俘获层12。
如图3所示，接着，在电荷阻挡层11的表面上形成由第二金属元素(Al、La、Ti或Zr)和氧元素形成的二元金属氧化物的薄膜层，作为电荷俘获层12。
在一些实施例中，在室温的环境下，采用物理气相沉积技术，在电荷阻挡层11的表面上生长厚度为10～20nm的Al2O3层121、La2O3层、TiO2层或ZrO2层，作为电荷俘获层12。其中，电荷俘获层12材料中的元素需要和电荷阻挡层11的三元金属高k氧化物中去除第一金属元素后的剩余元素保持一致，以实现高质量界面生长。例如，当电荷阻挡层11材料为HfAlOx时，电荷俘获层12材料相应为Al2O3；当电荷阻挡层11材料为HfLaOx时，电荷俘获层12材料相应为La2O3；当电荷阻挡层11材料为HfTiOx时，电荷俘获层12材料相应为TiO2；当电荷阻挡层11材料为HfZrOx时，电荷俘获层12材料相应为ZrO2。
本实施例中，在室温的环境下，采用物理气相沉积技术，在HfAlOx电荷阻挡层11的表面上生长厚度为15nm左右的二元金属氧化物Al2O3层121，形成电荷俘获层12。
步骤S3：在电荷俘获层12的表面上形成电荷隧穿层13。
如图4所示，接着，在电荷俘获层12的表面上形成由第一金属 元素和氧元素形成的二元金属高k氧化物的薄膜层，作为电荷隧穿层13。
在一些实施例中，利用托盘加热型物理气相沉积技术，对衬底10进行加热，加热温度设置为80～150℃，在电荷俘获层12的表面上生长厚度为3～12nm的HfO2层131，形成电荷隧穿层13。
本实施例中，利用托盘加热型物理气相沉积技术，对衬底10进行加热，加热温度设置为100℃，在Al2O3电荷俘获层12的表面上生长厚度为7nm左右的二元金属高k氧化物HfO2层131，形成电荷隧穿层13。
步骤S4：在电荷隧穿层13的表面上形成n型二维半导体层152。
在电荷隧穿层13的表面上形成n型二维半导体层152前，可先对电荷隧穿层13的表面进行处理，以提高电荷隧穿层13的界面质量。
如图5所示，在一些实施例中，采用氧等离子体处理技术，利用氧等离子体对电荷隧穿层13的表面进行处理。其中，进行氧等离子体处理时的处理功率为100～200W，处理时长为20～120s。
随后，采用机械剥离方法，将厚度为1～10nm的MoS2层1521、MoSe2层或WS2层作为沟道中的n型半导体材料，转移在电荷隧穿层13的表面上，形成n型二维半导体层152。
本实施例中，在150W的功率下，利用氧气形成的氧等离子体，对HfO2电荷隧穿层13处理40s左右。然后，采用机械剥离方法，将厚度为3nm左右的MoS2层1521转移在HfO2电荷隧穿层13的表面 上，形成n型二维半导体层152。
步骤S5：在n型二维半导体层152的一端上形成p型有机半导体层151，以形成沟道层15。
如图6所示，在一些实施例中，采用电子束光刻作为掩膜，即利用电子束光刻定义pn结的工作区域，采用光刻胶保护的方法，并采用有机蒸镀方法，在n型二维半导体层152的一端上生长C8-BTBT层1511、DNTT层、并五苯层或P3HT层，形成通过一端连接在n型二维半导体层152的一端上的厚度为20～50nm的p型有机半导体层151，且使p型有机半导体层151同时还形成于电荷隧穿层13的表面上。从而在电荷隧穿层13的表面上形成基于有机半导体与二维半导体(p型有机半导体层151和n型二维半导体层152)的pn结的沟道层15。
在一些实施例中，p型有机半导体层151沿n型二维半导体层152的长度延伸方向设置，并与n型二维半导体层152的一端相连。
本实施例中，利用电子束光刻定义pn结的工作区域，采用光刻胶保护的方法，利用有机蒸镀设备在HfO2电荷隧穿层13的表面上和n型MoS2二维半导体层152的一端上生长p型有机半导体材料C8-BTBT，厚度控制在30nm左右，形成C8-BTBT层1511，作为p型有机半导体层151，构建基于n型二维材料与p型有机材料的pn结沟道。
步骤S6：制备源漏电极14。
如图7所示，在一些实施例中，采用电子束蒸发技术，在n型二维半导体层152和p型有机半导体层151相背离的左右两端上分别形成叠层金属电极，使叠层金属电极包括相叠设的下层第三金属层和上层第四金属层，形成源漏电极14。其中，第三金属层材料包括Cr或Ti，第四金属层材料包括Au、Pt或Pd，第三金属层的厚度为5～15nm，第四金属层的厚度为30～100nm。
本实施例中，采用电子束蒸发技术，在n型MoS2二维半导体层152和p型C8-BTBT有机半导体层151相背离的左右两端的表面上分别生长Cr/Au叠层金属电极，在p型C8-BTBT有机半导体层151的表面上形成源电极141，并在n型MoS2二维半导体层152的表面上形成漏电极142，源电极141和漏电极142共同形成源漏电极14。其中，Cr第三金属层的厚度为10nm左右，Au第四金属层的厚度为50nm左右。
从而通过上述本发明的一种基于半导体异质结的光电存算一体器件的制备方法，可以制备形成例如图1所示的本发明的一种基于半导体异质结的光电存算一体器件。换言之，本发明图1所示的一种基于半导体异质结的光电存算一体器件，可以通过上述例如图2-图7所示的本发明的一种基于半导体异质结的光电存算一体器件的制备方法制备得到。
参考图8。当在上述图1中器件的高掺杂硅片101(背栅电极)上接Vgate电压(栅压)，在MoS2二维半导体层152一端的漏电极142上接VD电压(漏极电压)，并将C8-BTBT有机半导体层151一端的 源电极141接地(源极电压VS为地)，形成具有神经形态计算功能的存算一体型光电存储器件。利用光脉冲作用于二维材料与有机材料构建的pn结(MoS2二维半导体层152和C8-BTBT有机半导体层151组成的沟道层15)，实现高效的电子-空穴对分离，并在电压的激励下进入Al2O3电荷俘获层12，实现高性能的光电存储效果，利用光电存储器的电阻值更迭实现类脑计算，完成光电激励下的存算一体应用。
综上，本发明通过设计基于n型二维半导体与p型有机半导体的pn结的神经形态光电存储器件的新方案，构建了纳米级尺度的电荷俘获型存储器件，并借助二维半导体材料与有机半导体材料的优异载流子调控功能，实现了光场调控下的高效电荷存储，从而实现了具有神经形态计算功能的存算一体型光电存储器件。
虽然在上文中详细说明了本发明的实施方式，但是对于本领域的技术人员来说显而易见的是，能够对这些实施方式进行各种修改和变化。但是，应理解，这种修改和变化都属于权利要求书中所述的本发明的范围和精神之内。而且，在此说明的本发明可有其它的实施方式，并且可通过多种方式实施或实现。

Claims (10)

  1. 一种基于半导体异质结的光电存算一体器件，其特征在于，包括：
    依次设于衬底表面上的电荷阻挡层、电荷俘获层、电荷隧穿层和沟道层，以及设于所述沟道层的两端上的源漏电极；
    所述沟道层包括以一端相连并形成异质结的二维半导体层和有机半导体层，所述源漏电极分设于所述二维半导体层和所述有机半导体层上；
    其中，通过所述二维半导体层和所述有机半导体层形成的异质结，同时实现载流子调控和光电信号响应，以及实现能带匹配调控，并与所述电荷俘获层配合，以完成信息的原位计算与存储。
  2. 根据权利要求1所述的基于半导体异质结的光电存算一体器件，其特征在于，所述电荷阻挡层材料包括由第一金属元素、第二金属元素和氧元素形成的三元金属高k氧化物，所述电荷俘获层材料包括由第二金属元素和氧元素形成的二元金属氧化物，所述电荷隧穿层材料包括由第一金属元素和氧元素形成的二元金属高k氧化物。
  3. 根据权利要求2所述的基于半导体异质结的光电存算一体器件，其特征在于，所述第一金属元素包括Hf，所述第二金属元素包括Al、La、Ti或Zr，所述电荷阻挡层包括HfAlOx层、HfLaOx层、HfTiOx层或HfZrOx层，所述电荷俘获层包括Al2O3层、La2O3层、TiO2层或ZrO2层，所述电荷隧穿层包括HfO2层，和/或，所述电荷阻挡 层的厚度为20～50nm，所述电荷俘获层的厚度为10～20nm，所述电荷隧穿层的厚度为3～12nm。
  4. 根据权利要求1所述的基于半导体异质结的光电存算一体器件，其特征在于，所述二维半导体层为n型，所述有机半导体层为p型，所述有机半导体层与所述二维半导体层形成pn结，所述二维半导体层材料包括MoS2、MoSe2或WS2，所述有机半导体层材料包括C8-BTBT、DNTT、并五苯或P3HT，和/或，所述二维半导体层的厚度为1～10nm，所述有机半导体层的厚度为20～50nm。
  5. 根据权利要求1所述的基于半导体异质结的光电存算一体器件，其特征在于，所述衬底包括高掺杂硅片，所述高掺杂硅片还作为背栅电极；和/或，所述源漏电极包括叠层金属电极，所述叠层金属电极包括相叠设的第三金属层和第四金属层，所述第三金属层材料包括Cr或Ti，所述第四金属层材料包括Au、Pt或Pd，所述第三金属层的厚度为5～15nm，所述第四金属层的厚度为30～100nm。
  6. 一种基于半导体异质结的光电存算一体器件的制备方法，其特征在于，包括：
    提供衬底；
    在所述衬底的表面上依次形成电荷阻挡层、电荷俘获层、电荷隧穿层和沟道层，以及在所述沟道层的两端上形成源漏电极；
    其中，使所述沟道层包括以一端相连并形成异质结的二维半导体层和有机半导体层，并使所述源漏电极分设于所述二维半导体层和所述有机半导体层上；
    其中，通过所述二维半导体层和所述有机半导体层形成的异质结，同时实现载流子调控和光电信号响应，以及实现能带匹配调控，并与所述电荷俘获层配合，以完成信息的原位计算与存储。
  7. 根据权利要求6所述的基于半导体异质结的光电存算一体器件的制备方法，其特征在于，形成所述电荷阻挡层、所述电荷俘获层和所述电荷隧穿层的方法，具体包括：
    采用高掺杂硅片作为衬底和背栅电极；
    在所述高掺杂硅片的表面上形成由第一金属元素、第二金属元素和氧元素形成的三元金属高k氧化物的薄膜层，作为电荷阻挡层；
    在所述电荷阻挡层的表面上形成由第二金属元素和氧元素形成的二元金属氧化物的薄膜层，作为电荷俘获层；
    在所述电荷俘获层的表面上形成由第一金属元素和氧元素形成的二元金属高k氧化物的薄膜层，作为电荷隧穿层。
  8. 根据权利要求7所述的基于半导体异质结的光电存算一体器件的制备方法，其特征在于，所述第一金属元素包括Hf，所述第二金属元素包括Al、La、Ti或Zr；其中：
    采用原子层沉积技术，在所述高掺杂硅片的表面上生长厚度为20～50nm的HfAlOx层、HfLaOx层、HfTiOx层或HfZrOx层，形成所述电荷阻挡层；
    在室温的环境下，采用物理气相沉积技术，在所述电荷阻挡层的表面上生长厚度为10～20nm的Al2O3层、La2O3层、TiO2层或ZrO2层，形成所述电荷俘获层；
    利用托盘加热型物理气相沉积技术，对所述衬底进行加热，加热温度为80～150℃，在所述电荷俘获层的表面上生长厚度为3～12nm的HfO2层，形成所述电荷隧穿层。
  9. 根据权利要求8所述的基于半导体异质结的光电存算一体器件的制备方法，其特征在于，形成所述沟道层的方法，具体包括：
    采用氧等离子体处理技术，利用氧等离子体对所述电荷隧穿层的表面进行处理，处理功率为100～200W，处理时长为20～120s；
    采用机械剥离方法，将厚度为1～10nm的MoS2层、MoSe2层或WS2层转移在所述电荷隧穿层的表面上，形成n型二维半导体层；
    采用电子束光刻作为掩膜，并采用有机蒸镀方法，在n型二维半导体层的一端上生长C8-BTBT层、DNTT层、并五苯层或P3HT层，形成通过一端连接在n型二维半导体层的一端上的厚度为20～50nm的p型有机半导体层，从而在所述电荷隧穿层的表面上形成基于有机半导体与二维半导体的pn结的沟道层。
  10. 根据权利要求6所述的基于半导体异质结的光电存算一体器件的制备方法，其特征在于，形成所述源漏电极的方法，具体包括：
    采用电子束蒸发技术，在二维半导体层和有机半导体层相背离的两端上分别形成叠层金属电极，使所述叠层金属电极包括相叠设的下层第三金属层和上层第四金属层，形成源漏电极；其中，所述第三金属层材料包括Cr或Ti，所述第四金属层材料包括Au、Pt或Pd，所述第三金属层的厚度为5～15nm，所述第四金属层的厚度为30～100nm。
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