WO2025256470A1 - 阵列基板和电子纸显示面板 - Google Patents

阵列基板和电子纸显示面板

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Publication number
WO2025256470A1
WO2025256470A1 PCT/CN2025/099463 CN2025099463W WO2025256470A1 WO 2025256470 A1 WO2025256470 A1 WO 2025256470A1 CN 2025099463 W CN2025099463 W CN 2025099463W WO 2025256470 A1 WO2025256470 A1 WO 2025256470A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal line
sub
line portion
metal layer
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/099463
Other languages
English (en)
French (fr)
Inventor
曹军红
叶利丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Publication of WO2025256470A1 publication Critical patent/WO2025256470A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1685—Operation of cells; Circuit arrangements affecting the entire cell
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/166—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect
    • G02F1/167—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field characterised by the electro-optical or magneto-optical effect by electrophoresis
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • This application relates to the field of display technology, and more particularly to an array substrate and an electronic paper display panel.
  • the purpose of this application is to provide an array substrate and an electronic paper display panel that reduces the impedance difference between two adjacent signal lines and improves the display effect of the display panel.
  • an array substrate which includes a substrate, a display area and a non-display area.
  • the array substrate also includes multiple pixel driving lines and multiple pins.
  • the multiple pixel driving lines are disposed on the substrate and located within the display area of the substrate.
  • the multiple pins are arranged at intervals on the substrate, and the pixel driving lines are connected to the pins one-to-one.
  • the array substrate also includes multiple signal lines, one end of which is connected to the pixel driving lines and the other end of which is connected to the pins.
  • a signal line includes at least a first sub-signal line portion and a second sub-signal line portion connected together.
  • the end of the first sub-signal line portion away from the second sub-signal line portion is connected to the pin.
  • the end of the second sub-signal line portion away from the first sub-signal line portion is connected to the pixel driving line.
  • the first sub-signal line portion and the second sub-signal line portion are disposed on different layers. At least a portion of the first sub-signal line portions of two adjacent signal lines are not on the same layer. At least a portion of the second sub-signal line portions of two adjacent signal lines are not on the same layer.
  • the first sub-signal line portion and the second sub-signal line portion have the same length, and two adjacent signal lines are defined as the first signal line and the second signal line.
  • the first sub-signal line portion of the first signal line and the first sub-signal line portion of the second signal line are disposed on different layers, and the second sub-signal line portion of the first signal line and the second sub-signal line portion of the second signal line are disposed on different layers.
  • the array substrate includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a pin layer.
  • the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, and the pin layer are sequentially disposed on the substrate.
  • the pixel driving line includes a scan line located in the first metal layer.
  • the pin includes a scan pin, and all scan pins are located on the pin layer.
  • the first sub-signal line portion of the first signal line is located on the first metal layer, and the second sub-signal line portion of the first signal line is located on the second metal layer; the first sub-signal line portion of the second sub-signal line is located on the second metal layer, and the second sub-signal line portion of the second sub-signal line is located on the first metal layer.
  • the first sub-signal line portion of the first signal line, at one end away from the second sub-signal line portion, is connected to the scan pin through a first via; the first sub-signal line portion and the second sub-signal line portion of the first signal line are connected through a second via; the second sub-signal line portion of the first signal line, at one end away from the first sub-signal line portion, is connected to the scan line through a third via.
  • the first sub-signal line portion of the second signal line, at one end away from the second sub-signal line portion, is connected to the scan pin through a fourth via; the first sub-signal line portion and the second sub-signal line portion of the second signal line are connected through a fifth via; the second sub-signal line portion of the second signal line, at one end away from the first sub-signal line portion, is directly connected to the scan pin;
  • the sum of the resistances of the first via, the second via, and the third via is equal to the sum of the resistances of the fourth via and the fifth via.
  • the array substrate includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a pin layer.
  • the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, and the pin layer are sequentially disposed on the substrate.
  • the pixel driving line includes a scan line located in the first metal layer.
  • the pin includes a scan pin, and all scan pins are located on the pin layer.
  • Both ends of the scan line are connected to the signal line;
  • the first sub-signal line portion of the signal line connected to the left side of the scan line is located in the first metal layer, and the second sub-signal line portion of the signal line connected to the left side of the scan line is located in the second metal layer;
  • the first sub-signal line portion of the signal line connected to the right side of the scan line is located in the second metal layer, and the second sub-signal line portion of the signal line connected to the right side of the scan line is located in the first metal layer.
  • the array substrate includes a substrate, a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer, wherein the first metal layer, the first insulating layer, the second metal layer, and the second insulating layer are sequentially disposed on the substrate, the pixel driving line includes a scan line located in the first metal layer, and the pin includes a scan pin, wherein all the scan pins are located on the first metal layer;
  • the first sub-signal line portion of the first signal line is located on the first metal layer, and the second sub-signal line portion of the first signal line is located on the second metal layer; the first sub-signal line portion of the second sub-signal line is located on the second metal layer, and the second sub-signal line portion of the second sub-signal line is located on the first metal layer.
  • the end of the first sub-signal line that is away from the second sub-signal line is connected to the scan pin, and the end of the second sub-signal line that is away from the first sub-signal line is connected to the scan line.
  • the array substrate includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a pin layer.
  • the first metal layer, the first insulating layer, the second metal layer, the second insulating layer, and the pin layer are sequentially disposed on the substrate.
  • the pixel driving line includes a data line located in the second metal layer.
  • the pin includes a data pin, and all data pins are located on the pin layer.
  • the first sub-signal line portion of the first signal line is located on the first metal layer, and the second sub-signal line portion of the first signal line is located on the second metal layer; the first sub-signal line portion of the second sub-signal line is located on the second metal layer, and the second sub-signal line portion of the second sub-signal line is located on the first metal layer.
  • the first sub-signal line portion of the first signal line, at one end away from the second sub-signal line portion, is connected to the data pin through a sixth via; the first sub-signal line portion and the second sub-signal line portion of the first signal line are connected through a seventh via; the second sub-signal line portion of the first signal line, at one end away from the first sub-signal line portion, is directly connected to the data line; the first sub-signal line portion of the second signal line, at one end away from the second sub-signal line portion, is connected to the data pin through an eighth via; the first sub-signal line portion and the second sub-signal line portion of the second signal line are connected through a ninth via; the second sub-signal line portion of the second signal line, at one end away from the first sub-signal line portion, is connected to the data line through a tenth via.
  • the sum of the resistances of the sixth and seventh vias is equal to the sum of the resistances of the eighth, ninth, and tenth vias.
  • the array substrate includes a substrate, a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer, wherein the first metal layer, the first insulating layer, the second metal layer, and the second insulating layer are sequentially disposed on the substrate, the pixel driving line includes a data line located in the second metal layer, and the pin includes a data pin located on the second metal layer.
  • the first sub-signal line portion of the first signal line is located on the first metal layer, and the second sub-signal line portion of the first signal line is located on the second metal layer; the first sub-signal line portion of the second sub-signal line is located on the second metal layer, and the second sub-signal line portion of the second sub-signal line is located on the first metal layer.
  • the end of the first sub-signal line that is away from the second sub-signal line is connected to the data pin, and the end of the second sub-signal line that is away from the first sub-signal line is connected to the data line.
  • the signal line includes an arc-shaped winding area and a straight area, wherein the signal line is straight in the straight area and arc-shaped in the arc-shaped winding area;
  • the first sub-signal line portion and the second sub-signal line portion are connected by a via, the via being located in the arc-shaped winding area.
  • the first sub-signal line portion within the arc-shaped winding area includes multiple first horizontal segments and multiple first vertical segments, wherein the two ends of each first horizontal segment are connected to two first vertical segments, and the two ends of each first vertical segment are connected to two first horizontal segments, the first horizontal segments being perpendicular to the first vertical segments;
  • the second sub-signal line portion within the arc-shaped winding area includes multiple second horizontal segments and multiple second vertical segments, wherein the two ends of the second horizontal segment are respectively connected to two second vertical segments, the two ends of the second vertical segment are respectively connected to two second horizontal segments, and the second horizontal segment and the second vertical segment are perpendicular to each other;
  • the end of the first sub-signal line portion closest to the second sub-signal line portion is the first vertical segment, and the end of the second sub-signal line portion closest to the first sub-signal line portion is the second vertical segment.
  • This application also discloses an electronic paper display panel, which includes an electronic paper film and an array substrate, wherein the electronic paper film is attached to the array substrate.
  • this application divides the signal line into a first sub-signal line section and a second sub-signal line section, which are placed on different layers. Therefore, even if the width of two adjacent signal lines varies along the two directions of wider and narrower, the first sub-signal line section and the second sub-signal line section can also vary along the two directions of wider and narrower, respectively. This makes the impedance change of each signal line more consistent, reduces the impedance difference between two adjacent signal lines, and improves the display effect of the display panel.
  • Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of this application.
  • Figure 2 is a plan view of an array substrate according to the first embodiment of this application.
  • Figure 3 is a schematic diagram of a signal line according to the first embodiment of this application.
  • Figure 4 is a cross-sectional schematic diagram of a scan line connecting a first signal line according to a first embodiment of this application;
  • Figure 5 is a cross-sectional schematic diagram of a scan line connecting a second signal line according to a first embodiment of this application;
  • Figure 6 is a cross-sectional schematic diagram of a data line connecting a first signal line according to a first embodiment of this application;
  • Figure 9 is a cross-sectional schematic diagram of a scan line connecting a first signal line according to a second embodiment of this application.
  • Figure 10 is a cross-sectional schematic diagram of a scan line connecting a second signal line according to a second embodiment of this application;
  • Figure 11 is a cross-sectional schematic diagram of a data line connecting a first signal line according to a second embodiment of this application;
  • Figure 13 is a plan view of an array substrate according to a third embodiment of this application.
  • Figure 14 is a cross-sectional schematic diagram of a scan line connected to the first signal line on the left side according to a third embodiment of this application;
  • Figure 15 is a cross-sectional schematic diagram of a second signal line connected to the left side of a scan line according to a third embodiment of this application.
  • first and second are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as “first” or “second” may explicitly or implicitly include one or more of that feature; “multiple” means two or more.
  • the term “comprising” and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.
  • connection should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
  • FIG 1 is a schematic diagram of an electronic paper display panel according to an embodiment of this application. As shown in Figure 1, this application discloses an electronic paper display panel 10, which includes an electronic paper film 20 and an array substrate 30. The electronic paper film 20 is attached to the array substrate 30.
  • a common electrode is provided on the side of the electronic paper film 20 away from the array substrate 30, and a pixel electrode is provided on the side of the array substrate 30 close to the electronic paper film 20.
  • the common electrode and the pixel electrode control the movement of electrophoretic particles in the electronic paper film 20 to display an image.
  • This application also discloses an array substrate 30, which can be used in the electronic paper display panel 10 described above.
  • this application provides the following design, which is specifically described through several embodiments:
  • Figure 2 is a plan view of an array substrate according to a first embodiment of this application
  • Figure 3 is a schematic diagram of a signal line according to a first embodiment of this application.
  • this application discloses an array substrate 30, which includes a substrate 100, a display area 110, and a non-display area 120.
  • the array substrate 30 also includes multiple pixel driving lines 260 and multiple pins 400.
  • the multiple pixel driving lines 260 are disposed on the substrate 100 and located within the display area 110 of the substrate 100.
  • the multiple pins 400 are arranged at intervals on the substrate 100, and the pixel driving lines 260 and the pins 400 are connected one-to-one.
  • the array substrate 30 also includes multiple signal lines 300, one end of each signal line 300 being connected to a pixel driving line 260, and the other end being connected to a pin 400.
  • the pins 400 can be used to bond driver chips.
  • a signal line 300 includes at least a first sub-signal line portion 310 and a second sub-signal line portion 320 connected together.
  • the end of the first sub-signal line portion 310 away from the second sub-signal line portion 320 is connected to the pin 400, and the end of the second sub-signal line portion 320 away from the first sub-signal line portion 310 is connected to the pixel driving line 260.
  • the first sub-signal line portion 310 and the second sub-signal line portion 320 are disposed on different layers. At least a portion of the first sub-signal line portion 310 of two adjacent signal lines 300 are not on the same layer, and at least a portion of the second sub-signal line portion 320 of two adjacent signal lines 300 are not on the same layer.
  • the pixel driving line 260 includes a data line 261 and/or a scan line 262.
  • the pin 400 is used to connect to the driving chip.
  • the signal line 300 connected to the data line 261 can be divided into a first sub-signal line portion 310 and a second sub-signal line portion 320; or only the signal line 300 connected to the scan line 262 can be divided into a first sub-signal line portion 310 and a second sub-signal line portion 320; or both the signal line 300 connected to the data line 261 and the signal line 300 connected to the scan line 262 can be divided into a first sub-signal line portion 310 and a second sub-signal line portion 320; or all the signal lines 300 can be divided into a first sub-signal line portion 310 and a second sub-signal line portion 320, or only a portion of the signal lines 300 can be divided into a first sub-signal line portion 310 and a second sub-signal line portion 320.
  • the distance between adjacent signal lines 300 is close.
  • incomplete etching can easily lead to short circuits between adjacent signal lines 300.
  • the presence of foreign matter or particles during fabrication can also cause short circuits. Therefore, a common approach is to place adjacent signal lines 300 on different layers to prevent short circuits.
  • two adjacent signal lines 300 may exhibit the following variations due to variations in the metal layer process: First case: the signal line 300 on the first metal layer 210 is wider than the signal line 300 on the second metal layer 230; Second case: the signal line 300 on the first metal layer 210 is narrower than the signal line 300 on the second metal layer 230; Third case: the signal line 300 on the first metal layer 210 is wider than the signal line 300 on the second metal layer 230; Fourth case: the signal line 300 on the first metal layer 210 is narrower than the signal line 300 on the second metal layer 230 is wider than the signal line 300.
  • this application divides the signal line 300 into a first sub-signal line portion 310 and a second sub-signal line portion 320.
  • the first sub-signal line portion 310 and the second sub-signal line portion 320 are arranged in different layers.
  • the first sub-signal line portion 310 and the second sub-signal line portion 320 can also vary along the two directions (wider and narrower), thereby controlling the impedance change of each signal line 300 to be more consistent, reducing the impedance difference between two adjacent signal lines 300, and improving the display effect of the display panel.
  • the first sub-signal line portion 310 and the second sub-signal line portion 320 have the same length; this ensures that the impedance difference generated between the first sub-signal line 300 and the second sub-signal line 300 can be completely canceled out. Since the length of each signal line 300 is the same, the resistance value between two adjacent signal lines 300 is the same.
  • Two adjacent signal lines 300 are defined as a first signal line 331 and a second signal line 332.
  • the first sub-signal line portion 310 of the first signal line 331 and the first sub-signal line portion 310 of the second signal line 332 are disposed on different layers, and the second sub-signal line portion 320 of the first signal line 331 and the second sub-signal line portion 320 of the second signal line 332 are disposed on different layers. This avoids the problem of short circuits between two adjacent signal lines 300.
  • the array substrate 30 includes a substrate 100, a first metal layer 210, a first insulating layer 220, a second metal layer 230, a second insulating layer 240, and a pin layer 250.
  • the first metal layer 210, the first insulating layer 220, the second metal layer 230, the second insulating layer 240, and the pin layer 250 are sequentially disposed on the substrate 100.
  • the pixel driving line 260 includes a scan line 262, which is located in the first metal layer 210.
  • the pin 400 includes a scan pin 420, which is located on the pin layer 250.
  • the first sub-signal line portion 310 of the first signal line 331 is located on the first metal layer 210, and the second sub-signal line portion 320 of the first signal line 331 is located on the second metal layer 230; the first sub-signal line portion 310 of the second sub-signal line 300 is located on the second metal layer 230, and the second sub-signal line portion 320 of the second sub-signal line 300 is located on the first metal layer 210.
  • the first sub-signal line portion 310 of the first signal line 331, away from the second sub-signal line portion 320, is connected to the scan pin 420 through a first via 501; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the first signal line 331 are connected through a second via 502; the second sub-signal line portion 320 of the first signal line 331, away from the first sub-signal line portion 310, is connected to the scan line 262 through a third via 503.
  • the first sub-signal line portion 310 of the second signal line 332, away from the second sub-signal line portion 320, is connected to the scan pin 420 through a fourth via 504; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the second signal line 332 are connected through a fifth via 505; the second sub-signal line portion 320 of the second signal line 332, away from the first sub-signal line portion 310, is directly connected to the scan pin 420.
  • the sum of the resistances of the first via 501, the second via 502, and the third via 503 is equal to the sum of the resistances of the fourth via 504 and the fifth via 505.
  • the impedance between the first signal line 331 and the second signal line 332 will be different. Therefore, by increasing the diameter of at least one of the three vias 501, 502 and 503, the resistance of the first signal line 331 can be reduced, so that the resistances of the first signal line 331 and the second signal line 332 are equal.
  • the second via 502, the third via 503, the fourth via 504, and the fifth via 505 all have the same diameter, d1, while the first via 501 has a diameter of d2, where d2 is greater than d1.
  • increasing the diameter of the first via 501 can prevent short circuits between adjacent first signal lines 331 and 332.
  • Figure 6 is a cross-sectional schematic diagram of a data line connecting a first signal line according to a first embodiment of this application
  • Figure 7 is a cross-sectional schematic diagram of a data line connecting a second signal line according to a first embodiment of this application.
  • the array substrate 30 includes a substrate 100, a first metal layer 210, a first insulating layer 220, a second metal layer 230, a second insulating layer 240, and a pin layer 250.
  • the first metal layer 210, the first insulating layer 220, the second metal layer 230, the second insulating layer 240, and the pin layer 250 are sequentially disposed on the substrate 100.
  • the pixel driving line 260 includes a data line 261, which is located in the second metal layer 230.
  • the pin 400 includes a data pin 410, which is located on the pin layer 250.
  • the first sub-signal line portion 310 of the first signal line 331 is located on the first metal layer 210, and the second sub-signal line portion 320 of the first signal line 331 is located on the second metal layer 230; the first sub-signal line portion 310 of the second sub-signal line 300 is located on the second metal layer 230, and the second sub-signal line portion 320 of the second sub-signal line 300 is located on the first metal layer 210.
  • the first sub-signal line portion 310 of the first signal line 331, away from the second sub-signal line portion 320, is connected to the data pin 410 through a sixth via 506; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the first signal line 331 are connected through a seventh via 507; the second sub-signal line portion 320 of the first signal line 331, away from the first sub-signal line portion 310, is directly connected to the data line 261.
  • the first sub-signal line portion 310 of the second signal line 332, away from the second sub-signal line portion 320, is connected to the data pin 410 through an eighth via 508; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the second signal line 332 are connected through a ninth via 509; the second sub-signal line portion 320 of the second signal line 332, away from the first sub-signal line portion 310, is connected to the data line 261 through a tenth via 510.
  • the sum of the resistances of the sixth via 506 and the seventh via 507 is equal to the sum of the resistances of the eighth via 508, the ninth via 509 and the tenth via 510.
  • the impedance between the first signal line 331 and the second signal line 332 will be different. Therefore, by increasing the diameter of at least one of the sixth via 506 and the seventh via 507, the resistance of the first signal line 331 can be reduced, so that the resistance of the first signal line 331 and the second signal line 332 are equal.
  • the seventh via 507, the eighth via 508, the ninth via 509, and the tenth via 510 all have the same diameter, d3, while the sixth via 506 has a diameter of d4, which is greater than d3.
  • increasing the diameter of the sixth via 506 can prevent short circuits between adjacent first signal lines 331 and 332.
  • Figure 8 is a plan view of an arc-shaped winding area according to the first embodiment of this application.
  • an arc-shaped winding area 341 is provided in order to ensure that the lengths of adjacent root signal lines 300 are the same. That is, the signal line 300 includes an arc-shaped winding area 341 and a straight area 342. The signal line 300 is straight in the straight area 342 and arc-shaped in the arc-shaped winding area 341.
  • the first sub-signal line portion 310 and the second sub-signal line portion 320 are connected by a via 500, which is located in the arc-shaped winding area 341.
  • the distance between the via 500 connecting the first sub-signal line portion 310 and the second sub-signal line portion 320 of the first signal line 331 and the via 500 connecting the first sub-signal line portion 310 and the second sub-signal line portion 320 of the second signal line 332 can be increased, thus avoiding the problem of short circuits caused by the via 500s of two adjacent signal lines 300 being too close together.
  • the first sub-signal line portion 310 within the arc-shaped winding area 341 includes a plurality of first horizontal segments 311 and a plurality of first vertical segments 312, with the two ends of the first horizontal segment 311 respectively connected to two first vertical segments 312, and the two ends of the first vertical segment 312 respectively connected to two first horizontal segments 311, wherein the first horizontal segment 311 is perpendicular to the first vertical segment 312.
  • the second sub-signal line portion 320 within the arc-shaped winding area 341 includes a plurality of second horizontal segments 321 and a plurality of second vertical segments 322.
  • the two ends of the second horizontal segments 321 are respectively connected to two second vertical segments 322, and the two ends of the second vertical segments 322 are respectively connected to two second horizontal segments 321.
  • the second horizontal segments 321 and the second vertical segments 322 are perpendicular.
  • the end of the first sub-signal line portion 310 near the second sub-signal line portion 320 is the first vertical segment 312, and the end of the second sub-signal line portion 320 near the first sub-signal line portion 310 is the second vertical segment 322.
  • the via 500 is located at the connection between the first vertical segment 312 and the second vertical segment 322, thereby ensuring that the via 500 connecting the first sub-signal line portion 310 and the second sub-signal line portion 320 on the first signal line 331 and the via 500 connecting the first sub-signal line portion 310 and the second sub-signal line portion 320 on the second signal line 332 are kept at a sufficiently large distance to prevent short circuits from occurring at the via 500.
  • all vias 500 of the signal line 300 connected to the data line 261 are located on the same horizontal line, and all vias 500 of the signal line 300 connected to the scan line 262 are located on the same horizontal line, so that adjacent signal lines 300 will not short-circuit due to the presence of foreign objects.
  • Figure 9 is a cross-sectional schematic diagram of a scan line connecting to a first signal line according to a second embodiment of this application
  • Figure 10 is a cross-sectional schematic diagram of a scan line connecting to a second signal line according to a second embodiment of this application.
  • the scan pin 420 is disposed on the first metal layer 210
  • the data pin 410 is disposed on the second metal layer 230.
  • the array substrate 30 includes a substrate 100, a first metal layer 210, a first insulating layer 220, a second metal layer 230, and a second insulating layer 240.
  • the first metal layer 210, the first insulating layer 220, the second metal layer 230, and the second insulating layer 240 are sequentially disposed on the substrate 100.
  • the pixel driving line 260 includes a scan line 262 located in the first metal layer 210.
  • the pin 400 includes a scan pin 420, all of which are located on the first metal layer 210.
  • the first sub-signal line portion 310 of the first signal line 331 is located on the first metal layer 210, and the second sub-signal line portion 320 of the first signal line 331 is located on the second metal layer 230; the first sub-signal line portion 310 of the second sub-signal line 300 is located on the second metal layer 230, and the second sub-signal line portion 320 of the second sub-signal line 300 is located on the first metal layer 210.
  • the end of the first sub-signal line portion 310 facing away from the second sub-signal line portion 320 is connected to the scan pin 420, and the end of the second sub-signal line portion 320 facing away from the first sub-signal line portion 310 is connected to the scan line 262.
  • the end of the first sub-signal line portion 310 of the first signal line 331 facing away from the second sub-signal line portion 320 is directly connected to the scan pin 420.
  • the scan pin 420 and the first sub-signal line portion 310 of the first signal line 331 are both located in the first metal layer 210, they can be directly connected together without needing a via 500; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the first signal line 331 are connected through an eleventh via 511; the end of the second sub-signal line portion 320 of the first signal line 331 facing away from the first sub-signal line portion 310 is connected to the scan line 262 through a twelfth via 512.
  • the end of the first sub-signal line portion 310 of the second signal line 332 that is away from the second sub-signal line portion 320 is connected to the scan pin 420 through the thirteenth via 513; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the second signal line 332 are connected through the fourteenth via 514; the end of the second sub-signal line portion 320 of the second signal line 332 that is away from the first sub-signal line portion 310 is directly connected to the scan line 262.
  • the second sub-signal line portion 320 and the scan line 262 of the second signal line 332 are both located in the first metal layer 210, they can be directly connected together without the need for via 500.
  • the diameters of the eleventh via 511, the twelfth via 512, the thirteenth via 513, and the fourteenth via 514 are all equal; the total length of the eleventh via 511 and the twelfth via 512 is equal to the total length of the thirteenth via 513 and the fourteenth via 514.
  • this embodiment by placing the scan pin 420 on the first metal layer 210, can ensure that the total length of the via 500 on the first signal line 331 connected to the scan line 262 is equal to the total length of the via 500 on the second signal line 332, thus eliminating the need to adjust the aperture of the via 500.
  • Figure 11 is a cross-sectional schematic diagram of a data line connecting a first signal line according to a second embodiment of this application
  • Figure 12 is a cross-sectional schematic diagram of a data line connecting a second signal line according to a second embodiment of this application.
  • the array substrate 30 includes a substrate 100, a first metal layer 210, a first insulating layer 220, a second metal layer 230, and a second insulating layer 240.
  • the first metal layer 210, the first insulating layer 220, the second metal layer 230, and the second insulating layer 240 are sequentially disposed on the substrate 100.
  • the pixel driving line 260 includes a data line 261, which is located in the second metal layer 230.
  • the pin 400 includes a data pin 410, which is located on the second metal layer 230.
  • the first sub-signal line portion 310 of the first signal line 331 is located on the first metal layer 210, and the second sub-signal line portion 320 of the first signal line 331 is located on the second metal layer 230; the first sub-signal line portion 310 of the second sub-signal line 300 is located on the second metal layer 230, and the second sub-signal line portion 320 of the second sub-signal line 300 is located on the first metal layer 210.
  • One end of the first sub-signal line portion 310 away from the second sub-signal line portion 320 is connected to the data pin 410, and the other end of the second sub-signal line portion 320 away from the first sub-signal line portion 310 is connected to the data line 261.
  • the end of the first sub-signal line portion 310 of the first signal line 331 away from the second sub-signal line portion 320 is connected to the data pin 410 through a fifteenth via 515; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the first signal line 331 are connected through a sixteenth via 516; and the end of the second sub-signal line portion 320 of the first signal line 331 away from the first sub-signal line portion 310 is directly connected to the data line 261.
  • the first sub-signal line portion 310 of the second signal line 332, away from the second sub-signal line portion 320, is directly connected to the data pin 410; the first sub-signal line portion 310 and the second sub-signal line portion 320 of the second signal line 332 are connected through the seventeenth via 517; the second sub-signal line portion 320 of the second signal line 332, away from the first sub-signal line portion 310, is connected to the data line 261 through the eighteenth via 518.
  • the diameters of the fifteenth through hole 515, the sixteenth through hole 516, the seventeenth through hole 517, and the eighteenth through hole 518 are all equal; the total length of the fifteenth through hole 515 and the sixteenth through hole 516 is equal to the total length of the seventeenth through hole 517 and the eighteenth through hole 518.
  • this embodiment by placing the data pin 410 on the second metal layer 230, can ensure that the total length of the via 500 on the first signal line 331 connected to the data line 261 is equal to the total length of the via 500 on the second signal line 332. Therefore, it is not necessary to adjust the aperture of the via 500, which means that the resistance values of the first signal line 331 and the second signal line 332 are the same.
  • Figure 13 is a plan view of an array substrate according to the third embodiment of this application.
  • Figure 14 is a cross-sectional view of a scan line connected to a first signal line on the left side according to the third embodiment of this application.
  • Figure 15 is a cross-sectional view of a scan line connected to a second signal line on the left side according to the third embodiment of this application.
  • the driving type of this embodiment is bilateral driving, that is, signal lines 300 are connected to both sides of the scan line 262.
  • the array substrate 30 includes a substrate 100, a first metal layer 210, a first insulating layer 220, a second metal layer 230, a second insulating layer 240, and a pin layer 250.
  • the first metal layer 210, the first insulating layer 220, the second metal layer 230, the second insulating layer 240, and the pin layer 250 are sequentially disposed on the substrate 100.
  • the pixel driving line 260 includes a scan line 262, which is located in the first metal layer 210.
  • the pin 400 includes a scan pin 420, which is located on the pin layer 250.
  • Both ends of the scan line 262 are connected to the signal line 300;
  • the first sub-signal line portion 310 of the signal line 300 connected to the left side of the scan line 262 is located in the first metal layer 210
  • the second sub-signal line portion 320 of the signal line 300 connected to the left side of the scan line 262 is located in the second metal layer 230.
  • the first sub-signal line portion 310 of the signal line 300 connected to the right side of the scan line 262 is located in the second metal layer 230
  • the second sub-signal line portion 320 of the signal line 300 connected to the right side of the scan line 262 is located in the first metal layer 210.
  • one of the two adjacent scan lines 262 has a first signal line 331 connected to its left and a second signal line 332 connected to its right
  • the other scan line has a second signal line 332 connected to its left and a first signal line 331 connected to its right. This ensures that the total resistance of the signal lines 300 connected to the left and right sides of each of the two adjacent scan lines 262 is the same.
  • this embodiment does not require adjusting the aperture size to ensure that the total resistance of the signal lines 300 connected to the left and right sides of each of the two adjacent scan lines 262 is the same; compared to the second embodiment, this embodiment does not require placing the scan pin 420 on the first metal layer 210 to ensure that the total resistance of the signal lines 300 connected to the left and right sides of each of the two adjacent scan lines 262 is the same.
  • TN Transmission Nematic
  • IPS In-Plane Switching
  • VA Vertical Alignment
  • MVA Multi-Domain Vertical Alignment
  • OLED Organic Light-Emitting Diode

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Abstract

本申请公开了一种阵列基板(30)和电子纸显示面板(10)，主要涉及显示技术领域，多条像素驱动线(260)设置在衬底(100)上，且位于衬底(100)的显示区域(110)内，多个引脚(400)间隔排列设置在衬底(100)上，且像素驱动线(260)与引脚(400)一一对应连接，一条信号线(300)包括至少连接的第一子信号线部(310)和第二子信号线部(320)，第一子信号线部(310)背离第二子信号线部(320)的一端与引脚(400)连接，第二子信号线部(320)背离第一子信号线部(310)的一端与像素驱动线(260)连接，且第一子信号线部(310)和第二子信号线部(320)不同层设置，相邻的两根信号线(300)的第一子信号线部(310)至少存在部分不在同一层上，相邻的两根信号线(300)的第二子信号线部(320)至少存在部分不在同一层上。通过上述设计，减小相邻的两根信号线(300)之间的阻抗差异，提高显示面板的显示效果。

Description

阵列基板和电子纸显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板和电子纸显示面板。
背景技术
由于阵列基板的制备工艺中，表面出现异物和颗粒是一种很常见的问题，如果清洁不到位，就会导致阵列基板上相邻的信号线发生短路的情况，而发生显示异常问题。
通常采用将相邻的两根信号线设置在不同层的方案来防止相邻的两根信号线发生短路的情况，但是将相邻的两根信号线设置在不同层的方案会导致两根信号线之间的阻抗差异过大，出现阻值跳变的问题，而影响显示面板的显示效果。
发明内容
本申请的目的是提供一种阵列基板和电子纸显示面板，减小相邻的两根信号线之间的阻抗差异，提高显示面板的显示效果。
本申请公开了一种阵列基板，所述阵列基板包括衬底，所述衬底包括显示区域和非显示区域，所述阵列基板还包括多条像素驱动线和多个引脚，多条像素驱动线设置在所述衬底上，且位于所述衬底的所述显示区域内，多个所述引脚间隔排列设置在所述衬底上，且所述像素驱动线与所述引脚一一对应连接，所述阵列基板还包括多条信号线，多条所述信号线的一端分别与所述像素驱动线连接，另一端分别与所述引脚连接；
一条所述信号线包括至少连接的第一子信号线部和第二子信号线部，所述第一子信号线部背离所述第二子信号线部的一端与所述引脚连接，所述第二子信号线部背离所述第一子信号线部的一端与所述像素驱动线连接，且所述第一子信号线部和所述第二子信号线部不同层设置，相邻的两根所述信号线的所述第一子信号线部至少存在部分不在同一层上，相邻的两根所述信号线的所述第二子信号线部至少存在部分不在同一层上。
可选的，所述第一子信号线部和所述第二子信号线部的长度相同，相邻的两根所述信号线定义为第一信号线和第二信号线，所述第一信号线的第一子信号线部和所述第二信号线的第一子信号线部不同层设置，所述第一信号线的第二子信号线部和所述第二信号线的第二子信号线部不同层设置。
可选的，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层、第二绝缘层和引脚层，所述第一金属层、所述第一绝缘层、所述第二金属层、所述第二绝缘层和所述引脚层依次设置在所述衬底上，所述像素驱动线包括扫描线，所述扫描线位于所述第一金属层中，所述引脚包括扫描引脚，所述扫描引脚均位于所述引脚层上；
所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
所述第一信号线的所述第一子信号线部背离所述第二子信号线部的一端通过第一过孔与所述扫描引脚连接；所述第一信号线的所述第一子信号线部与所述第二子信号线部通过第二过孔连接；所述第一信号线的所述第二子信号线部背离所述第一子信号线部的一端通过第三过孔与所述扫描线连接；
所述第二信号线的所述第一子信号线部背离所述第二子信号线部的一端通过第四过孔与所述扫描引脚连接；所述第二信号线的所述第一子信号线部与所述第二子信号线部通过第五过孔连接；所述第二信号线的所述第二子信号线部背离所述第一子信号线部的一端与所述扫描引脚直接连接；
所述第一过孔、所述第二过孔和所述第三过孔的电阻之和等于所述第四过孔和所述第五过孔的电阻之和。
可选的，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层、第二绝缘层和引脚层，所述第一金属层、所述第一绝缘层、所述第二金属层、所述第二绝缘层和所述引脚层依次设置在所述衬底上，所述像素驱动线包括扫描线，所述扫描线位于所述第一金属层中，所述引脚包括扫描引脚，所述扫描引脚均位于所述引脚层上；
所述扫描线的两端均连接有所述信号线；
所述扫描线左侧连接的所述信号线的第一子信号线部位于第一金属层，所述扫描线左侧连接的所述信号线的第二子信号线部位于第二金属层；
所述扫描线右侧连接的所述信号线的第一子信号线部位于第二金属层，所述扫描线右侧连接的所述信号线的第二子信号线部位于第一金属层。
可选的，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层和第二绝缘层，所述第一金属层、所述第一绝缘层、所述第二金属层和所述第二绝缘层依次设置在所述衬底上，所述像素驱动线包括扫描线，所述扫描线位于所述第一金属层中，所述引脚包括扫描引脚，所述扫描引脚均位于所述第一金属层上；
所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
所述第一子信号线部背离所述第二子信号线部的一端与所述扫描引脚连接，所述第二子信号线部背离所述第一子信号线部的一端与所述扫描线连接。
可选的，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层、第二绝缘层和引脚层，所述第一金属层、所述第一绝缘层、所述第二金属层、所述第二绝缘层和所述引脚层依次设置在所述衬底上，所述像素驱动线包括数据线，所述数据线位于所述第二金属层中，所述引脚包括数据引脚，所述数据引脚均位于所述引脚层上；
所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
所述第一信号线的第一子信号线部背离所述第二子信号线部的一端通过第六过孔与所述数据引脚连接；所述第一信号线的第一子信号线部与所述第二子信号线部通过第七过孔连接；所述第一信号线的第二子信号线部远离所述第一子信号线部的一端与所述数据线直接连接；所述第二信号线的第一子信号线部背离所述第二子信号线部的一端通过第八过孔与所述数据引脚连接；所述第二信号线的第一子信号线部与所述第二子信号线部通过第九过孔连接；所述第二信号线的所述第二子信号线部背离所述第一子信号线部的一端通过第十过孔与所述数据线连接；
所述第六过孔和所述第七过孔的电阻之和等于所述第八过孔、所述第九过孔和所述第十过孔的电阻之和。
可选的，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层和第二绝缘层，所述第一金属层、所述第一绝缘层、所述第二金属层和所述第二绝缘层依次设置在所述衬底上，所述像素驱动线包括数据线，所述数据线位于所述第二金属层中，所述引脚包括数据引脚，所述数据引脚均位于所述第二金属层上；
所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
所述第一子信号线部背离所述第二子信号线部的一端与所述数据引脚连接，所述第二子信号线部背离所述第一子信号线部的一端与所述数据线连接。
可选的，所述信号线包括弓形绕线区和直线区，在所述直线区内所述信号线呈直线，在所述弓形绕线区内所述信号线呈弓字形；
所述第一子信号线部和所述第二子信号线部通过过孔连接，所述过孔位于所述弓形绕线区。可选的，所述弓形绕线区内的所述第一子信号线部包括多个第一水平段和多个第一竖直段，且所述第一水平段的两端分别与两个第一竖直段连接，所述第一竖直段的两端分别与两个所述第一水平段连接，所述第一水平段与所述第一竖直段垂直；
所述弓形绕线区内的所述第二子信号线部包括多个第二水平段和多个第二竖直段，且所述第二水平段的两端分别与两个第二竖直段连接，所述第二竖直段的两端分别与两个所述第二水平段连接，所述第二水平段和所述第二竖直段垂直；
所述第一子信号线部靠近所述第二子信号线部的一端为所述第一竖直段，所述第二子信号线部靠近所述第一子信号线部的一端为所述第二竖直段。
本申请还公开了一种电子纸显示面板，所述电子纸显示面板包括电子纸膜片和阵列基板，所述电子纸膜片贴附在所述阵列基板上。
相对于将相邻的两根信号线设置在不同层的方案来说，本申请通过将信号线分成第一子信号线部和第二子信号线部，所述第一子信号线部和所述第二子信号线部不同层设置，故，哪怕在相邻的两根信号线的宽度分别沿着偏宽和偏窄的两个方向变化时，所述第一子信号线部和所述第二子信号线部也可以分别沿着偏宽和偏窄的两个方向变化，从而控制每根信号线的阻抗变化更加一致，而减小相邻的两根信号线之间的阻抗差异，提高显示面板的显示效果。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种电子纸显示面板的示意图；
图2是本申请的第一实施例的一种阵列基板的平面示意图；
图3是本申请的第一实施例的一种信号线的示意图；
图4是本申请的第一实施例的一种扫描线连接第一信号线的截面示意图；
图5是本申请的第一实施例的一种扫描线连接第二信号线的截面示意图；
图6是本申请的第一实施例的一种数据线连接第一信号线的截面示意图；
图7是本申请的第一实施例的一种数据线连接第二信号线的截面示意图；
图8是本申请的第一实施例的一种弓形绕线区的平面示意图；
图9是本申请的第二实施例的一种扫描线连接第一信号线的截面示意图；
图10是本申请的第二实施例的一种扫描线连接第二信号线的截面示意图；
图11是本申请的第二实施例的一种数据线连接第一信号线的截面示意图；
图12是本申请的第二实施例的一种数据线连接第二信号线的截面示意图；
图13是本申请的第三实施例的一种阵列基板的平面示意图；
图14是本申请的第三实施例的一种扫描线左边连接第一信号线的截面示意图；
图15是本申请的第三实施例的一种扫描线左边连接第二信号线的截面示意图。
其中，10、电子纸显示面板；20、电子纸膜片；30、阵列基板；100、衬底；110、显示区域；120、非显示区域；210、第一金属层；220、第一绝缘层；230、第二金属层；240、第二绝缘层；250、引脚层；260、像素驱动线；261、数据线；262、扫描线；300、信号线；310、第一子信号线部；311、第一水平段；312、第一竖直段；320、第二子信号线部；321、第二水平段；322、第二竖直段；331、第一信号线；332、第二信号线；341、弓形绕线区；342、直线区；400、引脚；410、数据引脚；420、扫描引脚；500、过孔；501、第一过孔；502、第二过孔；503、第三过孔；504、第四过孔；505、第五过孔；506、第六过孔；507、第七过孔；508、第八过孔；509、第九过孔；510、第十过孔；511、第十一过孔；512、第十二过孔；513、第十三过孔；514、第十四过孔；515、第十五过孔；516、第十六过孔；517、第十七过孔；518、第十八过孔。
具体实施方式
需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作详细说明。
图1是本申请的一实施例的一种电子纸显示面板的示意图，如图1所示，本申请公开了一种电子纸显示面板10，所述电子纸显示面板10包括电子纸膜片20和阵列基板30，所述电子纸膜片20贴附在所述阵列基板30上。
所述电子纸膜片20背离所述阵列基板30的一侧设置有公共电极，所述阵列基板30靠近所述电子纸膜片20的一侧设置有像素电极，所述公共电极与所述像素电极控制所述电子纸膜片20内的电泳粒子运动，以显示画面。
本申请还公开了一种阵列基板30，所述阵列基板30可用于上述所述的电子纸显示面板10中，针对所述阵列基板30，本申请提供了如下设计，并具体通过几个实施例进行介绍：
实施例1：
图2是本申请的第一实施例的一种阵列基板的平面示意图，图3是本申请的第一实施例的一种信号线的示意图，如图2-3所示，本申请公开了一种阵列基板30，所述阵列基板30包括衬底100，所述衬底100包括显示区域110和非显示区域120，所述阵列基板30还包括多条像素驱动线260和多个引脚400，多条像素驱动线260设置在所述衬底100上，且位于所述衬底100的所述显示区域110内，多个所述引脚400间隔排列设置在所述衬底100上，且所述像素驱动线260与所述引脚400一一对应连接，所述阵列基板30还包括多条信号线300，多条所述信号线300的一端分别与所述像素驱动线260连接，另一端分别与所述引脚400连接。所述引脚400可以用于绑定驱动芯片。
一条所述信号线300包括至少连接的第一子信号线部310和第二子信号线部320，所述第一子信号线部310背离所述第二子信号线部320的一端与所述引脚400连接，所述第二子信号线部320背离所述第一子信号线部310的一端与所述像素驱动线260连接，且所述第一子信号线部310和所述第二子信号线部320不同层设置，相邻的两根所述信号线300的所述第一子信号线部310至少存在部分不在同一层上，相邻的两根所述信号线300的所述第二子信号线部320至少存在部分不在同一层上。
其中，所述像素驱动线260包括数据线261和/或所述扫描线262，所述引脚400用于与驱动芯片连接，可以仅将与数据线261连接的信号线300分成第一子信号线部310和第二子信号线部320；也可以仅将与扫描线262连接的信号线300分成第一子信号线部310和第二子信号线部320；当然还可以同时将与数据线261连接的信号线300和与扫描线262连接的信号线300分成第一子信号线部310和第二子信号线部320；并且可以是全部的信号线300分成第一子信号线部310和第二子信号线部320，也可以是仅对部分的信号线300分成第一子信号线部310和第二子信号线部320。
在现有的阵列基板30中，由于非显示区域120的面积小，因此在设置信号线300的时候，相邻的两根信号线300之间的距离近，在制备过程中容易出现刻蚀不干净导致相邻的两根信号线300出现导通短路，或者是在制备过程中出现异物或颗粒时也会导致相邻的两根信号线300发生导通短路的问题。因此通常采用将相邻的两根信号线300设置在不同层的方案来防止相邻的两根信号线300发生短路的情况。
但是在阵列基板30的制备过程中，由于信号线300的制程波动会导致不同层信号线300出现宽度的差异，示例性的，两根相邻的信号线300，第一根设置在第一金属层210、第二根设置在第二金属层230，由于金属层制程的波动，则可能会出现：第一种情况：第一金属层210上的信号线300的宽度偏宽，第二金属层230上的信号线300的宽度也偏宽；第二种情况：第一金属层210上的信号线300的宽度偏窄，第二金属层230上的信号线300的宽度也偏窄；第三种情况：第一金属层210上的信号线300的宽度偏宽，第二金属层230上的信号线300的宽度偏窄；第四种情况：第一金属层210上的信号线300的宽度偏窄，第二金属层230上的信号线300的宽度偏宽。
当出现第三种情况或者是第四种情况的时候，则会导致相邻的两根信号线300出现阻抗差异的问题，而导致电子纸显示面板10显示的时候出现横纹不良的显示异常问题。
因此，本申请通过将信号线300分成第一子信号线部310和第二子信号线部320，所述第一子信号线部310和所述第二子信号线部320不同层设置，故，哪怕在相邻的两根信号线300的宽度分别沿着偏宽和偏窄的两个方向变化时，所述第一子信号线部310和所述第二子信号线部320也可以分别沿着偏宽和偏窄的两个方向变化，从而控制每根信号线300的阻抗变化更加一致，而减小相邻的两根信号线300之间的阻抗差异，提高显示面板的显示效果。所述第一子信号线部310和所述第二子信号线部320的长度相同；从而保证第一子信号线300和第二子信号线300之间产生的阻抗差异可以完全抵消，由于每根信号线300的长度是相同，使得相邻的两根信号线300之间的阻值相同。
相邻的两根所述信号线300定义为第一信号线331和第二信号线332，所述第一信号线331的第一子信号线部310和所述第二信号线332的第一子信号线部310不同层设置，所述第一信号线331的第二子信号线部320和所述第二信号线332的第二子信号线部320不同层设置。可以避免相邻的两根信号线300发生短路的问题。
图4是本申请的第一实施例的一种扫描线连接第一信号线的截面示意图，图5是本申请的第一实施例的一种扫描线连接第二信号线的截面示意图，如图4-5所示，所述阵列基板30包括衬底100、第一金属层210、第一绝缘层220、第二金属层230、第二绝缘层240和引脚层250，所述第一金属层210、所述第一绝缘层220、所述第二金属层230、所述第二绝缘层240和所述引脚层250依次设置在所述衬底100上，所述像素驱动线260包括扫描线262，所述扫描线262位于所述第一金属层210中，所述引脚400包括扫描引脚420，所述扫描引脚420均位于所述引脚层250上。
所述第一信号线331的第一子信号线部310位于所述第一金属层210上，所述第一信号线331的第二子信号线部320位于所述第二金属层230上；所述第二子信号线300的所述第一子信号线部310位于第二金属层230上，所述第二子信号线300的所述第二子信号线部320位于第一金属层210上。
所述第一信号线331的所述第一子信号线部310背离所述第二子信号线部320的一端通过第一过孔501与所述扫描引脚420连接；所述第一信号线331的所述第一子信号线部310与所述第二子信号线部320通过第二过孔502连接；所述第一信号线331的所述第二子信号线部320背离所述第一子信号线部310的一端通过第三过孔503与所述扫描线262连接。所述第二信号线332的所述第一子信号线部310背离所述第二子信号线部320的一端通过第四过孔504与所述扫描引脚420连接；所述第二信号线332的所述第一子信号线部310与所述第二子信号线部320通过第五过孔505连接；所述第二信号线332的所述第二子信号线部320背离所述第一子信号线部310的一端与所述扫描引脚420直接连接。
所述第一过孔501、所述第二过孔502和所述第三过孔503的电阻之和等于所述第四过孔504和所述第五过孔505的电阻之和。
简单来说，由于第一信号线331内全部的过孔500总长度和第二信号线332内的全部的过孔500总长度不同，会导致第一信号线331和第二信号线332之间的阻抗不同，因此可以通过增大第一过孔501、所述第二过孔502和所述第三过孔503三者的至少一个孔径，降低第一信号线331的阻值，使得第一信号线331和第二信号线332的阻值相等。
示例性的包括，所述第二过孔502、所述第三过孔503、所述第四过孔504和所述第五过孔505的孔径相同均为d1，所述第一过孔501的孔径为d2，d2大于d1。相对于增加所述第二过孔502和所述第三过孔503的孔径的方式，增加第一过孔501的孔径，可以避免相邻的第一信号线331和第二信号线332发生导通短路的问题。
图6是本申请的第一实施例的一种数据线连接第一信号线的截面示意图，图7是本申请的第一实施例的一种数据线连接第二信号线的截面示意图，如图6-7所示，所述阵列基板30包括衬底100、第一金属层210、第一绝缘层220、第二金属层230、第二绝缘层240和引脚层250，所述第一金属层210、所述第一绝缘层220、所述第二金属层230、所述第二绝缘层240和所述引脚层250依次设置在所述衬底100上，所述像素驱动线260包括数据线261，所述数据线261位于所述第二金属层230中，所述引脚400包括数据引脚410，所述数据引脚410均位于所述引脚层250上。
所述第一信号线331的第一子信号线部310位于所述第一金属层210上，所述第一信号线331的第二子信号线部320位于所述第二金属层230上；所述第二子信号线300的所述第一子信号线部310位于第二金属层230上，所述第二子信号线300的所述第二子信号线部320位于第一金属层210上。
所述第一信号线331的第一子信号线部310背离所述第二子信号线部320的一端通过第六过孔506与所述数据引脚410连接；所述第一信号线331的第一子信号线部310与所述第二子信号线部320通过第七过孔507连接；所述第一信号线331的第二子信号线部320远离所述第一子信号线部310的一端与所述数据线261直接连接。
所述第二信号线332的第一子信号线部310背离所述第二子信号线部320的一端通过第八过孔508与所述数据引脚410连接；所述第二信号线332的第一子信号线部310与所述第二子信号线部320通过第九过孔509连接；所述第二信号线332的所述第二子信号线部320背离所述第一子信号线部310的一端通过第十过孔510与所述数据线261连接。
所述第六过孔506和所述第七过孔507的电阻之和等于所述第八过孔508、所述第九过孔509和所述第十过孔510的电阻之和。
简单来说，由于第一信号线331内全部的过孔500总长度和第二信号线332内的全部的过孔500总长度不同，会导致第一信号线331和第二信号线332之间的阻抗不同，因此可以通过增大第六过孔506和所述第七过孔507两者的至少一个孔径，降低第一信号线331的阻值，使得第一信号线331和第二信号线332的阻值相等。
示例性的包括，所述第七过孔507、所述第八过孔508、所述第九过孔509和所述第十过孔510的孔径相同均为d3，所述第六过孔506的孔径为d4，d4大于d3。相对于增加所述第七过孔507的方式来说，增加第六过孔506的孔径，可以避免相邻的第一信号线331和第二信号线332发生导通短路的问题。
图8是本申请的第一实施例的一种弓形绕线区的平面示意图，如图8所示，为了保证相邻的根信号线300的长度相同，因此都会设置弓形绕线区341，即所述信号线300包括弓形绕线区341和直线区342，在所述直线区342内所述信号线300呈直线，在所述弓形绕线区341内所述信号线300呈弓字形；所述第一子信号线部310和所述第二子信号线部320通过过孔500连接，所述过孔500位于所述弓形绕线区341。
将所述第一子信号线部310和所述第二子信号线部320之间连接的所述过孔500的位置设置在所述弓形绕线区341内，可以增加第一信号线331的第一子信号线部310和所述第二子信号线部320连接的所述过孔500和第二信号线332的第一子信号线部310和所述第二子信号线部320连接的过孔500之间距离，避免在相邻两根信号线300的过孔500距离较近导致短路的问题。
而且，所述弓形绕线区341内的所述第一子信号线部310包括多个第一水平段311和多个第一竖直段312，且所述第一水平段311的两端分别与两个第一竖直段312连接，所述第一竖直段312的两端分别与两个所述第一水平段311连接，所述第一水平段311与所述第一竖直段312垂直。
所述弓形绕线区341内的所述第二子信号线部320包括多个第二水平段321和多个第二竖直段322，且所述第二水平段321的两端分别与两个第二竖直段322连接，所述第二竖直段322的两端分别与两个所述第二水平段321连接，所述第二水平段321和所述第二竖直段322垂直；第一子信号线部310靠近所述第二子信号线部320的一端为第一竖直段312，第二子信号线部320靠近所述第一子信号线部310的一端为第二竖直段322。
简单来说就是，所述过孔500设置在所述第一竖直段312和所述第二竖直段322的连接处，从而保证第一信号线331上的第一子信号线部310和所述第二子信号线部320连接的所述过孔500和第二信号线332上的第一子信号线部310和所述第二子信号线部320连接的所述过孔500保持足够远的距离，防止在过孔500处发生短路的情况。
并且与所述数据线261连接的信号线300的全部过孔500位于同一水平线上，与所述扫描线262连接的信号线300的全部过孔500位于同一水平线上，以使得相邻的信号线300之间不会因为存在异物而发生短路的情况。
实施例2：
图9是本申请的第二实施例的一种扫描线连接第一信号线的截面示意图，图10是本申请的第二实施例的一种扫描线连接第二信号线的截面示意图，如图9-10所示，与第一实施例不同的是，本实施例的扫描引脚420设置在第一金属层210上，数据引脚410设置在所述第二金属层230上，具体的：
所述阵列基板30包括衬底100、第一金属层210、第一绝缘层220、第二金属层230和第二绝缘层240，所述第一金属层210、所述第一绝缘层220、所述第二金属层230和所述第二绝缘层240依次设置在所述衬底100上，所述像素驱动线260包括扫描线262，所述扫描线262位于所述第一金属层210中，所述引脚400包括扫描引脚420，所述扫描引脚420均位于所述第一金属层210上。
所述第一信号线331的第一子信号线部310位于所述第一金属层210上，所述第一信号线331的第二子信号线部320位于所述第二金属层230上；所述第二子信号线300的所述第一子信号线部310位于第二金属层230上，所述第二子信号线300的所述第二子信号线部320位于第一金属层210上。
所述第一子信号线部310背离所述第二子信号线部320的一端与所述扫描引脚420连接，所述第二子信号线部320背离所述第一子信号线部310的一端与所述扫描线262连接。示例性的：所述第一信号线331的所述第一子信号线部310背离所述第二子信号线部320的一端与所述扫描引脚420直接连接，简单来说由于扫描引脚420和所述第一信号线331的所述第一子信号线部310均位于第一金属层210因此可以直接连接在一起，而不需要设置过孔500；所述第一信号线331的所述第一子信号线部310与所述第二子信号线部320通过第十一过孔511连接；所述第一信号线331的所述第二子信号线部320背离所述第一子信号线部310的一端通过第十二过孔512与所述扫描线262连接；
所述第二信号线332的所述第一子信号线部310的背离所述第二子信号线部320的一端通过第十三过孔513与所述扫描引脚420连接；所述第二信号线332的所述第一子信号线部310与所述第二子信号线部320通过第十四过孔514连接；所述第二信号线332的所述第二子信号线部320背离所述第一子信号线部310的一端与所述扫描线262直接连接，简单来说，由于所述第二信号线332的所述第二子信号线部320和扫描线262均位于第一金属层210，因此可以直接连接在一起，而不需要设置过孔500。
所述第十一过孔511、所述第十二过孔512、所述第十三过孔513和所述第十四过孔514的孔径均相等；所述第十一过孔511和所述第十二过孔512的总长度与所述第十三过孔513和所述第十四过孔514的总长度相等。
相对于第一实施例的方案来说，本实施例通过将所述扫描引脚420设置在所述第一金属层210上，可以保证所述扫描线262连接的第一信号线331上的过孔500总长度和第二信号线332上的过孔500总长度是相等的，从而不需要去调整过孔500的孔径。
图11是本申请的第二实施例的一种数据线连接第一信号线的截面示意图，图12是本申请的第二实施例的一种数据线连接第二信号线的截面示意图，如图11-12所示，所述阵列基板30包括衬底100、第一金属层210、第一绝缘层220、第二金属层230和第二绝缘层240，所述第一金属层210、所述第一绝缘层220、所述第二金属层230和所述第二绝缘层240依次设置在所述衬底100上，所述像素驱动线260包括数据线261，所述数据线261位于所述第二金属层230中，所述引脚400包括数据引脚410，所述数据引脚410均位于所述第二金属层230上。
所述第一信号线331的第一子信号线部310位于所述第一金属层210上，所述第一信号线331的第二子信号线部320位于所述第二金属层230上；所述第二子信号线300的所述第一子信号线部310位于第二金属层230上，所述第二子信号线300的所述第二子信号线部320位于第一金属层210上。
所述第一子信号线部310背离所述第二子信号线部320的一端与所述数据引脚410连接，所述第二子信号线部320背离所述第一子信号线部310的一端与所述数据线261连接。示例性的，所述第一信号线331的所述第一子信号线部310背离所述第二子信号线部320的一端与所述数据引脚410通过第十五过孔515连接；所述第一信号线331的所述第一子信号线部310与所述第二子信号线部320通过第十六过孔516连接；所述第一信号线331的所述第二子信号线部320背离所述第一子信号线部310的一端与所述数据线261直接连接；
所述第二信号线332的所述第一子信号线部310背离所述第二子信号线部320的一端与所述数据引脚410直接连接；所述第二信号线332的所述第一子信号线部310与所述第二子信号线部320通过第十七过孔517连接；所述第二信号线332的所述第二子信号线部320背离所述第一子信号线部310的一端通过第十八过孔518与所述数据线261连接；
所述第十五过孔515、所述第十六过孔516、所述第十七过孔517和所述第十八过孔518的孔径均相等；所述第十五过孔515和所述第十六过孔516的总长度与所述第十七过孔517和所述第十八过孔518的总长度相等。
相对于第一实施例的方案来说，本实施例通过将所述数据引脚410设置在所述第二金属层230上，可以保证所述数据线261连接的第一信号线331上的过孔500总长度和第二信号线332上的过孔500总长度是相等的，从而不需要去调整过孔500的孔径，即可以保证第一信号线331和第二信号线332的阻值相同。
实施例3：
图13是本申请的第三实施例的一种阵列基板的平面示意图，图14是本申请的第三实施例的一种扫描线左边连接第一信号线的截面示意图，图15是本申请的第三实施例的一种扫描线左边连接第二信号线的截面示意图，如图13-15所示，与第一实施例不同的是，本实施例的驱动类型为双边驱动，即在所述扫描线262的左右两边均连接有信号线300，具体的：所述阵列基板30包括衬底100、第一金属层210、第一绝缘层220、第二金属层230、第二绝缘层240和引脚层250，所述第一金属层210、所述第一绝缘层220、所述第二金属层230、所述第二绝缘层240和所述引脚层250依次设置在所述衬底100上，所述像素驱动线260包括扫描线262，所述扫描线262位于所述第一金属层210中，所述引脚400包括扫描引脚420，所述扫描引脚420均位于所述引脚层250上；
所述扫描线262的两端均连接有所述信号线300；
所述扫描线262左侧连接的所述信号线300的第一子信号线部310位于第一金属层210，所述扫描线262左侧连接的所述信号线300的第二子信号线部320位于第二金属层230；
所述扫描线262右侧连接的所述信号线300的第一子信号线部310位于第二金属层230，所述扫描线262右侧连接的所述信号线300的第二子信号线部320位于第一金属层210。简单来说，就是在相邻两根扫描线262中的其中一根扫描线262的左边连接第一信号线331和右边连接第二信号线332，另外一根描线的左边连接第二信号线332和右边连接的第一信号线331。使得相邻两条扫描线262各自连接左右两边的信号线300的总电阻是相同。相对于第一实施例的方案来说，本实施例不需要将调整孔径的大小，也可以保证相邻两条扫描线262各自的左右两边连接的信号线300的总电阻是相同；相对于第二实施例的方案来说，本实施例不需要将所述扫描引脚420设置在所述第一金属层210上，也可以保证相邻两条扫描线262各自的左右两边连接的信号线300的总电阻是相同。
当然本申请的技术方案可以广泛用于各种显示面板，如TN(Twisted Nematic，扭曲向列型)显示面板、IPS(In-Plane Switching，平面转换型)显示面板、VA(Vertical Alignment，垂直配向型)显示面板、MVA(Multi-Domain Vertical Alignment，多象限垂直配向型)显示面板，当然，也可以是其他类型的显示面板，如OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板，均可适用上述方案。
需要说明的是,本申请的发明构思可以形成非常多的实施例，但是申请文件的篇幅有限，无法一一列出，因而，在不相冲突的前提下,以上描述的各实施例之间或各技术特征之间可以任意组合形成新的实施例，各实施例或技术特征组合之后，将会增强原有的技术效果。以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (18)

  1. 一种阵列基板，所述阵列基板包括衬底，所述衬底包括显示区域和非显示区域，所述阵列基板还包括多条像素驱动线和多个引脚，多条所述像素驱动线设置在所述衬底上，且位于所述衬底的所述显示区域内，多个所述引脚间隔排列设置在所述衬底上，且所述像素驱动线与所述引脚一一对应连接，其中，所述阵列基板还包括多条信号线，多条所述信号线的一端分别与所述像素驱动线连接，另一端分别与所述引脚连接；
    一条所述信号线包括至少连接的第一子信号线部和第二子信号线部，所述第一子信号线部背离所述第二子信号线部的一端与所述引脚连接，所述第二子信号线部背离所述第一子信号线部的一端与所述像素驱动线连接，且所述第一子信号线部和所述第二子信号线部不同层设置，相邻的两根所述信号线的所述第一子信号线部至少存在部分不在同一层上，相邻的两根所述信号线的所述第二子信号线部至少存在部分不在同一层上。
  2. 根据权利要求1所述的阵列基板，其中，所述第一子信号线部和所述第二子信号线部的长度相同，相邻的两根所述信号线定义为第一信号线和第二信号线，所述第一信号线的第一子信号线部和所述第二信号线的第一子信号线部不同层设置，所述第一信号线的第二子信号线部和所述第二信号线的第二子信号线部不同层设置。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层、第二绝缘层和引脚层，所述第一金属层、所述第一绝缘层、所述第二金属层、所述第二绝缘层和所述引脚层依次设置在所述衬底上，所述像素驱动线包括扫描线，所述扫描线位于所述第一金属层中，所述引脚包括扫描引脚，所述扫描引脚均位于所述引脚层上；
    所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
    所述第一信号线的所述第一子信号线部背离所述第二子信号线部的一端通过第一过孔与所述扫描引脚连接；所述第一信号线的所述第一子信号线部与所述第二子信号线部通过第二过孔连接；所述第一信号线的所述第二子信号线部背离所述第一子信号线部的一端通过第三过孔与所述扫描线连接；
    所述第二信号线的所述第一子信号线部背离所述第二子信号线部的一端通过第四过孔与所述扫描引脚连接；所述第二信号线的所述第一子信号线部与所述第二子信号线部通过第五过孔连接；所述第二信号线的所述第二子信号线部背离所述第一子信号线部的一端与所述扫描引脚直接连接；
    所述第一过孔、所述第二过孔和所述第三过孔的电阻之和等于所述第四过孔和所述第五过孔的电阻之和。
  4. 根据权利要求3所述的阵列基板，其中，所述第二过孔、所述第三过孔、所述第四过孔和所述第五过孔的孔径相同均为d1，所述第一过孔的孔径为d2，d2大于d1。
  5. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层、第二绝缘层和引脚层，所述第一金属层、所述第一绝缘层、所述第二金属层、所述第二绝缘层和所述引脚层依次设置在所述衬底上，所述像素驱动线包括扫描线，所述扫描线位于所述第一金属层中，所述引脚包括扫描引脚，所述扫描引脚均位于所述引脚层上；
    所述扫描线的两端均连接有所述信号线；
    所述扫描线左侧连接的所述信号线的第一子信号线部位于第一金属层，所述扫描线左侧连接的所述信号线的第二子信号线部位于第二金属层；
    所述扫描线右侧连接的所述信号线的第一子信号线部位于第二金属层，所述扫描线右侧连接的所述信号线的第二子信号线部位于第一金属层。
  6. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层和第二绝缘层，所述第一金属层、所述第一绝缘层、所述第二金属层和所述第二绝缘层依次设置在所述衬底上，所述像素驱动线包括扫描线，所述扫描线位于所述第一金属层中，所述引脚包括扫描引脚，所述扫描引脚均位于所述第一金属层上；
    所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
    所述第一子信号线部背离所述第二子信号线部的一端与所述扫描引脚连接，所述第二子信号线部背离所述第一子信号线部的一端与所述扫描线连接。
  7. 根据权利要求6所述的阵列基板，其中，所述第一信号线的所述第一子信号线部与所述第二子信号线部通过第十一过孔连接；所述第一信号线的所述第二子信号线部背离所述第一子信号线部的一端通过第十二过孔与所述扫描线连接；
    所述第二信号线的所述第一子信号线部的背离所述第二子信号线部的一端通过第十三过孔与所述扫描引脚连接；所述第二信号线的所述第一子信号线部与所述第二子信号线部通过第十四过孔连接；所述第二信号线的所述第二子信号线部背离所述第一子信号线部的一端与所述扫描线直接连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第十一过孔、所述第十二过孔、所述第十三过孔和所述第十四过孔的孔径均相等；所述第十一过孔和所述第十二过孔的总长度与所述第十三过孔和所述第十四过孔的总长度相等。
  9. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层、第二绝缘层和引脚层，所述第一金属层、所述第一绝缘层、所述第二金属层、所述第二绝缘层和所述引脚层依次设置在所述衬底上，所述像素驱动线包括数据线，所述数据线位于所述第二金属层中，所述引脚包括数据引脚，所述数据引脚均位于所述引脚层上；
    所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
    所述第一信号线的第一子信号线部背离所述第二子信号线部的一端通过第六过孔与所述数据引脚连接；所述第一信号线的第一子信号线部与所述第二子信号线部通过第七过孔连接；所述第一信号线的第二子信号线部远离所述第一子信号线部的一端与所述数据线直接连接；
    所述第二信号线的第一子信号线部背离所述第二子信号线部的一端通过第八过孔与所述数据引脚连接；所述第二信号线的第一子信号线部与所述第二子信号线部通过第九过孔连接；所述第二信号线的所述第二子信号线部背离所述第一子信号线部的一端通过第十过孔与所述数据线连接；
    所述第六过孔和所述第七过孔的电阻之和等于所述第八过孔、所述第九过孔和所述第十过孔的电阻之和。
  10. 根据权利要求9所述的阵列基板，其中，所述第七过孔、所述第八过孔、所述第九过孔和所述第十过孔的孔径相同均为d3，所述第六过孔的孔径为d4，d4大于d3。
  11. 根据权利要求2所述的阵列基板，其中，所述阵列基板包括衬底、第一金属层、第一绝缘层、第二金属层和第二绝缘层，所述第一金属层、所述第一绝缘层、所述第二金属层和所述第二绝缘层依次设置在所述衬底上，所述像素驱动线包括数据线，所述数据线位于所述第二金属层中，所述引脚包括数据引脚，所述数据引脚均位于所述第二金属层上；
    所述第一信号线的第一子信号线部位于所述第一金属层上，所述第一信号线的第二子信号线部位于所述第二金属层上；所述第二子信号线的所述第一子信号线部位于第二金属层上，所述第二子信号线的所述第二子信号线部位于第一金属层上；
    所述第一子信号线部背离所述第二子信号线部的一端与所述数据引脚连接，所述第二子信号线部背离所述第一子信号线部的一端与所述数据线连接。
  12. 根据权利要求11所述的阵列基板，其中，所述第一信号线的所述第一子信号线部背离所述第二子信号线部的一端与所述数据引脚通过第十五过孔连接；所述第一信号线的所述第一子信号线部与所述第二子信号线部通过第十六过孔连接；所述第一信号线的所述第二子信号线部背离所述第一子信号线部的一端与所述数据线直接连接；
    所述第二信号线的所述第一子信号线部背离所述第二子信号线部的一端与所述数据引脚直接连接；所述第二信号线的所述第一子信号线部与所述第二子信号线部通过第十七过孔连接；所述第二信号线的所述第二子信号线部背离所述第一子信号线部的一端通过第十八过孔与所述数据线连接。
  13. 根据权利要求12所述的阵列基板，其中，所述第十五过孔、所述第十六过孔、所述第十七过孔和所述第十八过孔的孔径均相等；所述第十五过孔和所述第十六过孔的总长度与所述第十七过孔和所述第十八过孔的总长度相等。
  14. 根据权利要求2所述的阵列基板，其中，所述信号线包括弓形绕线区和直线区，在所述直线区内所述信号线呈直线，在所述弓形绕线区内所述信号线呈弓字形；
    所述第一子信号线部和所述第二子信号线部通过过孔连接，所述过孔位于所述弓形绕线区。
  15. 根据权利要求14所述的阵列基板，其中，所述弓形绕线区内的所述第一子信号线部包括多个第一水平段和多个第一竖直段，且所述第一水平段的两端分别与两个第一竖直段连接，所述第一竖直段的两端分别与两个所述第一水平段连接，所述第一水平段与所述第一竖直段垂直；
    所述弓形绕线区内的所述第二子信号线部包括多个第二水平段和多个第二竖直段，且所述第二水平段的两端分别与两个第二竖直段连接，所述第二竖直段的两端分别与两个所述第二水平段连接，所述第二水平段和所述第二竖直段垂直；
    所述第一子信号线部靠近所述第二子信号线部的一端为所述第一竖直段，所述第二子信号线部靠近所述第一子信号线部的一端为所述第二竖直段。
  16. 根据权利要求15所述的阵列基板，其中，所述像素驱动线包括数据线，与所述数据线连接的信号线的全部过孔位于同一水平线上。
  17. 根据权利要求15所述的阵列基板，其中，所述像素驱动线包括扫描线，与所述扫描线连接的信号线的全部过孔位于同一水平线上。
  18. 一种电子纸显示面板，其中，所述电子纸显示面板包括电子纸膜片和如权利要求1-17中任意一条所述的阵列基板，所述电子纸膜片贴附在所述阵列基板上。
PCT/CN2025/099463 2024-06-12 2025-06-06 阵列基板和电子纸显示面板 Pending WO2025256470A1 (zh)

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KR20140078203A (ko) * 2012-12-17 2014-06-25 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
CN208938618U (zh) * 2018-11-08 2019-06-04 信利半导体有限公司 显示驱动芯片及显示面板
CN211182209U (zh) * 2020-03-23 2020-08-04 北京京东方技术开发有限公司 一种用于oled显示装置的引线布置结构和显示装置
CN115308957A (zh) * 2022-08-15 2022-11-08 合肥京东方显示技术有限公司 显示面板和显示装置
CN118335754A (zh) * 2024-06-12 2024-07-12 惠科股份有限公司 阵列基板和电子纸显示面板

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