WO2025256166A1 - 一种芯片、芯片制造方法、存储器、接口芯片和电子设备 - Google Patents

一种芯片、芯片制造方法、存储器、接口芯片和电子设备

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Publication number
WO2025256166A1
WO2025256166A1 PCT/CN2025/076890 CN2025076890W WO2025256166A1 WO 2025256166 A1 WO2025256166 A1 WO 2025256166A1 CN 2025076890 W CN2025076890 W CN 2025076890W WO 2025256166 A1 WO2025256166 A1 WO 2025256166A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
transistor
metal
interface circuit
serial interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/076890
Other languages
English (en)
French (fr)
Inventor
柴泾睿
潘鹏飞
曾亮宇
刘海飞
郭炜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of WO2025256166A1 publication Critical patent/WO2025256166A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Definitions

  • This application relates to the field of chip technology, and more particularly to a chip, a chip manufacturing method, a memory, an interface chip, and an electronic device.
  • Memory such as dynamic random access memory, DRAM
  • I/O interface circuits input/output interface circuits. Memory can transmit data with external devices through these I/O interface circuits.
  • I/O interface circuits As memory speeds continue to increase, the structure of I/O interface circuits has become increasingly complex in order to transmit data faster, resulting in larger I/O interface circuit areas.
  • This application provides a chip, a chip manufacturing method, a memory, an interface chip, and an electronic device, which can save the area of the chip's interface circuit.
  • a chip including a serial interface circuit, the serial interface circuit including a plurality of metal pillars, the plurality of metal pillars being formed by a subsequent process.
  • the plurality of metal pillars serve as load devices for the serial interface circuit.
  • the metal pillars are formed on the metal layer through a subsequent process, and the metal pillars serve as load devices in the serial interface circuit. Therefore, the load devices can be formed on the metal layer, which saves the area of the load devices in the serial interface circuit on the substrate. Furthermore, the metal pillars have a partial structural similarity to the capacitors in the memory cells, allowing the metal pillars to be formed using the mask of the memory cells, thus saving process costs.
  • the serial interface circuit further includes multiple transistors, each of the multiple metal pillars being coupled to one of the transistors, and the multiple transistors being formed through a back-end process.
  • forming the transistors on a metal layer through a back-end process can save the area of the transistors on the substrate.
  • the metal pillars and transistors do not need to be on the same plane; the metal pillars can be positioned above the transistors, further saving the area of the transistors and metal pillars in the metal layer.
  • the structure of the metal pillars and transistors is partially the same as the structure of a memory cell, allowing the metal pillars and transistors to be formed using a mask of the memory cell, saving process costs.
  • the transistors in a memory cell act as switches, with a large number of coupled loads (such as one or more capacitors), resulting in high power consumption.
  • the transistors in the serial interface circuit when acting as amplifiers, have lower power consumption.
  • the transistors in the serial interface circuit when acting as switches, have fewer coupled loads and also lower power consumption. Therefore, compared to the memory cells of a memory, the transistors in the serial interface circuit have lower power consumption.
  • the transistor is a vertical junctionless field-effect transistor (VFET).
  • VFET vertical junctionless field-effect transistor
  • the VFET has lower power consumption and current draw, saving power consumption in the serial interface circuitry.
  • the VFET can be fabricated using back-end processes. Therefore, the VFET can be applied to current-mode logic circuits and can save area in complex current-mode logic circuits.
  • the load device includes an equivalent resistive device, with at least one of the plurality of metal pillars serving as the equivalent resistive device for the serial interface circuit.
  • using a metal pillar as the equivalent resistive device can save resistor area.
  • the load device includes an equivalent inductor, which comprises a metal transmission line. Multiple metal pillars are arranged in multiple columns, and metal pillars in different columns are connected via metal transmission lines to serve as the equivalent inductor of the serial interface circuit.
  • using metal pillars and metal transmission lines as the equivalent inductor not only saves on process costs but also saves chip circuit area.
  • setting metal pillars and metal transmission lines as loop inductors in the serial interface circuit can increase the transmission speed of the serial interface circuit. For example, the transmission speed of the serial interface circuit can be increased by 50%.
  • the serial interface circuit includes at least one of a D latch, a D flip-flop, and a multiplexer. At least one of the D latch, D flip-flop, or multiplexer includes a metal pillar. In the above possible implementations, at least one of the D latch, D flip-flop, and multiplexer in the serial interface circuit is implemented using multiple metal pillars. Even if the structure of the D latch, D flip-flop, and multiplexer is complex, chip circuit area can be saved.
  • the ratio of the number of data inputs to the number of data outputs of the multiplexer is n, where n is an integer greater than or equal to 4.
  • n is an integer greater than or equal to 4.
  • a more complex n:1 multiplexer (n greater than or equal to 4) can be used to achieve faster transmission speeds while saving area and manufacturing costs.
  • the serial interface circuit further includes a bandgap reference source, which comprises a back-end transistor formed using a back-end process.
  • the bandgap reference source is implemented using a back-end transistor. This provides the serial interface circuit with a dedicated bias voltage and voltage distribution, better maintaining the circuit's pressure-volume-temperature (PVT) and improving circuit reliability.
  • the back-end transistor can be fabricated using a mask from a memory cell, resulting in lower processing costs.
  • the serial interface circuit further includes a plurality of metal capacitor pads, at least one of which is arranged around a metal pillar.
  • the structure of the metal pillar and the metal capacitor pads is the same as the structure of the capacitors in the memory cell, and the metal pillar and metal capacitor pads can be generated using a mask of the memory cell, saving process costs.
  • a chip manufacturing method for generating a chip, the chip including a serial interface circuit.
  • the serial interface circuit includes multiple metal pillars
  • the chip manufacturing method includes a back-end process, which includes: generating multiple metal pillars on a metal layer through a first back-end mask, the multiple metal pillars serving as load devices for the serial interface circuit.
  • the serial interface circuit further includes transistors.
  • a plurality of metal pillars are formed on a metal layer using a first back-end mask, comprising: forming a plurality of transistors on the metal layer using the first back-end mask, and forming a metal pillar coupled to each of the plurality of transistors.
  • the serial interface circuit further includes a bandgap reference source, which includes a back-end transistor, and the back-end process further includes: generating the back-end transistor on a metal layer through a second back-end mask.
  • the serial interface circuit further includes a plurality of metal capacitor pads; and a plurality of metal pillars are generated on the metal layer through a first back-end mask, including: generating a plurality of metal pillars and a plurality of metal capacitor pads on the metal layer through the first back-end mask, wherein at least one of the plurality of metal capacitor pads is disposed around the metal pillar.
  • a memory including a controller and a chip provided by the first aspect or any possible implementation of the first aspect, the controller being coupled to the chip.
  • an interface chip including a processor and a chip provided in the first aspect or any possible implementation of the first aspect, the processor being coupled to the chip.
  • an electronic device comprising a circuit board and a chip provided in the first aspect or any possible implementation thereof, the chip being disposed on the circuit board.
  • any of the chip manufacturing methods, memories, interface chips, and electronic devices provided above all utilize the chips described above. Therefore, the beneficial effects they can achieve can be referenced from the beneficial effects of the corresponding chips described above, and will not be repeated here.
  • Figure 1 is a schematic diagram of the structure of a memory provided in an embodiment of this application.
  • Figure 2 is a schematic diagram of the structure of a chip provided in an embodiment of this application.
  • Figure 3 is a schematic diagram of a metal column provided in an embodiment of this application.
  • Figure 4 is a schematic diagram of the structure of a chip provided in an embodiment of this application.
  • Figure 5 is a schematic diagram of a plurality of transistors and a plurality of metal pillars provided in an embodiment of this application;
  • Figure 6 is a schematic diagram of a D latch provided in an embodiment of this application.
  • Figure 7 is a schematic diagram of a D flip-flop provided in an embodiment of this application.
  • Figure 8 is a schematic diagram of a multiplexer provided in an embodiment of this application.
  • Figure 9 is a schematic diagram of an inductor provided in an embodiment of this application.
  • Figure 10 is a schematic diagram of a D latch provided in an embodiment of this application.
  • Figure 11 is a schematic diagram of a D flip-flop provided in an embodiment of this application.
  • Figure 12 is a schematic diagram of a multiplexer provided in an embodiment of this application.
  • Figure 13 is a schematic diagram of the structure of a multiplexer provided in an embodiment of this application.
  • Figure 14 is a schematic diagram of a serial interface circuit provided in an embodiment of this application.
  • Figure 15 is a three-dimensional structural schematic diagram of a serial interface circuit provided in an embodiment of this application.
  • Figure 16 is a three-dimensional structural schematic diagram of a serial interface circuit and a bandgap reference source provided in an embodiment of this application;
  • Figure 17 is a schematic flowchart of a chip manufacturing method provided in an embodiment of this application.
  • Coupled and “connection” used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.
  • Chip manufacturing processes include front-end of line (FEOL) and back-end of line (BEOL) processes.
  • Integrated circuits on a chip are fabricated layer by layer using planar processes. For example, for logic devices, regions for transistor fabrication are first defined on a substrate. Then, ion implantation is used to create N-type and P-type regions, followed by gate generation. This is then repeated with ion implantation to create the source and drain. This part of the process flow is the front-end of line.
  • the back-end of line in contrast, involves building several layers of conductive metal lines, connected by pillar-shaped metal columns. These metal lines connect the transistors on the substrate according to design requirements to achieve specific functions.
  • Chip manufacturing processes also include masking and photolithography.
  • a mask corresponding to the chip to be processed is designed based on the designed chip circuit structure. This mask is printed with the pre-designed structural pattern of the chip circuit.
  • photoresist PR
  • ultraviolet light is used to irradiate the photoresist through a pre-designed mask.
  • the areas of photoresist irradiated by the ultraviolet light become dissolvable.
  • the dissolved photoresist exposes the wafer, and the resulting pattern matches the structural pattern on the mask.
  • the desired chip circuitry can be obtained.
  • DRAM 1000 includes a memory cell array 100 and peripheral circuitry 200.
  • Peripheral circuitry 200 may include at least an input/output (I/O) interface circuit 210, which includes a transmitting circuit 211 and a receiving circuit 212.
  • the transmitting circuit 211 includes a serializer 20, which includes a D-latch 21, a D-flip-flop 22, and a multiplexer (MUX) 23.
  • the memory cell array 100 contains multiple memory cells arranged in an array, and these memory cells are used to store data.
  • the peripheral circuit 200 is used to control the writing of data to the memory cell array 100, or to control the erasure of data from the memory cell array 100, or to read data from the memory cell array 100.
  • the peripheral circuit 200 applies a voltage to the memory cells in the memory cell array 100, thereby controlling the writing of data to the memory cells.
  • the I/O interface circuit 210 in the peripheral circuit 200 is used for data transmission with external devices (such as memory controllers or processors). For example, when the peripheral circuit 200 reads data from the memory cell array 100, the I/O interface circuit 210 sends the data from the memory cell array 100 to the external device through the transmitting circuit 211.
  • the I/O interface circuit 210 receives data from the external device through the receiving circuit 212, and the peripheral circuit 200 writes the data from the external device into the memory cell array 100.
  • the transmitting circuit 211 needs to serialize the parallel data in order to output a high-speed data signal.
  • Serialization can refer to converting m parallel data streams into n serial data streams, where n is less than m.
  • the transmission speed of serial data is greater than that of parallel data; therefore, serial data can also be called high-speed data.
  • Serializer 20 is used to perform data serialization.
  • serializer 20 is used to input multiple parallel data streams, output one serial data stream, and send the serial data to the output port with the largest possible signal bandwidth.
  • the transmission speed of serializer 20 is a key aspect of the design of IO interface circuit 210.
  • CML circuits As memory speeds continue to increase, traditional complementary metal-oxide-semiconductor (CMOS) logic I/O interface circuits are gradually becoming insufficient to meet the demands of high-speed DRAM interfaces. In contrast, the use of current-mode logic (CML) circuits as I/O interface circuits is beginning to show its advantages. At higher signal rates, CML circuits offer lower power consumption and a higher signal-to-noise ratio. Furthermore, CML circuits possess characteristics that low-voltage differential signaling (LVDS) circuits lack. For example, CML circuits can modify load characteristics to improve high-frequency performance; that is, CML circuits can use active loads to extend bandwidth and achieve equalization.
  • LVDS low-voltage differential signaling
  • CML circuits As I/O interface circuits, the structure of CML circuits is becoming increasingly complex to achieve faster data transmission, resulting in larger CML circuit areas. Additionally, CML circuits suffer from high power consumption and non-dedicated bias voltages. Therefore, designing CML circuits has become a significant challenge.
  • This application provides a chip whose I/O interface circuit can be a serial interface circuit.
  • the structure and function of the serial interface circuit can refer to the I/O interface circuit described above.
  • the serial interface circuit is used for data transmission with external devices connected to the chip.
  • the components of the serial interface circuit can be fabricated into a three-dimensional structure using post-processing, thereby saving chip area.
  • chip 300 includes a serial interface circuit 310.
  • the serial interface circuit 310 includes a plurality of metal pillars 31, which are formed by subsequent processes.
  • the plurality of metal pillars 31 serve as load devices for the serial interface circuit 310.
  • the metal pillar 31 has a partial structure identical to that of the capacitor in a memory cell.
  • Multiple metal pillars 31 can be arranged in an array and formed on a metal layer. Therefore, the metal pillars 31 can be formed using a partial mask for fabricating the memory cell of a memory chip.
  • a DRAM memory cell includes a transistor and at least one capacitor.
  • the capacitor structure includes a metal pillar and at least one metal capacitor plate surrounding the metal pillar.
  • the metal pillar of the DRAM memory cell serves as the first plate of at least one capacitor, and each metal capacitor plate of the DRAM memory cell serves as the second plate of each capacitor.
  • the structure of the metal pillar 31 can be identical to the metal pillar structure in the memory cell.
  • the metal pillar 31 can serve as a load device in a serial interface circuit 310.
  • the serial interface circuit 310 also includes a metal transmission line, through which the metal pillar 31 is connected to other devices in the serial interface circuit 310, so that the metal pillar 31 is connected to the serial interface circuit 310 as a load device.
  • the metal pillar 31 can also serve as a load device together with the metal transmission line.
  • multiple metal pillars 31 are connected by a metal transmission line so that the connected multiple metal pillars 31 and the metal transmission line as a whole serve as a load device in the serial interface circuit 310.
  • the metal capacitor plates surrounding the metal pillars of the DRAM memory cell are implemented using pads.
  • the metal pillars of the serial interface circuit can be fabricated using a mask of the capacitor of the DRAM memory cell.
  • the serial interface circuit further includes a plurality of metal capacitor pads 32, at least one of which is disposed around the metal pillar 31.
  • the structure of the metal capacitor pads 32 surrounding the metal pillar 31 is the same as the capacitor structure of the memory cell.
  • at least one metal capacitor pad 32 may not be used as a component in the serial interface circuit 310.
  • the metal capacitor plates surrounding the metal pillars of the DRAM memory cells are implemented using antipads.
  • the anti-pad has multiple holes, with each metal pillar located inside one hole. A gap exists between the metal pillar and the edge of the hole in the anti-pad; the metal pillar and the edge of the hole in the anti-pad respectively serve as the two plates of a capacitor, forming a capacitor together.
  • the metal pillars of the serial interface circuit can be fabricated using a mask of the capacitor of the DRAM-to-memory cell. In this case, the serial interface circuit may only include metal pillars 31, excluding the anti-pad. Alternatively, the serial interface circuit may include both metal pillars 31 and the anti-pad. Optionally, the anti-pad may not be used as a component in the serial interface circuit 310.
  • the metal pillar 31 is formed on the metal layer through a back-end process, and the metal pillar 31 serves as a load device in the serial interface circuit 310. Therefore, the load device can be formed on the metal layer, which saves the area of the load device on the substrate. Furthermore, the metal pillar 31 has a partial structure similar to the capacitor of the memory cell in the memory, and the metal pillar 31 can be formed using the mask of the memory cell, saving process costs.
  • the serial interface circuit 310 includes not only a metal pillar structure but also a transistor structure.
  • the serial interface circuit 310 also includes transistors 33, with each metal pillar 31 coupled to one transistor 33.
  • a coupled metal pillar 31 and a transistor 33 can form a back-end string structure, which is identical to a portion of the structure of a memory cell (such as the metal pillar and transistor of a capacitor) in a memory.
  • Multiple back-end string structures can be arranged in an array and generated on a metal layer. Therefore, a mask for fabricating memory cells in a memory chip can be used to generate the back-end string structure.
  • Multiple back-end string structures can be fabricated to facilitate circuit fabrication. When forming a serial interface circuit using these back-end string structures, some metal pillars or transistors of the back-end string structures may not be connected to the serial interface circuit, while other metal pillars and transistors of the back-end string structures may be connected to the serial interface circuit.
  • only the metal pillar 31 of a back-end string structure can be used as a resistor in the serial interface circuit 310, without using the transistor 33 of the back-end string structure as a device in the serial interface circuit 310.
  • both ends of the metal pillar 31 of a back-end string structure are connected to the circuit. Since the metal pillar 31 of the back-end string structure is coupled to the transistor 33, the end of the transistor 33 coupled to the metal pillar 31 is also connected to the circuit. However, the other two ends of transistor 33 are not connected to the circuit, and transistor 33 is not used as a device in serial interface circuit 310.
  • only one back-end string structure transistor 33 can be used as a transistor in serial interface circuit 310, without using the back-end string structure metal pillar 31 as a device in serial interface circuit 310.
  • a back-end string structure transistor 33 is electrically connected to other devices in serial interface circuit 310. Since the back-end string structure metal pillar 31 is coupled to transistor 33, one end of the metal pillar 31 coupled to transistor 33 is also connected to the circuit. However, the other end of the metal pillar 31 is not connected to the circuit, and metal pillar 31 is not used as a device in serial interface circuit 310.
  • a back-end string structure metal pillar 31 and transistor 33 can be used as a coupled resistor and transistor structure in serial interface circuit 310.
  • a metal layer 41 is located above the substrate 42, on which multiple rows and columns of transistors 33 are formed.
  • Each transistor 33 is coupled to a metal pillar 31, and each metal pillar 31 is surrounded by at least one metal capacitor pad 32.
  • FIG5 only shows 3 rows and 2 columns of transistors 33, but the transistors 33 may have more or fewer rows and more or fewer columns.
  • transistor 33 is fabricated on metal layer 41 using a back-end process, which saves area of transistors on substrate 42. Furthermore, metal pillar 31 and transistor 33 do not need to be on the same plane; metal pillar 31 can be positioned above transistor 33, further saving area of transistor 33 and metal pillar 31 in metal layer 41. Also, the structure of the coupled metal pillar 31 and transistor 33 is the same as a portion of the structure of a memory cell (such as a partial structure of a capacitor and a transistor), allowing the metal pillar 31 and transistor 33 to be fabricated using a partial mask of the memory cell, saving process costs. Furthermore, transistors in memory cells act as switches, with more coupled loads (such as one or more capacitors), resulting in higher power consumption.
  • Transistor 33 in serial interface circuit 310 acting as an amplifier, has lower power consumption.
  • Transistor 33 in serial interface circuit 310 acting as a switch, has fewer coupled loads (such as a resistor), also resulting in lower power consumption. Therefore, compared to memory cells, transistor 33 in serial interface circuit 310 has lower power consumption.
  • transistor 33 is a vertical junctionless field-effect transistor (JFET) or other transistors that can be used in back-end processes.
  • JFET refers to a transistor that can be used in back-end processes.
  • JFET is used as transistor 33, resulting in lower power consumption and current draw. This saves power consumption in the serial interface circuit 310. Furthermore, JFETs are vertical transistors and can be fabricated using back-end processes. Therefore, JFETs can be applied to CML circuits, saving area in complex CML circuits.
  • the load device includes an equivalent resistance device, with at least one of the plurality of metal pillars 31 serving as the equivalent resistance device for the serial interface circuit 310.
  • the equivalent resistance device can be a resistor or other device with equivalent resistance. In this embodiment, using the metal pillar 31 as the equivalent resistance device saves the area of the resistor.
  • the serial interface circuit 310 includes at least one of a D latch, a D flip-flop, and a multiplexer. At least one of the D latch, D flip-flop, or multiplexer includes a metal pillar 31, or includes a transistor 33, or includes both a metal pillar 31 and a transistor 33.
  • Figure 6 illustrates a possible implementation of a D latch, where the first D latch can be a CML circuit.
  • the first input terminal D1 and the second input terminal D2 of the first D latch are differential input terminals, and the first output terminal Q1 and the second output terminal Q2 of the first D latch are differential output terminals.
  • the first D latch includes a first resistor R1, a second resistor R2, a third resistor R3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.
  • the control terminal of the transistors refers to the gate
  • the first terminal refers to one of the source and drain terminals
  • the second terminal refers to the other of the source and drain terminals.
  • the first terminal of the first resistor R1 and the first terminal of the second resistor R2 are connected to the power supply terminal VDD.
  • the second terminal of the second resistor R2, the first terminal of the second transistor T2, the control terminal of the fourth transistor T4, and the first terminal of the third transistor T3 are all connected to the first output terminal Q1 of the first D latch.
  • the second terminal of the first resistor R1, the first terminal of the first transistor T1, the control terminal of the third transistor T3, and the first terminal of the fourth transistor T4 are all connected to the second output terminal Q2 of the first D latch.
  • the control terminal of the first transistor T1 is connected to the first input terminal D1 of the first D latch, and the control terminal of the second transistor T2 is connected to the second input terminal D2 of the first D latch.
  • the second terminals of both the first transistor T1 and the second transistor T2 are connected to the first terminal of the fifth transistor T5.
  • the second terminals of both the third transistor T3 and the fourth transistor T4 are connected to the first terminal of the sixth transistor T6.
  • the control terminal of the fifth transistor T5 is connected to the first clock terminal CLK1 of the first D latch.
  • the control terminal of the sixth transistor T6 is connected to the second clock terminal CLK2 of the first D latch.
  • the second terminals of both the fifth transistor T5 and the sixth transistor T6 are connected to the first terminal of the third resistor R3.
  • the second terminal of the third resistor R3 is grounded.
  • the first transistor T1 and the first resistor R1 can be implemented using a back-end string structure (coupled to a metal pillar 31 and a transistor 33).
  • the fifth transistor T5 and the third resistor R3 can be implemented using a back-end string structure.
  • the second transistor T2 and the second resistor R2 can be implemented using a back-end string structure.
  • the third transistor T3, the fourth transistor T4, and the sixth transistor T6 can each be implemented using one transistor in a back-end string structure. These six back-end string structures are electrically connected to realize the circuit schematic shown in Figure 6.
  • Figure 7 illustrates one possible implementation of a D flip-flop, where the first D flip-flop can be a CML circuit.
  • the first input D3 and the second input D4 of the first D flip-flop are differential inputs, and the first output Q3 and the second output Q4 of the first D flip-flop are differential outputs.
  • the first D flip-flop includes two first D latches. The first input D1 of the left first D latch is connected to the first input D3 of the first D flip-flop, and the second input D2 of the left first D latch is connected to the second input D4 of the first D flip-flop.
  • the first output Q1 of the right first D latch is connected to the first output Q3 of the first D flip-flop, and the second output Q2 of the right first D latch is connected to the second output Q4 of the first D flip-flop.
  • the first clock input CLK1 of both first D latches is connected to the first clock input CLK3 of the first D flip-flop.
  • the second clock input CLK2 of both first D latches is connected to the second clock input CLK4 of the first D flip-flop.
  • the first output terminal Q1 of the first D latch on the left is connected to the first input terminal D1 of the first D latch on the right, and the second output terminal Q2 of the first D latch on the left is connected to the second input terminal D2 of the first D latch on the right.
  • the first D flip-flop can be implemented using a multiple back-track string structure, referencing the first D latch.
  • Figure 8 illustrates one possible implementation of a multiplexer.
  • This first multiplexer can be a CML circuit, and it is a 2:1 multiplexer, meaning the ratio of the number of inputs to the number of outputs is 2:1.
  • the first input D5 and the second input D6 of the first multiplexer are differential inputs.
  • the third input D7 and the fourth input D8 of the first multiplexer are differential inputs.
  • the first output Q5 and the second output Q6 of the first multiplexer are differential outputs.
  • the first multiplexer includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12.
  • the first terminals of the fourth resistor R4 and the fifth resistor R5 are connected to the power supply terminal VDD.
  • the second terminal of the fourth resistor R4, the first terminal of the sixth resistor R6, and the first terminal of the seventh transistor T7 are all connected to the first output terminal Q5 of the first multiplexer.
  • the second terminal of the fifth resistor R5, the first terminal of the seventh resistor R7, and the first terminal of the tenth transistor T10 are all connected to the second output terminal Q6 of the first multiplexer.
  • the first terminal of the eighth transistor T8 is connected to the second terminal of the seventh resistor R7.
  • the first terminal of the ninth transistor T9 is connected to the second terminal of the sixth resistor R6.
  • the control terminal of the seventh transistor T7 is connected to the first input terminal D5 of the first multiplexer.
  • the control terminal of the eighth transistor T8 is connected to the second input terminal D6 of the first multiplexer.
  • the control terminal of the tenth transistor T10 is connected to the third input terminal D7 of the first multiplexer.
  • the control terminal of the ninth transistor T9 is connected to the fourth input terminal D8 of the first multiplexer.
  • the second terminals of the seventh transistor T7 and the eighth transistor T8 are both connected to the first terminal of the eleventh transistor T11.
  • the second terminals of the ninth transistor T9 and the tenth transistor T10 are both connected to the first terminal of the twelfth transistor T12.
  • the control terminal of the eleventh transistor T11 is connected to the first clock terminal CLK5 of the first multiplexer.
  • the control terminal of the twelfth transistor T12 is connected to the second clock terminal CLK6 of the first multiplexer.
  • the second terminals of both the eleventh transistor T11 and the twelfth transistor T12 are connected to the first terminal of the eighth resistor R8.
  • the second terminal of the eighth resistor R8 is grounded.
  • the seventh transistor T7 and the fourth resistor R4 can be implemented using a back-end string structure (coupled to a metal pillar 31 and a transistor 33).
  • the eighth transistor T8 and the seventh resistor R7 can be implemented using a back-end string structure.
  • the ninth transistor T9 and the sixth resistor R6 can be implemented using a back-end string structure.
  • the tenth transistor T10 and the fifth resistor R5 can be implemented using a back-end string structure.
  • the eleventh transistor T11 and the eighth resistor R8 can be implemented using a back-end string structure.
  • the twelfth transistor T12 can be implemented using a back-end string structure with transistor 33.
  • At least one of the D latch, D flip-flop, and multiplexer of the serial interface circuit 310 is implemented using at least one of the metal pillars 31 and transistors 33. Even if the structure of the D latch, D flip-flop, and multiplexer is complex, the circuit area of the chip 300 can be saved.
  • the load device includes an equivalent inductor, which comprises a metal transmission line. Multiple metal pillars 31 are arranged in multiple columns, and different columns of metal pillars 31 are connected via metal transmission lines to the equivalent inductor serving as the serial interface circuit 310.
  • the multiple columns of metal pillars 31 include a first metal pillar 51 and a second metal pillar 52 in the first column, and a third metal pillar 53 and a fourth metal pillar 54 in the second column.
  • the first end of the first metal pillar 51 is connected to the first end of the third metal pillar 53 via a metal transmission line.
  • the first end of the second metal pillar 52 is connected to the first end of the fourth metal pillar 54 via a metal transmission line.
  • the second end of the third metal pillar 53 is connected to the second end of the second metal pillar 52 via a metal transmission line.
  • a coil can be formed, which can serve as a loop inductor.
  • FIG9 only shows a coil formed by four metal pillars 31 and metal transmission lines.
  • a coil can also be formed using fewer or more metal pillars 31 and metal transmission lines, and this embodiment of the application does not limit this.
  • the above-mentioned loop inductor can be achieved by spacing them.
  • the equivalent inductor device is formed by the metal pillar 31 and the metal transmission line, which not only saves process costs but also saves the circuit area of the chip 300.
  • At least one of the D latch, D flip-flop, and multiplexer includes an equivalent inductor device formed by a metal pillar 31.
  • a first inductor L1 is provided between the first resistor R1 and the power supply terminal VDD
  • a second inductor L2 is provided between the second resistor R2 and the power supply terminal VDD.
  • the first inductor L1 and the second inductor L2 can be implemented in the form shown in Figure 9.
  • a third inductor L3 is connected between the first resistor R1 of the first D latch on the left and the power supply terminal VDD; a fourth inductor L4 is connected between the second resistor R2 of the first D latch on the left and the power supply terminal VDD.
  • a fifth inductor L5 is connected between the first resistor R1 of the first D latch on the right and the power supply terminal VDD; a sixth inductor L6 is connected between the second resistor R2 of the first D latch on the right and the power supply terminal VDD.
  • a ninth resistor R9 and a seventh inductor L7 are connected in series between the second output terminal Q2 of the first D latch on the left and the second input terminal D2 of the first D latch on the right.
  • a tenth resistor R10 and an eighth inductor L8 are connected in series between the first output terminal Q1 of the first D latch on the left and the first input terminal D1 of the first D latch on the right.
  • An eleventh resistor R11 and a ninth inductor L9 are connected in series between the second output terminal Q2 of the first D latch on the right and the first output terminal Q3 of the first D flip-flop.
  • a twelfth resistor R12 and a tenth inductor L10 are connected in series between the first output terminal Q1 of the first D latch on the right and the second output terminal Q4 of the first D flip-flop.
  • the third inductor L3, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, the seventh inductor L7, the eighth inductor L8, the ninth inductor L9, and the tenth inductor L10 can all be implemented in the form shown in Figure 9.
  • an eleventh inductor L11 is provided between the fourth resistor R4 and the power supply terminal VDD, and a twelfth inductor L12 is provided between the fifth resistor R5 and the power supply terminal VDD.
  • the eleventh inductor L11 and the twelfth inductor L12 can be implemented as shown in Figure 9.
  • the transmission speed of the serial interface circuit 310 can be increased.
  • the transmission speed of the serial interface circuit 310 can be increased by 50%.
  • the ratio of the number of data inputs to the number of data outputs of the multiplexer is n, where n is an integer greater than or equal to 4.
  • Figure 13 illustrates another possible implementation of the multiplexer.
  • the second multiplexer can be a CML circuit, and it is a 4:1 multiplexer, meaning the ratio of the number of inputs to the number of outputs is 2:1.
  • the first input D9 and the second input D10 of the second multiplexer are differential inputs.
  • the third input D11 and the fourth input D12 of the second multiplexer are differential inputs.
  • the fifth input D13 and the sixth input D14 of the second multiplexer are differential inputs.
  • the seventh input D15 and the eighth input D16 of the second multiplexer are differential inputs.
  • the first output Q7 and the second output Q8 of the second multiplexer are differential inputs.
  • the second multiplexer includes a ninth resistor R9, a tenth resistor R10, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor T27, and a twenty-eighth transistor T28.
  • the first terminals of the ninth resistor R9 and the tenth resistor R10 are connected to the power supply terminal VDD.
  • the second terminal of the ninth resistor R9, and the first terminals of the thirteenth transistor T13, the fifteenth transistor T15, the seventeenth transistor T17, and the nineteenth transistor T19 are all connected to the first output terminal Q7 of the second multiplexer.
  • the second terminal of the tenth resistor R10, the first terminal of the fourteenth transistor T14, the first terminal of the sixteenth transistor T16, the first terminal of the eighteenth transistor T18, and the first terminal of the twentieth transistor T20 are all connected to the second output terminal Q8 of the second multiplexer.
  • the control terminal of the thirteenth transistor T13 is connected to the first input terminal D9 of the second multiplexer.
  • the control terminal of the fourteenth transistor T14 is connected to the second input terminal D10 of the second multiplexer.
  • the control terminal of the fifteenth transistor T15 is connected to the third input terminal D11 of the second multiplexer.
  • the control terminal of the sixteenth transistor T16 is connected to the fourth input terminal D12 of the second multiplexer.
  • the control terminal of the seventeenth transistor T17 is connected to the fifth input terminal D13 of the second multiplexer.
  • the control terminal of the eighteenth transistor T18 is connected to the sixth input terminal D14 of the second multiplexer.
  • the control terminal of the nineteenth transistor T19 is connected to the seventh input terminal D15 of the second multiplexer.
  • the control terminal of the twentieth transistor T20 is connected to the eighth input terminal D16 of the second multiplexer.
  • the second terminals of transistors T13 (13th generation) and T14 (14th generation) are both connected to the first terminal of transistor T21 (21st generation).
  • the second terminals of transistors T15 (15th generation) and T16 (16th generation) are both connected to the first terminal of transistor T23 (23rd generation).
  • the second terminals of transistors T17 (17th generation) and T18 (18th generation) are both connected to the first terminal of transistor T25 (25th generation).
  • the second terminals of transistors T19 (19th generation) and T20 (20th generation) are both connected to the first terminal of transistor T27 (27th generation).
  • the control terminal of transistor T21 (21st generation) is connected to the first clock terminal CLK7 of the second multiplexer.
  • the control terminal of transistor T23 (23rd generation) is connected to the second clock terminal CLK8 of the second multiplexer.
  • the control terminal of transistor T25 (25th generation) is connected to the third clock terminal CLK9 of the second multiplexer.
  • the control terminal of transistor T27 (27th generation) is connected to the fourth clock terminal CLK10 of the second multiplexer.
  • the second terminal of transistor T21 (21st generation) is connected to the first terminal of transistor T22 (22nd generation).
  • the second terminal of transistor T23 (23rd generation) is connected to the first terminal of transistor T24 (24th generation).
  • the second terminal of transistor T25 (25th transistor) is connected to the first terminal of transistor T26 (26th transistor).
  • the second terminal of transistor T27 (27th transistor) is connected to the first terminal of transistor T28 (28th transistor).
  • the control terminal of transistor T22 (22nd transistor) is connected to the fourth clock terminal CLK10 of the second multiplexer.
  • the control terminal of transistor T24 (24th transistor) is connected to the first clock terminal CLK7 of the second multiplexer.
  • the control terminal of transistor T26 (26th transistor) is connected to the second clock terminal CLK8 of the second multiplexer.
  • the control terminal of transistor T28 (28th transistor) is connected to the third clock terminal CLK9 of the second multiplexer.
  • the second terminals of transistors T22 (22nd transistor), T24 (24th transistor), T26 (26th transistor), and T28 (28th transistor) are all grounded.
  • the first clock terminal CLK7 through the eighth clock terminal can all be connected to a phase clock generator.
  • the thirteenth transistor T13 and the ninth resistor R9 can be implemented using a back-end string structure (coupled to a metal pillar 31 and a transistor 33).
  • the fourteenth transistor T14 and the tenth resistor R10 can also be implemented using a back-end string structure.
  • the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27, and the twenty-eighth transistor T28 can each be implemented using a back-end string structure transistor 33. These sixteen back-end string structures are electrically connected to realize the circuit schematic shown in Figure 13.
  • the second multiplexer shown in Figure 13 may also include a loop inductor.
  • a thirteenth inductor L13 is provided between the ninth resistor R9 and the power supply terminal VDD.
  • a fourteenth inductor L14 is provided between the tenth resistor R10 and the power supply terminal VDD.
  • the thirteenth inductor L13 and the fourteenth inductor L14 can be implemented as shown in Figure 9.
  • n is greater than or equal to 4
  • n is greater than or equal to 4
  • a fully three-dimensional serial interface circuit 310 can be constructed using the D latch shown in Figure 6 or Figure 10, the D flip-flop shown in Figure 7 or Figure 10, and the multiplexer shown in Figure 8, Figure 12, or Figure 13.
  • the serial interface circuit 310 includes a multi-stage parallel-to-serial conversion circuit, a first D flip-flop, and at least one frequency divider.
  • Figure 14 only shows two stages of parallel-to-serial conversion circuits; fewer or more stages are possible, and this embodiment does not impose limitations.
  • Each parallel-to-serial conversion circuit includes two data inputs, one clock input, and one data output.
  • the two parallel-to-serial conversion circuits in the first stage can receive four data inputs
  • the one parallel-to-serial conversion circuit in the second stage can receive two data inputs from the first stage
  • the first D flip-flop can receive one data input from the second stage.
  • Each parallel-to-serial conversion circuit can also receive a clock signal processed by the frequency divider.
  • the structure of each parallel-to-serial conversion circuit can be the same; the parallel-to-serial conversion circuit in the dashed box is used as an example for description.
  • the parallel-to-serial conversion circuit may include two first D flip-flops, a first D latch, and a first multiplexer.
  • the structure of the first D flip-flops can refer to the structure shown in Figure 7 or Figure 11.
  • the structure of the first D latch can refer to the structure shown in Figure 6 or Figure 10.
  • the structure of the first multiplexer can refer to the structure shown in Figure 8 or Figure 12.
  • the outputs of the two first D flip-flops are respectively connected to the inputs of the first multiplexer, and the lower first D flip-flop is connected to the first multiplexer through the first D latch.
  • the connection relationship of each port is shown in Figure 14, and will not be repeated here in this embodiment.
  • the clock terminals of the two first D flip-flops, the first D latch, and the first multiplexer are all connected to the same clock.
  • the D latch, the D flip-flops, and the multiplexer are generated in a three-dimensional architecture on the metal layer 41. This can significantly improve the transmission speed of the serial interface circuit 310.
  • the overall three-dimensional architecture of the serial interface circuit 310 can save approximately 46,200 square micrometers in area, while significantly improving power consumption and performance.
  • the serial interface circuit 310 further includes a bandgap reference source, which includes a back-end transistor formed by a back-end process.
  • the bandgap reference source can be used as the voltage source VDD for the aforementioned circuits (such as D latches, D flip-flops, or multiplexers).
  • the bandgap reference source and other circuits in the serial interface circuit besides the bandgap reference source are generated in a three-dimensional architecture on metal layer 41.
  • the multiple back-end string structures of other circuits can be arranged in a multi-column configuration as shown in Figure 5.
  • the multiple back-end transistors in the bandgap reference source can be arranged in a multi-column configuration, referring to the multiple back-end transistors shown in Figure 5.
  • a bandgap reference source is implemented using multiple back-end transistors. This provides a dedicated bias voltage and voltage distribution for the serial interface circuit 310, better maintaining the circuit's pressure-volume-temperature (PVT) and improving circuit reliability. Furthermore, the back-end transistors can be fabricated using a mask from a memory cell, resulting in lower manufacturing costs.
  • the chip 300 housing the serial interface circuit 310 is a memory or interface chip.
  • the chip 300 can also be other chips, and this application embodiment does not limit this.
  • the application scenarios of the serial interface circuit 310 are quite flexible.
  • This application also provides a chip manufacturing method.
  • the method is used to generate a chip 300, which includes a serial interface circuit 310.
  • the serial interface circuit 310 includes a plurality of metal pillars 31.
  • the chip manufacturing method includes back-end processes. As shown in FIG17, the back-end processes may include the following steps.
  • a plurality of metal pillars 31 are generated on the metal layer through the first back-end mask.
  • the metal pillars 31 may have the same partial structure as the capacitor of the memory cell in the memory, and the first back-end mask may be the mask of the memory cell.
  • the serial interface circuit 310 further includes transistors 33.
  • S100 may specifically include: generating a plurality of transistors 33 on a metal layer through a first back-end mask, and generating a metal pillar 31 coupled to each of the plurality of transistors 33.
  • the structure of the coupled metal pillars 31 and transistors 33 may be the same as a portion of the structure of a memory cell in the memory, and the first back-end mask may be a mask for that memory cell.
  • the serial interface circuit 310 also includes a plurality of metal capacitor pads.
  • S100 may further include: generating a plurality of metal pillars 31 and a plurality of metal capacitor pads 32 on a metal layer through a first back-end mask. At least one of the plurality of metal capacitor pads 32 is disposed around a metal pillar 31.
  • the serial interface circuit 310 further includes a bandgap reference source comprising a back-end transistor.
  • the back-end process further includes generating the back-end transistor on a metal layer using a second back-end mask.
  • the bandgap reference source is used to provide power signals to other circuits in the serial interface circuit.
  • the back-end transistor in the bandgap reference source may have the same structure as the transistor in a memory cell, and the second back-end mask may be a mask for the transistor in that memory cell.
  • This application embodiment also provides a memory, which includes a controller and the aforementioned chip 300, with the controller coupled to the chip 300.
  • the controller is used to control the chip 300 to read and write data.
  • This application also provides an interface chip, which includes a processor and the aforementioned chip 300, with the processor coupled to the chip 300.
  • this interface chip may be a switching chip.
  • This application also provides an electronic device, which includes a circuit board and the aforementioned chip 300, the chip 300 being disposed on the circuit board.
  • This electronic device includes, but is not limited to, mobile phones, tablets, computers, laptops, cameras, wearable devices, in-vehicle devices, or terminal devices.
  • the disclosed systems, devices, and methods can be implemented in other ways.
  • the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods.
  • multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed.
  • the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.
  • the modules described as separate components may or may not be physically separate.
  • the components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
  • the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

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Abstract

本申请涉及一种芯片、芯片制造方法、存储器、接口芯片和电子设备，涉及芯片技术领域。该芯片包括串行接口电路，串行接口电路包括多个金属柱；多个金属柱通过后道工艺形成；多个金属柱作为串行接口电路的负载器件。如此，可以节省芯片电路面积。

Description

一种芯片、芯片制造方法、存储器、接口芯片和电子设备
本申请要求于2024年6月12日提交国家知识产权局、申请号为202410761110.3、申请名称为“一种芯片、芯片制造方法、存储器、接口芯片和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及芯片技术领域，尤其涉及一种芯片、芯片制造方法、存储器、接口芯片和电子设备。
背景技术
存储器(如动态随机存取存储器(dynamic random access memory，DRAM))含有输入输出(input output，IO)接口电路。存储器可以通过IO接口电路与外部器件进行数据传输。随着存储器的速度不断提升，为了使IO接口电路更快地传输数据，IO接口电路的结构越来越复杂，这导致IO接口电路的面积较大。
发明内容
本申请实施例提供一种芯片、芯片制造方法、存储器、接口芯片和电子设备，可以节省芯片的接口电路的面积。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种芯片，该芯片包括串行接口电路，串行接口电路包括多个金属柱，多个金属柱通过后道工艺形成。多个金属柱作为串行接口电路的负载器件。
上述技术方案中，通过后道工艺将金属柱生成在金属层上，且金属柱作为串行接口电路中的负载器件，因此负载器件可以生成在金属层上。如此可以节省衬底上的串行接口电路的负载器件的面积。并且，金属柱与存储器中的存储单元的电容的部分结构相同，可以采用存储单元的掩膜生成金属柱，节省工艺成本。
在第一方面的一种可能的实现方式中，串行接口电路还包括多个晶体管，多个金属柱中的每个金属柱与多个晶体管中的一个晶体管耦合，多个晶体管通过后道工艺形成。上述可能的实现方式中，通过后道工艺将晶体管生成在金属层上，可以节省衬底上的晶体管的面积。并且，金属柱与晶体管可以不设置在同一平面上，金属柱可以设置在晶体管上方，从而进一步节省金属层中的晶体管和金属柱的面积。以及，金属柱和晶体管的结构与存储器的存储单元中的存储单元的部分结构相同，可以采用存储单元的掩膜生成金属柱和晶体管，节省工艺成本。进一步地，存储器的存储单元中的晶体管作为开关，其耦合的负载较多(如一个或多个电容)，功耗较大。串行接口电路中的晶体管作为放大器时功耗较小。串行接口电路中的晶体管作为开关时耦合的负载较少，功耗也较小。因此，与存储器的存储单元相比，串行接口电路中的晶体管功耗较小。
在第一方面的一种可能的实现方式中，晶体管为垂直无结场效应晶体管。上述可能的实现方式中，垂直无结场效应晶体管的功耗和电流更小，可以节省串行接口电路的功耗。并且，垂直无结场效应晶体管是垂直晶体管，可以采用后道工艺制作。因此垂直无结场效应晶体管可以应用于电流模式逻辑电路中、且可以节省复杂电流模式逻辑电路的面积。
在第一方面的一种可能的实现方式中，负载器件包括等效电阻器件，多个金属柱中的至少一个金属柱作为串行接口电路的等效电阻器件。上述可能的实现方式中，将金属柱作为等效电阻器件，可以节省电阻的面积。
在第一方面的一种可能的实现方式中，负载器件包括等效电感器件，等效电感器件包括金属传输线。多个金属柱以多列的形式排布，不同列的金属柱通过金属传输线连接作为串行接口电路的等效电感器件。上述可能的实现方式中，通过金属柱和金属传输线作为等效电感器件，不仅可以节省工艺成本，还可以节省芯片电路面积。进一步地，在串行接口电路中设置金属柱和金属传输线作为环线电感，可以增加串行接口电路的传输速度。例如，可以为串行接口电路增加50％的传输速度。
在第一方面的一种可能的实现方式中，串行接口电路包括D锁存器、D触发器和多路复用器中的至少一个。D锁存器、D触发器或多路复用器中的至少一个包括金属柱。上述可能的实现方式中，通过多个金属柱实现串行接口电路的D锁存器、D触发器和多路复用器中的至少一个。即使D锁存器、D触发器和多路复用器的结构复杂，也可以节省芯片电路面积。
在第一方面的一种可能的实现方式中，多路复用器的数据输入端与数据输出端的数量比值为n，n为大于或等于4的整数。上述可能的实现方式中，可以采用较为复杂的n:1多路复用器(n大于或等于4)，在节省面积和工艺成本的基础上，获取更快的传输速度。
在第一方面的一种可能的实现方式中，串行接口电路还包括带隙基准源，带隙基准源包括后道晶体管，后道晶体管通过后道工艺形成。上述可能的实现方式中，通过后道晶体管实现带隙基准源。如此可以为串行接口电路提供专用的偏置电压和电压分布，较好的保持电路的压力、体积、温度(pressure-volume-temperature，PVT)，可以提升电路的可靠性。并且，后道晶体管可以使用存储器的存储单元的掩膜来制作，工艺成本较低。
在第一方面的一种可能的实现方式中，串行接口电路还包括多个金属电容焊盘，多个金属电容焊盘中的至少一个金属电容焊盘环绕设置在金属柱上。上述可能的实现方式中，金属柱和金属电容焊盘的结构与存储器中的存储单元的电容的结构相同，可以采用存储单元的掩膜生成金属柱和金属电容焊盘，节省工艺成本。
第二方面，提供一种芯片制造方法，用于生成芯片，芯片包括串行接口电路。串行接口电路包括多个金属柱，芯片制造方法包括后道工艺，该后道工艺包括：通过第一后道掩膜，在金属层上生成多个金属柱，多个金属柱作为串行接口电路的负载器件。
在第二方面的一种可能的实现方式中，串行接口电路还包括晶体管。通过第一后道掩膜，在金属层上生成多个金属柱，包括：通过第一后道掩膜，在金属层上生成多个晶体管，在多个晶体管中的每个晶体管上生成与该晶体管耦合的金属柱。
在第二方面的一种可能的实现方式中，串行接口电路还包括带隙基准源，带隙基准源包括后道晶体管，该后道工艺还包括：通过第二后道掩膜，在金属层上生成后道晶体管。
在第二方面的一种可能的实现方式中，串行接口电路还包括多个金属电容焊盘；通过第一后道掩膜，在金属层上生成多个金属柱，包括：通过第一后道掩膜，在金属层上生成多个金属柱和多个金属电容焊盘，多个金属电容焊盘中的至少一个金属电容焊盘环绕设置在金属柱上。
第三方面，提供一种存储器，该存储器包括控制器和第一方面或第一方面的任一种可能的实现方式所提供的芯片，该控制器与该芯片耦合。
第四方面，提供一种接口芯片，该接口芯片包括处理器和第一方面或第一方面的任一种可能的实现方式所提供的芯片，该处理器与该芯片耦合。
第五方面，提供一种电子设备，该电子设备包括电路板和第一方面或第一方面的任一种可能的实现方式所提供的芯片，该芯片设置在该电路板上。
可以理解地，上述提供的任一种芯片制造方法、存储器、接口芯片和电子设备均应用上文所提供的芯片。因此，其所能达到的有益效果可参考上文所提供的对应的芯片中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种存储器的结构示意图；
图2为本申请实施例提供的一种芯片的结构示意图一；
图3为本申请实施例提供的一种金属柱的结构示意图；
图4为本申请实施例提供的一种芯片的结构示意图二；
图5为本申请实施例提供的一种多个晶体管和多个金属柱的示意图；
图6为本申请实施例提供的一种D锁存器的结构示意图一；
图7为本申请实施例提供的一种D触发器的结构示意图一；
图8为本申请实施例提供的一种多路复用器的结构示意图一；
图9为本申请实施例提供的一种电感的示意图；
图10为本申请实施例提供的一种D锁存器的结构示意图二；
图11为本申请实施例提供的一种D触发器的结构示意图二；
图12为本申请实施例提供的一种多路复用器的结构示意图二；
图13为本申请实施例提供的一种多路复用器的结构示意图三；
图14为本申请实施例提供的一种串行接口电路的示意图；
图15为本申请实施例提供的一种串行接口电路的三维结构示意图；
图16为本申请实施例提供的一种串行接口电路和带隙基准源的三维结构示意图；
图17为本申请实施例提供的一种芯片制造方法的流程示意图。
具体实施方式
需要说明的是，本申请实施例涉及的术语“第一”、“第二”等仅用于区分同一类型特征的目的，不能理解为用于指示相对重要性、数量、顺序等。
本申请实施例涉及的术语“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请实施例涉及的术语“耦合”、“连接”应做广义理解，例如，可以指物理上的直接连接，也可以指通过电子器件实现的间接连接，例如通过电阻、电感、电容或其他电子器件实现的连接。
首先对本申请实施例涉及的一些基础概念进行解释说明：
芯片制造工艺，包括前道工艺(front end of line，FEOL)和后道工艺(backend of line，BEOL)。芯片上的集成电路是依靠平面工艺一层一层制备起来的。示例性地，对于逻辑器件，先在衬底上划分制备晶体管的区域。然后离子注入实现N型和P型区域，再生成栅极。随后又是离子注入，生成源极和漏极。这部分工艺流程为前道工艺。与前道工艺相对的后道工艺，就是建立若干层导电金属线，不同金属线之间由柱状金属相连。这些金属线将衬底上的晶体管按照设计的要求连接起来，以实现特定的功能。芯片制造工艺还包括掩膜(mask)和光刻。在光刻之前，根据设计出的芯片电路结构，设计出待加工的芯片所对应的掩膜(mask)，该掩膜上印着预先设计好的芯片电路的结构图案。在光刻过程中，在晶圆上均匀铺上光刻胶(photo resist，PR)，然后使用紫外线通过预先设计好的掩膜对光刻胶进行照射，光刻胶被紫外线所照射的部位将变得可溶解。溶解掉光刻胶的部分会暴露出晶圆，且形成的图案与掩膜上的结构图案一致。经过后续处理，可以得到所需芯片电路。
存储器，通常用来存放操作系统中各种正在运行的软件、输入和输出数据以及与外存交换的信息等。以动态随机访问存储器(dynamic random access memory，DRAM)为例，如图1所示。DRAM1000包括存储单元阵列100和外围电路200，外围电路200至少可以包括输入输出(input output，IO)接口电路210，IO接口电路210包括发送电路211和接收电路212。发送电路211包括串行器20(serializer)，串行器20包括D锁存器(Dlatch)21、D触发器(data flip-flop，DFF)22和多路复用器(multiplexer，MUX)23。存储单元阵列100中有多个存储单元(memory cell)，多个存储单元以阵列的方式排布，存储单元用于存储数据。外围电路200用于控制存储单元阵列100写入数据、或者控制存储单元阵列100擦除数据、或者从存储单元阵列100中读取数据。例如，外围电路200对存储单元阵列100中的存储单元施加电压，从而控制存储单元写入数据。外围电路200中的IO接口电路210用于与外部器件(如存储器控制器或者处理器)进行数据传输。例如，外围电路200读取存储单元阵列100中的数据，IO接口电路210通过发送电路211将存储单元阵列100中的数据发送给外部器件。或者，IO接口电路210通过接收电路212接收来自外部器件的数据，外围电路200将来自外部器件的数据写入存储单元阵列100。其中，发送电路211为了输出高速数据信号，需要对并行数据进行串行化，串行化可以指将m路并行数据转换为n路串行数据，n小于m。通常，串行数据的传输速度大于并行数据的传输速度，因此串行数据又可以称为高速数据。串行器20用于执行数据的串行化。例如串行器20用于输入多路并行数据，输出一路串行数据，并以尽可能大的信号带宽将串行数据发送到输出端口上。串行器20的传输速度是IO接口电路210设计的关键点。
随着存储器的速度不断提升，传统的互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)逻辑(logic)IO接口电路已经逐渐不能满足高速DRAM接口的需求。相比之下，采用电流模式逻辑(current mode logic，CML)电路作为IO接口电路的方式，开始逐渐显现其优势。在较高的信号速率的情况下，CML电路具有较低的功耗和较高的信噪比。并且，CML电路还具有低电压差分信号(low voltage differential signaling，LVDS)电路难以具备的特性。例如，CML电路可以改变负载的特性来改善电路的高频特性，也就是CML电路可以采用有源负载来拓展带宽实现均衡的目的。但是，在采用CML电路作为IO接口电路的设计中，为了更快地传输数据，CML电路的结构越来越复杂，这导致CML电路的面积越来越大。以及CML电路还存在功耗高、偏置电压非专用等问题。如何设计CML电路成为难点。
本申请实施例提供了一种芯片，该芯片的IO接口电路可以是串行接口电路。串行接口电路的结构和功能可以参考上述IO接口电路。串行接口电路用于与连接该芯片的外部器件进行数据传输。串行接口电路的元器件可以采用后道工艺制作成三维结构，从而节省芯片面积。
在一些示例中，如图2所示，芯片300包括串行接口电路310。串行接口电路310包括多个金属柱(pilar)31，多个金属柱31通过后道工艺形成。多个金属柱31作为串行接口电路310的负载器件。
示例性地，金属柱31与存储器中的存储单元的电容的部分结构相同。多个金属柱31可以以阵列的方式排布，生成在金属层上。因此可以采用制备存储器芯片的存储单元的部分掩膜来生成金属柱31。以DRAM为例，DRAM的存储单元包括晶体管和至少一个电容，电容的结构包括金属柱和环绕于金属柱的至少一个金属电容极板。DRAM的存储单元的金属柱作为至少一个电容的第一极板，DRAM的存储单元的每个金属电容极板作为每个电容的第二极板。金属柱31的结构可以与存储单元中的金属柱结构相同。金属柱31可以作为串行接口电路310的负载器件。例如，串行接口电路310还包括金属传输线，金属柱31通过金属传输线与串行接口电路310中的其他器件连接，以使该金属柱31被连接到串行接口电路310中作为负载器件。金属柱31还可以与金属传输线一起作为负载器件。例如，多个金属柱31通过金属传输线连接，以使连接的多个金属柱31和金属传输线的整体作为串行接口电路310中的负载器件。
又示例性地，DRAM的存储单元的环绕于金属柱的金属电容极板以焊盘(pad)的方式实现。金属柱与焊盘之间存在空隙，金属柱与焊盘分别作为电容的两个极板，一起形成电容。串行接口电路的金属柱可以通过该DRAM的存储单元的电容的掩膜来制备。在这种情况下，如图3所示，串行接口电路还包括多个金属电容焊盘(pad)32，多个金属电容焊盘32中的至少一个金属电容焊盘32环绕设置在金属柱31上。金属柱31外围设置金属电容焊盘32的结构与存储器的存储单元的电容结构相同。可选地，可以不使用至少一个金属电容焊盘32作为串行接口电路310中的器件。
再示例性地，DRAM的存储单元的环绕于金属柱的金属电容极板以反焊盘(antipad)的方式实现。
反焊盘上有多个孔，每个金属柱位于一个孔内部。金属柱与反焊盘的孔边缘之间存在空隙，金属柱与反焊盘的孔边缘分别作为电容的两个极板，一起形成电容。串行接口电路的金属柱可以通过该DRAM到的存储单元的电容的掩膜来制备。在这种情况下，串行接口电路可以仅包括金属柱31，不包括反焊盘。或者，串行接口电路可以既包括金属柱31，又包括反焊盘。可选地，可以不使用反焊盘作为串行接口电路310中的器件。
在本申请实施例中，通过后道工艺将金属柱31生成在金属层上，且金属柱31作为串行接口电路310中的负载器件，因此负载器件可以生成在金属层上。如此可以节省衬底上的负载器件的面积。并且，金属柱31与存储器中的存储单元的电容的部分结构相同，可以采用存储单元的掩膜生成金属柱31，节省工艺成本。
在一种可能的实施方式中，串行接口电路310除了包括金属柱结构外，还包括晶体管结构。
在一些示例中，如图4所示，串行接口电路310还包括晶体管33，每个金属柱31与一个晶体管33耦合。
示例性地，耦合的一个金属柱31和一个晶体管33可以形成一个后道串结构，该后道串结构与存储器中的存储单元的部分结构(如电容的金属柱和晶体管)相同。多个后道串结构可以以阵列的方式排布，生成在金属层上。因此可以采用制备存储器芯片的存储单元的掩膜来生成后道串结构。为便于制备电路，可以制备多个后道串结构。在通过这些后道串结构形成串行接口电路时，一些后道串结构的金属柱或晶体管可以不连接到串行接口电路中，另一些后道串结构的金属柱和晶体管可以都连接到串行接口电路中。在一种情况中，可以仅使用一个后道串结构的金属柱31作为串行接口电路310的电阻，而不使用该后道串结构的晶体管33作为串行接口电路310中的器件。例如，一个后道串结构的金属柱31的两端接入电路。由于该后道串结构的金属柱31与晶体管33耦合，该晶体管33与该金属柱31耦合的一端也会接入电路。但该晶体管33的其他两端并未接入电路，该晶体管33不作为串行接口电路310中的器件。在另一种情况中，还可以仅使用一个后道串结构的晶体管33作为串行接口电路310的晶体管，而不使用该后道串结构的金属柱31作为串行接口电路310中的器件。例如，一个后道串结构的晶体管33电连接串行接口电路310中的其他器件。由于该后道串结构的金属柱31与晶体管33耦合，该金属柱31与该晶体管33耦合的一端也会接入电路。但该金属柱31的另一端并未接入电路，该金属柱31不作为串行接口电路310中的器件。在又一种情况中，还可以使用一个后道串结构的金属柱31和晶体管33作为串行接口电路310中耦合的电阻与晶体管的结构。例如，一个后道串结构与串行接口电路310中的其他器件电连接，以使该后道串结构的晶体管33和金属柱31被连接到串行接口电路310中作为耦合的电阻与晶体管。可以看出，不同后道串结构的金属柱31和晶体管33的接入电路情况可以不同。
示例性地，如图5所示，衬底42上方是金属层41，金属层41上生成有多行多列晶体管33，每个晶体管33上耦合一个金属柱31，每个金属柱31环绕设置有至少一个金属电容焊盘32。图5仅示出3行2列晶体管33，晶体管33还可以有更多或更少行、以及有更多或更少列。
在本申请实施例中，通过后道工艺将晶体管33生成在金属层41上，可以节省衬底42上的晶体管的面积。并且，金属柱31与晶体管33可以不设置在同一平面上，金属柱31可以设置在晶体管33上方，从而进一步节省金属层41中的晶体管33和金属柱31的面积。以及，耦合的金属柱31和晶体管33的结构与存储器的存储单元中的存储单元的部分结构(如电容的部分结构和晶体管)相同，可以采用存储单元的部分掩膜生成金属柱31和晶体管33，节省工艺成本。进一步地，存储器的存储单元中的晶体管作为开关，其耦合的负载较多(如一个或多个电容)，功耗较大。串行接口电路310中的晶体管33作为放大器时功耗较小。串行接口电路310中的晶体管33作为开关时耦合的负载(如一个电阻)较少，功耗也较小。因此，与存储器的存储单元相比，串行接口电路310中的晶体管33功耗较小。
在一些示例中，晶体管33为垂直无结场效应晶体管(junctionless field effect transistor，JFET)、或者其他可以使用后道工艺的晶体管。其中，JFET为可以使用后道工艺的晶体管。
在本申请实施例中，采用JFET作为晶体管33，功耗和电流更小。如此可以节省串行接口电路310的功耗。并且，JFET是垂直晶体管，且可以采用后道工艺制作。因此JFET可以应用于CML电路中、且可以节省复杂CML电路的面积。
在一种可能的实施方式中，负载器件包括等效电阻器件，多个金属柱31中的至少一个金属柱31作为串行接口电路310的等效电阻器件。示例性地，等效电阻器件可以是电阻，也可以是其他具有等效电阻的器件。在本申请实施例中，将金属柱31作为等效电阻器件，可以节省电阻的面积。
在一种可能的实施方式中，串行接口电路310包括D锁存器、D触发器和多路复用器中的至少一个。D锁存器、D触发器或多路复用器中的至少一个包括金属柱31，或者包括晶体管33，或者包括金属柱31和晶体管33。
在一些示例中，图6示出了D锁存器的一种可能的实施方式，第一D锁存器可以是CML电路。第一D锁存器的第一输入端D1和第二输入端D2为差分输入端，第一D锁存器的第一输出端Q1和第二输出端Q2为差分输出端。第一D锁存器包括第一电阻R1、第二电阻R2、第三电阻R3、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6。本申请实施例的晶体管的控制端指栅极，第一端指源极和漏极中的一个，第二端指源极和漏极中的另一个。第一电阻R1的第一端和第二电阻R2的第一端连接电源端VDD。第二电阻R2的第二端、第二晶体管T2的第一端、第四晶体管T4的控制端和第三晶体管T3的第一端均连接第一D锁存器的第一输出端Q1。第一电阻R1的第二端、第一晶体管T1的第一端、第三晶体管T3的控制端和第四晶体管T4的第一端均连接第一D锁存器的第二输出端Q2。第一晶体管T1的控制端连接第一D锁存器的第一输入端D1，第二晶体管T2的控制端连接第一D锁存器的第二输入端D2。第一晶体管T1的第二端和第二晶体管T2的第二端均连接第五晶体管T5的第一端。第三晶体管T3的第二端和第四晶体管T4的第二端均连接第六晶体管T6的第一端。第五晶体管T5的控制端连接第一D锁存器的第一时钟端CLK1。第六晶体管T6的控制端连接第一D锁存器的第二时钟端CLK2。第五晶体管T5的第二端和第六晶体管T6的第二端均连接第三电阻R3的第一端。第三电阻R3的第二端接地。其中，第一晶体管T1和第一电阻R1可以通过一个后道串结构(耦合的一个金属柱31和一个晶体管33)的形式实现。第五晶体管T5和第三电阻R3可以通过一个后道串结构的形式实现。第二晶体管T2和第二电阻R2可以通过一个后道串结构的形式实现。第三晶体管T3、第四晶体管T4和第六晶体管T6可以分别通过一个后道串结构中的一个晶体管的形式实现。这六个后道串结构通过电连接实现图6所示的电路原理图。
在另一些示例中，图7示出了D触发器的一种可能的实施方式，该第一D触发器可以是CML电路。第一D触发器的第一输入端D3和第二输入端D4为差分输入端，第一D触发器的第一输出端Q3和第二输出端Q4为差分输出端。第一D触发器包括2个第一D锁存器。左侧的第一D锁存器的第一输入端D1连接第一D触发器的第一输入端D3，左侧的第一D锁存器的第二输入端D2连接第一D触发器的第二输入端D4。右侧的第一D锁存器的第一输出端Q1连接第一D触发器的第一输出端Q3，右侧的第一D锁存器的第二输出端Q2连接第一D触发器的第二输出端Q4。2个第一D锁存器的第一时钟端CLK1均连接第一D触发器的第一时钟端CLK3。2个第一D锁存器的第二时钟端CLK2均连接第一D触发器的第二时钟端CLK4。左侧的第一D锁存器的第一输出端Q1与右侧的第一D锁存器的第一输入端D1连接，左侧的第一D锁存器的第二输出端Q2与右侧的第一D锁存器的第二输入端D2连接。其中，第一D触发器可以参考第一D锁存器，通过多个后道串结构的形式实现。
在又一些示例中，图8示出了多路复用器的一种可能的实施方式。该第一多路复用器可以是CML电路，且该第一多路复用器为2:1的第一多路复用器，也就是输入端的数量与输出端的数量的比值为2:1。第一多路复用器的第一输入端D5和第二输入端D6为差分输入端。第一多路复用器的第三输入端D7和第四输入端D8为差分输入端。第一多路复用器的第一输出端Q5和第二输出端Q6为差分输出端。第一多路复用器包括第四电阻R4、第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12。第四电阻R4的第一端和第五电阻R5的第一端连接电源端VDD。第四电阻R4的第二端、第六电阻R6的第一端、第七晶体管T7的第一端均连接第一多路复用器的第一输出端Q5。第五电阻R5的第二端、第七电阻R7的第一端和第十晶体管T10的第一端均连接第一多路复用器的第二输出端Q6。第八晶体管T8的第一端连接第七电阻R7的第二端。第九晶体管T9的第一端连接第六电阻R6的第二端。第七晶体管T7的控制端连接第一多路复用器的第一输入端D5。第八晶体管T8的控制端连接第一多路复用器的第二输入端D6。第十晶体管T10的控制端连接第一多路复用器的第三输入端D7。第九晶体管T9的控制端连接第一多路复用器的第四输入端D8。第七晶体管T7的第二端和第八个的第二端均连接第十一晶体管T11的第一端。第九晶体管T9的第二端和第十晶体管T10的第二端均连接第十二晶体管T12的第一端。第十一晶体管T11的控制端连接第一多路复用器的第一时钟端CLK5。第十二晶体管T12的控制端连接第一多路复用器的第二时钟端CLK6。第十一晶体管T11的第二端和第十二晶体管T12的第二端均连接第八电阻R8的第一端。第八电阻R8的第二端接地。其中，第七晶体管T7和第四电阻R4可以通过一个后道串结构(耦合的一个金属柱31和一个晶体管33)的形式实现。第八晶体管T8和第七电阻R7可以通过一个后道串结构的形式实现。第九晶体管T9和第六电阻R6可以通过一个后道串结构的形式实现。第十晶体管T10和第五电阻R5可以通过一个后道串结构的形式实现。第十一晶体管T11和第八电阻R8可以通过一个后道串结构的形式实现。第十二晶体管T12可以通过一个后道串结构的晶体管33的形式实现。这六个后道串结构通过电连接实现图8所示的电路原理图。
在本申请实施例中，通过金属柱31和晶体管33中的至少一种实现串行接口电路310的D锁存器、D触发器和多路复用器中的至少一个。即使D锁存器、D触发器和多路复用器的结构复杂，也可以节省芯片300电路面积。
在一种可能的实施方式中，负载器件包括等效电感器件，等效电感器件包括金属传输线。多个金属柱31以多列的形式排布，不同列的金属柱31通过金属传输线连接作为串行接口电路310的等效电感器件。
示例性地，如图9所示，多列金属柱31包括位于第一列的第一金属柱51和第二金属柱52、以及位于第二列的第三金属柱53和第四金属柱54。第一金属柱51的第一端与第三金属柱53的第一端通过金属传输线连接。第二金属柱52的第一端与第四金属柱54的第一端通过金属传输线连接。第三金属柱53的第二端与第二金属柱52的第二端通过金属传输线连接。如此，可以形成线圈，该线圈可以作为环线电感。图9仅示出了4个金属柱31和金属传输线形成的线圈，还可以用更少或更多的金属柱31和金属传输线形成线圈，本申请实施例对此不做限制。可选地，由于多个金属柱31存在设计尺寸的限制，可以通过间隔实现上述环线电感。
在本申请实施例中，通过金属柱31和金属传输线形成等效电感器件，不仅可以节省工艺成本，还可以节省芯片300电路面积。
在一种可能的实施方式中，D锁存器、D触发器和多路复用器中的至少一个包括金属柱31形成的等效电感器件。
在一些示例中，如图10所示。在图6所示的D锁存器的基础上，第一电阻R1与电源端VDD之间设置有第一电感L1，第二电阻R2与电源端VDD之间设置有第二电感L2。第一电感L1和第二电感L2可以以图9所示的形式实现。
在另一些示例中，如图11所示。在图7所示的D触发器的基础上，左侧的第一D锁存器的第一电阻R1与电源端VDD之间设置有第三电感L3，左侧的第一D锁存器的第二电阻R2与电源端VDD之间设置有第四电感L4。右侧的第一D锁存器的第一电阻R1与电源端VDD之间设置有第五电感L5，右侧的第一D锁存器的第二电阻R2与电源端VDD之间设置有第六电感L6。左侧的第一D锁存器的第二输出端Q2与右侧的第一D锁存器的第二输入端D2之间设置有串联的第九电阻R9和第七电感L7。左侧的第一D锁存器的第一输出端Q1与右侧的第一D锁存器的第一输入端D1之间设置有串联的第十电阻R10和第八电感L8。右侧的第一D锁存器的第二输出端Q2与第一D触发器的第一输出端Q3之间设置有串联的第十一电阻R11和第九电感L9。右侧的第一D锁存器的第一输出端Q1与第一D触发器的第二输出端Q4之间设置有串联的第十二电阻R12和第十电感L10。第三电感L3、第四电感L4、第五电感L5、第六电感L6、第七电感L7、第八电感L8、第九电感L9和第十电感L10均可以以图9所示的形式实现。
在又一些示例中，如图12所示。在图8所示的多路复用器的基础上，第四电阻R4与电源端VDD之间设置有第十一电感L11，第五电阻R5与电源端VDD之间设置有第十二电感L12。第十一电感L11和第十二电感L12可以以图9所示的形式实现。
在本申请实施例中，在串行接口电路310的D锁存器、D触发器和多路复用器的至少一个中设置金属柱31形成的环线电感，可以增加串行接口电路310的传输速度。例如，可以为串行接口电路310增加50％的传输速度。
在再一些示例中，多路复用器的数据输入端与数据输出端的数量比值为n，n为大于或等于4的整数。图13示出了多路复用器的另一种可能的实施方式。第二多路复用器可以是CML电路，且第二多路复用器为4:1的多路复用器，也就是输入端的数量与输出端的数量的比值为2:1。第二多路复用器的第一输入端D9和第二输入端D10为差分输入端。第二多路复用器的第三输入端D11和第四输入端D12为差分输入端。第二多路复用器的第五输入端D13和第六输入端D14为差分输入端。第二多路复用器的第七输入端D15和第八输入端D16为差分输入端。第二多路复用器的第一输出端Q7和第二输出端Q8为差分输入端。该第二多路复用器包括第九电阻R9、第十电阻R10、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17、第十八晶体管T18、第十九晶体管T19、第二十晶体管T20、第二十一晶体管T21、第二十二晶体管T22、第二十三晶体管T23、第二十四晶体管T24、第二十五晶体管T25、第二十六晶体管T26、第二十七晶体管T27和第二十八晶体管T28。第九电阻R9的第一端和第十电阻R10的第一端连接电源端VDD。第九电阻R9的第二端、第十三晶体管T13的第一端、第十五晶体管T15的第一端、第十七晶体管T17的第一端和第十九晶体管T19的第一端均连接第二多路复用器的第一输出端Q7。第十电阻R10的第二端、第十四晶体管T14的第一端、第十六晶体管T16的第一端、第十八晶体管T18的第一端和第二十晶体管T20的第一端均连接第二多路复用器的第二输出端Q8。第十三晶体管T13的控制端连接第二多路复用器的第一输入端D9。第十四晶体管T14的控制端连接第二多路复用器的第二输入端D10。第十五晶体管T15的控制端连接第二多路复用器的第三输入端D11。第十六晶体管T16的控制端连接第二多路复用器的第四输入端D12。第十七晶体管T17的控制端连接第二多路复用器的第五输入端D13。第十八晶体管T18的控制端连接第二多路复用器的第六输入端D14。第十九晶体管T19的控制端连接第二多路复用器的第七输入端D15。第二十晶体管T20的控制端连接第二多路复用器的第八输入端D16。第十三晶体管T13的第二端和第十四晶体管T14的第二端均连接第二十一晶体管T21的第一端。第十五晶体管T15的第二端和第十六晶体管T16的第二端均连接第二十三晶体管T23的第一端。第十七晶体管T17的第二端和第十八晶体管T18的第二端均连接第二十五晶体管T25的第一端。第十九晶体管T19的第二端和第二十晶体管T20的第二端均连接第二十七晶体管T27的第一端。第二十一晶体管T21的控制端连接第二多路复用器的第一时钟端CLK7。第二十三晶体管T23的控制端连接第二多路复用器的第二时钟端CLK8。第二十五晶体管T25的控制端连接第二多路复用器的第三时钟端CLK9。第二十七晶体管T27的控制端连接第二多路复用器的第四时钟端CLK10。第二十一晶体管T21的第二端连接第二十二晶体管T22的第一端。第二十三晶体管T23的第二端连接第二十四晶体管T24的第一端。第二十五晶体管T25的第二端连接第二十六晶体管T26的第一端。第二十七晶体管T27的第二端连接第二十八晶体管T28的第一端。第二十二晶体管T22的控制端连接第二多路复用器的第四时钟端CLK10。第二十四晶体管T24的控制端连接第二多路复用器的第一时钟端CLK7。第二十六晶体管T26的控制端连接第二多路复用器的第二时钟端CLK8。第二十八晶体管T28的控制端连接第二多路复用器的第三时钟端CLK9。第二十二晶体管T22的第二端、第二十四晶体管T24的第二端、第二十六晶体管T26的第二端和第二十八晶体管T28的第二端均接地。可选地，第一时钟端CLK7至第八时钟端可以均连接相位时钟发生器。其中，第十三晶体管T13和第九电阻R9可以通过一个后道串结构(耦合的一个金属柱31和一个晶体管33)的形式实现。第十四晶体管T14和第十电阻R10可以通过一个后道串结构的形式实现。第十五晶体管T15、第十六晶体管T16、第十七晶体管T17、第十八晶体管T18、第十九晶体管T19、第二十晶体管T20、第二十一晶体管T21、第二十二晶体管T22、第二十三晶体管T23、第二十四晶体管T24、第二十五晶体管T25、第二十六晶体管T26、第二十七晶体管T27和第二十八晶体管T28可以分别通过一个后道串结构的晶体管33的形式实现。这十六个后道串结构通过电连接实现图13所示的电路原理图。
在又一示例中，图13所示的第二多路复用器还可以包括环线电感。第九电阻R9与电源端VDD之间设置有第十三电感L13。第十电阻R10与电源端VDD之间设置有第十四电感L14。第十三电感L13和第十四电感L14可以以图9所示的形式实现。
在本申请实施例中，可以采用较为复杂的n:1多路复用器(n大于或等于4)，在节省面积和工艺成本的基础上，获取更快的传输速度。
在一种可能的实施方式中，可以使用上述图6或图10所示的D锁存器、图7或图10所示的D触发器、以及图8或图12或图13所示的多路复用器构建全三维架构的串行接口电路310。如图14所示，串行接口电路310包括多级并串转换电路、第一D触发器和至少一个分频器。图14仅示出2级并串转换电路，还可以有更少或更多级并串转换电路，本申请实施例在此不做限制。每个并串转换电路包括2路数据输入、1路时钟输入和1路数据输出。第一级的2个并串转换电路可以接收4路数据，第二级的1个并串转换电路可以接收来自第一级并串转换电路的2路数据，第一D触发器可以接收来自第二级并串转换电路的1路数据。每个并串转换电路还可以接收经过分频器处理后的时钟信号。每个并串转换电路的结构可以相同，以虚线框中的并串转换电路为例进行介绍。并串转换电路可以包括2个第一D触发器、第一D锁存器和第一多路复用器。第一D触发器的结构可以参考图7或图11所示的D触发器的结构。第一D锁存器的结构可以参考图6或图10所示的D锁存器的结构。第一多路复用器可以参考图8或图12所示的多路复用器的结构。2个第一D触发器的输出端分别与第一多路复用器的输入端连接，下面的第一D触发器通过第一D锁存器与第一多路复用器连接。各个端口的连接关系如图14所示，本申请实施例在此不再赘述。2个第一D触发器、第一D锁存器和第一多路复用器的时钟端均连接同一时钟。如图15所示，D锁存器、D触发器和多路复用器以三维架构生成在金属层41上。如此，可以更大程度地提高串行接口电路310的传输速度。整体三维架构的串行接口电路310在面积上可以节省约46200平方微米，且功耗和性能会有显著提高。
在一种可能的实施方式中，串行接口电路310还包括带隙基准源，带隙基准源包括后道晶体管，后道晶体管通过后道工艺形成。
示例性地，带隙基准源可以用作前述各个电路(如D锁存器、D触发器或多路复用器)的电压源VDD。如图16所示，带隙基准源和串行接口电路中除带隙基准源以外的其他电路(如D锁存器、D触发器或多路复用器)以三维架构生成在金属层41上。示例性地，其他电路的多个后道串结构可以以图5所示的多列的形式排布。带隙基准源中的多个后道晶体管可以参考图5所示的多个后道晶体管，以多列的形式排布。
在本申请实施例中，通过多个后道晶体管实现带隙基准源。如此可以为串行接口电路310提供专用的偏置电压和电压分布，较好的保持电路的压力、体积、温度(pressure-volume-temperature，PVT)，可以提升电路的可靠性。并且，后道晶体管可以使用存储器的存储单元的掩膜来制作，工艺成本较低。
在一种可能的实施方式中，串行接口电路310所在的芯片300为存储器或接口芯片。可选地，该芯片300还可以是其他芯片，本申请实施例对此不做限制。如此，串行接口电路310的应用场景较为灵活。
本申请实施例还提供了一种芯片制造方法。该方法用于生成芯片300，该芯片300包括串行接口电路310。串行接口电路310包括多个金属柱31，芯片制造方法包括后道工艺。如图17所示，该后道工艺可以包括以下步骤。
S100：通过第一后道掩膜，在金属层上生成多个金属柱31。金属柱31可以与存储器中的存储单元的电容的部分结构相同，第一后道掩膜可以是该存储单元的掩膜。
S200：通过第一后道掩膜，在多个金属柱31之间刻蚀出金属传输线，多个金属柱31通过金属传输线连接作为串行接口电路310的负载器件。
在一些可能的实施方式中，串行接口电路310还包括晶体管33。S100具体可以包括：通过第一后道掩膜，在金属层上生成多个晶体管33，在多个晶体管33的每个晶体管33上生成与晶体管33耦合的金属柱31。耦合的金属柱31和晶体管33的结构可以与存储器中的存储单元的部分结构相同，第一后道掩膜可以是该存储单元的掩膜。
在一些示例中，串行接口电路310还包括多个金属电容焊盘。S100具体还可以包括：通过第一后道掩膜，在金属层上生成多个金属柱31和多个金属电容焊盘32。多个金属电容焊盘32中的至少一个金属电容焊盘32环绕设置在一个金属柱31上。
在一些示例中，所述串行接口电路310还包括带隙基准源，所述带隙基准源包括后道晶体管，该后道工艺还包括：通过第二后道掩膜，在金属层上生成所述后道晶体管。示例性地，带隙基准源用于为串行接口电路中的其他电路提供电源信号。其中，带隙基准源中的后道晶体管可以与存储器中的存储单元的晶体管结构相同，第二后道掩膜可以是该存储单元的晶体管的掩膜。
本申请实施例还提供了一种存储器，该存储器包括控制器和上述芯片300，控制器与芯片300耦合。示例性地，控制器用于控制芯片300读写数据。
本申请实施例还提供了一种接口芯片，该接口芯片包括处理器和上述芯片300，处理器与芯片300耦合。示例性地，该接口芯片可以是交换芯片。
本申请实施例还提供了一种电子设备，该电子设备包括电路板和上述芯片300，芯片300可以设置在电路板上。该电子设备包括但不限于手机、平板电脑、计算机、笔记本电脑、摄像机、照相机、可穿戴设备、车载设备或者终端设备等。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个设备，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，设备或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个设备，或者也可以分布到多个设备上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能模块可以集成在一个设备中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个设备中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种芯片，其特征在于，所述芯片包括串行接口电路，所述串行接口电路包括多个金属柱；所述多个金属柱通过后道工艺形成；所述多个金属柱作为所述串行接口电路的负载器件。
  2. 根据权利要求1所述的芯片，其特征在于，所述串行接口电路还包括多个晶体管，所述多个金属柱中的每个金属柱与所述多个晶体管中的一个晶体管耦合，所述多个晶体管通过后道工艺形成。
  3. 根据权利要求2所述的芯片，其特征在于，所述晶体管为垂直无结场效应晶体管。
  4. 根据权利要求1-3任一项所述的芯片，其特征在于，所述负载器件包括等效电阻器件，所述多个金属柱中的至少一个金属柱作为所述串行接口电路的等效电阻器件。
  5. 根据权利要求1-4任一项所述的芯片，其特征在于，所述负载器件包括等效电感器件，所述等效电感器件包括金属传输线；
    所述多个金属柱以多列的形式排布，不同列的所述金属柱通过所述金属传输线连接作为所述串行接口电路的等效电感器件。
  6. 根据权利要求1-5任一项所述的芯片，其特征在于，所述串行接口电路包括D锁存器、D触发器和多路复用器中的至少一个；所述D锁存器、所述D触发器或所述多路复用器中的至少一个包括所述金属柱。
  7. 根据权利要求6所述的芯片，其特征在于，所述多路复用器的数据输入端与数据输出端的数量比值为n，n为大于或等于4的整数。
  8. 根据权利要求6或7所述的芯片，其特征在于，所述串行接口电路还包括带隙基准源，所述带隙基准源包括后道晶体管，所述后道晶体管通过后道工艺形成。
  9. 根据权利要求1-8任一项所述的芯片，其特征在于，所述串行接口电路还包括多个金属电容焊盘，所述多个金属电容焊盘中的至少一个金属电容焊盘环绕设置在所述金属柱上。
  10. 一种芯片制造方法，其特征在于，用于生成芯片，所述芯片包括串行接口电路；所述串行接口电路包括多个金属柱，所述芯片制造方法包括后道工艺，所述后道工艺包括：
    通过第一后道掩膜，在金属层上生成所述多个金属柱；所述多个金属柱作为所述串行接口电路的负载器件。
  11. 根据权利要求10所述的方法，其特征在于，所述串行接口电路还包括多个晶体管；所述通过第一后道掩膜，在金属层上生成所述多个金属柱，包括：
    通过所述第一后道掩膜，在金属层上生成所述多个晶体管，在所述多个晶体管中的每个晶体管上生成与所述晶体管耦合的金属柱。
  12. 根据权利要求10或11所述的方法，其特征在于，所述串行接口电路还包括带隙基准源，所述带隙基准源包括后道晶体管，所述后道工艺还包括：
    通过第二后道掩膜，在金属层上生成所述后道晶体管。
  13. 根据权利要求10-12任一项所述的方法，其特征在于，所述串行接口电路还包括多个金属电容焊盘；所述通过第一后道掩膜，在金属层上生成所述多个金属柱，包括：
    通过所述第一后道掩膜，在金属层上生成所述多个金属柱和多个金属电容焊盘，所述多个金属电容焊盘中的至少一个金属电容焊盘环绕设置在所述金属柱上。
  14. 一种存储器，其特征在于，所述存储器包括控制器和如权利要求1-9任一项所述的芯片，所述控制器与所述芯片耦合。
  15. 一种接口芯片，其特征在于，所述接口芯片包括处理器和如权利要求1-9任一项所述的芯片，所述处理器和所述芯片耦合。
  16. 一种电子设备，其特征在于，所述电子设备包括电路板和如权利要求1-9任一项所述的芯片，所述芯片设置在所述电路板上。
PCT/CN2025/076890 2024-06-12 2025-02-11 一种芯片、芯片制造方法、存储器、接口芯片和电子设备 Pending WO2025256166A1 (zh)

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