WO2025246729A1 - 阵列基板及触控显示装置 - Google Patents

阵列基板及触控显示装置

Info

Publication number
WO2025246729A1
WO2025246729A1 PCT/CN2025/090189 CN2025090189W WO2025246729A1 WO 2025246729 A1 WO2025246729 A1 WO 2025246729A1 CN 2025090189 W CN2025090189 W CN 2025090189W WO 2025246729 A1 WO2025246729 A1 WO 2025246729A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
insulating layer
sub
connection
touch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/090189
Other languages
English (en)
French (fr)
Inventor
杜瑞芳
张新霞
马小叶
杨坤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025246729A1 publication Critical patent/WO2025246729A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • This disclosure relates to the field of display technology, and more specifically, to an array substrate and a touch display device.
  • TDDI Touch and Display Driver Integration
  • the purpose of this disclosure is to overcome the shortcomings of the prior art and provide an array substrate and a touch display device.
  • an array substrate comprising:
  • a first conductive layer is disposed on one side of the first substrate, and the first conductive layer includes a touch signal line extending along a first direction;
  • An insulating layer group is disposed on the side of the first conductive layer away from the first substrate.
  • the insulating layer group includes a first insulating layer group and a second insulating layer stacked together.
  • the first insulating layer group has a plurality of first vias and a plurality of second vias, and the second insulating layer has a plurality of third vias.
  • a second conductive layer is disposed on at least one layer of the first insulating layer group and on the side of the second insulating layer opposite to the first substrate.
  • the second conductive layer includes a touch electrode, which is connected to the touch signal line through a first via and a third via, as well as a second via and a third via.
  • At least one first via and at least one second via are connected to the same touch signal line, and the third via has a first hole wall and a second hole wall disposed opposite to each other in the first direction.
  • the first via is disposed closer to the first hole wall than the second hole wall
  • the second via is disposed closer to the second hole wall than the first hole wall.
  • the first insulating layer group includes:
  • a first insulating layer is disposed on the side of the first conductive layer away from the first substrate.
  • the first insulating layer has a plurality of first sub-vias and a plurality of second sub-vias.
  • the second insulating layer is disposed on the side of the first insulating layer away from the first substrate.
  • a third insulating layer is disposed on the side of the second insulating layer opposite to the first substrate, and the third insulating layer is provided with a plurality of third sub-vias and a plurality of fourth sub-vias;
  • the first via includes the first sub-via and/or the third sub-via, and the first sub-via and the third sub-via are interconnected;
  • the second via includes the second sub-via and/or the fourth sub-via, and the second sub-via and the fourth sub-via are interconnected.
  • the orthographic projection of the first sub-via on the first substrate is located within the orthographic projection of the third via on the first substrate, and the orthographic projection of the third sub-via on the first substrate at least partially overlaps with the orthographic projection of the third via on the first substrate.
  • the third insulating layer covers the wall of the third via; or, the third insulating layer does not cover the first via wall and covers the second via wall; or, the third insulating layer does not cover the first via wall and does not cover a portion of the side of the second insulating layer facing away from the first substrate near the first via wall, and the third insulating layer covers the second via wall.
  • the orthographic projection of the second sub-via on the first substrate is located within the orthographic projection of the third via on the first substrate, and the orthographic projection of the fourth sub-via on the first substrate at least partially overlaps with the orthographic projection of the third via on the first substrate.
  • the third insulating layer covers the wall of the third via; or, the third insulating layer does not cover the second via wall and covers the first via wall; or, the third insulating layer does not cover the second via wall and does not cover a portion of the side of the second insulating layer facing away from the first substrate near the second via wall, and the third insulating layer covers the first via wall.
  • the first insulating layer and the third insulating layer are made of inorganic materials; the second insulating layer is made of organic materials.
  • the second conductive layer is disposed between the second insulating layer and the third insulating layer, and the touch electrode extends to one end of a second direction within the third via, the second direction intersecting the first direction and being parallel to the side of the first substrate where the first conductive layer is disposed;
  • the array substrate further includes:
  • a third conductive layer is disposed on the side of the third insulating layer opposite to the first substrate.
  • the third conductive layer includes a pixel electrode, a first connection portion, and a second connection portion.
  • the pixel electrode, the first connection portion, and the second connection portion are spaced apart.
  • the first connection portion connects the touch electrode and the touch signal line through the third via and the first via.
  • the second connection portion connects the touch electrode and the touch signal line through the third via and the second via.
  • the second conductive layer is disposed on the side of the third insulating layer opposite to the first substrate; the array substrate further includes:
  • a third conductive layer is disposed between the second insulating layer and the third insulating layer, and the third conductive layer includes a pixel electrode.
  • the array substrate further includes:
  • a gate layer is disposed on one side of the first substrate, the gate layer including a gate and a gate line, the gate being connected to the gate line;
  • a gate insulating layer is disposed on the side of the gate layer opposite to the first substrate.
  • An active layer is disposed on the side of the gate insulating layer away from the first substrate.
  • the active layer includes a channel portion and a source connection portion and a drain connection portion disposed at both ends of the channel portion.
  • the first conductive layer is disposed on the side of the active layer away from the first substrate.
  • the first conductive layer also includes a data line, a source electrode, and a drain electrode.
  • the data line extends along the first direction and is spaced apart from the touch signal line.
  • the source electrode is connected to the data line and to the source electrode connection portion.
  • the drain electrode is connected to the pixel electrode and to the drain electrode connection portion.
  • the first conductive layer further includes a gate and a gate line, the gate being connected to the gate line, the gate line extending along the first direction and spaced apart from the touch signal line;
  • the first insulating layer group further includes:
  • a gate insulating layer is disposed on the side of the first conductive layer opposite to the first substrate, and a plurality of fifth sub-vias and a plurality of sixth sub-vias are disposed on the gate insulating layer;
  • the first via includes a first sub-via, a third sub-via, and a fifth sub-via that are interconnected
  • the second via includes a second sub-via, a fourth sub-via, and a sixth sub-via that are interconnected.
  • the distance between the edge of the orthographic projection of the third sub-via on the first substrate and the edge of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the edge of the orthographic projection of the fourth sub-via on the first substrate and the edge of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the second direction intersects the first direction and is parallel to the side of the first substrate on which the first conductive layer is disposed.
  • the distance between the orthographic projection of the first via wall near the first hole wall on the first substrate and the orthographic projection of the first hole wall on the first substrate is less than or equal to 0.5 micrometers; the distance between the orthographic projection of the first via wall near the second hole wall on the first substrate and the orthographic projection of the second hole wall on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the orthographic projection of the second via wall near the second via wall on the first substrate and the orthographic projection of the second via wall on the first substrate is less than or equal to 0.5 micrometers; the distance between the orthographic projection of the second via wall near the first via wall on the first substrate and the orthographic projection of the first via wall on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the touch electrode is reused as a common electrode.
  • the array substrate includes:
  • the first connection structure includes the first via and the third via
  • the second connection structure includes the second via and the third via.
  • one of the touch electrodes is connected to a touch signal line via alternating first and second connection structures;
  • first connection structures are included in a first connection group
  • at least two of the second connection structures are included in a second connection group
  • one of the touch electrodes is connected to a touch signal line through alternating first and second connection groups.
  • one of the touch electrodes is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through an alternately arranged first connection structure and a second connection structure;
  • At least two of the first connection structures are included in a first connection group
  • at least two of the second connection structures are included in a second connection group
  • one of the touch electrodes is connected to at least two of the touch signal lines, with each of the touch signal lines connected to the touch electrode via alternating first and second connection groups.
  • the first connection structure and the second connection structure connected to two adjacent touch signal lines are staggered.
  • a fourth via is further provided on the first insulating layer group, wherein the orthographic projection of the fourth via onto the first substrate is located in the middle region of the orthographic projection of the third via onto the first substrate; the third via and the fourth via are included in the third connection structure.
  • the first connection structure, the second connection structure, and the third connection structure are included in a third connection group; one touch electrode is connected to one touch signal line through the third connection group; or, one touch electrode is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through the third connection structure.
  • a touch electrode is connected to a touch signal line through a plurality of connection structures; the third connection structure is located at both ends of the plurality of connection structures, and the remaining connection structures include the first connection structure and the second connection structure; or, the third connection structure is located in the middle of the plurality of connection structures, and the remaining connection structures include the first connection structure and the second connection structure.
  • a touch electrode is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through multiple connection structures; among the multiple connection structures, the third connection structure is located at both ends, and the remaining connection structures include the first connection structure and the second connection structure; or, among the multiple connection structures, the third connection structure is located in the middle, and the remaining connection structures include the first connection structure and the second connection structure.
  • one of the touch electrodes is connected to at least two touch signal lines, and the at least two touch signal lines connected to the same touch electrode form a group of touch signal lines.
  • the array substrate further includes:
  • a touch lead is connected to one end of at least two touch signal lines to make at least two touch signal lines connected in parallel.
  • a data line is provided between two adjacent touch signal lines belonging to the same group, and a data line is also provided between two adjacent groups of touch signal lines.
  • a touch display device comprising: an array substrate as described in any one of the preceding claims.
  • Figure 1 is a schematic diagram of the embedded touch display device.
  • Figure 2 is a schematic diagram showing the positional relationship between the touch signal lines and the sub-pixel areas in the embedded touch display device shown in Figure 1.
  • Figure 3 is a schematic diagram of the sub-pixel structure in the embedded touch display device shown in Figure 1.
  • Figure 4 is a schematic diagram of the structure of the touch electrode and touch signal line in the array substrate of this disclosure.
  • Figure 5 is a top view of an example embodiment of the array substrate disclosed herein.
  • Figure 6 is a schematic diagram of the touch electrode structure in Figure 5.
  • Figure 7 is a schematic diagram of the pixel electrode structure in Figure 5.
  • Figure 8 is a magnified view of the part indicated by H in Figure 5.
  • Figure 9 is a schematic cross-sectional view taken along line A-A in Figure 8.
  • Figure 10 is a cross-sectional view of the section cut along line B-B in Figure 8.
  • Figure 11 is a schematic cross-sectional view taken according to the C-C section in Figure 8.
  • Figure 12 is a cross-sectional view of another example embodiment cut along the C-C line in Figure 8.
  • Figure 13 is a cross-sectional view of another example embodiment cut along the C-C line in Figure 8.
  • Figure 14 is a top view of the second and third vias in the array substrate of this disclosure.
  • Figure 15 is a schematic cross-sectional view of the section cut according to the D-D section in Figure 13.
  • Figure 16 is a schematic cross-sectional view taken along line E-E in Figure 13.
  • Figure 17 is a cross-sectional schematic diagram of another example embodiment of the array substrate of this disclosure.
  • Figure 18 is a cross-sectional schematic diagram of the first and third vias in another exemplary embodiment of the array substrate of this disclosure.
  • Figure 19 is a cross-sectional schematic diagram of the second and third vias in another exemplary embodiment of the array substrate of this disclosure.
  • Figure 20 is a schematic diagram of the first example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 21 is a schematic diagram of the second example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 22 is a schematic diagram of the third example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 23 is a schematic diagram of the fourth example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 24 is a schematic diagram of the fifth example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 25 is a top view of the fourth and third vias in the array substrate of this disclosure.
  • Figure 26 is a schematic cross-sectional view of the section cut along line F-F in Figure 25.
  • Figure 27 is a schematic cross-sectional view taken according to the G-G section in Figure 25.
  • Figure 28 is a schematic diagram of the sixth example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 29 is a schematic diagram of the seventh example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 30 is a schematic diagram of the eighth example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 31 is a schematic diagram of the ninth example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 32 is a schematic diagram of the tenth example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 33 is a schematic diagram of the eleventh example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 34 is a schematic diagram of the twelfth example embodiment of the connection structure between the touch electrode and the touch signal line.
  • Figure 35 is a schematic diagram of the structure of the array disclosed herein, showing the interaction between the touch signal line and the data line in the non-display area.
  • Figure 36 is a schematic diagram of an example embodiment of the touch display device of this disclosure.
  • 100 Array substrate; 200, Color filter substrate; 300, Liquid crystal layer; 400, Frame; 1. First substrate; 2. Gate layer; 21. Gate; 22. Gate line; 23. Data lead; 3. Gate insulation layer; 31. Fifth sub-via; 32. Sixth sub-via; 33. Data via; 4. Active layer; 41. Channel section; 42. Source connection section; 43. Drain connection section; 5. First conductive layer; 51. Touch signal line; 51a. Touch signal line group; 52. Data line; 53. Source; 54. Drain; 55. Touch lead; 6. Insulating layer group; 601. Via; 6a. First insulating layer group; 6a1. First via; 6a2. Second via; 6a3, Fourth via; 61.
  • connection should be interpreted broadly.
  • connection can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.
  • And/or is merely a description of the relationship between related objects, indicating that three relationships can exist.
  • a and/or B can represent: A existing alone, A and B existing simultaneously, or B existing alone.
  • character "/" in this document generally indicates that the preceding and following related objects have an "or” relationship.
  • the inventors discovered that the main reason for the low-frequency flickering defect is as follows: Referring to Figures 1 and 2, a portion of the sub-pixels of the array substrate 100 require vias 601 to connect the touch electrode 71 and the touch signal line 51.
  • the vias 601 occupy a certain amount of space.
  • PPI Pixel Per Inch
  • the design of the sub-pixels with vias 601 differs from that of normal sub-pixels. This necessitates a reduction in the common electrode and pixel electrode 84 to accommodate the vias 601 or connecting parts. Consequently, the Cst (storage capacitance) of the sub-pixels with vias 601 is smaller than that of normal sub-pixels, resulting in poorer voltage retention capability, especially at low frequencies, which easily leads to low-frequency flickering.
  • the array substrate 100 may include a first substrate 1, a first conductive layer 5, an insulating layer group 6, and a second conductive layer 7.
  • the first conductive layer 5 is disposed on one side of the first substrate 1 and includes a touch signal line 51 extending along a first direction X.
  • the insulating layer group 6 is disposed on the side of the first conductive layer 5 away from the first substrate 1 and includes a first insulating layer group 6a and a second insulating layer 62 stacked together.
  • the first insulating layer group 6a has a plurality of first vias 6a1 and a plurality of second vias 6a2, and the second insulating layer 62 has a plurality of third vias 621.
  • the second conductive layer 7 is disposed on the first insulating layer group 6a. At least one and a second insulating layer 62 are disposed on the side opposite to the first substrate 1.
  • the second conductive layer 7 includes a touch electrode 71, which is connected to the touch signal line 51 through a first via 6a1 and a third via 621 and a second via 6a2 and a third via 621. At least one first via 6a1 and at least one second via 6a2 are connected to the same touch signal line 51.
  • the third via 621 has a first hole wall 6211 and a second hole wall 6212 disposed opposite to each other in a first direction X. In the first direction X, the first via 6a1 is disposed closer to the first hole wall 6211 than the second hole wall 6212, and the second via 6a2 is disposed closer to the second hole wall 6212 than the first hole wall 6211.
  • the array substrate 100 disclosed herein allows for several advantages. Firstly, regarding the first via 6a1, the overlap distance between the side of the first via 6a1 near the first hole wall 6211 and the third via 621 can be disregarded, thus allowing the first via 6a1 and the third via 621 to be set smaller. Secondly, regarding the second via 6a2, the overlap distance between the side of the second via 6a2 near the second hole wall 6212 and the third via 621 can be disregarded, thus allowing the second via 6a2 and the third via 621 to be set smaller.
  • the touch electrode 71 is not shown in Figure 5.
  • the touch electrode 71 is basically disposed on the entire layer. No touch electrode 71 is disposed at the thin film transistor T.
  • the array substrate 100 may include multiple touch electrodes 71 arranged in an array and multiple touch signal lines 51. Each touch electrode 71 is electrically connected to the corresponding touch signal line 51 through a via 601, thereby being electrically connected to the touch control circuit 9 through the touch signal line 51.
  • the array substrate 100 may include multiple pixel regions P (four pixel regions P1, P2, P3 and P4 are shown in FIG2 for illustrative purposes), each pixel region P includes three sub-pixel regions (see SP1, SP2 and SP3), each sub-pixel region is defined by adjacent gate lines 22 (two gate lines 221 and 222 are shown in FIG2 for illustrative purposes) and adjacent data lines 52 (521 to 526 are shown in FIG2 for illustrative purposes) intersecting each other.
  • the array substrate 100 also includes multiple touch signal lines 51 located on the first substrate 1 ( Figure 2 shows 511 to 512 as examples). These multiple touch signal lines 51 extend along a first direction X and are arranged sequentially along a second direction Y. Each touch signal line 51 passes through an opening area of the sub-pixel region SP that is not blocked by the black matrix layer in the display device.
  • a via 601 is provided at the sub-pixel region SP3 of the pixel region P1.
  • the touch electrode 71 and the touch signal line 51 are connected through the via 601.
  • the Cst (storage capacitance) of the sub-pixel region SP3 is smaller than that of the normal sub-pixel regions SP1 and SP2. This results in the voltage retention capability of the sub-pixel region SP3 being worse than that of the normal sub-pixels, especially at low frequencies, which can easily cause low-frequency flicker.
  • the first substrate 1 may be a glass substrate; of course, in some other example embodiments of this disclosure, the first substrate 1 may also be quartz, etc.; the first substrate 1 may also include an insulating material layer, which may be disposed on one side of the glass substrate, and the insulating material layer may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate.
  • a gate layer 2 may be disposed on one side of the first substrate 1.
  • the gate layer 2 may include multiple gate lines 22 and multiple gates 21.
  • the gate lines 22 may extend along the second direction Y, and the multiple gates 21 arranged along the second direction Y may be connected to the same gate line 22, or a portion of the gate line 22 may serve as a gate 21.
  • a gate insulating layer 3 is provided on the side of the gate layer 2 away from the first substrate 1.
  • An active layer 4 is provided on the side of the gate insulating layer 3 away from the first substrate 1.
  • the active layer may include a channel portion 41 and conductor portions disposed at both ends of the channel portion 41.
  • One of the two conductor portions is a source connection portion 42, and the other is a drain connection portion 43.
  • the channel portion 41 is disposed on the side of the gate line 22 away from the first substrate 1, that is, a portion of the gate line 22 opposite to the channel portion 41 serves as the gate 21.
  • a first conductive layer 5 is disposed on the side of the active layer 4 away from the first substrate 1.
  • the first conductive layer 5 may include a source electrode 53, a drain electrode 54, a data line 52, and a touch signal line 51.
  • the touch signal line 51 extends along a first direction X
  • the data line 52 extends along the first direction X.
  • the first direction X intersects with the second direction Y, for example, the first direction X may be perpendicular to the second direction Y.
  • the source 53 is connected to the data line 52 and to the source connection portion 42, thereby connecting the source connection portion 42 and the data line 52 through the source 53;
  • the drain 54 is connected to the subsequently formed pixel electrode and to the drain connection portion 43, thereby connecting the drain connection portion 43 and the pixel electrode through the drain 54.
  • the gate 21, the channel portion 41, the source 53, the drain 54, and the source connection portion 42 and the drain connection portion 43 form a switching unit, which is a thin-film transistor.
  • the thin-film transistor described in this specification is a bottom-gate thin-film transistor.
  • the thin-film transistor may also be a top-gate or dual-gate type, and its specific structure will not be described in detail here.
  • the functions of the "source 53" and “drain 54" are sometimes interchanged. Therefore, in this specification, the "source 53" and “drain 54" can be interchanged.
  • an insulating layer group 6 is provided on the side of the first conductive layer 5 away from the first substrate 1.
  • the insulating layer group 6 may include a first insulating layer group 6a and a second insulating layer 62.
  • the material of the first insulating layer group 6a may include inorganic materials, such as silicon nitride, silicon oxide, etc.
  • the material of the second insulating layer 62 may include organic materials, such as polyimide, polycarbonate, polyacrylate, etc.
  • the material of the second insulating layer 62 may be photoresist.
  • the first insulating layer group 6a may also include organic materials
  • the second insulating layer 62 may also include inorganic materials.
  • the first insulating layer group 6a and the second insulating layer 62 are not shown; only the first via 6a1, the second via 6a2, and the third via 621 are shown.
  • the first insulating layer group 6a has multiple first vias 6a1 and multiple second vias 6a2.
  • At least one first via 6a1 and at least one second via 6a2 are connected to the same touch signal line 51. That is, the orthographic projection of at least one first via 6a1 and at least one second via 6a2 on the substrate overlaps with the orthographic projection of the same touch signal line 51 on the substrate.
  • at least two portions of the same touch signal line 51 are not covered by the first insulating layer group 6a.
  • one first via 6a1 and one second via 6a2 can be connected to the same touch signal line 51, or two or more first vias 6a1 and two or more second vias 6a2 can be connected to the same touch signal line 51.
  • the first insulating layer group 6a may include a first insulating layer 61, which is disposed on the side of the first conductive layer 5 away from the first substrate 1.
  • the material of the first insulating layer 61 may be an inorganic material, such as silicon nitride, silicon oxide, etc.
  • the first insulating layer 61 is provided with a plurality of first sub-vias 611 and a plurality of second sub-vias 612.
  • a second insulating layer 62 is provided on the side of the first insulating layer 61 facing away from the first substrate 1.
  • a plurality of third vias 621 are provided on the second insulating layer 62.
  • the third vias 621 have a first hole wall 6211 and a second hole wall 6212 disposed opposite to each other in the first direction X.
  • the second conductive layer 7 is disposed on at least one layer of the first insulating layer group 6a and on the side of the second insulating layer 62 away from the first substrate 1. Specifically, the second conductive layer 7 is disposed on the side of the second insulating layer 62 away from the first substrate 1.
  • the second conductive layer 7 may include a touch electrode 71. Referring to FIG4, the touch electrode 71 is connected to the touch signal line 51 through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621.
  • the second conductive layer 7 can be made of a transparent conductive material.
  • the first conductive layer 5 can be made of ITO (indium tin oxide), IZO (indium zinc oxide), etc.
  • the touch electrode 71 extends to one end of the third via 621 in the second direction Y. That is, the touch electrode 71 does not occupy the entire third via 621, but only one end in the second direction Y.
  • the other part of the third via 621 in the second direction Y is for exposing the touch signal line 51.
  • the first via 6a1 and the second via 6a2 are offset in the first direction X. Regardless of the offset, as long as the first via 6a1 is connected to the third via 621 or the second via 6a2 is connected to the third via 621, the connection between the touch electrode 71 and the touch signal line 51 can be guaranteed.
  • the touch electrode 71 can be reused as a common electrode.
  • the touch electrode 71 can be time-division multiplexed as a common electrode. That is, during the first time period, a touch signal is applied to the touch signal line 51, and the touch electrode 71 is used as a touch electrode to realize the touch function; during the second time period, a common voltage is applied to the touch signal line 51, and the touch electrode 71 is used as a common electrode to realize the display function.
  • the first insulating layer group 6a may further include a third insulating layer 63.
  • the third insulating layer 63 is disposed on the side of the second conductive layer 7 away from the first substrate 1, that is, the second conductive layer 7 is disposed between the second insulating layer 62 and the third insulating layer 63.
  • the material of the third insulating layer 63 can be an inorganic material, such as silicon nitride, silicon oxide, etc.
  • the third insulating layer 63 is provided with a plurality of third sub-vias 631 and a plurality of fourth sub-vias 632.
  • the first via 6a1 may include a first sub-via 611 and a third sub-via 631, which are interconnected, i.e., the third sub-via 631 is connected to the first sub-via 611.
  • the second via 6a2 may include a second sub-via 612 and a fourth sub-via 632, which are interconnected, i.e., the fourth sub-via 632 is connected to the second sub-via 612, thereby enabling at least one third sub-via 631 and at least one fourth sub-via 632 to be connected to the same touch signal line 51.
  • At least one third sub-via 631 and at least one fourth sub-via 632 are connected to the same touch electrode 71, i.e., the same touch electrode 71 is exposed at the locations of at least one third sub-via 631 and at least one fourth sub-via 632 where it is not covered by the third insulating layer 63.
  • the first insulating layer group 6a may include only the first insulating layer 61.
  • the second conductive layer 7 is disposed on the side of the second insulating layer 62 away from the first substrate 1, the first via 6a1 may include only the first sub-via 611, and the second via 6a2 may include only the second sub-via 612; the first insulating layer group 6a may include only the third insulating layer 63.
  • the first via 6a1 may include only the third sub-via 631, and the second via 6a2 may include only the fourth sub-via 632.
  • the third via 621 formed first needs to be set larger so that the periphery of the third via 621 forms an overlay margin with the periphery of the first via 6a1 and the periphery of the second via 6a2. This ensures that the first via 6a1 and the second via 6a2 formed later can be connected to the third via 621 to realize the electrical connection between the touch electrode 71 and the touch signal line 51.
  • the first via 6a1 in the first direction, is disposed closer to the second hole wall 6211 than the second hole wall 6212, such that the first via 6a1 is located on one side of the third via 621 in the first direction X; the second via 6a2 is disposed closer to the second hole wall 6212 than the first hole wall 6211, such that the second via 6a2 is located on the opposite side of the third via 621 in the first direction X; that is, the first via 6a1 and the second via 6a2 are disposed off-center from the third via 621 relative to the center of the third via 621.
  • the overlap distance between the side of the first via 6a1 closest to the first hole wall 6211 and the third via 621 can be disregarded, thus allowing the first via 6a1 and the third via 621 to be set smaller;
  • the overlap distance between the side of the second via 6a2 closest to the second hole wall 6212 and the third via 621 can be disregarded, thus allowing the second via 6a2 and the third via 621 to be set smaller, thereby increasing the setting space for the capacitance of the sub-pixel to ensure the voltage holding capability of the sub-pixel and avoid the defect of low-frequency flicker.
  • first via 6a1 and the second via 6a2 are located at opposite ends of the third via 621, even if the alignment process of the mask plate deviates during the patterning process, and the second via 6a2 shifts towards the center of the third via 6211 when it shifts towards the first hole wall 6211, although the first via 6a1 and the third via 621 may have poor communication, this causes the second via 6a2 to shift towards the center of the third via 621, thereby ensuring the communication between the second via 6a2 and the third via 621, and thus ensuring the connection between the touch electrode 71 and the touch signal line 51.
  • a third conductive layer 8 is provided on the side of the third insulating layer 63 facing away from the first substrate 1.
  • the material of the third conductive layer 8 can be a transparent conductive material.
  • the material of the first conductive layer 5 can be ITO (indium tin oxide), IZO (indium zinc oxide), etc.
  • the third conductive layer 8 may include a pixel electrode 84, a first connecting portion 81, and a second connecting portion 82.
  • the pixel electrode 84, the first connecting portion 81, and the second connecting portion 82 are spaced apart, that is, there is no connection between the pixel electrode 84, the first connecting portion 81, and the second connecting portion 82.
  • the first connecting part 81 connects the touch control electrode 71 and the touch signal line 51 through the third via 621 and the first via 6a1
  • the second connecting part 82 connects the touch control electrode 71 and the touch signal line 51 through the third via 621 and the second via 6a2.
  • the touch control electrode 71 and the touch signal line 51 are connected as a single unit through the first connecting part 81 and the second connecting part 82, and touch signals can be transmitted to the touch electrode 71 through the touch signal line 51.
  • This configuration reduces the opening area of the first via 6a1, the second via 6a2, and the third via 621, thereby reducing the area of the first connecting portion 81 and the second connecting portion 82.
  • This increases the area of the pixel electrode 84 and the Cst of the sub-pixel with the via, ensuring the voltage retention capability of the sub-pixel with the via and preventing low-frequency flicker.
  • the orthogonal projection of the first sub-via 611 on the first substrate 1 is located within the orthogonal projection of the third via 621 on the first substrate 1. Specifically, the area of the orthogonal projection of the first sub-via 611 on the first substrate 1 is smaller than the area of the orthogonal projection of the third via 621 on the first substrate 1, and the orthogonal projection of the third via 621 on the first substrate 1 completely covers the orthogonal projection of the first sub-via 611 on the first substrate 1.
  • the orthographic projection of the third via 631 on the first substrate 1 at least partially overlaps with the orthographic projection of the third via 621 on the first substrate 1.
  • the orthographic projection of the third sub-via 631 on the first substrate 1 may be located within the orthographic projection of the third via 621 on the first substrate 1, and one side edge of the orthographic projection of the third sub-via 631 on the first substrate 1 may coincide with the orthographic projection of the first hole wall 6211 of the third via 621 on the first substrate 1, such that at the first via 6a1 and the third via 621, the third insulating layer 63 does not cover the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212.
  • a portion of the orthographic projection of the third sub-via 631 on the first substrate 1 may overlap with a portion of the orthographic projection of the third via 621 on the first substrate 1, such that at the first via 6a1 and the third via 621, the third insulating layer 63 does not cover the first hole wall 6211 and does not cover the portion of the side of the second insulating layer away from the first substrate 1 near the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212.
  • the orthogonal projection of the third sub-via 631 on the first substrate 1 may be located within the orthogonal projection of the third via 621 on the first substrate 1, so that at the first via 6a1 and the third via 621, the third insulating layer 63 covers the hole wall of the third via 621, that is, the third insulating layer 63 almost completely covers the surrounding hole walls of the third via 621.
  • the third insulating layer 63 covers the two sidewalls of the third via 621 that are disposed opposite to each other in the second direction Y.
  • the orthogonal projection of the second sub-via 612 on the first substrate 1 is located within the orthogonal projection of the third via 621 on the first substrate 1. Specifically, the area of the orthogonal projection of the second sub-via 612 on the first substrate 1 is smaller than the area of the orthogonal projection of the third via 621 on the first substrate 1, and the orthogonal projection of the third via 621 on the first substrate 1 completely covers the orthogonal projection of the second sub-via 612 on the first substrate 1.
  • the orthographic projection of the fourth sub-via 632 on the first substrate 1 at least partially overlaps with the orthographic projection of the third via 621 on the first substrate 1.
  • the orthographic projection of the fourth sub-via 632 on the first substrate 1 may be located within the orthographic projection of the third via 621 on the first substrate 1, and one side edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 may coincide with the orthographic projection of the second hole wall 6212 of the third via 621 on the first substrate 1, such that at the second via 6a12 and the third via 621, the third insulating layer 63 does not cover the second hole wall 6212, and the third insulating layer 63 covers the first hole wall 6211.
  • the orthogonal projection of the fourth sub-via 632 on the first substrate 1 may be located within the orthogonal projection of the third via 621 on the first substrate 1, so that at the second via 6a12 and the third via 621, the third insulating layer 63 covers the hole wall of the third via 621, that is, the third insulating layer 63 almost completely covers the surrounding hole walls of the third via 621.
  • the third insulating layer 63 not covering the second hole wall 6212 and not covering a portion of the side of the second insulating layer facing away from the first substrate 1 near the second hole wall 6212 at the second via 6a12 and the third via 621, and the third insulating layer 63 covering the first hole wall 6211.
  • the third insulating layer 63 covers the two sidewalls of the third via 621 that are disposed opposite to each other in the second direction Y.
  • the second conductive layer 7 is disposed on the side of the third insulating layer 63 facing away from the first substrate 1; the touch electrode 71 can be directly connected to the touch signal line 51 through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621, without the need for the first connection portion 81 and the second connection portion 82.
  • the array substrate may also include a third conductive layer 8, which is disposed between the second insulating layer 62 and the third insulating layer 63, and includes a pixel electrode 84.
  • connection between the touch electrode 71 and the touch signal line 51 also requires the connection through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621, the above-mentioned arrangement of the first via 6a1, second via 6a2 and third via 621 is also applicable to this example embodiment, and the specific structure will not be described here.
  • the first conductive layer 5 may further include a gate 21 and a gate line 22, that is, the first conductive layer 5 is the gate layer 2.
  • the touch signal line 51 and the gate line 22 are disposed on the same layer to avoid the touch signal line 51 and the gate line 22 from crossing.
  • the gate line 22 also extends along the first direction X and is spaced apart from the touch signal line 51.
  • the gate 21 is connected to the gate line 22, and its specific structure will not be described in detail here.
  • the first insulating layer group 6a may further include a gate insulating layer 3.
  • the gate insulating layer 3 is disposed on the side of the first conductive layer 5 away from the first substrate 1.
  • the gate insulating layer 3 is provided with a plurality of fifth sub-vias 31 and a plurality of sixth sub-vias 32.
  • the plurality of fifth sub-vias 31 and the plurality of sixth sub-vias 32 are formed in the same patterning process as the first sub-vias 611 and the second sub-vias 612 on the first insulating layer 61 and the third sub-vias 631 and the fourth sub-vias 632 on the third insulating layer 63.
  • first via 6a1 to include the interconnected first sub-vias 611, the third sub-vias 631 and the fifth sub-vias 31, and the second via 6a2 to include the interconnected second sub-vias 612, the fourth sub-vias 632 and the sixth sub-vias 32.
  • the orthographic projection of the fifth sub-via 31 on the first substrate 1 is located within the orthographic projection of the third via 621 on the first substrate 1. Specifically, the area of the orthographic projection of the fifth sub-via 31 on the first substrate 1 is smaller than the area of the orthographic projection of the third via 621 on the first substrate 1, and the orthographic projection of the third via 621 on the first substrate 1 completely covers the orthographic projection of the fifth sub-via 31 on the first substrate 1.
  • the orthographic projection of the sixth sub-via 32 on the first substrate 1 is located within the orthographic projection of the third via 621 on the first substrate 1. Specifically, the area of the orthographic projection of the sixth sub-via 32 on the first substrate 1 is smaller than the area of the orthographic projection of the third via 621 on the first substrate 1, and the orthographic projection of the third via 621 on the first substrate 1 completely covers the orthographic projection of the sixth sub-via 32 on the first substrate 1.
  • this example embodiment limits the touch signal line 51 to be located in the gate layer 2. Therefore, other structures in the above example embodiment can be combined as long as they do not conflict with this example embodiment, and will not be described one by one here.
  • the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.
  • the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100.
  • the third sub-via 631 needs to be reduced, which may easily lead to the third sub-via 631 and the third via 621 being unable to communicate.
  • the above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the third sub-via 631 and the third via 621 are connected.
  • the distance between the corresponding edge lines of the orthographic projection of the first sub-via 611 near the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is the length of the touch electrode 71 extending into the third sub-via 621, and the distance between the corresponding edge lines of the orthographic projection of the first sub-via 611 away from the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is also greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.
  • the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100.
  • the fourth sub-via 632 needs to be reduced, which may result in the fourth sub-via 632 and the third via 621 being unable to communicate.
  • the above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the fourth sub-via 632 and the third via 621 are connected.
  • the distance between the corresponding edge lines of the orthographic projection of the second sub-via 612 near the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is the length of the touch electrode 71 extending into the third sub-via 621, and the distance between the corresponding edge lines of the orthographic projection of the second sub-via 612 away from the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is also greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is less than or equal to 0.5 micrometers.
  • the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 can be 0.05 micrometers, 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, 0.35 micrometers, 0.4 micrometers, 0.45 micrometers, etc.
  • the first via 6a1 will deviate too far from the center of the third via 621, or the first via 6a1 will not deviate much from the center of the third via 621. This will result in the first via 6a1 being set too large, failing to achieve the purpose of reducing the first via 6a1 to reduce the first connection portion 81 and increase the pixel electrode 84, and low-frequency flickering will still occur.
  • the first via 6a1 may include a first sub-via 611 and a third sub-via 631
  • the first sub-via 611 will not be offset to the outside of the third via 621 due to the shielding of the second insulating layer 62.
  • the hole wall of the first sub-via 611 near the first hole wall 6211 is basically flush with the first hole wall 6211.
  • the above-mentioned numerical range may refer to the distance between the orthographic projection of the hole wall of the third sub-via 631 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1.
  • the distance between the orthographic projection of the first via 6a1 near the second via wall 6212 on the first substrate 1 and the orthographic projection of the second via wall 6212 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the orthographic projection of the first via 6a1 near the second via wall 6212 on the first substrate 1 and the orthographic projection of the second via wall 6212 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.
  • the first via 6a1 and the second via 6a2 on the first insulating layer group 6a and the third via 621 on the second insulating layer 62 are formed by two different patterning processes. Due to the deviation of the mask alignment process during the two patterning processes, the deviation range is between -2 micrometers and +2 micrometers (positive and negative indicate direction).
  • the third via 621 formed first needs to be set to a larger value to ensure that the first via 6a1 and the second via 6a2 formed later can be connected to the third via 621.
  • the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100, or the first via 6a1 needs to be reduced, which may easily lead to the first via 6a1 and the third via 621 being unable to communicate.
  • the above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the first via 6a1 and the third via 621 are connected.
  • the walls of the first sub-via 611, the third sub-via 631, the first hole wall 6211, and the second hole wall 6212 are generally all inclined, the orthogonal projections of the walls of the third sub-via 631, the first hole wall 6211, and the second hole wall 6212 on the first substrate 1 have a certain width. Therefore, the wall of the third sub-via 631 near the first hole wall 6211 needs to be in a corresponding position, and the wall of the third sub-via 631 near the second hole wall 6212 also needs to be in a corresponding position. For example, they can all be away from the edge of the first substrate 1, or they can all be close to the edge of the first substrate 1.
  • the distance between the orthographic projection of the second via 6a2 near the second hole wall 6212 on the first substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate 1 is less than or equal to 0.5 micrometers.
  • the distance between the orthographic projection of the second via 6a2 near the second hole wall 6212 on the first substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate 1 can be 0.05 micrometers, 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, 0.35 micrometers, 0.4 micrometers, 0.45 micrometers, etc.
  • the second via 6a2 will deviate too far from the center of the third via 621, or the second via 6a2 will not deviate much from the center of the third via 621. This will result in the second via 6a2 being set too large, failing to achieve the purpose of reducing the second via 6a2 to reduce the second connection portion 82 and increase the pixel electrode 84, and low-frequency flickering will still occur.
  • the second via 6a2 may include the second sub-via 612 and the fourth sub-via 632
  • the second sub-via 612 when a part of the second via 6a2 is offset to the outside of the third via 621, the second sub-via 612 will not be offset to the outside of the third via 621 due to the shielding of the second insulating layer 62.
  • the hole wall of the second sub-via 612 near the second hole wall 6212 is basically flush with the second hole wall 6212.
  • the above-mentioned numerical range may refer to the distance between the orthographic projection of the hole wall of the fourth sub-via 632 near the second hole wall 6212 on the first substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate 1.
  • the distance between the orthographic projection of the second via 6a2 near the first via wall 6211 on the first substrate 1 and the orthographic projection of the first via wall 6211 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.
  • the distance between the orthographic projection of the second via 6a2 near the first via wall 6211 on the first substrate 1 and the orthographic projection of the first via wall 6211 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.
  • the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100, or the second via 6a2 needs to be reduced, which may easily lead to the second via 6a2 and the third via 621 being unable to communicate.
  • the above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the second via 6a2 and the third via 621 are connected.
  • the walls of the second sub-via 612, the fourth sub-via 632, the first hole wall 6211, and the second hole wall 6212 are generally all inclined, the orthogonal projections of the walls of the fourth sub-via 632, the first hole wall 6211, and the second hole wall 6212 on the first substrate 1 have a certain width. Therefore, the wall of the fourth sub-via 632 near the first hole wall 6211 needs to be in a corresponding position, and the wall of the fourth sub-via 632 near the second hole wall 6212 also needs to be in a corresponding position. For example, they can all be away from the edge of the first substrate 1, or they can all be close to the edge of the first substrate 1.
  • the first sub-via 611 has a size greater than or equal to 2 micrometers and less than or equal to 15 micrometers in the first direction X.
  • the size of the first sub-via 611 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, etc.
  • the second sub-via 612 has a size greater than or equal to 2 micrometers and less than or equal to 15 micrometers in the first direction X.
  • the size of the second sub-via 612 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, etc.; this reduces the size by 15%-35% compared to the structure in the prior art.
  • the size of the third via 621 in the first direction X is greater than or equal to 2 micrometers and less than or equal to 20 micrometers.
  • the size of the third via 621 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, 15 micrometers, 18 micrometers, etc.; which is 15%-35% smaller than the structure in the prior art.
  • the third sub-via 631 has a dimension in the first direction X that is greater than or equal to 2 micrometers and less than or equal to 20 micrometers.
  • the dimension of the third sub-via 631 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, 15 micrometers, 18 micrometers, etc.
  • the fourth sub-via 632 has a dimension in the first direction X that is greater than or equal to 2 micrometers and less than or equal to 20 micrometers.
  • the dimension of the fourth sub-via 632 in the first direction X can be 5 micrometers, 7 micrometers, 10 micrometers, 13 micrometers, 15 micrometers, 18 micrometers, etc. This reduces the size by 15%-35% compared to the structure in the prior art.
  • the array substrate may include a first connection structure 11 and a second connection structure 12; the first connection structure may include a first via 6a1 and a third via 621; the second connection structure may include a second via 6a2 and a third via 621.
  • the first connection portion 81, the third via 621, and the first via 6a1 are included in the first connection structure 11, that is, the first connection structure 11 may include the first connection portion 81 and the interconnected third via 621 and the first via 6a1; the second connection portion 82, the third via 621, and the second via 6a2 are included in the second connection structure 12, that is, the second connection structure 12 may include the second connection portion 82, the interconnected third via 621, and the second via 6a2.
  • a touch electrode 71 is connected to a touch signal line 51 through alternating first connection structures 11 and second connection structures 12, such that a second connection structure 12 is provided between two adjacent first connection structures 11, and a first connection structure 11 is provided between two adjacent second connection structures 12; for example, both the first connection structure 11 and the second connection structure 12 can be set to ten; referring to Figure 20, the first one can be a first connection structure 11; referring to Figure 21, the first one can be a second connection structure 12.
  • At least two first connection structures 11 are included in the first connection group 14, that is, the first connection group 14 may include at least two first connection structures 11.
  • the first connection group 14 may include two first connection structures 11, or the first connection group 14 may include three or more first connection structures 11.
  • At least two second connection structures 12 are included in the second connection group 15, that is, the second connection group 15 may include at least two second connection structures 12.
  • the second connection group 15 may include two second connection structures 12, or the second connection group 15 may include three or more second connection structures 12.
  • a touch electrode 71 is connected to a touch signal line 51 through alternating first connection group 14 and second connection group 15, such that a second connection group 15 is provided between two adjacent first connection groups 14, and a first connection group 14 is provided between two adjacent second connection groups 15;
  • the initial group can be a first connection group 14; the initial group can also be a second connection group 15.
  • a touch electrode 71 is connected to at least two touch signal lines 51.
  • the at least two touch signal lines 51 can be connected in parallel.
  • a touch electrode 71 can be connected to two touch signal lines 51, or a touch electrode 71 can be connected to three or more touch signal lines 51.
  • Each touch signal line 51 is connected to the touch electrode 71 via an alternately arranged first connection structure 11 and second connection structure 12.
  • the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512.
  • the first touch signal line 511 is connected to the touch electrode 71 via an alternately arranged first connection structure 11 and second connection structure 12
  • the second touch signal line 512 is also connected to the touch electrode 71 via an alternately arranged first connection structure 11 and second connection structure 12.
  • a second connection structure 12 is provided between two adjacent first connection structures 11, and a first connection structure 11 is provided between two adjacent second connection structures 12.
  • first connection structures 11 and ten second connection structures 12 connected to each touch signal line 51;
  • the first connection structure can be a first connection structure 11, and the first connection structure can be a second connection structure 12.
  • the initial connection structures of two adjacent touch signal lines 51 can be the same or different.
  • At least two first connection structures 11 are included in the first connection group 14, that is, the first connection group 14 may include at least two first connection structures 11.
  • the first connection group 14 may include two first connection structures 11, or the first connection group 14 may include three or more first connection structures 11.
  • At least two second connection structures 12 are included in the second connection group 15, that is, the second connection group 15 may include at least two second connection structures 12.
  • the second connection group 15 may include two second connection structures 12, or the second connection group 15 may include three or more second connection structures 12.
  • a touch electrode 71 is connected to at least two touch signal lines 51.
  • the at least two touch signal lines 51 can be connected in parallel.
  • a touch electrode 71 can be connected to two touch signal lines 51, or a touch electrode 71 can be connected to three or more touch signal lines 51.
  • Each touch signal line 51 is connected to the touch electrode 71 via an alternately arranged first connection group 14 and second connection group 15.
  • the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512.
  • the first touch signal line 511 is connected to the touch electrode 71 via an alternately arranged first connection group 14 and second connection group 15, and the second touch signal line 512 is also connected to the touch electrode 71 via an alternately arranged first connection group 14 and second connection group 15.
  • a second connection group 15 is provided between two adjacent first connection groups 14, and a first connection group 14 is provided between two adjacent second connection groups 15.
  • the number of first connection groups 14 and second connection groups 15 connected to each touch signal line 51 can be ten; the first group can be a first connection group 14; the first group can be a second connection group 15. Furthermore, the initial connection structures of two adjacent touch signal lines 51 can be the same or different.
  • first connection structure 11 and the second connection structure 12 connected to two adjacent touch signal lines 51 are staggered, that is, the first connection structure 11 and the second connection structure 12 connected to two adjacent touch signal lines 51 are not arranged opposite each other, so as to avoid mutual interference between the first connection structure 11 and the second connection structure 12.
  • a fourth via 6a3 is further provided on the first insulating layer group 6a.
  • the fourth via 6a3 may include a seventh sub-via 613 provided on the first insulating layer 61 and an eighth sub-via 633 provided on the third insulating layer 63.
  • the orthographic projection of the fourth via 6a3 on the first substrate 1 is located in the middle region of the orthographic projection of the third via 621 on the first substrate 1. That is, the entire orthographic projection of the fourth via 6a3 on the first substrate 1 overlaps with the middle region of the orthographic projection of the third via 621 on the first substrate 1. In other words, the distance between each hole wall of the fourth via 6a3 and each hole wall of the third via 621 is substantially the same.
  • the third conductive layer 8 may also include a third connection portion 83.
  • the third connection portion 83 is spaced apart from the pixel electrode 84, the first connection portion 81, and the second connection portion 82, that is, there is no connection between the third connection portion 83 and the pixel electrode 84, the first connection portion 81, and the second connection portion 82.
  • the third connection portion 83 is connected to the touch electrode 71 and the touch signal line 51 through the fourth via 6a3 and the third via 621.
  • the touch signal line 51 can transmit touch signals to the touch electrode 71.
  • the third via 621 and the fourth via 6a3 are included in the third connecting structure 13.
  • the third connecting part 83, the fourth via 6a3 and the third via 621 are included in the third connecting structure 13, that is, the third connecting structure 13 may include the third connecting part 83, the fourth via 6a3 and the third via 621.
  • the first connecting structure 11, the second connecting structure 12, and the third connecting structure 13 are included in the third connecting group 16. That is, the third connecting group 16 may include one first connecting structure 11, one second connecting structure 12, and one third connecting structure 13.
  • the first connecting structure 11, the third connecting structure 13, and the second connecting structure 12 can be arranged in sequence, or the first connecting structure 11, the second connecting structure 12, and the third connecting structure 13 can be arranged in sequence.
  • other arrangements are also possible, which will not be described in detail here.
  • a touch electrode 71 is connected to a touch signal line 51 through a third connection group 16.
  • a touch electrode 71 is connected to a touch signal line 51 through a third connection group 16, or a touch electrode 71 is connected to a touch signal line 51 through two or more third connection groups 16.
  • a touch electrode 71 is connected to at least two touch signal lines 51.
  • a touch electrode 71 may be connected to two touch signal lines 51, or a touch electrode 71 may be connected to three or more touch signal lines 51.
  • Each touch signal line 51 is connected to the touch electrode 71 through the third connection structure 13; for example, when two touch signal lines 51 are connected to one touch electrode 71, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512.
  • the first touch signal line 511 is connected to the touch electrode 71 through the third connection structure 13; the second touch signal line 512 is also connected to the touch electrode 71 through the third connection structure 13.
  • a touch electrode 71 is connected to a touch signal line 51 through multiple connection structures; among the multiple connection structures, the third connection structure 13 is located at both ends, and the remaining connection structures include a first connection structure 11 and a second connection structure 12; the first connection structure 11 and the second connection structure 12 can be arranged in an overlapping manner.
  • the third connection structure 13 is located in the middle of the multiple connection structures, and the remaining connection structures include the first connection structure 11 and the second connection structure 12; the first connection structure 11 and the second connection structure 12 can be arranged in an overlapping manner.
  • a touch electrode 71 is connected to at least two touch signal lines 51.
  • a touch electrode 71 may be connected to two touch signal lines 51, or a touch electrode 71 may be connected to three or more touch signal lines 51.
  • Each touch signal line 51 is connected to the touch electrode 71 through multiple connection structures; for example, when two touch signal lines 51 are connected to one touch electrode 71, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512.
  • the first touch signal line 511 is connected to the touch electrode 71 through multiple connection structures; the second touch signal line 512 is also connected to the touch electrode 71 through multiple connection structures.
  • connection structure 13 is located in the middle of the multiple connection structures, and the remaining connection structures may include the first connection structure 11 or the second connection structure 12.
  • the first connection structure 11 and the second connection structure 12 may be arranged in an overlapping manner.
  • the third connection structure 13 is located at both ends of the multiple connection structures, and the remaining connection structures may include the first connection structure 11 and the second connection structure 12; the first connection structure 11 and the second connection structure 12 may be arranged in an overlapping manner.
  • the middle part of multiple connection structures is not only the one located in the exact middle of multiple connection structures.
  • the middle part of nine connection structures can be the fifth one, that is, the fifth one of the nine connection structures is the third connection structure 13.
  • the middle part of multiple connection structures can also be a middle region.
  • the middle part of nine connection structures can be the fourth, fifth and sixth, and the middle part of ten connection structures can be the fourth, fifth, sixth and seventh.
  • a first connection structure 11 or a second connection structure 12 may be provided between two adjacent third connection structures 13, and the first connection structure 11 and the second connection structure 12 may be alternately provided between two adjacent third connection structures 13.
  • a touch electrode 71 is connected to at least two touch signal lines 51, and the at least two touch signal lines 51 connected to the same touch electrode 71 form a group of touch signal lines 51a.
  • the array substrate may also include touch leads 55, which may be located in the non-display area where the touch control circuit 9 is disposed.
  • the touch leads 55 are connected to one end of at least two touch signal lines 51 so that at least two touch signal lines 51 are connected in parallel.
  • a data line 52 is provided between two adjacent touch signal lines 51 belonging to the same group. Specifically, a data line 52 is provided between two adjacent touch signal lines 51 belonging to the same group.
  • a data line 52 is provided between two adjacent groups of touch signal lines 51a.
  • a data line 52 is provided between two adjacent groups of touch signal lines 51a.
  • the touch signal line 51, data line 52 and touch lead 55 can be disposed on the same layer, that is, the touch signal line 51, data line 52 and touch lead 55 can be disposed on the first conductive layer 5.
  • the array substrate may also include data leads 23, which may be located in the non-display area where the touch control circuit 9 is located.
  • the data leads 23 may be located in the gate layer 2.
  • the data leads 23 may be connected to the data line 52 through the data via 33 located in the gate insulating layer 3, thereby avoiding the intersection of the data leads 23 and the touch leads 55 in the same layer.
  • the present disclosure provides a touch display device.
  • the touch display device may include the array substrate 100 described in any of the above-mentioned claims. The specific structure of the array substrate 100 has been described in detail above, and therefore will not be repeated here.
  • the touch display device may be a liquid crystal touch display device. Specifically, the touch display device may not include a color filter substrate 200, a frame 400, or a liquid crystal layer 300.
  • the color filter substrate 200 is disposed on the side of the array substrate 100 away from the first substrate 1.
  • the frame 400 is disposed between the array substrate 100 and the color filter substrate 200.
  • the liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200 and is located within the frame 400.
  • the specific type of the touch display device is not particularly limited; any type of touch display device commonly used in the field is acceptable, such as mobile devices like mobile phones, wearable devices like watches, etc. Those skilled in the art can make the appropriate selection based on the specific purpose of the display device, which will not be elaborated here.
  • the touch display device also includes other necessary components and parts. Taking the display as an example, these include, for instance, the casing, circuit board, power cord, etc. Those skilled in the art can supplement these components according to the specific usage requirements of the touch display device, and will not elaborate further here.
  • the beneficial effects of the touch display device provided by the example embodiments of the present invention are the same as the beneficial effects of the array substrate 100 provided by the example embodiments described above, and will not be repeated here.

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Abstract

一种阵列基板及触控显示装置，涉及显示技术领域，该阵列基板包括：第一衬底基板；第一导电层设于第一衬底基板的一侧，第一导电层包括沿第一方向延伸的触控信号线；绝缘层组设于第一导电层背离第一衬底基板的一侧，绝缘层组包括层叠设置的第一绝缘层组和第二绝缘层，第一绝缘层组上设置有多个第一过孔和多个第二过孔，第二绝缘层上设置有多个第三过孔；第二导电层设于第一绝缘层组中的至少一层和第二绝缘层背离第一衬底基板的一侧，第二导电层包括触控电极，触控电极通过连通的第一过孔和第三过孔以及连通的第二过孔和第三过孔连接至触控信号线；至少一个第一过孔和至少一个第二过孔连通至同一根触控信号线，第三过孔具有在第一方向上相对设置的第一孔壁和第二孔壁，第一过孔靠近第一孔壁设置，第二过孔靠近第二孔壁设置。该阵列基板能够避免出现低频闪烁。

Description

阵列基板及触控显示装置
交叉引用
本公开要求于2024年5月30日提交的申请号为202410693900.2，名称为“阵列基板及触控显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种阵列基板及触控显示装置。
背景技术
现有的触控与显示驱动器集成(Touch and Display Driver Integration，TDDI)产品，是一种将触控电极设置于显示面板内部的触控显示装置，也称为内嵌式触控显示装置。该触控显示装置具有较高的集成度、更加轻薄，因此具有广泛的应用前景。
但是，目前一些触控显示装置容易出现低频闪烁的不良。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种阵列基板及触控显示装置。
根据本公开的一个方面，提供了一种阵列基板，包括：
第一衬底基板；
第一导电层，设于所述第一衬底基板的一侧，所述第一导电层包括触控信号线，所述触控信号线沿第一方向延伸；
绝缘层组，设于所述第一导电层背离所述第一衬底基板的一侧，所述绝缘层组包括层叠设置的第一绝缘层组和第二绝缘层，所述第一绝缘层组上设置有多个第一过孔和多个第二过孔，所述第二绝缘层上设置有多个第三过孔；
第二导电层，设于所述第一绝缘层组中的至少一层和所述第二绝缘层背离所述第一衬底基板的一侧，所述第二导电层包括触控电极，所述触控电极通过连通的所述第一过孔和所述第三过孔以及连通的所述第二过孔和所述第三过孔连接至所述触控信号线；
其中，至少一个所述第一过孔和至少一个所述第二过孔连通至同一根所述触控信号线，所述第三过孔具有在所述第一方向上相对设置的第一孔壁和第二孔壁，在所述第一方向上，所述第一过孔相对于所述第二孔壁更靠近所述第一孔壁设置，所述第二过孔相对于所述第一孔壁更靠近所述第二孔壁设置。
在本公开的一种示例性实施例中，所述第一绝缘层组包括：
第一绝缘层，设于所述第一导电层背离所述第一衬底基板的一侧，所述第一绝缘层上设置有多个第一子过孔和多个第二子过孔，所述第二绝缘层设于所述第一绝缘层背离所述第一衬底基板的一侧；
和/或，第三绝缘层，设于所述第二绝缘层背离所述第一衬底基板的一侧，所述第三绝缘层上设置有多个第三子过孔和多个第四子过孔；
其中，所述第一过孔包括所述第一子过孔和/或所述第三子过孔，所述第一子过孔和所述第三子过孔相互连通；所述第二过孔包括所述第二子过孔和/或所述第四子过孔，所述第二子过孔和所述第四子过孔相互连通。
在本公开的一种示例性实施例中，所述第一子过孔在所述第一衬底基板上的正投影位于所述第三过孔在所述第一衬底基板上的正投影之内，所述第三子过孔在所述第一衬底基板上的正投影与所述第三过孔在所述第一衬底基板上的正投影至少部分交叠。
在本公开的一种示例性实施例中，在所述第一过孔和所述第三过孔处，所述第三绝缘层覆盖所述第三过孔的孔壁；或者，所述第三绝缘层未覆盖所述第一孔壁，且所述第三绝缘层覆盖所述第二孔壁；或者，所述第三绝缘层未覆盖所述第一孔壁且未覆盖所述第二绝缘层背离所述第一衬底基板的一面的靠近所述第一孔壁的一部分，且所述第三绝缘层覆盖所述第二孔壁。
在本公开的一种示例性实施例中，所述第二子过孔在所述第一衬底基板上的正投影位于所述第三过孔在所述第一衬底基板上的正投影之内，所述第四子过孔在所述第一衬底基板上的正投影与所述第三过孔在所述第一衬底基板上的正投影至少部分交叠。
在本公开的一种示例性实施例中，在所述第二过孔和所述第三过孔处，所述第三绝缘层覆盖所述第三过孔的孔壁；或者，所述第三绝缘层未覆盖所述第二孔壁，且所述第三绝缘层覆盖所述第一孔壁；或者，所述第三绝缘层未覆盖所述第二孔壁且未覆盖所述第二绝缘层背离所述第一衬底基板的一面的靠近所述第二孔壁的一部分，且所述第三绝缘层覆盖所述第一孔壁。
在本公开的一种示例性实施例中，所述第一绝缘层和所述第三绝缘层的材质包括无机材料；所述第二绝缘层的材质包括有机材料。
在本公开的一种示例性实施例中，所述第二导电层设于所述第二绝缘层与所述第三绝缘层之间，所述触控电极延伸至所述第三过孔内的第二方向的一端部，所述第二方向与所述第一方向相交，且与所述第一衬底基板设置所述第一导电层的一面平行；所述阵列基板还包括：
第三导电层，设于所述第三绝缘层背离所述第一衬底基板的一侧，所述第三导电层包括像素电极、第一连接部和第二连接部，所述像素电极与所述第一连接部以及所述第二连接部三者间隔设置，所述第一连接部通过所述第三过孔和所述第一过孔连接所述触控电极和所述触控信号线，所述第二连接部通过所述第三过孔和所述第二过孔连接所述触控电极和所述触控信号线；
或者，所述第二导电层设于所述第三绝缘层背离所述第一衬底基板的一侧；所述阵列基板还包括：
第三导电层，设于所述第二绝缘层与所述第三绝缘层之间，所述第三导电层包括像素电极。
在本公开的一种示例性实施例中，所述阵列基板还包括：
栅极层，设于所述第一衬底基板的一侧，所述栅极层包括栅极和栅线，所述栅极连接于所述栅线；
栅绝缘层，设于所述栅极层背离所述第一衬底基板的一侧；
有源层，设于所述栅绝缘层背离所述第一衬底基板的一侧，所述有源层包括沟道部以及设置在所述沟道部两端的源极连接部和漏极连接部；
其中，所述第一导电层设于所述有源层背离所述第一衬底基板的一侧，所述第一导电层还包括数据线、源极和漏极，所述数据线沿所述第一方向延伸，并与所述触控信号线间隔设置，所述源极连接于所述数据线且连接于所述源极连接部，所述漏极连接于所述像素电极且连接于所述漏极连接部。
在本公开的一种示例性实施例中，所述第一导电层还包括栅极和栅线，所述栅极连接于所述栅线，所述栅线沿所述第一方向延伸，并与所述触控信号线间隔设置；所述第一绝缘层组还包括：
栅绝缘层，设于所述第一导电层背离所述第一衬底基板的一侧，所述栅绝缘层上设置有多个第五子过孔和多个第六子过孔；
其中，所述第一过孔包括相互连通的所述第一子过孔、所述第三子过孔和所述第五子过孔，所述第二过孔包括相互连通的所述第二子过孔、所述第四子过孔和所述第六子过孔。
在本公开的一种示例性实施例中，在第二方向上，所述第三子过孔在所述第一衬底基板上的正投影的边沿线与所述第三过孔在所述第一衬底基板上的正投影的边沿线之间的距离大于等于1微米且小于等于2.5微米；
在所述第二方向上，所述第四子过孔在所述第一衬底基板上的正投影的边沿线与所述第三过孔在所述第一衬底基板上的正投影的边沿线之间的距离大于等于1微米且小于等于2.5微米，所述第二方向与所述第一方向相交，且与所述第一衬底基板设置所述第一导电层的一面平行。
在本公开的一种示例性实施例中，在所述第一方向上，所述第一过孔靠近所述第一孔壁的孔壁在所述第一衬底基板上的正投影与所述第一孔壁在所述第一衬底基板上的正投影之间的距离小于等于0.5微米；所述第一过孔靠近所述第二孔壁的孔壁在所述第一衬底基板上的正投影与所述第二孔壁在所述第一衬底基板上的正投影之间的距离大于等于1微米且小于等于2.5微米。
在本公开的一种示例性实施例中，在所述第一方向上，所述第二过孔靠近所述第二孔壁的孔壁在所述第一衬底基板上的正投影与所述第二孔壁在所述第一衬底基板上的正投影之间的距离小于等于0.5微米；所述第二过孔靠近所述第一孔壁的孔壁在所述第一衬底基板上的正投影与所述第一孔壁在所述第一衬底基板上的正投影之间的距离大于等于1微米且小于等于2.5微米。
在本公开的一种示例性实施例中，所述触控电极复用为公共电极。
在本公开的一种示例性实施例中，所述阵列基板包括：
第一连接结构，包括所述第一过孔以及所述第三过孔；
第二连接结构，包括所述第二过孔以及所述第三过孔。
在本公开的一种示例性实施例中，一个所述触控电极通过交替设置的所述第一连接结构和所述第二连接结构连接于一根所述触控信号线；
或者，至少两个所述第一连接结构被包括于第一连接组，至少两个所述第二连接结构被包括于第二连接组，一个所述触控电极通过交替设置的所述第一连接组和所述第二连接组连接于一根所述触控信号线。
在本公开的一种示例性实施例中，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过交替设置的所述第一连接结构和所述第二连接结构连接于所述触控电极；
或者，至少两个所述第一连接结构被包括于第一连接组，至少两个所述第二连接结构被包括于第二连接组，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过交替设置的所述第一连接组和所述第二连接组连接于所述触控电极。
在本公开的一种示例性实施例中，连接于相邻两根所述触控信号线的第一连接结构和第二连接结构错位设置。
在本公开的一种示例性实施例中，所述第一绝缘层组上还设置有第四过孔，所述第四过孔在所述第一衬底基板的正投影位于所述第三过孔在所述第一衬底基板上的正投影的中部区域；所述第三过孔以及所述第四过孔被包括于第三连接结构。
在本公开的一种示例性实施例中，所述第一连接结构、所述第二连接结构以及所述第三连接结构被包括于第三连接组；一个所述触控电极通过所述第三连接组连接于一根所述触控信号线；或者，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过所述第三连接结构连接于所述触控电极。
在本公开的一种示例性实施例中，一个所述触控电极通过多个连接结构连接一根所述触控信号线；多个所述连接结构中位于两端的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构；或者，多个所述连接结构中位于中部的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构。
在本公开的一种示例性实施例中，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过多个连接结构连接于所述触控电极；多个所述连接结构中位于两端的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构；或者，多个所述连接结构中位于中部的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构。
在本公开的一种示例性实施例中，一个所述触控电极连接有至少两根所述触控信号线，连接于同一个所述触控电极的至少两根所述触控信号线形成一组触控信号线组，所述阵列基板还包括：
触控引线，连接于至少两根所述触控信号线的一端，以使至少两根所述触控信号线并联，在属于同一组的相邻两根所述触控信号线之间设置有数据线，在相邻两组触控信号线组之间也设置有数据线。
根据本公开的另一个方面，提供了一种触控显示装置，包括：上述任意一项所述的阵列基板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为内嵌式触控显示装置的结构示意图。
图2为图1所示内嵌式触控显示装置中触控信号线与子像素区域的位置关系示意图。
图3为图1所示内嵌式触控显示装置中子像素的结构示意图。
图4为本公开阵列基板中触控电极和触控信号线配合的结构示意图。
图5为本公开阵列基板一示例实施方式的俯视结构示意图。
图6为图5中触控电极的结构示意图。
图7为图5中像素电极的结构示意图。
图8为图5中H所指部分的局部放大示意图。
图9为按照图8中的A-A剖切的剖视示意图。
图10为按照图8中的B-B剖切的剖视示意图。
图11为按照图8中的C-C剖切的剖视示意图。
图12为按照图8中的C-C剖切的另一示例实施方式的剖视示意图。
图13为按照图8中的C-C剖切的又一示例实施方式的剖视示意图。
图14为本公开阵列基板中第二过孔和第三过孔处的俯视示意图。
图15为按照图13中的D-D剖切的剖视示意图。
图16为按照图13中的E-E剖切的剖视示意图。
图17为本公开阵列基板另一示例实施方式的剖视示意图。
图18为本公开阵列基板再一示例实施方式中第一过孔和第三过孔处的剖视示意图。
图19为本公开阵列基板再一示例实施方式中第二过孔和第三过孔处的剖视示意图。
图20为触控电极与触控信号线之间连接结构第一示例实施方式的结构示意图。
图21为触控电极与触控信号线之间连接结构第二示例实施方式的结构示意图。
图22为触控电极与触控信号线之间连接结构第三示例实施方式的结构示意图。
图23为触控电极与触控信号线之间连接结构第四示例实施方式的结构示意图。
图24为触控电极与触控信号线之间连接结构第五示例实施方式的结构示意图。
图25为本公开阵列基板中第四过孔和第三过孔处的俯视示意图。
图26为按照图25中的F-F剖切的剖视示意图。
图27为按照图25中的G-G剖切的剖视示意图。
图28为触控电极与触控信号线之间连接结构第六示例实施方式的结构示意图。
图29为触控电极与触控信号线之间连接结构第七示例实施方式的结构示意图。
图30为触控电极与触控信号线之间连接结构第八示例实施方式的结构示意图。
图31为触控电极与触控信号线之间连接结构第九示例实施方式的结构示意图。
图32为触控电极与触控信号线之间连接结构第十示例实施方式的结构示意图。
图33为触控电极与触控信号线之间连接结构第十一示例实施方式的结构示意图。
图34为触控电极与触控信号线之间连接结构第十二示例实施方式的结构示意图。
图35为本公开阵列基本在非显示区域触控信号线与数据线配合的结构示意图。
图36为本公开触控显示装置一示例实施方式的结构示意图。
附图标记说明：
100、阵列基板；200、彩膜基板；300、液晶层；400、胶框；
1、第一衬底基板；
2、栅极层；21、栅极；22、栅线；23、数据引线；
3、栅绝缘层；31、第五子过孔；32、第六子过孔；33、数据过孔；
4、有源层；41、沟道部；42、源极连接部；43、漏极连接部；
5、第一导电层；51、触控信号线；51a、触控信号线组；52、数据
线；53、源极；54、漏极；55、触控引线；
6、绝缘层组；601、过孔；6a、第一绝缘层组；6a1、第一过孔；6a2、
第二过孔；6a3、第四过孔；
61、第一绝缘层；611、第一子过孔；612、第二子过孔；613、第七
子过孔；62、第二绝缘层；621、第三过孔；6211、第一孔壁；6212、第二孔壁；63、第三绝缘层；631、第三子过孔；632、第四子过孔；633、第八子过孔；
7、第二导电层；71、触控电极；
8、第三导电层；81、第一连接部；82、第二连接部；83、第三连接
部；84、像素电极；
9、触控控制电路；
11、第一连接结构；12、第二连接结构；13、第三连接结构；14、
第一连接组；15、第二连接组；16、第三连接组；
X、第一方向；Y、第二方向。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
发明人发现出现低频闪烁的不良的主要原因在于：参照图1和图2所示，阵列基板100的一部分子像素中需要设置过孔601，通过过孔601连接触控电极71和触控信号线51，过孔601需要占用一定的空间。对于PPI(Pixels Per Inch，像素密度)比较高，子像素较小的产品，导致设置过孔601的子像素与正常子像素设计不同，需要对公共电极和像素电极84做一定的削减，以放置过孔601或连接部，从而导致设置过孔601的子像素的Cst(存储电容)就会比正常子像素的Cst(存储电容)小，导致设置过孔601的子像素的电压保持能力比正常子像素差，特别是在低频情况下，容易出现低频闪烁。
本公开示例实施方式提供了一种阵列基板100，参照图1-图35所示，该阵列基板100可以包括第一衬底基板1、第一导电层5、绝缘层组6以及第二导电层7；第一导电层5设于第一衬底基板1的一侧，第一导电层5包括触控信号线51，触控信号线51沿第一方向X延伸；绝缘层组6设于第一导电层5背离第一衬底基板1的一侧，绝缘层组6包括层叠设置的第一绝缘层组6a和第二绝缘层62，第一绝缘层组6a上设置有多个第一过孔6a1和多个第二过孔6a2，第二绝缘层62上设置有多个第三过孔621；第二导电层7设于第一绝缘层组6a中的至少一层和第二绝缘层62背离第一衬底基板1的一侧，第二导电层7包括触控电极71，触控电极71通过连通的第一过孔6a1和第三过孔621以及连通的第二过孔6a2和第三过孔621连接至触控信号线51；其中，至少一个第一过孔6a1和至少一个第二过孔6a2连通至同一根触控信号线51，第三过孔621具有在第一方向X上相对设置的第一孔壁6211和第二孔壁6212，在第一方向X上，第一过孔6a1相对于第二孔壁6212更靠近第一孔壁6211设置，第二过孔6a2相对于第一孔壁6211更靠近第二孔壁6212设置。
本公开的阵列基板100，一方面，对于第一过孔6a1来讲可以不考虑第一过孔6a1靠近第一孔壁6211一侧与第三过孔621的重叠边距，从而可以将第一过孔6a1和第三过孔621设置的较小；对于第二过孔6a2来讲可以不考虑第二过孔6a2靠近第二孔壁6212一侧与第三过孔621的重叠边距，从而可以将第二过孔6a2和第三过孔621设置的较小，即可以减小第一过孔6a1、第二过孔6a2以及第三过孔621的占用面积，从而增加子像素的电容的设置空间，以保证子像素的电压保持能力，避免出现低频闪烁的不良。
另一方面，即使在构图工艺过程中，掩膜板的对位工艺产生偏差，在向第一孔壁6211偏移时，虽然第一过孔6a1和第三过孔621可能产生连通不良，但使得第二过孔6a2向第三过孔621的中心位置偏移，从而保证第二过孔6a2与第三过孔621的连通，从而保证触控电极71与触控信号线51之间的连接；同理，在向第二孔壁6212偏移时，虽然第二过孔6a2与第三过孔621可能产生连通不良，但使得第一过孔6a1向第三过孔621的中心位置偏移，从而保证第一过孔6a1与第三过孔621的连通，从而保证触控电极71与触控信号线51之间的连接；而且，均是在第一方向X上偏移，而触控信号线51沿第一方向X延伸，无论如何偏移，也不会脱离触控信号线51。
参照图1、图5和图6所示，避免图5多层层叠无法看出各层结构，图5中没有示出触控电极71，触控电极71基本是整层设置的，在薄膜晶体管T处没有设置触控电极71，该阵列基板100可以包括呈阵列排布的多个触控电极71以及多条触控信号线51，每个触控电极71通过过孔601电连接对应的触控信号线51，从而通过该触控信号线51电连接至触控控制电路9。
参照图2所示，该阵列基板100可以包括多个像素区域P(图2中示出四个像素区域P1、P2、P3和P4进行举例说明)，每个像素区域P包括三个子像素区域(参见SP1、SP2、SP3)，每个子像素区域由相邻的栅线22(图2示出221、222这两个栅线22进行举例说明)和相邻的数据线52(图2示出了521至526进行举例说明)相互交叉限定。
阵列基板100还包括位于第一衬底基板1上的多条触控信号线51(图2示出了511至512进行举例说明)，该多条触控信号线51沿第一方向X延伸并且沿第二方向Y依次排列；并且每条触控信号线51都经过子像素区域SP的未被显示装置中的黑矩阵层遮挡的开口区。在像素区域P1的子像素区域SP3处设置有过孔601，通过过孔601连接触控电极71和触控信号线51，导致子像素区域SP3的Cst(存储电容)就会比正常子像素区域SP1、SP2的Cst(存储电容)小，导致子像素区域SP3的电压保持能力比正常子像素差，特别是在低频情况下，容易出现低频闪烁。
在本示例实施方式中，第一衬底基板1可以是玻璃基板；当然，在本公开的其他一些示例实施方式中，第一衬底基板1还可以是石英等等；第一衬底基板1还可以包括绝缘材料层，绝缘材料层可以设置在玻璃基板的一侧，该绝缘材料层可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。
在本示例实施方式中，参照图3所示，在第一衬底基板1的一侧可以设置有栅极层2，栅极层2可以包括多根栅线22和多个栅极21。栅线22可以沿第二方向Y延伸，沿第二方向Y排列的多个栅极21可以连接于同一根栅线22，或者栅线22的一部分可以作为栅极21。
在本示例实施方式中，参照图3所示，在栅极层2远离第一衬底基板1的一侧设置有栅绝缘层3。在栅绝缘层3远离第一衬底基板1的一侧设置有有源层4，有源层可以包括沟道部41以及设置在沟道部41两端的导体部，两个导体部中的一个为源极连接部42，另一个为漏极连接部43。沟道部41设于栅线22的远离第一衬底基板1的一侧，即与沟道部41相对的栅线22的一部分作为栅极21。
在本示例实施方式中，参照图3所示，在有源层4远离第一衬底基板1的一侧设置有第一导电层5，第一导电层5可以包括源极53、漏极54、数据线52以及触控信号线51。触控信号线51沿第一方向X延伸，数据线52沿第一方向X延伸，第一方向X与所述第二方向Y相交，例如，可以是第一方向X与所述第二方向Y垂直。
源极53连接于数据线52，且连接于源极连接部42，从而通过源极53将源极连接部42与数据线52连接；漏极54连接于后续形成的像素电极，且连接于漏极连接部43，从而通过漏极54将漏极连接部43与像素电极连接。栅极21、沟道部41、源极53、漏极54以及源极连接部42和漏极连接部43形成一个开关单元，该开关单元是薄膜晶体管。
需要说明的是，本说明书中说明的薄膜晶体管为底栅型薄膜晶体管，在本公开的其他示例实施方式中，薄膜晶体管还可以是顶栅型或双栅型，对其具体结构在此不再赘述。而且，在使用极性相反的薄膜晶体管的情况或电路工作中的电流方向变化的情况等下，“源极53”及“漏极54”的功能有时互相调换。因此，在本说明书中，“源极53”和“漏极54”可以互相调换。
在本示例实施方式中，参照图3所示，在第一导电层5远离第一衬底基板1的一侧设置有绝缘层组6，绝缘层组6可以包括第一绝缘层组6a和第二绝缘层62。第一绝缘层组6a的材料可以包括无机材料，例如，可以是氮化硅、氧化硅等等。第二绝缘层62的材料可以包括有机材料，例如，可以是聚酰亚胺、聚碳酸酯、聚丙烯酸酯等等。第二绝缘层62的材质可以是光刻胶，在第二绝缘层62上形成第二子过孔612时只需要进行曝光显影即可，节省工艺步骤；而在其他膜层上形成第二子过孔612时，在曝光显影后，还需要以光刻胶为掩模对其他膜层进行刻蚀。
当然，在本公开的其他一些示例实施方式中，第一绝缘层组6a也可以包括有机材料，第二绝缘层62也可以包括无机材料。
参照图4所示，图中未示出第一绝缘层组6a和第二绝缘层62，仅示出第一过孔6a1、第二过孔6a2和第三过孔621；第一绝缘层组6a上设置有多个第一过孔6a1和多个第二过孔6a2，至少一个第一过孔6a1和至少一个第二过孔6a2连通至同一根触控信号线51，即至少一个第一过孔6a1和至少一个第二过孔6a2在衬底基板上的正投影与同一根触控信号线51在衬底基板上的正投影有交叠；也可以说是，同一根触控信号线51至少有两部分未被第一绝缘层组6a覆盖；例如，可以是一个第一过孔6a1和一个第二过孔6a2连通至同一根触控信号线51，也可以是两个或更多个第一过孔6a1和两个或更多个第二过孔6a2连通至同一根触控信号线51。
具体地，参照图3所示，第一绝缘层组6a可以包括第一绝缘层61，第一绝缘层61设于第一导电层5远离第一衬底基板1的一侧。第一绝缘层61的材料可以是无机材料，例如，可以是氮化硅、氧化硅等等。第一绝缘层61上设置有多个第一子过孔611和多个第二子过孔612。
在本示例实施方式中，参照图3所示，在第一绝缘层61背离第一衬底基板1的一侧设置有第二绝缘层62，第二绝缘层62上设置有多个第三过孔621，第三过孔621具有在第一方向X上相对设置的第一孔壁6211和第二孔壁6212。
第二导电层7设于第一绝缘层组6a中的至少一层和第二绝缘层62背离第一衬底基板1的一侧，具体地，在第二绝缘层62背离第一衬底基板1的一侧设置有第二导电层7，第二导电层7可以包括触控电极71，参照图4所示，触控电极71通过连通的第一过孔6a1和第三过孔621以及连通的第二过孔6a2和第三过孔621连接至触控信号线51。
第二导电层7的材质可以是透明导电材料，具体地，第一导电层5的材质可以是ITO(氧化铟锡)、IZO(铟锌氧化物)等等。
参照图8、图9和图14所示，触控电极71延伸至第三过孔621内的第二方向Y的一端部，即触控电极71没有占据第三过孔621的全部，仅占据第三过孔621第二方向Y的一端部，第三过孔621的第二方向Y另一部分是为了裸露触控信号线51。而第一过孔6a1和第二过孔6a2是在第一方向X上偏移，无论如何偏移，只要第一过孔6a1与第三过孔621连通或者第二过孔6a2与第三过孔621连通，就能够保证触控电极71与触控信号线51的连接。
触控电极71可以复用为公共电极，具体地，触控电极71可以分时复用为公共电极，即在第一时间段内，为触控信号线51加载触控信号，触控电极71用作触控电极71，以实现触控功能；在第二时间段内，为触控信号线51加载公共电压，触控电极71用作公共电极，以实现显示功能。
参照图3所示，第一绝缘层组6a还可以包括第三绝缘层63，具体地，在第二导电层7背离第一衬底基板1的一侧设置有第三绝缘层63，即第二导电层7设于第二绝缘层62与第三绝缘层63之间，第三绝缘层63的材料可以是无机材料，例如，可以是氮化硅、氧化硅等等。第三绝缘层63上设置有多个第三子过孔631和多个第四子过孔632。
第一过孔6a1可以包括第一子过孔611和第三子过孔631，第一子过孔611和第三子过孔631相互连通，即第三子过孔631连通至第一子过孔611。第二过孔6a2可以包括第二子过孔612和第四子过孔632，第二子过孔612和第四子过孔632相互连通，即第四子过孔632连通至第二子过孔612，从而使得至少一个第三子过孔631和至少一个第四子过孔632连通至同一根触控信号线51。而且，至少一个第三子过孔631和至少一个第四子过孔632连通至同一个触控电极71，即同一个触控电极71在至少一个第三子过孔631和至少一个第四子过孔632的位置没有被第三绝缘层63覆盖而裸露部分。
当然，在本公开的其他一些示例实施方式中，第一绝缘层组6a可以仅包括第一绝缘层61，这种情况下，第二导电层7设于第二绝缘层62背离第一衬底基板1的一侧，第一过孔6a1可以仅包括第一子过孔611，第二过孔6a2可以仅包括第二子过孔612；第一绝缘层组6a可以仅包括第三绝缘层63，这种情况下，第一过孔6a1可以仅包括第三子过孔631，第二过孔6a2可以仅包括第四子过孔632。
由于第一绝缘层组6a上的第一过孔6a1和第二过孔6a2与第二绝缘层62上的第三过孔621分别通过两次不同的构图工艺形成，在两次构图工艺过程中由于掩膜板的对位工艺的偏差，偏差范围在-2微米～+2微米之间(正负表示方向)，需要将先形成的第三过孔621设置的较大，使得第三过孔621的周边与第一过孔6a1的周边和第二过孔6a2的周边形成overlay margin(重叠边距)，才能保证后面形成的第一过孔6a1和第二过孔6a2能够连通至第三过孔621，以实现触控电极71和触控信号线51的电连接。
在本示例实施方式中，在第一方向上，第一过孔6a1相对于第二孔壁6212更靠近第一孔壁6211设置，使得第一过孔6a1位于第三过孔621的第一方向X的一侧；第二过孔6a2相对于第一孔壁6211更靠近第二孔壁6212设置，使得第二过孔6a2位于第三过孔621的第一方向X的相对另一侧；即使得第一过孔6a1和第二过孔6a2相对于第三过孔621而言偏离第三过孔621的中心设置。
如此设置，对于第一过孔6a1来讲可以不考虑第一过孔6a1靠近第一孔壁6211一侧与第三过孔621的重叠边距，从而可以将第一过孔6a1和第三过孔621设置的较小；对于第二过孔6a2来讲可以不考虑第二过孔6a2靠近第二孔壁6212一侧与第三过孔621的重叠边距，从而可以将第二过孔6a2和第三过孔621设置的较小，从而增加子像素的电容的设置空间，以保证子像素的电压保持能力，避免出现低频闪烁的不良。
而且，由于第一过孔6a1和第二过孔6a2设置在第三过孔621的相对两端部，即使在构图工艺过程中，掩膜板的对位工艺产生偏差，在向第一孔壁6211偏移时，虽然第一过孔6a1和第三过孔621可能产生连通不良，但使得第二过孔6a2向第三过孔621的中心位置偏移，从而保证第二过孔6a2与第三过孔621的连通，从而保证触控电极71与触控信号线51之间的连接；同理，在向第二孔壁6212偏移时，虽然第二过孔6a2与第三过孔621可能产生连通不良，但使得第一过孔6a1向第三过孔621的中心位置偏移，从而保证第一过孔6a1与第三过孔621的连通，从而保证触控电极71与触控信号线51之间的连接。
在本示例实施方式中，在第三绝缘层63背离第一衬底基板1的一侧设置有第三导电层8，第三导电层8的材质可以是透明导电材料，具体地，第一导电层5的材质可以是ITO(氧化铟锡)、IZO(铟锌氧化物)等等。参照图7、图8和图14所示，第三导电层8可以包括像素电极84、第一连接部81和第二连接部82，而且，像素电极84、第一连接部81和第二连接部82三者之间间隔设置，即像素电极84、第一连接部81和第二连接部82三者之间没有连接。
第一连接部81通过第三过孔621和第一过孔6a1连接触控电极71和触控信号线51，第二连接部82通过第三过孔621和第二过孔6a2连接触控电极71和触控信号线51。从而通过第一连接部81和第二连接部82将接触控电极71和触控信号线51连接为一体，通过触控信号线51可以为触控电极71传输触控信号。
如此设置，可以减小第一过孔6a1的开口面积、第二过孔6a2的开口面积和第三过孔621的开口面积，从而可以减小第一连接部81和第二连接部82的面积，以增大像素电极84的面积，增大设置过孔的子像素的Cst，以保证设置过孔的子像素的电压保持能力，避免出现低频闪烁的不良。
参照图8-图13所示，由于形成第一子过孔611时第二绝缘层62以及触控电极71对第一绝缘层61能够进行遮挡，使得第一子过孔611在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，具体地，第一子过孔611在第一衬底基板1上的正投影的面积小于第三过孔621在第一衬底基板1上的正投影的面积，而且第三过孔621在第一衬底基板1上的正投影完全覆盖第一子过孔611在第一衬底基板1上的正投影。
第三子过孔631在第一衬底基板1上的正投影与第三过孔621在第一衬底基板1上的正投影至少部分交叠。
例如，参照图10和图11所示，可以是第三子过孔631在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，且第三子过孔631在第一衬底基板1上的正投影的一侧边沿线与第三过孔621的第一孔壁6211在第一衬底基板1上的正投影重合，使得在第一过孔6a1和第三过孔621处，第三绝缘层63未覆盖第一孔壁6211，且第三绝缘层63覆盖第二孔壁6212。
参照图12所示，在形成第一过孔6a1时，掩膜板向第一孔壁6211一侧偏移较多的情况下，也可以是第三子过孔631在第一衬底基板1上的正投影的一部分与第三过孔621在第一衬底基板1上的正投影的一部分交叠，使得在第一过孔6a1和第三过孔621处，第三绝缘层63未覆盖第一孔壁6211且未覆盖第二绝缘层背离第一衬底基板1的一面的靠近第一孔壁6211的一部分，且第三绝缘层63覆盖第二孔壁6212。
参照图13所示，在形成第一过孔6a1时，掩膜板向第二孔壁6212一侧偏移较多的情况下，还可以是第三子过孔631在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，使得在第一过孔6a1和第三过孔621处，第三绝缘层63覆盖第三过孔621的孔壁，即第三绝缘层63将第三过孔621的四周孔壁几乎完全覆盖。
另外，参照图9所示，在上述示例实施方式中，在第一过孔6a1和第三过孔621处，第三绝缘层63覆盖第三过孔621的在第二方向Y上相对设置的两个侧壁。
参照图9、图14-图16所示，由于形成第二子过孔612时第二绝缘层62以及触控电极71对第一绝缘层61能够进行遮挡，使得第二子过孔612在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，具体地，第二子过孔612在第一衬底基板1上的正投影的面积小于第三过孔621在第一衬底基板1上的正投影的面积，而且第三过孔621在第一衬底基板1上的正投影完全覆盖第二子过孔612在第一衬底基板1上的正投影。
第四子过孔632在第一衬底基板1上的正投影与第三过孔621在第一衬底基板1上的正投影至少部分交叠。
例如，参照图15和图16所示，可以是第四子过孔632在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，且第四子过孔632在第一衬底基板1上的正投影的一侧边沿线与第三过孔621的第二孔壁6212在第一衬底基板1上的正投影重合，使得在第二过孔6a12和第三过孔621处，第三绝缘层63未覆盖第二孔壁6212，且第三绝缘层63覆盖第一孔壁6211。
在形成第二过孔6a2时，掩膜板向第一孔壁6211一侧偏移较多的情况下，也可以是第四子过孔632在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，使得在第二过孔6a12和第三过孔621处，第三绝缘层63覆盖第三过孔621的孔壁，即第三绝缘层63将第三过孔621的四周孔壁几乎完全覆盖。
在形成第二过孔6a2时，掩膜板向第二孔壁6212一侧偏移较多的情况下，还可以是第四子过孔632在第一衬底基板1上的正投影的一部分与第三过孔621在第一衬底基板1上的正投影的一部分交叠，使得在第二过孔6a12和第三过孔621处，第三绝缘层63未覆盖第二孔壁6212且未覆盖第二绝缘层背离第一衬底基板1的一面的靠近第二孔壁6212的一部分，且第三绝缘层63覆盖第一孔壁6211。
另外，参照图9所示，在上述示例实施方式中，在第二过孔6a12和第三过孔621处，第三绝缘层63覆盖第三过孔621的在第二方向Y上相对设置的两个侧壁。
另外，在本公开的另外一些示例实施方式中，参照图17所示，第二导电层7设于第三绝缘层63背离第一衬底基板1的一侧；触控电极71可以直接通过连通的第一过孔6a1和第三过孔621以及连通的第二过孔6a2和第三过孔621连接至触控信号线51，不需要设置第一连接部81和第二连接部82。这种情况下，阵列基板还可以包括第三导电层8，第三导电层8设于第二绝缘层62与第三绝缘层63之间，第三导电层8包括像素电极84。由于触控电极71与触控信号线51的连接也需要通过连通的第一过孔6a1和第三过孔621以及连通的第二过孔6a2和第三过孔621，因此，上述第一过孔6a1、第二过孔6a2和第三过孔621的设置也适用于该示例实施方式，具体结构，在此不再说明。
在本公开的另外一些示例实施方式中，参照图18和图19所示，第一导电层5还可以包括栅极21和栅线22，即第一导电层5就是栅极层2，触控信号线51与栅线22设置在同一层，避免触控信号线51与栅线22交叉，栅线22也沿第一方向X延伸，并与触控信号线51间隔设置。栅极21连接于栅线22，其具体结构在此不再赘述。
这种情况下，第一绝缘层组6a还可以包括栅绝缘层3，栅绝缘层3设于第一导电层5背离第一衬底基板1的一侧，栅绝缘层3上设置有多个第五子过孔31和多个第六子过孔32；多个第五子过孔31和多个第六子过孔32与第一绝缘层61上的第一子过孔611和第二子过孔612以及第三绝缘层63上的第三子过孔631以及第四子过孔632通过同一次构图工艺形成，使得第一过孔6a1可以包括相互连通的第一子过孔611、第三子过孔631和第五子过孔31，第二过孔6a2可以包括相互连通的第二子过孔612、第四子过孔632和第六子过孔32。
第五子过孔31在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，具体地，第五子过孔31在第一衬底基板1上的正投影的面积小于第三过孔621在第一衬底基板1上的正投影的面积，而且第三过孔621在第一衬底基板1上的正投影完全覆盖第五子过孔31在第一衬底基板1上的正投影。
第六子过孔32在第一衬底基板1上的正投影位于第三过孔621在第一衬底基板1上的正投影之内，具体地，第六子过孔32在第一衬底基板1上的正投影的面积小于第三过孔621在第一衬底基板1上的正投影的面积，而且第三过孔621在第一衬底基板1上的正投影完全覆盖第六子过孔32在第一衬底基板1上的正投影。
另外，需要说明的是，本示例实施方式限定了触控信号线51位于栅极层2，因此，上述示例实施方式中的其他结构只要与本示例实施方式中不冲突，都可以结合，在此就不一一说明。
在本示例实施方式中，在第二方向Y上，第三子过孔631在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离大于等于1微米且小于等于2.5微米，例如，第三子过孔631在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离可以是1.2微米、1.5微米、1.7微米、2微米、2.3微米等等。
如果第三子过孔631在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离过小，会增加对位工艺的难度，从而增加制备成本。
如果第三子过孔631在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离过大，需要增大第三过孔621，不利于阵列基板100上其他结构的布设，或者需要减小第三子过孔631，容易导致第三子过孔631与第三过孔621无法连通。
上述数值范围，不仅不会增加对位工艺的难度，不会增加制备成本；而且，能够满足两次构图工艺对位偏差的要求，能够保证第三子过孔631与第三过孔621连通。
需要说明的是，参照图9所示，由于第一子过孔611与第三子过孔631通过同一次构图工艺形成，而第一子过孔611的第二方向Y的一端被触控电极71遮挡，另一端没有遮挡；因此，在第二方向Y上，第一子过孔611靠近触控电极71的孔壁在第一衬底基板1上的正投影与第三过孔621在第一衬底基板1上的正投影的对应边沿线之间的距离为触控电极71延伸至第三过孔621内的长度，第一子过孔611远离触控电极71的孔壁在第一衬底基板1上的正投影与第三过孔621在第一衬底基板1上的正投影的对应边沿线之间的距离也大于等于1微米且小于等于2.5微米。
在本示例实施方式中，在第二方向Y上，第四子过孔632在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离大于等于1微米且小于等于2.5微米，例如，第四子过孔632在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离可以是1.2微米、1.5微米、1.7微米、2微米、2.3微米等等。
如果第四子过孔632在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离过小，会增加对位工艺的难度，从而增加制备成本。
如果第四子过孔632在第一衬底基板1上的正投影的边沿线与第三过孔621在第一衬底基板1上的正投影的边沿线之间的距离过大，需要增大第三过孔621，不利于阵列基板100上其他结构的布设，或者需要减小第四子过孔632，容易导致第四子过孔632与第三过孔621无法连通。
上述数值范围，不仅不会增加对位工艺的难度，不会增加制备成本；而且，能够满足两次构图工艺对位偏差的要求，能够保证第四子过孔632与第三过孔621连通。
需要说明的是，参照图9所示，由于第二子过孔612与第三子过孔631通过同一次构图工艺形成，而第二子过孔612的第二方向Y的一端被触控电极71遮挡，另一端没有遮挡；因此，在第二方向Y上，第二子过孔612靠近触控电极71的孔壁在第一衬底基板1上的正投影与第三过孔621在第一衬底基板1上的正投影的对应边沿线之间的距离为触控电极71延伸至第三过孔621内的长度，第二子过孔612远离触控电极71的孔壁在第一衬底基板1上的正投影与第三过孔621在第一衬底基板1上的正投影的对应边沿线之间的距离也大于等于1微米且小于等于2.5微米。
在本示例实施方式中，在第一方向X上，第一过孔6a1靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离小于等于0.5微米，例如，第一过孔6a1靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离可以是0.05微米、0.1微米、0.15微米、0.2微米、0.25微米、0.3微米、0.35微米、0.4微米、0.45微米等等。
如果第一过孔6a1靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离过大，会使得第一过孔6a1偏离第三过孔621的中心太远或者会使得第一过孔6a1基本没有偏离第三过孔621的中心，导致第一过孔6a1设置的较大，不能达到减小第一过孔6a1，以减小第一连接部81同时增大像素电极84的目的，还是会出现低频闪烁的不良。
需要说明的是，参照图12所示，由于第一过孔6a1可以包括第一子过孔611和第三子过孔631，在第一过孔6a1的一部分偏移至第三过孔621的外部的情况下，第一子过孔611由于有第二绝缘层62的遮挡不会偏移至第三过孔621外，这种情况下，第一子过孔611靠近第一孔壁6211的孔壁与第一孔壁6211基本平齐，上述数值范围可以指的是第三子过孔631靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离。
第一过孔6a1靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离大于等于1微米且小于等于2.5微米，例如，第一过孔6a1靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离可以是1.2微米、1.5微米、1.7微米、2微米、2.3微米等等。
第一绝缘层组6a上的第一过孔6a1和第二过孔6a2与第二绝缘层62上的第三过孔621分别通过两次不同的构图工艺形成；在两次构图工艺过程中由于掩膜板的对位工艺的偏差，偏差范围在-2微米～+2微米之间(正负表示方向)，需要将先形成的第三过孔621设置的较大，才能保证后面形成的第一过孔6a1和第二过孔6a2能够连通至第三过孔621。
如果第一过孔6a1靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离过小，会增加对位工艺的难度，从而增加制备成本。
如果第一过孔6a1靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离过大，需要增大第三过孔621，不利于阵列基板100上其他结构的布设，或者需要减小第一过孔6a1，容易导致第一过孔6a1与第三过孔621无法连通。
上述数值范围，不仅不会增加对位工艺的难度，不会增加制备成本；而且，能够满足两次构图工艺对位偏差的要求，能够保证第一过孔6a1与第三过孔621连通。
需要说明的是，由于第一子过孔611的孔壁、第三子过孔631的孔壁、第一孔壁6211以及第二孔壁6212一般情况下全部是倾斜设置的，导致第三子过孔631的孔壁、第一孔壁6211以及第二孔壁6212在第一衬底基板1上的正投影是有一定的宽度；因此，上述第三子过孔631靠近第一孔壁6211的孔壁与第一孔壁6211需要是相应位置，第三子过孔631靠近第二孔壁6212的孔壁与第二孔壁6212也需要是相应位置；例如，可以全部是背离第一衬底基板1的边沿，还可以全部是靠近第一衬底基板1的边沿。
在本示例实施方式中，在第一方向X上，第二过孔6a2靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离小于等于0.5微米，例如，第二过孔6a2靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离可以是0.05微米、0.1微米、0.15微米、0.2微米、0.25微米、0.3微米、0.35微米、0.4微米、0.45微米等等；
如果第二过孔6a2靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离过大，会使得第二过孔6a2偏离第三过孔621的中心太远或者会使得第二过孔6a2基本没有偏离第三过孔621的中心，导致第二过孔6a2设置的较大，不能达到减小第二过孔6a2，以减小第二连接部82同时增大像素电极84的目的，还是会出现低频闪烁的不良。
需要说明的是，由于第二过孔6a2可以包括第二子过孔612和第四子过孔632，在第二过孔6a2的一部分偏移至第三过孔621的外部的情况下，第二子过孔612由于有第二绝缘层62的遮挡不会偏移至第三过孔621外，这种情况下，第二子过孔612靠近第二孔壁6212的孔壁与第二孔壁6212基本平齐，上述数值范围可以指的是第四子过孔632靠近第二孔壁6212的孔壁在第一衬底基板1上的正投影与第二孔壁6212在第一衬底基板1上的正投影之间的距离。
第二过孔6a2靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离大于等于1微米且小于等于2.5微米，例如，第二过孔6a2靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离可以是1.2微米、1.5微米、1.7微米、2微米、2.3微米等等。
如果第二过孔6a2靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离过小，会增加对位工艺的难度，从而增加制备成本。
如果第二过孔6a2靠近第一孔壁6211的孔壁在第一衬底基板1上的正投影与第一孔壁6211在第一衬底基板1上的正投影之间的距离过大，需要增大第三过孔621，不利于阵列基板100上其他结构的布设，或者需要减小第二过孔6a2，容易导致第二过孔6a2与第三过孔621无法连通。
上述数值范围，不仅不会增加对位工艺的难度，不会增加制备成本；而且，能够满足两次构图工艺对位偏差的要求，能够保证第二过孔6a2与第三过孔621连通。
需要说明的是，由于第二子过孔612的孔壁、第四子过孔632的孔壁、第一孔壁6211以及第二孔壁6212一般情况下全部是倾斜设置的，导致第四子过孔632的孔壁、第一孔壁6211以及第二孔壁6212在第一衬底基板1上的正投影是有一定的宽度；因此，上述第四子过孔632靠近第一孔壁6211的孔壁与第一孔壁6211需要是相应位置，第四子过孔632靠近第二孔壁6212的孔壁与第二孔壁6212也需要是相应位置；例如，可以全部是背离第一衬底基板1的边沿，还可以全部是靠近第一衬底基板1的边沿。
具体地，第一子过孔611在第一方向X上的尺寸大于等于2微米且小于等于15微米，例如，第一子过孔611在第一方向X上的尺寸可以是5微米、7微米、10微米、13微米等等。第二子过孔612在第一方向X上的尺寸大于等于2微米且小于等于15微米，例如，第二子过孔612在第一方向X上的尺寸可以是5微米、7微米、10微米、13微米等等；相对于现有技术中的结构减小了15％-35％。
第三过孔621在第一方向X上的尺寸大于等于2微米且小于等于20微米，例如，第三过孔621在第一方向X上的尺寸可以是5微米、7微米、10微米、13微米、15微米、18微米等等；相对于现有技术中的结构减小15％-35％。
第三子过孔631在第一方向X上的尺寸大于等于2微米且小于等于20微米，例如，第三子过孔631在第一方向X上的尺寸可以是5微米、7微米、10微米、13微米、15微米、18微米等等。第四子过孔632在第一方向X上的尺寸大于等于2微米且小于等于20微米，例如，第四子过孔632在第一方向X上的尺寸可以是5微米、7微米、10微米、13微米、15微米、18微米等等。相对于现有技术中的结构减小15％-35％。
阵列基板可以包括第一连接结构11和第二连接结构12；第一连接结构可以包括第一过孔6a1以及第三过孔621；第二连接结构可以包括第二过孔6a2以及第三过孔621。在本示例实施方式中，第一连接部81、第三过孔621以及第一过孔6a1被包括于第一连接结构11，即第一连接结构11可以包括第一连接部81以及相互连通的第三过孔621以及第一过孔6a1；第二连接部82、第三过孔621以及第二过孔6a2被包括于第二连接结构12，即第二连接结构12可以包括第二连接部82、相互连通的第三过孔621以及第二过孔6a2。
参照图20和图21所示，一个触控电极71通过交替设置的第一连接结构11和第二连接结构12连接于一根触控信号线51，使得相邻两个第一连接结构11之间设置有一个第二连接结构12，相邻两个第二连接结构12之间设置有一个第一连接结构11；例如，第一连接结构11和第二连接结构12均可以设置为十个；参照图20所示，起始的一个可以是第一连接结构11；参照图21所示，起始的一个可以是第二连接结构12。
在本公开的一些示例实施方式中，参照图22所示，至少两个第一连接结构11被包括于第一连接组14，即第一连接组14可以包括至少两个第一连接结构11，例如，第一连接组14可以包括两个第一连接结构11，第一连接组14也可以包括三个或更多个第一连接结构11。至少两个第二连接结构12被包括于第二连接组15，即第二连接组15可以包括至少两个第二连接结构12，例如，第二连接组15可以包括两个第二连接结构12，第二连接组15也可以包括三个或更多个第二连接结构12。
一个触控电极71通过交替设置的第一连接组14和第二连接组15连接于一根触控信号线51，使得相邻两个第一连接组14之间设置有一个第二连接组15，相邻两个第二连接组15之间设置有一个第一连接组14；起始的一组可以是第一连接组14；起始的一组也可以是第二连接组15。
在本公开的一些示例实施方式中，参照图23所示，一个触控电极71连接有至少两根触控信号线51，至少两根触控信号线51可以并联连接，例如，一个触控电极71可以连接有两根触控信号线51，一个触控电极71也可以连接有三根或更多根触控信号线51。
每根触控信号线51通过交替设置的第一连接结构11和第二连接结构12连接于触控电极71。例如，在一个触控电极71连接有两根触控信号线51的情况下，两根触控信号线51包括第一触控信号线511和第二触控信号线512，第一触控信号线511通过交替设置的第一连接结构11和第二连接结构12连接于触控电极71，第二触控信号线512也通过交替设置的第一连接结构11和第二连接结构12连接于触控电极71。使得相邻两个第一连接结构11之间设置有一个第二连接结构12，相邻两个第二连接结构12之间设置有一个第一连接结构11；与每根触控信号线51连接的第一连接结构11和第二连接结构12均可以设置为十个；起始的一个可以是第一连接结构11；起始的一个可以是第二连接结构12。而且，相邻两根触控信号线51的起始的连接结构可以相同，也可以不同。
在本公开的一些示例实施方式中，参照图24所示，至少两个第一连接结构11被包括于第一连接组14，即第一连接组14可以包括至少两个第一连接结构11，例如，第一连接组14可以包括两个第一连接结构11，第一连接组14也可以包括三个或更多个第一连接结构11。至少两个第二连接结构12被包括于第二连接组15，即第二连接组15可以包括至少两个第二连接结构12，例如，第二连接组15可以包括两个第二连接结构12，第二连接组15也可以包括三个或更多个第二连接结构12。
一个触控电极71连接有至少两根触控信号线51，至少两根触控信号线51可以并联连接，例如，一个触控电极71可以连接有两根触控信号线51，一个触控电极71也可以连接有三根或更多根触控信号线51。
每根触控信号线51通过交替设置的第一连接组14和第二连接组15连接于触控电极71。例如，在一个触控电极71连接有两根触控信号线51的情况下，两根触控信号线51包括第一触控信号线511和第二触控信号线512，第一触控信号线511通过交替设置的第一连接组14和第二连接组15连接于触控电极71，第二触控信号线512也通过交替设置的第一连接组14和第二连接组15连接于触控电极71。使得相邻两个第一连接组14之间设置有一个第二连接组15，相邻两个第二连接组15之间设置有一个第一连接组14；与每根触控信号线51连接的第一连接组14和第二连接组15均可以设置为十个；起始的一个可以是第一连接组14；起始的一个可以是第二连接组15。而且，相邻两根触控信号线51的起始的连接结构可以相同，也可以不同。
可选择地，连接于相邻两根触控信号线51的第一连接结构11和第二连接结构12错位设置，即连接于相邻两根触控信号线51的第一连接结构11和第二连接结构12没有相对设置，避免第一连接结构11与第二连接结构12之间相互影响。
在本公开的一些示例实施方式中，参照图25-27所示，第一绝缘层组6a上还设置有第四过孔6a3，第四过孔6a3可以包括设置在第一绝缘层61上的第七子过孔613和设置在第三绝缘层63上的第八子过孔633。第四过孔6a3在第一衬底基板1的正投影位于第三过孔621在第一衬底基板1上的正投影的中部区域，即第四过孔6a3在第一衬底基板1的正投影的全部与第三过孔621在第一衬底基板1上的正投影的中部区域交叠，也可以说是，第四过孔6a3的各个孔壁与第三过孔621的各个孔壁之间的距离基本相同。
这种情况下，第三导电层8还可以包括第三连接部83，第三连接部83与像素电极84、第一连接部81以及第二连接部82四者间隔设置，即第三连接部83与像素电极84、第一连接部81以及第二连接部82四者之间没有连接；第三连接部83通过第四过孔6a3和第三过孔621连接触控电极71和触控信号线51，通过触控信号线51可以为触控电极71传输触控信号。
第三过孔621以及第四过孔6a3被包括于第三连接结构13，具体地，第三连接部83、第四过孔6a3以及第三过孔621被包括于第三连接结构13，即第三连接结构13可以包括第三连接部83、第四过孔6a3以及第三过孔621。
参照图28所示，第一连接结构11、第二连接结构12以及第三连接结构13被包括于第三连接组16，即第三连接组16可以包括一个第一连接结构11、一个第二连接结构12以及一个第三连接结构13，可以是第一连接结构11、第三连接结构13以及第二连接结构12依次排列，也可以是第一连接结构11、第二连接结构12以及第三连接结构13依次排列。当然，还可以是其他排列方式，在此不再一一说明。
参照图28所示，一个触控电极71通过第三连接组16连接于一根触控信号线51，例如，一个触控电极71通过一个第三连接组16连接于一根触控信号线51，一个触控电极71通过两个或更多个第三连接组16连接于一根触控信号线51。
或者，参照图29所示，一个触控电极71连接有至少两根触控信号线51，例如，一个触控电极71可以连接有两根触控信号线51，一个触控电极71也可以连接有三根或更多根触控信号线51。
每根触控信号线51通过第三连接结构13连接于触控电极71；例如，在一个触控电极71连接有两根触控信号线51的情况下，两根触控信号线51包括第一触控信号线511和第二触控信号线512，第一触控信号线511通过第三连接结构13连接于触控电极71；第二触控信号线512也通过第三连接结构13连接于触控电极71。
在本公开的一些示例实施方式中，参照图30所示，一个触控电极71通过多个连接结构连接一根触控信号线51；多个连接结构中位于两端的是第三连接结构13，其余的连接结构包括第一连接结构11和第二连接结构12；第一连接结构11和第二连接结构12可以交叠设置。
或者，参照图31所示，多个连接结构中位于中部的是第三连接结构13，其余的连接结构包括第一连接结构11和第二连接结构12；第一连接结构11和第二连接结构12可以交叠设置。
在本公开的一些示例实施方式中，参照图32和图33所示，一个触控电极71连接有至少两根触控信号线51，例如，一个触控电极71可以连接有两根触控信号线51，一个触控电极71也可以连接有三根或更多根触控信号线51。
每根触控信号线51通过多个连接结构连接于触控电极71；例如，在一个触控电极71连接有两根触控信号线51的情况下，两根触控信号线51包括第一触控信号线511和第二触控信号线512，第一触控信号线511通过多个连接结构连接于触控电极71；第二触控信号线512也通过多个连接结构连接于触控电极71。
参照图32所示，多个连接结构中位于中部的是第三连接结构13，其余的连接结构可以包括第一连接结构11或第二连接结构12，第一连接结构11和第二连接结构12可以交叠设置。
或者，参照图33所示，多个连接结构中位于两端的是第三连接结构13，其余的连接结构可以包括第一连接结构11和第二连接结构12；第一连接结构11和第二连接结构12可以交叠设置。
需要说明的是，多个连接结构的中部不仅仅可以是多个连接结构中位于正中间的一个，例如，九个连接结构的中部可以是第五个，即九个连接结构中第五个是第三连接结构13；多个连接结构的中部还可以是中间一个区域内，例如，九个连接结构的中部可以是第四个、第五个和第六个，十个连接结构的中部可以是第四个、第五个、第六个和第七个。
另外，在本公开的其他一些示例实施方式中，参照图34所示，还可以是相邻两个第三连接结构13之间设置有一个第一连接结构11或第二连接结构12，而且第一连接结构11与第二连接结构12交替设置于相邻两个第三连接结构13之间。
参照图35所示，一个触控电极71连接有至少两根触控信号线51，连接于同一个触控电极71的至少两根触控信号线51形成一组触控信号线组51a。阵列基板还可以包括触控引线55，触控引线55可以位于设置触控控制电路9的非显示区域，触控引线55连接于至少两根触控信号线51的一端，以使至少两根触控信号线51并联，在属于同一组的相邻两根触控信号线51之间设置有数据线52，具体地，在属于同一组的相邻两根触控信号线51之间设置有一根数据线52；在相邻两组触控信号线组51a之间设置有数据线52，具体地，在相邻两组触控信号线组51a之间设置有一根数据线52。触控信号线51、数据线52以及触控引线55可以设置在同一层，即触控信号线51、数据线52以及触控引线55可以设置在第一导电层5。
阵列基板还可以包括数据引线23，数据引线23也可以位于设置触控控制电路9的非显示区域，数据引线23可以设置在栅极层2，数据引线23可以通过设置在栅绝缘层3上的数据过孔33与数据线52连接，从而避免数据引线23与触控引线55在同一层的交叉。
基于同一发明构思，本公开示例实施方式提供了一种触控显示装置，参照图36所示，该触控显示装置可以包括上述任意一项所述的阵列基板100，阵列基板100的具体结构上述已经进行了详细说明，因此，此处不再赘述。
该触控显示装置可以是液晶触控显示装置，具体地，该触控显示装置还不可以包括彩膜基板200、胶框400以及液晶层300；彩膜基板200设于阵列基板100背离第一衬底基板1的一侧；胶框400设于阵列基板100与彩膜基板200之间；液晶层300设于阵列基板100与彩膜基板200之间，且位于胶框400内。
而该触控显示装置的具体类型不受特别的限制，本领域常用的触控显示装置类型均可，具体例如手机等移动装置、手表等可穿戴设备等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该触控显示装置除了阵列基板100以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该触控显示装置的具体使用要求进行相应地补充，在此不再赘述。
与现有技术相比，本发明示例实施方式提供的触控显示装置的有益效果与上述示例实施方式提供的阵列基板100的有益效果相同，在此不做赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (24)

  1. 一种阵列基板，其中，包括：
    第一衬底基板；
    第一导电层，设于所述第一衬底基板的一侧，所述第一导电层包括触控信号线，所述触控信号线沿第一方向延伸；
    绝缘层组，设于所述第一导电层背离所述第一衬底基板的一侧，所述绝缘层组包括层叠设置的第一绝缘层组和第二绝缘层，所述第一绝缘层组上设置有多个第一过孔和多个第二过孔，所述第二绝缘层上设置有多个第三过孔；
    第二导电层，设于所述第一绝缘层组中的至少一层和所述第二绝缘层背离所述第一衬底基板的一侧，所述第二导电层包括触控电极，所述触控电极通过连通的所述第一过孔和所述第三过孔以及连通的所述第二过孔和所述第三过孔连接至所述触控信号线；
    其中，至少一个所述第一过孔和至少一个所述第二过孔连通至同一根所述触控信号线，所述第三过孔具有在所述第一方向上相对设置的第一孔壁和第二孔壁，在所述第一方向上，所述第一过孔相对于所述第二孔壁更靠近所述第一孔壁设置，所述第二过孔相对于所述第一孔壁更靠近所述第二孔壁设置。
  2. 根据权利要求1所述的阵列基板，其中，所述第一绝缘层组包括：
    第一绝缘层，设于所述第一导电层背离所述第一衬底基板的一侧，所述第一绝缘层上设置有多个第一子过孔和多个第二子过孔，所述第二绝缘层设于所述第一绝缘层背离所述第一衬底基板的一侧；
    和/或，第三绝缘层，设于所述第二绝缘层背离所述第一衬底基板的一侧，所述第三绝缘层上设置有多个第三子过孔和多个第四子过孔；
    其中，所述第一过孔包括所述第一子过孔和/或所述第三子过孔，所述第一子过孔和所述第三子过孔相互连通；所述第二过孔包括所述第二子过孔和/或所述第四子过孔，所述第二子过孔和所述第四子过孔相互连通。
  3. 根据权利要求2所述的阵列基板，其中，所述第一子过孔在所述第一衬底基板上的正投影位于所述第三过孔在所述第一衬底基板上的正投影之内，所述第三子过孔在所述第一衬底基板上的正投影与所述第三过孔在所述第一衬底基板上的正投影至少部分交叠。
  4. 根据权利要求3所述的阵列基板，其中，在所述第一过孔和所述第三过孔处，所述第三绝缘层覆盖所述第三过孔的孔壁；或者，所述第三绝缘层未覆盖所述第一孔壁，且所述第三绝缘层覆盖所述第二孔壁；或者，所述第三绝缘层未覆盖所述第一孔壁且未覆盖所述第二绝缘层背离所述第一衬底基板的一面的靠近所述第一孔壁的一部分，且所述第三绝缘层覆盖所述第二孔壁。
  5. 根据权利要求2所述的阵列基板，其中，所述第二子过孔在所述第一衬底基板上的正投影位于所述第三过孔在所述第一衬底基板上的正投影之内，所述第四子过孔在所述第一衬底基板上的正投影与所述第三过孔在所述第一衬底基板上的正投影至少部分交叠。
  6. 根据权利要求5所述的阵列基板，其中，在所述第二过孔和所述第三过孔处，所述第三绝缘层覆盖所述第三过孔的孔壁；或者，所述第三绝缘层未覆盖所述第二孔壁，且所述第三绝缘层覆盖所述第一孔壁；或者，所述第三绝缘层未覆盖所述第二孔壁且未覆盖所述第二绝缘层背离所述第一衬底基板的一面的靠近所述第二孔壁的一部分，且所述第三绝缘层覆盖所述第一孔壁。
  7. 根据权利要求2所述的阵列基板，其中，所述第一绝缘层和所述第三绝缘层的材质包括无机材料；所述第二绝缘层的材质包括有机材料。
  8. 根据权利要求2所述的阵列基板，其中，所述第二导电层设于所述第二绝缘层与所述第三绝缘层之间，所述触控电极延伸至所述第三过孔内的第二方向的一端部，所述第二方向与所述第一方向相交，且与所述第一衬底基板设置所述第一导电层的一面平行；所述阵列基板还包括：
    第三导电层，设于所述第三绝缘层背离所述第一衬底基板的一侧，所述第三导电层包括像素电极、第一连接部和第二连接部，所述像素电极与所述第一连接部以及所述第二连接部三者间隔设置，所述第一连接部通过所述第三过孔和所述第一过孔连接所述触控电极和所述触控信号线，所述第二连接部通过所述第三过孔和所述第二过孔连接所述触控电极和所述触控信号线；
    或者，所述第二导电层设于所述第三绝缘层背离所述第一衬底基板的一侧；所述阵列基板还包括：
    第三导电层，设于所述第二绝缘层与所述第三绝缘层之间，所述第三导电层包括像素电极。
  9. 根据权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    栅极层，设于所述第一衬底基板的一侧，所述栅极层包括栅极和栅线，所述栅极连接于所述栅线；
    栅绝缘层，设于所述栅极层背离所述第一衬底基板的一侧；
    有源层，设于所述栅绝缘层背离所述第一衬底基板的一侧，所述有源层包括沟道部以及设置在所述沟道部两端的源极连接部和漏极连接部；
    其中，所述第一导电层设于所述有源层背离所述第一衬底基板的一侧，所述第一导电层还包括数据线、源极和漏极，所述数据线沿所述第一方向延伸，并与所述触控信号线间隔设置，所述源极连接于所述数据线且连接于所述源极连接部，所述漏极连接于所述像素电极且连接于所述漏极连接部。
  10. 根据权利要求8所述的阵列基板，其中，所述第一导电层还包括栅极和栅线，所述栅极连接于所述栅线，所述栅线沿所述第一方向延伸，并与所述触控信号线间隔设置；所述第一绝缘层组还包括：
    栅绝缘层，设于所述第一导电层背离所述第一衬底基板的一侧，所述栅绝缘层上设置有多个第五子过孔和多个第六子过孔；
    其中，所述第一过孔包括相互连通的所述第一子过孔、所述第三子过孔和所述第五子过孔，所述第二过孔包括相互连通的所述第二子过孔、所述第四子过孔和所述第六子过孔。
  11. 根据权利要求8所述的阵列基板，其中，在第二方向上，所述第三子过孔在所述第一衬底基板上的正投影的边沿线与所述第三过孔在所述第一衬底基板上的正投影的边沿线之间的距离大于等于1微米且小于等于2.5微米；
    在所述第二方向上，所述第四子过孔在所述第一衬底基板上的正投影的边沿线与所述第三过孔在所述第一衬底基板上的正投影的边沿线之间的距离大于等于1微米且小于等于2.5微米，所述第二方向与所述第一方向相交，且与所述第一衬底基板设置所述第一导电层的一面平行。
  12. 根据权利要求1所述的阵列基板，其中，在所述第一方向上，所述第一过孔靠近所述第一孔壁的孔壁在所述第一衬底基板上的正投影与所述第一孔壁在所述第一衬底基板上的正投影之间的距离小于等于0.5微米；所述第一过孔靠近所述第二孔壁的孔壁在所述第一衬底基板上的正投影与所述第二孔壁在所述第一衬底基板上的正投影之间的距离大于等于1微米且小于等于2.5微米。
  13. 根据权利要求1所述的阵列基板，其中，在所述第一方向上，所述第二过孔靠近所述第二孔壁的孔壁在所述第一衬底基板上的正投影与所述第二孔壁在所述第一衬底基板上的正投影之间的距离小于等于0.5微米；所述第二过孔靠近所述第一孔壁的孔壁在所述第一衬底基板上的正投影与所述第一孔壁在所述第一衬底基板上的正投影之间的距离大于等于1微米且小于等于2.5微米。
  14. 根据权利要求1所述的阵列基板，其中，所述触控电极复用为公共电极。
  15. 根据权利要求1～14任意一项所述的阵列基板，其中，所述阵列基板包括：
    第一连接结构，包括所述第一过孔以及所述第三过孔；
    第二连接结构，包括所述第二过孔以及所述第三过孔。
  16. 根据权利要求15所述的阵列基板，其中，一个所述触控电极通过交替设置的所述第一连接结构和所述第二连接结构连接于一根所述触控信号线；
    或者，至少两个所述第一连接结构被包括于第一连接组，至少两个所述第二连接结构被包括于第二连接组，一个所述触控电极通过交替设置的所述第一连接组和所述第二连接组连接于一根所述触控信号线。
  17. 根据权利要求15所述的阵列基板，其中，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过交替设置的所述第一连接结构和所述第二连接结构连接于所述触控电极；
    或者，至少两个所述第一连接结构被包括于第一连接组，至少两个所述第二连接结构被包括于第二连接组，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过交替设置的所述第一连接组和所述第二连接组连接于所述触控电极。
  18. 根据权利要求17所述的阵列基板，其中，连接于相邻两根所述触控信号线的第一连接结构和第二连接结构错位设置。
  19. 根据权利要求15所述的阵列基板，其中，所述第一绝缘层组上还设置有第四过孔，所述第四过孔在所述第一衬底基板的正投影位于所述第三过孔在所述第一衬底基板上的正投影的中部区域；所述第三过孔以及所述第四过孔被包括于第三连接结构。
  20. 根据权利要求19所述的阵列基板，其中，所述第一连接结构、所述第二连接结构以及所述第三连接结构被包括于第三连接组；一个所述触控电极通过所述第三连接组连接于一根所述触控信号线；或者，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过所述第三连接结构连接于所述触控电极。
  21. 根据权利要求19所述的阵列基板，其中，一个所述触控电极通过多个连接结构连接一根所述触控信号线；多个所述连接结构中位于两端的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构；或者，多个所述连接结构中位于中部的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构。
  22. 根据权利要求19所述的阵列基板，其中，一个所述触控电极连接有至少两根所述触控信号线，每根所述触控信号线通过多个连接结构连接于所述触控电极；多个所述连接结构中位于两端的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构；或者，多个所述连接结构中位于中部的是所述第三连接结构，其余的所述连接结构包括所述第一连接结构和所述第二连接结构。
  23. 根据权利要求1～14任意一项所述的阵列基板，其中，一个所述触控电极连接有至少两根所述触控信号线，连接于同一个所述触控电极的至少两根所述触控信号线形成一组触控信号线组，所述阵列基板还包括：
    触控引线，连接于至少两根所述触控信号线的一端，以使至少两根所述触控信号线并联，在属于同一组的相邻两根所述触控信号线之间设置有数据线，在相邻两组触控信号线组之间也设置有数据线。
  24. 一种触控显示装置，其中，包括：权利要求1～23任意一项所述的阵列基板。
PCT/CN2025/090189 2024-05-30 2025-04-21 阵列基板及触控显示装置 Pending WO2025246729A1 (zh)

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