WO2025227331A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置

Info

Publication number
WO2025227331A1
WO2025227331A1 PCT/CN2024/090673 CN2024090673W WO2025227331A1 WO 2025227331 A1 WO2025227331 A1 WO 2025227331A1 CN 2024090673 W CN2024090673 W CN 2024090673W WO 2025227331 A1 WO2025227331 A1 WO 2025227331A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive block
display panel
conductive
orthographic projection
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/090673
Other languages
English (en)
French (fr)
Other versions
WO2025227331A9 (zh
Inventor
程羽雕
张顺
邓江涛
嵇凤丽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2024/090673 priority Critical patent/WO2025227331A1/zh
Priority to CN202480000851.8A priority patent/CN121241697A/zh
Publication of WO2025227331A1 publication Critical patent/WO2025227331A1/zh
Publication of WO2025227331A9 publication Critical patent/WO2025227331A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • This disclosure relates to the field of display technology, and more particularly to a display panel and display device.
  • OLED organic light-emitting diode
  • a display panel includes at least one semiconductor layer, a first scan signal line, and a second capacitor.
  • the at least one semiconductor layer includes a first channel portion and a first conductive portion.
  • the first scan signal line overlaps with the first conductive portion to form a first capacitor, and overlaps with the first channel portion to form a first transistor;
  • the second capacitor includes a first conductive block and a second conductive block, the second conductive block being disposed between the first conductive block and the semiconductor layer including the first channel portion, and the second conductive block being connected to the first conductive portion; wherein, in an orthographic projection onto a reference plane, the first conductive block covers a portion of the second conductive block disposed within the outer boundary of the first conductive block; and/or, the second capacitor further includes a third conductive block, the third conductive block being disposed on the side of the first conductive block away from the second conductive block, and the third conductive block at least partially overlapping the first conductive block; the third conductive block being connected to the
  • the second conductive block includes a first main body and a first connecting portion.
  • the orthographic projection of the first main body on the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference plane; the first connecting portion is connected to the first main body; at least a portion of the orthographic projection of the first connecting portion on the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block on the reference plane, and is connected to the first conductive portion.
  • the orthographic projection of the third conductive block on the reference surface is disposed within the range of the orthographic projection of the first conductive block on the reference surface; the display panel further includes a first connecting line, one end of which is connected to the first conductive part, and the other end of which is connected to the third conductive block.
  • the third conductive block includes a second main body and a second connecting portion.
  • the orthographic projection of the second main body on the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference plane; the second connecting portion is connected to the second main body; the second connecting portion is disposed on the periphery of the second main body; the display panel further includes a first connecting line, one end of the first connecting line being connected to the first conductive portion and the other end being connected to the second connecting portion.
  • At least a portion of the orthographic projection of the second connection portion onto the reference plane is disposed on the first...
  • a conductive block is located outside the outer boundary of its orthographic projection on the reference plane, and the portion of the second connecting part located outside the outer boundary of the first conductive block is connected to the first conductive part.
  • the orthographic projection of the first connecting portion on the reference surface is offset from the orthographic projection of the second connecting portion on the reference surface; the first connecting line is disposed on the side of the third conductive block away from the second conductive block, and the first connecting line is also connected to the first connecting portion.
  • the first conductive block is provided with a first through hole penetrating the first conductive block, and the third conductive block extends into the first through hole and connects with the second conductive block.
  • the third conductive block includes a second main body and a second connecting portion.
  • the orthographic projection of the second main body on the reference surface is disposed within the outer boundary of the orthographic projection of the second conductive block on the reference surface; the second main body extends into the first through hole and connects to the second conductive block; the second connecting portion is connected to the second main body, and at least a portion of the orthographic projection of the second connecting portion on the reference surface is disposed outside the outer boundary of the orthographic projection of the second conductive block on the reference surface; the display panel further includes a first connecting line, one end of which is connected to the first conductive portion, and the other end of which is connected to the second connecting portion.
  • the at least one semiconductor layer further includes a second channel portion; the display panel further includes a second scan signal line; the second scan signal line overlaps with the second channel portion to form a second transistor; the second scan signal line includes a first straight segment and a first bent segment.
  • the first straight segment extends along a first direction; in orthographic projection onto the reference surface, along the first direction, the first straight segment is disposed on one side of the connecting portion; along a second direction, the first straight segment is disposed between the main body portion and the first scan signal line; the first direction intersects the second direction; in orthographic projection onto the reference surface, the first bent segment bends toward the side of the first straight segment away from the main body portion.
  • the first scan signal line includes a first trace segment.
  • the orthographic projection of the first trace segment onto the reference plane coincides with the orthographic projection of the first conductive portion onto the reference plane, and the linewidth of the first trace segment is less than or equal to 2.5 ⁇ m.
  • the display panel includes a pixel circuit.
  • the pixel circuit includes a driving transistor, the driving transistor including a fourth channel portion; the orthographic projection of the fourth channel portion onto the reference plane coincides with the orthographic projection portion of the second conductive block onto the reference plane, and the portion of the second conductive block that coincides with the fourth channel portion forms the gate of the driving transistor.
  • the pixel circuit further includes a compensation transistor; a first terminal of the compensation transistor is connected to a second terminal of the driving transistor, and the second terminal is connected to the gate of the driving transistor; wherein the first conductive portion forms the second terminal of the compensation transistor.
  • the display panel further includes a pixel circuit, the pixel circuit including a data writing transistor; the data writing transistor is connected to a data signal terminal; wherein, the first transistor is the data writing transistor, and the portion of the first scan signal line that overlaps with the first channel portion forms the gate of the data writing transistor.
  • the display panel further includes a pixel circuit, the pixel circuit further includes a first reset transistor, the first terminal of the first reset transistor is connected to a first initialization signal terminal; the first reset transistor includes a third channel portion, the orthographic projection of the third channel portion on the reference plane coincides with the orthographic projection portion of the first scan signal line on the reference plane, and the portion of the first scan signal line that coincides with the third channel portion forms the gate of the first reset transistor.
  • the display device includes a display panel as described in any of the above embodiments.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is another structural diagram of a display device according to some embodiments.
  • Figure 3 is a structural diagram of a display device according to some embodiments, including a display panel and a driving circuit board;
  • Figure 4 is a structural diagram of a display panel according to some embodiments.
  • Figure 5 is a cross-sectional view along the cutting line A-A in Figure 4.
  • Figure 6 is another structural diagram of a display panel according to some embodiments.
  • Figure 7 is another structural diagram of a display panel according to some embodiments.
  • Figure 8 is a structural diagram of a second conductive block according to some embodiments, including a first main body and a first connecting part;
  • Figure 9 is another structural diagram of a display panel according to some embodiments.
  • Figure 10 is a structural diagram of a first conductive block having a first through hole according to some embodiments.
  • Figure 11 is another structural diagram of a display panel according to some embodiments.
  • Figure 12 is another structural diagram of a display panel according to some embodiments.
  • Figure 13 is another structural diagram of a display panel according to some embodiments.
  • Figure 14 is another structural diagram of a display panel according to some embodiments.
  • Figure 15 is a structural diagram of a pixel circuit according to some embodiments.
  • Figure 16 is another structural diagram of a display panel according to some embodiments.
  • Figure 17 is another cross-sectional view along the cutting line A-A in Figure 4.
  • first and second are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of that feature.
  • a plurality of means two or more.
  • Coupled and “connected,” and their derivative expressions, may be used.
  • the term “connected” should be interpreted broadly; for example, a “connection” can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.
  • the term “coupled,” for example, indicates that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”.
  • the phrase “if it is determined that...” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that...”, “in response to determination that...”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.
  • parallel As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).
  • parallel includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°
  • equal includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
  • a layer or element when referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
  • a display device 1000 which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) text or images.
  • the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, or flight display.
  • PDA personal digital assistant
  • AR augmented reality
  • VR virtual reality
  • in-vehicle display or flight display.
  • the display device 1000 can be a portable display product.
  • the display device 1000 can be a mobile phone as shown in Figure 1.
  • the display device 1000 can be a wearable device.
  • the display device 1000 can be a watch as shown in Figure 2.
  • the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.
  • the display panel 100 has opposing light-emitting side 100A and non-light-emitting side 100B.
  • the light-emitting side 100A refers to the light-emitting side...
  • the side of the display panel 100 that emits light (the upper side of the display panel 100 in Figure 3) is the side that emits light, while the non-emitting side 100B refers to the other side opposite to the emitting side 100A (the lower side of the display panel 100 in Figure 3).
  • the driving circuit board 200 is located on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide light-emitting signals to the display panel 100.
  • the housing 300 can be a box-shaped structure with an opening.
  • the display panel 100 and the driving circuit board 200 can be disposed inside the housing 300.
  • the cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.
  • the longitudinal section of the housing 300 can be U-shaped, for example.
  • the display panel 100 and the driving circuit board 200 are disposed inside the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.
  • the aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.
  • the display panel 100 described above may be: an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, or a mini/micro light-emitting display (MLED) display panel, etc.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • AMOLED active matrix organic light-emitting diode
  • LCD liquid crystal display
  • MLED mini/micro light-emitting display
  • the following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.
  • the display panel 100 includes a reference surface and a plurality of sub-pixels 20.
  • the reference surface can be made of polymer resin or glass.
  • the reference surface can be flexible, and the material used includes polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP).
  • PES polyethersulfone
  • PAR polyarylate
  • PEI polyetherimide
  • PEN polyethylene naphthalate
  • PET polyethylene terephthalate
  • PPS polyphenylene sulfide
  • PI polyimide
  • PC polycarbonate
  • CAP cellulose acetate propionate
  • the reference surface can be rigid, including glass materials containing SiO2 as a main component.
  • multiple sub-pixels 20 are disposed on a reference plane. These sub-pixels 20 can be arranged in multiple rows and columns, for example. Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X, and each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y.
  • the first direction X intersects the second direction Y; for example, the first direction X is perpendicular to the second direction Y.
  • the aforementioned plurality of sub-pixels 20 may include a first sub-pixel with a first emission color, a second sub-pixel with a second emission color, and a third sub-pixel with a third emission color.
  • the third color is one of the three primary colors.
  • the first color is red
  • the second color is blue
  • the third color is green. This disclosure does not specifically limit the embodiments herein.
  • each sub-pixel 20 includes a pixel circuit 21 and a light-emitting device 22 disposed on a reference surface.
  • the pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (C).
  • the transistors used in the circuits provided in some embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics.
  • thin-film transistors are used as an example for illustration.
  • transistor 211 is an oxide thin-film transistor, which has a higher carrier mobility, thus improving the response speed of transistor 211.
  • transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114, with the source 2112 and drain 2113 respectively in contact with the active portion 2111.
  • Storage capacitor 212 includes two plates disposed opposite to each other.
  • source 2112 and drain 2113 mentioned above can be interchanged, that is, 2112 in Figure 5 represents the drain and 2113 represents the source.
  • the active portion 2111 includes a source portion, a drain portion, and a channel portion, with the channel portion disposed between the source portion and the drain portion, the source portion being in contact with the source, and the drain portion being connected to the drain.
  • the light-emitting device 22 includes a first electrode 221, a light-emitting functional layer 222, and a second electrode 223.
  • the first electrode 221 may be electrically connected to, for example, the source 2112 or drain 2113 of a plurality of transistors 211 that serve as driving transistors.
  • FIG5 illustrates the electrical connection between the first electrode 221 and the drain 2113 of the transistor 211.
  • the material of the first electrode 221 includes indium tin oxide (ITO) or silver (Ag).
  • the material of the second electrode includes aluminum (Al), Ag, or magnesium (Mg).
  • the first electrode 221 is the anode of the light-emitting device 22, and the second electrode 223 is the cathode of the light-emitting device 22; or, the first electrode 221 is the cathode of the light-emitting device 22, and the second electrode 223 is the anode of the light-emitting device 22.
  • the following example using the first electrode 221 as the anode of the light-emitting device 22 and the second electrode 223 as the cathode of the light-emitting device 22, provides an exemplary description of the embodiments of this disclosure.
  • the second electrode 223 (cathode) is a monolayer structure.
  • the aforementioned light-emitting functional layer 222 may include only the light-emitting layer, or it may include, in addition to the light-emitting layer, at least one of the following: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).
  • ETL electron transport layer
  • EIL electron injection layer
  • HTL hole transport layer
  • HIL hole injection layer
  • the display panel 100 further includes an encapsulation layer 30.
  • the encapsulation layer 30 is disposed on the side of the plurality of sub-pixels 20 away from the reference surface, and the encapsulation layer 30 is used to encapsulate the light-emitting device 22, improving the light-emitting device 22's performance. Lifespan.
  • the encapsulation layer 30 can be an encapsulation film or an encapsulation substrate; this embodiment does not specifically limit the application.
  • the encapsulation layer 30 may include a single encapsulation film, or it may include two or more encapsulation films stacked together.
  • the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 stacked along a direction perpendicular to and away from the reference plane.
  • the materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide.
  • the material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.
  • the display panel 100 further includes at least one semiconductor layer 40, which includes a first channel portion 41 and a first conductive portion 42.
  • the first conductive portion 42 may be either the source portion or the drain portion described above.
  • the display panel 100 includes only one semiconductor layer 40, that is, the display panel 100 includes a first semiconductor layer, the first semiconductor layer including a first channel portion 41 and a first conductive portion 42.
  • the display panel includes two semiconductor layers 40, that is, the display panel 100 includes a first semiconductor layer and a second semiconductor layer.
  • a first channel portion 41 is disposed on the first semiconductor layer, and a first conductive portion 42 is disposed on the second semiconductor layer; or, the first channel portion 41 is disposed on the second semiconductor layer, and the first conductive portion 42 is disposed on the first semiconductor layer.
  • the first semiconductor layer is a low-temperature polycrystalline silicon (LTPS) semiconductor layer
  • the second semiconductor layer is an oxide semiconductor layer.
  • LTPS transistors and oxide transistors can be integrated on a single display panel 100.
  • the power consumption of the display panel 100 can be reduced, and the display quality of the display panel 100 can be improved.
  • the display panel 100 also includes a first scan signal line 60.
  • the first scan signal line 60 is connected to the pixel circuit 21.
  • the first scan signal line 60 overlaps with the first conductive portion 42 to form a first capacitor 1, and overlaps with the first channel portion 41 to form a first transistor 2.
  • the first scan signal line 60 is used to control the conduction and cutoff of the first transistor 2.
  • the display panel 100 also includes a second capacitor 50 (e.g., a storage capacitor 212 in the pixel circuit 21).
  • the second capacitor 50 includes a first conductive block 51 and a second conductive block 52.
  • the second conductive block 52 is disposed between the first conductive block 51 and the semiconductor layer 40 including the first channel portion 41, and the second conductive block 52 is connected to the first conductive portion 42. That is, the first capacitor 50 and the second capacitor 50 are connected in parallel.
  • the first conductive block has a through-hole
  • the display panel also includes a connecting wire.
  • One end of the connecting wire is connected to the first channel portion, and the other end passes through the through-hole to connect to the second conductive block.
  • the through-hole in the first conductive block results in a small overlap area between the first and second conductive blocks, leading to a smaller capacitance in the second capacitor.
  • the smaller capacitance of the second capacitor results in a larger capacitance of the first capacitor, thus causing a larger voltage drop on the first scan signal. This leads to severe lateral crosstalk and poor brightness uniformity in the display panel. Poor sexual performance.
  • some embodiments of the present disclosure provide a display panel 100, in which a first conductive block 51 covers a portion of a second conductive block 52 disposed within the outer boundary of the first conductive block 51 in a projection onto a reference plane.
  • some embodiments of this disclosure do not provide through holes in the portion of the first conductive block 51 that forms the second capacitor 50. This increases the relative area of the two plates of the second capacitor 50, thereby increasing its capacitance. At this time, while keeping the total capacitance of the first capacitor 1 and the second capacitor 50 constant, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing lateral crosstalk of the display panel 100, and improving the brightness uniformity of the display panel 100, which is beneficial for improving the display effect of the display panel 100.
  • the reference plane is the plane on which the display surface of the display panel 100 is located.
  • the second capacitor 50 further includes a third conductive block 53.
  • the third conductive block 53 is disposed on the side of the first conductive block 51 away from the second conductive block 52; the third conductive block 53 at least partially overlaps with the first conductive block 51, and the third conductive block 53 is connected to the first conductive portion 42.
  • the third conductive block 53 and the second conductive block 52 are connected, and together they form one plate of the second capacitor 50, thereby increasing the relative area of the two plates of the second capacitor 50.
  • the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing lateral crosstalk of the display panel 100, and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.
  • the second conductive block 52 includes a first main body portion 521 and a first connecting portion 522.
  • the orthographic projection of the first main body portion 521 on the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 on the reference plane.
  • the first connecting portion 522 is connected to the first main body portion 521, and at least a portion of the orthographic projection of the first connecting portion 522 on the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block 52 on the reference plane, and is connected to the first conductive portion 42.
  • the orthographic projection of the third conductive block 53 on the reference plane is set within the range of the orthographic projection of the first conductive block 51 on the reference plane.
  • the display panel 100 also includes a first connecting line 70, one end of which is connected to the first conductive part 42, and the other end is connected to the third conductive block 53, so that the third conductive block 53 and the first conductive part 42 are connected.
  • the third conductive block 53 includes a second main body portion 531 and a second connecting portion 532.
  • the orthographic projection of the second main body portion 531 onto the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane.
  • the second connecting portion 532 is connected to the second main body portion 531 and is disposed on the periphery of the second main body portion 531.
  • the display panel 100 also includes a first connecting line 70, one end of which is connected to a first conductive line. One end is connected to the first conductive part 42, and the other end is connected to the second connecting part 532. This connects the third conductive block 53 and the first conductive part 42.
  • At least a portion of the orthographic projection of the second connecting portion 532 on the reference plane is disposed outside the outer boundary of the orthographic projection of the first conductive block 51 on the reference plane, and the portion of the second connecting portion 532 disposed outside the outer boundary of the first conductive block 51 is connected to the first conductive portion 42.
  • the relative area of the third conductive block 53 and the second conductive block 52 can be increased, further increasing the relative area of the two plates of the second capacitor 50 and increasing the capacitance of the second capacitor 50.
  • the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.
  • the orthographic projection of the first connecting portion 522 on the reference plane is offset from the orthographic projection of the second connecting portion 532 on the reference plane.
  • the first connecting line 70 is also connected to the first connecting portion 522.
  • the film layer between the second conductive block 52 and/or the third conductive block 53 and the first conductive block 51 is reduced, which can decrease the distance between the second conductive block 52 and/or the third conductive block 53 and the first conductive block 51, reduce the distance between the two plates of the second capacitor 50, and further increase the capacitance of the second capacitor 50.
  • the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.
  • the first conductive block 51 is provided with a first through hole 511 penetrating the first conductive block 51.
  • the third conductive block 53 extends into the first through hole 511 and connects with the second conductive block 52. In this way, the second conductive block 52 and the third conductive block 53 can be connected.
  • the third conductive block 53 includes a second main body portion 531 and a second connecting portion 532.
  • the orthographic projection of the second main body portion 531 onto the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane.
  • the second main body portion 531 extends into the first through hole 511 and connects to the second conductive block 52.
  • the second connecting portion 532 is connected to the second main body portion 531, and at least a portion of the orthographic projection of the second connecting portion 532 onto the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane.
  • the display panel 100 also includes a first connecting line 70, one end of which is connected to the first conductive part 42, and the other end is connected to the second connecting part 532. In this way, the first conductive part 42, the second conductive block 52, and the third conductive block 53 can be connected.
  • the second conductive block 52 includes a first main body portion 521 and a first connecting portion 522.
  • the orthographic projection of the first main body portion 521 onto the reference plane is disposed within the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane.
  • At least a portion of the orthographic projection of the first connecting portion 522 onto the reference plane is disposed outside the outer boundary of the orthographic projection of the second conductive block 52 onto the reference plane.
  • a third conductive block 53 extends into the first through hole 511 and connects to the first main body portion 521.
  • the display panel 100 also includes a first connecting line 70, one end of which is connected to a first conductive line. One end is connected to part 42, and the other end is connected to the first connecting part 522. In this way, the first conductive part 42, the second conductive block 52, and the third conductive block 53 can be connected.
  • At least one semiconductor layer 40 further includes a second channel portion 43.
  • the display panel also includes a second scan signal line 80, which is connected to the pixel circuit 21.
  • the second scan signal line 80 overlaps with the second channel portion 43 to form a second transistor 3.
  • the second scan signal line 80 is used to control the conduction or cutoff of the second transistor 3.
  • the second channel portion 43 may be disposed in the same layer as the first channel portion 41, or the second channel portion 43 may be disposed in the same layer as the first conductive portion 42.
  • the second channel portion 43 and the first conductive portion 42 are disposed in the same layer.
  • the second scan signal line 80 includes a first straight segment 81 and a first bent segment 82.
  • the first straight segment 81 extends along a first direction X.
  • the first straight segment 81 is disposed on one side of the connecting portion (first connecting portion 522 or second connecting portion 532), and along the second direction Y, the first straight segment 81 is disposed between the main body portion (first main body portion 521 or second main body portion 531) and the first scan signal line 60.
  • the first bent segment 82 bends toward the side of the first straight segment 81 away from the main body portion to avoid the connecting portion. In this way, the size of the pixel circuit 21 along the second direction Y can be reduced, thereby increasing the number of pixel circuits 21, which is beneficial to improving the resolution of the display panel 100.
  • the first scan signal line 60 includes a first trace segment 61
  • the orthographic projection of the first trace segment 61 on the reference plane coincides with the orthographic projection of the first conductive portion 42 on the reference plane
  • the line width of the first trace segment 61 is less than or equal to 2.5 ⁇ m.
  • the relative area between the first scan signal line 60 and the first conductive part 42 can be reduced, the capacitance of the first capacitor 1 can be reduced, thereby reducing the voltage drop of the first scan signal line 60, reducing the lateral crosstalk of the display panel 100 and improving the brightness uniformity of the display panel 100, which is beneficial to improving the display effect of the display panel 100.
  • the line width of the third trace segment is 2.5 ⁇ m, 2 ⁇ m, 1.4 ⁇ m or 0.9 ⁇ m.
  • the pixel circuit 21 includes a driving transistor T1, a compensation transistor T2, a data writing transistor T3, a first reset transistor T4, a second reset transistor T5, a first light-emitting transistor T6, a second light-emitting transistor T7, and a first storage capacitor C1.
  • the control gate of the driving crystal T1 is connected to the first node N1, the first gate is connected to the second node N2, and the second gate is connected to the third node N3.
  • the first gate of the compensation transistor T2 is connected to the third node N3, the second gate is connected to the first node N1, and the control gate is connected to the first scan signal terminal GATE1.
  • the first gate of the data writing transistor T3 is connected to the data signal terminal DATA, the second gate is connected to the second node N2, and the control gate is connected to the second scan signal terminal GATE2.
  • the first gate of the first reset transistor T4 is connected to the first initialization signal terminal VINIT1, the second gate is connected to the anode of the light-emitting device 22, and the control gate is connected to the first reset signal terminal RESET1.
  • the first gate of the second reset transistor T5 is connected to the first initialization signal terminal VINIT1.
  • the first light-emitting transistor T6 is connected to the second initialization signal terminal VINIT2, its second electrode is connected to the first node N1, and its control electrode is connected to the second reset signal terminal RESET2.
  • the first electrode of the first light-emitting transistor T6 is connected to the first voltage signal terminal VDD, its second electrode is connected to the second node N2, and its control electrode is connected to the light-emitting signal terminal EM.
  • the first electrode of the second light-emitting transistor T7 is connected to the third node N3, its second electrode is connected to the anode of the light-emitting device 22, and its control electrode is connected to the light-emitting signal terminal EM.
  • the cathode of the light-emitting device 22 is connected to the second voltage signal terminal VSS.
  • the output level of the second voltage signal terminal VSS is lower than the output level of the first voltage signal terminal VDD.
  • the driving transistor T1 includes a fourth channel portion T13.
  • the orthographic projection of the fourth channel portion T13 onto the reference plane coincides with the orthographic projection of the second conductive block 52 onto the reference plane.
  • the portion of the second conductive block 52 that coincides with the fourth channel portion T13 forms the gate of the driving transistor T1.
  • the fourth channel portion T13 is disposed on the first semiconductor layer 101.
  • the first conductive part 42 forms the second electrode of the compensation transistor T2.
  • the first transistor 2 is a data writing transistor T3, and the portion of the first scan signal line 60 that overlaps with the first channel portion 41 forms the gate of the data writing transistor T3.
  • the first reset transistor T4 includes a third channel portion T43.
  • the orthographic projection of the third channel portion T43 on the reference plane coincides with the orthographic projection of the first scan signal line 60 on the reference plane.
  • the portion of the first scan signal line 60 that coincides with the third channel portion T43 forms the gate of the first reset transistor T4.
  • the difference in potential between the anodes of the light-emitting devices 22 of the multiple sub-pixels 20 can be reduced, thereby improving the brightness uniformity of the display panel 100.
  • the first reset signal terminal RESET1 and the first scan signal terminal GATE1 in a pixel circuit 21 are connected to the same first scan signal line 60.
  • the sub-pixels 20 are arranged in an array with multiple rows and columns, and the first scan signal terminal GATE1 in a pixel circuit 21 and the first reset signal terminal RESET1 in a pixel circuit 21 in the previous row are connected to the same first scan signal line 60.
  • the first conductive layer 103, the second conductive layer 104, the third conductive layer 105, the fourth conductive layer 106, and the fifth conductive layer 107 are illustrated below with reference to the film layers included in the display panel 100.
  • the pixel circuit 21 includes a low-temperature polycrystalline silicon thin-film transistor and an oxide thin-film transistor.
  • the display panel 100 further includes a low-temperature polycrystalline silicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first interlayer insulating layer ILD1, an oxide semiconductor layer ACT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a second interlayer insulating layer ILD2, a first source/drain conductive layer SD1, a first planarization layer PLN1, a second source/drain conductive layer SD2, and a second planarization layer PLN2.
  • the first channel portion 41 is disposed on the low-temperature polycrystalline silicon semiconductor layer ACT1, and the second conductive block 52 and The first scan signal line 60 is disposed on the first gate conductive layer GT1, the first conductive block 51 is disposed on the second gate conductive layer GT2, the first conductive portion 42 and the second channel portion 43 are disposed on the oxide semiconductor layer ACT2, the third conductive block 53 and the second scan signal line 80 are disposed on the third gate conductive layer GT3, and the first connecting line 70 is disposed on the first source-drain conductive layer SD1.
  • the pixel circuit 21 includes only low-temperature polycrystalline silicon thin-film transistors.
  • the display panel 100 further includes a low-temperature polycrystalline silicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a first interlayer insulating layer ILD1, a first source-drain conductive layer SD1, a first planarization layer PLN1, a second source-drain conductive layer SD2, and a second planarization layer PLN2.
  • the first channel portion 41, the second channel portion 43, and the first conductive portion 42 are disposed on the low-temperature polycrystalline silicon semiconductor layer ACT1
  • the second conductive block 52 and the first scan signal line 60 are disposed on the first gate conductive layer GT1
  • the first conductive block 51 is disposed on the second gate conductive layer GT2
  • the third conductive block 53 and the second scan signal line 80 are disposed on the third gate conductive layer GT3
  • the first connecting line 70 is disposed on the first source-drain conductive layer SD1.

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Abstract

一种显示面板及显示装置，显示面板包括至少一层半导体层、第一扫描信号线和第二电容器。至少一层半导体层包括第一沟道部和第一导电部。第一扫描信号线与第一导电部交叠形成第一电容器，且与第一沟道部交叠形成第一晶体管；第二电容器包括第一导电块和第二导电块，第二导电块设置于第一导电块和包括第一沟道部的半导体层之间，且第二导电块与第一导电部连接；其中，在向参考面上的正投影中，第一导电块覆盖，第二导电块中设置于第一导电块的外侧边界内的部分；和/或，第二电容器还包括第三导电块，第三导电块设置于第一导电块远离第二导电块的一侧，且第三导电块与第一导电块至少部分交叠；第三导电块和第一导电部连接。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
随着显示技术的发展，显示装置(比如手机、笔记本电脑或者平板电脑等)越来越多的应用于人们的生活中。其中，有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示装置具有主动发光、广视角、对比度高、响应速度快、耗电低、超轻薄等优点，因此受到广泛关注。
发明内容
一方面，提供一种显示面板。所述显示面板包括至少一层半导体层、第一扫描信号线和第二电容器。所述至少一层半导体层包括第一沟道部和第一导电部。所述第一扫描信号线与所述第一导电部交叠形成第一电容器，且与所述第一沟道部交叠形成第一晶体管；所述第二电容器包括第一导电块和第二导电块，所述第二导电块设置于所述第一导电块和包括所述第一沟道部的半导体层之间，且所述第二导电块与所述第一导电部连接；其中，在向参考面上的正投影中，所述第一导电块覆盖，所述第二导电块中设置于所述第一导电块的外侧边界内的部分；和/或，所述第二电容器还包括第三导电块，所述第三导电块设置于所述第一导电块远离所述第二导电块的一侧，且所述第三导电块与所述第一导电块至少部分交叠；所述第三导电块和所述第一导电部连接。
在一些实施例中，所述第二导电块包括第一主体部和第一连接部。所述第一主体部在所述参考面上的正投影设置于所述第二导电块在所述参考面上的正投影的外侧边界内；所述第一连接部与所述第一主体部连接；所述第一连接部的至少部分在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界外，且与所述第一导电部连接。
在一些实施例中，所述第三导电块在所述参考面上的正投影，设置于所述第一导电块在所述参考面上的正投影的范围内；所述显示面板还包括第一连接线，所述第一连接线的一端与所述第一导电部连接，另一端与所述第三导电块连接。
在一些实施例中，所述第三导电块包括第二主体部和第二连接部。所述第二主体部在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界内；所述第二连接部与所述第二主体部连接；所述第二连接部设置于所述第二主体部的周侧；所述显示面板还包括第一连接线，所述第一连接线的一端与所述第一导电部连接，另一端与所述第二连接部连接。
在一些实施例中，至少部分所述第二连接部在所述参考面上的正投影，设置于所述第 一导电块在所述参考面上的正投影的外侧边界外，所述第二连接部中设置于所述第一导电块外侧边界外的部分与所述第一导电部连接。
在一些实施例中，所述第一连接部在所述参考面上的正投影，与所述第二连接部在所述参考面上的正投影错开设置；所述第一连接线设置于所述第三导电块远离所述第二导电块的一侧，所述第一连接线还与所述第一连接部连接。
在一些实施例中，所述第一导电块设有贯穿所述第一导电块第一通孔，所述第三导电块伸入所述第一通孔与所述第二导电块连接。
在一些实施例中，所述第三导电块包括第二主体部和第二连接部。所述第二主体部在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界内；所述第二主体部伸入所述第一通孔与所述第二导电块连接；所述第二连接部与所述第二主体部连接，至少部分所述第二连接部在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界外；所述显示面板还包括第一连接线，所述第一连接线的一端与所述第一导电部连接，另一端与所述第二连接部连接。
在一些实施例中，所述至少一层半导体层还包括第二沟道部；所述显示面板还包括第二扫描信号线；所述第二扫描信号线，与所述第二沟道部交叠形成第二晶体管；所述第二扫描信号线包括第一直线段和第一弯折段。所述第一直线段沿第一方向延伸；在向所述参考面的正投影中，沿所述第一方向，所述第一直线段设置于连接部的一侧；沿第二方向，所述第一直线段设置于主体部和所述第一扫描信号线之间；所述第一方向与所述第二方向交叉；所述第一弯折段在向所述参考面的正投影中，所述第一弯折段朝向所述第一直线段远离所述主体部的一侧弯曲。
在一些实施例中，所述第一扫描信号线包括第一走线段。所述第一走线段在所述参考面上的正投影，与所述第一导电部在所述参考面上的正投影重合，所述第一走线段的线宽小于或者等于2.5μm。
在一些实施例中，所述显示面板包括像素电路。所述像素电路包括驱动晶体管，所述驱动晶体管包括第四沟道部；所述第四沟道部在所述参考面上的正投影，与所述第二导电块在所述参考面上的正投影部分重合，所述第二导电块中与所述第四沟道部中重合的部分形成所述驱动晶体管的栅极。
在一些实施例中，所述像素电路还包括补偿晶体管；所述补偿晶体管的第一极与所述驱动晶体管的第二极连接，第二极与所述驱动晶体管的栅极连接；其中，所述第一导电部形成所述补偿晶体管的第二极。
在一些实施例中，所述显示面板还包括像素电路，所述像素电路包括数据写入晶体管；所述数据写入晶体管与数据信号端连接；其中，所述第一晶体管为所述数据写入晶体管，所述第一扫描信号线中与所述第一沟道部交叠的部分形成所述数据写入晶体管的栅极。
在一些实施例中，所述的显示面板还包括像素电路，所述像素电路还包括第一复位晶体管，所述第一复位晶体管的第一极与第一初始化信号端连接；所述第一复位晶体管包括第三沟道部，所述第三沟道部在所述参考面上的正投影，与所述第一扫描信号线在所述参考面上的正投影部分重合，所述第一扫描信号线中与所述第三沟道部重合的部分形成所述第一复位晶体管的栅极。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的一种结构图；
图2为根据一些实施例的显示装置的另一种结构图；
图3为根据一些实施例的显示装置包括显示面板和驱动电路板的结构图；
图4为根据一些实施例的显示面板的结构图；
图5为图4中沿剖切线A-A的一种截面图；
图6为根据一些实施例的显示面板的另一种结构图；
图7为根据一些实施例的显示面板的又一种结构图；
图8为根据一些实施例的第二导电块包括第一主体部和第一连接部的结构图；
图9为根据一些实施例的显示面板的又一种结构图；
图10为根据一些实施例的第一导电块设置有第一通孔的结构图；
图11为根据一些实施例的显示面板的又一种结构图；
图12为根据一些实施例的显示面板的又一种结构图；
图13为根据一些实施例的显示面板的又一种结构图；
图14为根据一些实施例的显示面板的又一种结构图；
图15为根据一些实施例的像素电路的结构图；
图16为根据一些实施例的显示面板的又一种结构图；
图17为图4中沿剖切线A-A的另一种截面图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的 实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。术语“耦接”例如表明两个或两个以上部件有直接物理接触或电接触。术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
如图1和图2所示，本公开的一些实施例提供了一种显示装置1000，显示装置1000可以是显示不论运动(例如，视频)的还是固定(例如，静止图像)的且不论文字的还是图像的任何装置。
示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(英文：Personal Digital Assistant，简称：PDA)、导航仪、可穿戴设备、增强现实(英文：Augmented Reality，简称：AR)设备、虚拟现实(英文：Virtual Reality，简称：VR)设备、车载显示器、飞行显示器等任何具有显示功能的产品或者部件。
在一些示例中，如图1所示，该显示装置1000可以为便携式显示产品。比如，该显示装置1000可以为图1所示的手机。
在又一些示例中，如图2所示，该显示装置1000可以为可穿戴设备。比如，该显示装置1000可以为图2所示的手表。
在一些实施例中，如图3所示，显示装置1000包括显示面板100、驱动电路板200、壳体300和盖板400。
其中，显示面板100具有相对的发光侧100A和非发光侧100B，发光侧100A是指显 示面板100能够出光的一侧(图3中显示面板100的上侧)，非发光侧100B是指与发光侧100A相对的另一侧(图3中显示面板100的下侧)。
驱动电路板200设置于显示面板100的非发光侧，且与显示面板100连接，以向显示面板100提供发光信号。
壳体300可以为具有开口的盒状结构，显示面板100和驱动电路板200可以设置于壳体300内，盖板400设置于显示面板100的出光侧，且位于壳体300的开口处。
如图3所示，壳体300的纵截面例如可以呈U型，显示面板100和驱动电路板200设置于壳体300内，盖板400设置于壳体300的开口处。
上述显示面板100的类型包括多种，可以根据实际需要选择设置。
示例性地，上述显示面板100可以为：有机电致发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)显示面板、量子点电致发光二极管(英文：Quantum Dot Light Emitting Diodes，简称：QLED)显示面板、有源矩阵有机发光二极管(英文：Active Matrix Organic Light Emitting Diode，简称：AMOLED)显示面板、液晶(英文：Liquid Crystal Display，简称：LCD)显示面板或微型发光(英文：Mini/Micro Light Emitting Display，简称：MLED)显示面板等，本公开实施例在此不做具体限定。
下面以上述显示面板100为OLED显示面板为例，对本公开的一些实施例进行示意性的说明。
在一些实施例中，如图4和图5所示，显示面板100包括参考面和多个子像素20。
上述参考面采用的材料可以包括聚合物树脂或玻璃。示例性地，参考面可以是柔性的，参考面采用的材料包括聚合物树脂，比如聚醚砜(英文：Polyethersulfone，简称：PES)、聚芳酯(英文：Polyarylate，简称：PAR)、聚醚酰亚胺(英文：Polyetherimide，简称：PEI)、聚萘二甲酸乙二醇酯(英文：Polyethylene Naphthalate Two Formic Acid Glycol Ester，简称：PEN)、聚对苯二甲酸乙二醇酯(英文：Polyethylene Terephthalate，简称：PET)、聚苯硫醚(英文：Polyphenyl Sulfide Granula，简称：PPS)、聚酰亚胺(英文：Polyimide，简称：PI)、聚碳酸酯(英文：Polycarbonate，简称：PC)和乙酸丙酸纤维素(英文：Cellulose Acetate Propionate，简称：CAP)中的一种。示例性地，参考面可以是刚性的，包括包含SiO2作为主要成分的玻璃材料。
如图4所示，多个子像素20设置于参考面上，多个子像素20例如可以排列成多行多列，每行子像素20包括沿第一方向X排列的至少两个子像素20，每列子像素20包括沿第二方向Y排列的至少两个子像素20。其中，第一方向X与第二方向Y交叉，例如，第一方向X与第二方向Y垂直。
上述多个子像素20可以包括发光颜色为第一颜色的第一子像素、发光颜色为第二颜色的第二子像素、以及发光颜色为第三颜色的第三子像素。其中，第一颜色、第二颜色和 第三颜色为三基色。例如，第一颜色为红色，第二颜色为蓝色，第三颜色为绿色，本公开实施例在此不做具体限定。
在一些实施例中，如图4和图5所示，每个子像素20均包括设置于参考面上的像素电路21和发光器件22。
在一些实施例中，像素电路21包括多个晶体管211和存储电容器212(英文：Capacitor，简称：C)。
本公开的一些实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的一些实施例中均以薄膜晶体管为例进行说明。
示例性地，晶体管211例如为氧化物薄膜晶体管，氧化物薄膜晶体管的载流子迁移率较高，能够提高晶体管211的响应速度。
在一些实施例中，如图5所示，晶体管211包括有源部2111、源极2112、漏极2113和栅极2114，源极2112和漏极2113分别与有源部2111接触。存储电容器212包括相对设置的两个极板。
需要说明的是，上述源极2112和漏极2113可以互换，即图5中的2112表示漏极，2113表示源极。
在一些示例中，有源部2111包括源极部、漏极部和沟道部，沟道部设置于源极部和漏极部之间，源极部和源极接触，漏极部和漏极连接。
在一些实施例中，如图5所示，发光器件22包括第一电极221、发光功能层222和第二电极223，第一电极221例如可以和多个晶体管211中作为驱动晶体管的源极2112或漏极2113电连接，图5中以第一电极221和晶体管211的漏极2113电连接进行示意。其中，第一电极221的材料包括铟锡氧化物(英文：Indium Tin Oxide，简称：ITO)或者银(Ag)。第二电极的材料包括铝(Al)、Ag或者镁(Mg)。
需要说明的是，上述第一电极221为发光器件22的阳极，第二电极223为发光器件22的阴极；或者，第一电极221为发光器件22的阴极，第二电极223为发光器件22的阳极。以下以第一电极221为发光器件22的阳极，第二电极223为发光器件22的阴极为例对本公开实施例进行示例性说明。
示例性地，如图5所示，第二电极223(阴极)为整层结构。
其中，上述发光功能层222可以仅包括发光层，也可以除包括发光层外，还包括电子传输层(英文：Election Transporting Layer，简称：ETL)、电子注入层(英文：Election Injection Layer，简称：EIL)、空穴传输层(英文：Hole Transporting Layer，简称：HTL)和空穴注入层(英文：Hole Injection Layer，简称：HIL)中的至少一个。
在一些实施例中，如图5所示，显示面板100还包括封装层30。封装层30设置于多个子像素20远离参考面的一侧，封装层30用于封装发光器件22，提高发光器件22的使 用寿命。其中，封装层30可以为封装薄膜，也可以为封装基板，本公开实施例在此不做具体限定。
示例性地，封装层30可以包括一层封装薄膜，也可以包括叠加设置的两层或两层以上封装薄膜。比如，如图5所示，封装层30包括沿垂直于参考面且远离参考面的方向叠加设置的第一无机封装层31、第一有机封装层32和第二无机封装层33。其中，第一无机封装层31和第二无机封装层33的材料包括氮化硅、氮氧化硅或氧化硅中的任意一种或多种。第一有机封装层32的材料包括聚合物树脂，例如聚酰亚胺。
在一些实施例中，如图6所示，显示面板100还包括至少一层半导体层40，至少一层半导体层40包括第一沟道部41和第一导电部42。其中，第一导电部42可以为上述源极部，也可以为上述漏极部。
在一些示例中，显示面板100仅包括一层半导体层40，即显示面板100包括第一半导体层，第一半导体层包括第一沟道部41和第一导电部42。
在另一些示例中，如图6所示，显示面板包括两层半导体层40，即显示面板100包括第一半导体层和第二半导体层。其中，第一沟道部41设置于第一半导体层，第一导电部42设置于第二半导体层；或者，第一沟道部41设置于第二半导体层，第一导电部42设置于第一半导体层。
示例性地，第一半导体层为低温多晶硅半导体层，第二半导体层为氧化物半导体层。这样的话，可以将低温多晶硅晶体管和氧化物晶体管集成在一个显示面板100上，利用两者的优势(低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点)，可以降低显示面板100的功耗，提高显示面板100的显示品质。
如图6所示，显示面板100还包括第一扫描信号线60。第一扫描信号线60与像素电路21连接。第一扫描信号线60与第一导电部42交叠形成第一电容器1，且与第一沟道部41交叠形成第一晶体管2，第一扫描信号线60用于控制包括第一晶体管2的导通与截止。
如图6所示，显示面板100还包括第二电容器50(例如，像素电路21中的存储电容器212)。第二电容器50包括第一导电块51和第二导电块52，第二导电块52设置于第一导电块51和包括第一沟道部41的半导体层40之间，且第二导电块52与第一导电部42连接。即第一电容器1和第二电容器50并联。
相关技术中，显示面板的横向串扰较为严重和亮度均一性较差，导致显示面板的显示效果较差。经研究，发明人发现，第一导电块设置有通孔，显示面板还包括连接线，连接线的一端与第一沟道部连接，另一端穿过通孔与第二导电块连接。第一导电块设置有通孔导致第一导电块和第二导电块的交叠面积小，导致第二电容器的的电容较小，在第一电容器和第二电容器的总电容不变的情况下，第二电容器的电容较小导致第一电容器的电容较大，从而导致第一扫描信号上的压降较大，导致显示面板的横向串扰较为严重和亮度均一 性较差。
为了解决上述技术问题，如图6所示，本公开的一些实施例提供一种显示面板100，在向参考面的正投影中，第一导电块51覆盖，第二导电块52中设置于第一导电块51的外侧边界内的部分。
也就是说，相较于相关技术中的第一导电块，本公开的一些实施例提供的第一导电块51中形成第二电容器50的部分未设置通孔。这样的话，可以增加第二电容器50的两个极板的相对面积，增大第二电容器50的电容。此时，在第一电容器1和第二电容器50的总电容不变的情况下，可以减小第一电容器1的电容，从而减小第一扫描信号线60的压降，减小显示面板100的横向串扰和提高显示面板100的亮度均一性，有利于提高显示面板100的显示效果。
可以理解的是，需要说明的是，参考面为显示面板100的显示面所在的平面。
在另一些实施例中，如图7所示，第二电容器50还包括第三导电块53。第三导电块53设置于第一导电块51远离第二导电块52的一侧；第三导电块53与第一导电块51至少部分交叠，且第三导电块53与第一导电部42连接。
以这种方式设置，第三导电块53和第二导电块52连接，第三导电块53和第二导电块52一起形成第二电容器50的一个极板，从而可以增加第二电容器50的两个极板的相对面积。此时，在第一电容器1和第二电容器50的总电容不变的情况下，可以减小第一电容器1的电容，从而减小第一扫描信号线60的压降，减小显示面板100的横向串扰和提高显示面板100的亮度均一性，有利于提高显示面板100的显示效果。
在一些实施例中，如图8所示，第二导电块52包括第一主体部521和第一连接部522。第一主体部521在参考面上的正投影设置于第二导电块52在参考面上的正投影的外侧边界内。第一连接部522与第一主体部521连接，第一连接部522的至少部分在参考面上的正投影，设置于第二导电块52在参考面上的正投影的外侧边界外，且与第一导电部42连接。
在一些实施中，如图7所示，第三导电块53在参考面上的正投影，设置于第一导电块51在参考面上的正投影的范围内。
在此基础上，显示面板100还包括第一连接线70，第一连接线70的一端与第一导电部42连接，另一端与第三导电块53连接。以使第三导电块53和第一导电部42连接。
在另一些实施例中，如图9所示，第三导电块53包括第二主体部531和第二连接部532。第二主体部531在参考面上的正投影，设置于第二导电块52在参考面上的正投影的外侧边界内。第二连接部532与第二主体部531连接，第二连接部532设置于第二主体部531的周侧。
在此基础上，显示面板100还包括第一连接线70，第一连接线70的一端与第一导电 部42连接，另一端与第二连接部532连接。以使第三导电块53和第一导电部42连接。
在一些实施例中，如图9所示，至少部分第二连接部532在参考面上的正投影，设置于第一导电块51在参考面上的正投影的外侧边界外，第二连接部532中设置于第一导电块51外侧边界外的部分与第一导电部42连接。
以这种方式设置，可以增大第三导电块53和第二导电块52的相对面积，进一步增加第二电容器50的两个极板的相对面积，增大第二电容器50的电容。此时，在第一电容器1和第二电容器50的总电容不变的情况下，可以减小第一电容器1的电容，进而减小第一扫描信号线60的压降，减小显示面板100的横向串扰和提高显示面板100的亮度均一性，有利于提高显示面板100的显示效果。
在一些实施例中，如图9所示，第一连接部522在参考面上的正投影，与第二连接部532在参考面上的正投影错开设置。第一连接线70还与第一连接部522连接。
以这种方式，第二导电块52和/或第三导电块53，与第一导电块51之间的膜层较少，可以减小第二导电块52和/或第三导电块53，与第一导电块51之间的距离，减小第二电容器50的两个极板之间的距离，进一步增大第二电容器50的电容。此时，在第一电容器1和第二电容器50的总电容不变的情况下，可以减小第一电容器1的电容，进而减小第一扫描信号线60的压降，减小显示面板100的横向串扰和提高显示面板100的亮度均一性，有利于提高显示面板100的显示效果。
在一些实施例中，如图10所示，第一导电块51设有贯穿第一导电块51的第一通孔511，如图11所示，第三导电块53伸入第一通孔511与第二导电块52连接。这样的话，可以使第二导电块52和第三导电块53连接。
在一些实施例中，如图11所示，第三导电块53包括第二主体部531和第二连接部532。第二主体部531在参考面上的正投影，设置于第二导电块52在参考面上的正投影的外侧边界内。第二主体部531伸入第一通孔511与第二导电块52连接。第二连接部532与第二主体部531连接，至少部分第二连接部532在参考面上的正投影，设置于第二导电块52在参考面上的正投影的外侧边界外。
在此基础上，显示面板100还包括第一连接线70，第一连接线70的一端与第一导电部42连接，另一端与第二连接部532连接。这样的话，可以使第一导电部42和第二导电块52和第三导电块53连接。
在另一些实施例中，如图12所示，第二导电块52包括第一主体部521和第一连接部522。第一主体部521在参考面上的正投影，设置于第二导电块52在参考面上的正投影的外侧边界内。至少部分第一连接部522在参考面上的正投影，设置于第二导电块52在参考面上的正投影的外侧边界外。第三导电块53伸入第一通孔511与第一主体部521连接。
在此基础上，显示面板100还包括第一连接线70，第一连接线70的一端与第一导电 部42连接，另一端与第一连接部522连接。这样的话，可以使第一导电部42和第二导电块52和第三导电块53连接。
在一些实施例中，如图6所示，至少一层半导体层40还包括第二沟道部43。显示面板板还包括第二扫描信号线80，第二扫描信号线80与像素电路21连接，第二扫描信号线80与第二沟道部43交叠形成第二晶体管3。第二扫描信号线80用于控制第二晶体管3的导通或者截止。
示例性地，第二沟道部43可以与第一沟道部41同层设置，或者第二沟道部43也可以与第一导电部42同层设置。例如，如图6所示，第二沟道部43与第一导电部42同层设置。
如图13和图14所示，第二扫描信号线80包括第一直线段81和第一弯折段82。第一直线段81沿第一方向X延伸。在向参考面的正投影中，沿第一方向X，第一直线段81设置于连接部(第一连接部522或者第二连接部532)的一侧，沿第二方向Y，第一直线段81设置于主体部(第一主体部521或者第二主体部531)和第一扫描信号线60之间，第一弯折段82朝向第一直线段81远离主体部的一侧弯曲，以避让连接部。这样的话，可以减小像素电路21沿第二方向Y的尺寸，从而增大像素电路21的数量，有利于提高显示面板100的分辨率。
在一些实施例中，如图13和图14所示，第一扫描信号线60包括第一走线段61，第一走线段61在参考面上的正投影，与第一导电部42在参考面上的正投影重合，第一走线段61的线宽小于或者等于2.5μm。
以这种方式设置，可以减小第一扫描信号线60和第一导电部42的相对面积，减小第一电容器1的电容，从而减小第一扫描信号线60的压降，减小显示面板100的横向串扰和提高显示面板100的亮度均一性，有利于提高显示面板100的显示效果。
例如，第三走线段的线宽为2.5μm、2μm、1.4μm或者0.9μm。
在一些实施中，以像素电路21为7T1C结构为例，对本公开的一些实施例进行示例性说明，如图15所示，像素电路21包括驱动晶体管T1、补偿晶体管T2、数据写入晶体管T3、第一复位晶体管T4、第二复位晶体管T5、第一发光晶体管T6、第二发光晶体管T7和第一存储电容器C1。
其中，驱动晶体T1的控制极(栅极)和第一节点N1连接，第一极和第二节点N2连接，第二极和第三节点N3连接。补偿晶体管T2的第一极与第三节点N3连接，第二极与第一节点N1连接，控制极与第一扫描信号端GATE1连接。数据写入晶体管T3的第一极与数据信号端DATA连接、第二极与第二节点N2连接，控制极与第二扫描信号端GATE2连接。第一复位晶体管T4的第一极与第一初始化信号端VINIT1连接、第二极与发光器件22的阳极连接，控制极与第一复位信号端RESET1连接。第二复位晶体管T5T4的第一极 与第二初始化信号端VINIT2连接，第二极与第一节点N1连接，控制极与第二复位信号端RESET2连接。第一发光晶体管T6的第一极和第一电压信号端VDD连接，第二极和第二节点N2连接，控制极和发光信号端EM连接。第二发光晶体管T7的第一极和第三节点N3连接，第二极和发光器件22的阳极连接，控制极和发光信号端EM连接。
此外，如图15所示，发光器件22的阴极和第二电压信号端VSS连接。其中，第二电压信号端VSS输出的电平低于第一电压信号端VDD输出的电平。
在一些实施例中。如图16所示，驱动晶体管T1包括第四沟道部T13，第四沟道部T13在参考面上的正投影，与第二导电块52在参考面上的正投影部分重合，第二导电块52中与第四沟道部T13中重合的部分形成驱动晶体管T1的栅极。其中，第四沟道部T13设置于第一半导体层101。
在此基础上，如图16所示，上述第一导电部42形成补偿晶体管T2的第二极。
在一些实施例中，上述第一晶体管2为数据写入晶体管T3，第一扫描信号线60中与第一沟道部41重合的部分形成数据写入晶体管T3的栅极。
以这种方式设置，在所有的子像素灰阶相同的情况下，可以减小多个像素电路21的驱动晶体管T1写入的数据信号之间的差异，提高显示面板100的亮度均一性。
在一些实施例中，如图16所示，第一复位晶体管T4包括第三沟道部T43，第三沟道部T43在参考面上的正投影，与第一扫描信号线60在参考面上的正投影部分重合，第一扫描信号线60中与第三沟道部T43重合的部分形成第一复位晶体管T4的栅极。
以这种方式设置，可以减小多个子像素20的发光器件22的阳极的电势之间的差异，提高显示面板100的亮度均一性。
在一些示例中，一个像素电路21中的第一复位信号端RESET1和第一扫描信号端GATE1与同一条第一扫描信号线60连接。在另一些示例中，如图16所示，子像素20以多行多列进行阵列式排列，一个像素电路21中的第一扫描信号端GATE1和上一行像素电路21中一个像素电路21第一复位信号端RESET1，与同一条第一扫描信号线60连接。
以下结合显示面板100包括的膜层对第一导电层103、第二导电层104、第三导电层105、第四导电层106和第五导电层107进行举例说明。
在一些实施例中，如图5所示，像素电路21包括低温多晶硅薄膜晶体管和氧化物薄膜晶体管。此时，沿垂直于参考面且远离参考面的方向，显示面板100还包括包括依次设置的低温多晶硅半导体层ACT1、第一栅绝缘层GI1、第一栅导电层GT1、第二栅绝缘层GI2、第二栅导电层GT2、第一层间绝缘层ILD1、氧化物半导体层ACT2、第三栅绝缘层GI3、第三栅导电层GT3、第二层间绝缘层ILD2、第一源漏导电层SD1、第一平坦层PLN1、第二源漏导电层SD2和第二平坦层PLN2。
在这种情况下，第一沟道部41设置于低温多晶硅半导体层ACT1，第二导电块52和 第一扫描信号线60设置于第一栅导电层GT1，第一导电块51设置于第二栅导电层GT2，第一导电部42和第二沟道部43设置于氧化物半导体层ACT2，第三导电块53和第二扫描信号线80设置于第三栅导电层GT3，第一连接线70设置于第一源漏导电层SD1。
在另一些实施例中，如图17所示，像素电路21仅包括低温多晶硅薄膜晶体管。此时，沿垂直于参考面且远离参考面的方向，显示面板100还包括包括依次设置的低温多晶硅半导体层ACT1、第一栅绝缘层GI1、第一栅导电层GT1、第二栅绝缘层GI2、第二栅导电层GT2、第三栅绝缘层GI3、第三栅导电层GT3、第一层间绝缘层ILD1、第一源漏导电层SD1、第一平坦层PLN1、第二源漏导电层SD2和第二平坦层PLN2。
在这种情况下，第一沟道部41、第二沟道部43和第一导电部42和设置于低温多晶硅半导体层ACT1，第二导电块52和第一扫描信号线60设置于第一栅导电层GT1，第一导电块51设置于第二栅导电层GT2，第三导电块53和第二扫描信号线80设置于第三栅导电层GT3，第一连接线70设置于第一源漏导电层SD1。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种显示面板，包括：
    至少一层半导体层，包括第一沟道部和第一导电部；
    第一扫描信号线，与所述第一导电部交叠形成第一电容器，且与所述第一沟道部交叠形成第一晶体管；
    第二电容器，包括第一导电块和第二导电块，所述第二导电块设置于所述第一导电块和包括所述第一沟道部的半导体层之间，且所述第二导电块与所述第一导电部连接；
    其中，在向参考面上的正投影中，所述第一导电块覆盖，所述第二导电块中设置于所述第一导电块的外侧边界内的部分；和/或，所述第二电容器还包括第三导电块，所述第三导电块设置于所述第一导电块远离所述第二导电块的一侧，且所述第三导电块与所述第一导电块至少部分交叠；所述第三导电块和所述第一导电部连接。
  2. 根据权利要求1所述的显示面板，其中，所述，所述第二导电块包括：
    第一主体部，在所述参考面上的正投影设置于所述第二导电块在所述参考面上的正投影的外侧边界内；
    第一连接部，与所述第一主体部连接；所述第一连接部的至少部分在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界外，且与所述第一导电部连接。
  3. 根据权利要求2所述的显示面板，其中，所述第三导电块在所述参考面上的正投影，设置于所述第一导电块在所述参考面上的正投影的范围内；
    所述显示面板还包括：
    第一连接线；所述第一连接线的一端与所述第一导电部连接，另一端与所述第三导电块连接。
  4. 根据权利要求2所述的显示面板，其中，所述第三导电块包括：
    第二主体部，在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界内；
    第二连接部，与所述第二主体部连接；所述第二连接部设置于所述第二主体部的周侧；
    所述显示面板还包括：
    第一连接线；所述第一连接线的一端与所述第一导电部连接，另一端与所述第二连接部连接。
  5. 根据权利要求4所述的显示面板，其中，至少部分所述第二连接部在所述参考面上的正投影，设置于所述第一导电块在所述参考面上的正投影的外侧边界外，所述第二连接部中设置于所述第一导电块外侧边界外的部分与所述第一导电部连接。
  6. 根据权利要求5所述的显示面板，其中，所述第一连接部在所述参考面上的正投影，与所述第二连接部在所述参考面上的正投影错开设置；
    所述第一连接线设置于所述第三导电块远离所述第二导电块的一侧，所述第一连接线还与所述第一连接部连接。
  7. 根据权利要求1所述的显示面板，其中，所述第一导电块设有贯穿所述第一导电块的第一通孔，所述第三导电块伸入所述第一通孔与所述第二导电块连接。
  8. 根据权利要求7所述的显示面板，其中，所述第三导电块包括：
    第二主体部，在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界内；所述第二主体部伸入所述第一通孔与所述第二导电块连接；
    第二连接部，与所述第二主体部连接，至少部分所述第二连接部在所述参考面上的正投影，设置于所述第二导电块在所述参考面上的正投影的外侧边界外；
    所述显示面板还包括：
    第一连接线，所述第一连接线的一端与所述第一导电部连接，另一端与所述第二连接部连接。
  9. 根据权利要求2～8中任一项所述的显示面板，其中，所述至少一层半导体层还包括第二沟道部；
    所述显示面板还包括:
    第二扫描信号线，与所述第二沟道部交叠形成第二晶体管；所述第二扫描信号线包括：
    第一直线段，沿第一方向延伸；在向所述参考面的正投影中，沿所述第一方向，所述第一直线段设置于连接部的一侧；沿第二方向，所述第一直线段设置于主体部和所述第一扫描信号线之间；所述第一方向与所述第二方向交叉；
    第一弯折段；在向所述参考面的正投影中，所述第一弯折段朝向所述第一直线段远离所述主体部的一侧弯曲。
  10. 根据权利要求1～9中任一项所述的显示面板，其中，所述第一扫描信号线包括：
    第一走线段，在所述参考面上的正投影，与所述第一导电部在所述参考面上的正投影重合，所述第一走线段的线宽小于或者等于2.5μm。
  11. 根据权利要求1～10中任一项所述的显示面板，包括：
    像素电路，包括驱动晶体管；所述驱动晶体管包括第四沟道部；所述第四沟道部在所述参考面上的正投影，与所述第二导电块在所述参考面上的正投影部分重合，所述第二导电块中与所述第四沟道部中重合的部分形成所述驱动晶体管的栅极。
  12. 根据权利要求11所述的显示面板，其中，所述像素电路还包括：
    补偿晶体管；所述补偿晶体管的第一极与所述驱动晶体管的第二极连接，第二极与所述驱动晶体管的栅极连接；其中，所述第一导电部形成所述补偿晶体管的第二极。
  13. 根据权利要求1～12中任一项所述的显示面板，还包括：
    像素电路，包括数据写入晶体管；所述数据写入晶体管与数据信号端连接；其中，所 述第一晶体管为所述数据写入晶体管，所述第一扫描信号线中与所述第一沟道部交叠的部分形成所述数据写入晶体管的栅极。
  14. 根据权利要求1～13中任一项所述的显示面板，还包括：
    像素电路，还包括第一复位晶体管，所述第一复位晶体管的第一极与第一初始化信号端连接；所述第一复位晶体管包括第三沟道部，所述第三沟道部在所述参考面上的正投影，与所述第一扫描信号线在所述参考面上的正投影部分重合，所述第一扫描信号线中与所述第三沟道部重合的部分形成所述第一复位晶体管的栅极。
  15. 一种显示装置，包括如权利要求1～14中任一项所述的显示面板。
PCT/CN2024/090673 2024-04-29 2024-04-29 显示面板及显示装置 Pending WO2025227331A1 (zh)

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WO2022232987A1 (zh) * 2021-05-06 2022-11-10 京东方科技集团股份有限公司 显示基板及显示装置
WO2023168670A1 (zh) * 2022-03-10 2023-09-14 京东方科技集团股份有限公司 显示面板及显示装置
CN117082928A (zh) * 2023-09-25 2023-11-17 京东方科技集团股份有限公司 阵列基板和显示面板

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WO2022232987A1 (zh) * 2021-05-06 2022-11-10 京东方科技集团股份有限公司 显示基板及显示装置
WO2023168670A1 (zh) * 2022-03-10 2023-09-14 京东方科技集团股份有限公司 显示面板及显示装置
CN117082928A (zh) * 2023-09-25 2023-11-17 京东方科技集团股份有限公司 阵列基板和显示面板

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