WO2025213701A1 - 光模块 - Google Patents

光模块

Info

Publication number
WO2025213701A1
WO2025213701A1 PCT/CN2024/117452 CN2024117452W WO2025213701A1 WO 2025213701 A1 WO2025213701 A1 WO 2025213701A1 CN 2024117452 W CN2024117452 W CN 2024117452W WO 2025213701 A1 WO2025213701 A1 WO 2025213701A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal line
light emitting
light
emitting chip
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/117452
Other languages
English (en)
French (fr)
Inventor
王欣南
张加傲
慕建伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hisense Broadband Multimedia Technology Co Ltd
Original Assignee
Hisense Broadband Multimedia Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202420762007.6U external-priority patent/CN221946225U/zh
Priority claimed from CN202410444771.3A external-priority patent/CN120630400A/zh
Application filed by Hisense Broadband Multimedia Technology Co Ltd filed Critical Hisense Broadband Multimedia Technology Co Ltd
Publication of WO2025213701A1 publication Critical patent/WO2025213701A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters

Definitions

  • the present disclosure relates to the field of optical fiber communication technology, and in particular to an optical module.
  • optical communication technology optical modules are tools for converting optical and electrical signals, and are key components in optical communication equipment. Furthermore, the transmission distance of optical modules continues to increase as optical communication technology evolves.
  • An embodiment of the present disclosure provides an optical module, including:
  • the first optical transmission assembly comprises:
  • Substrate including:
  • a first platform, a grounding conductive area and a first resistance conductive area are provided on its surface;
  • a second matching resistor located between the ground conductive area and the first resistive conductive area
  • a second platform located above the first platform; an upper surface of the second platform is higher than an upper surface of the first platform;
  • An EA signal line is provided on the surface of the second platform, and one end of the EA signal line is electrically connected to the circuit board;
  • a first matching resistor is connected in series with the EA signal line
  • a first light emitting chip is located on the first platform, wherein the cathode of the first light emitting chip is electrically connected to the ground conductive area; and an EA pad of the first light emitting chip is electrically connected to the other end of the EA signal line;
  • a driver chip is located on the circuit board
  • the first light emitting chip is electrically connected to the driving chip, and the first light emitting chip is configured to emit a first signal light;
  • the second light emitting assembly comprises: a second light emitting chip, the second light emitting chip being electrically connected to the driving chip, and the second light emitting chip being configured to emit a second signal light;
  • the wavelength of the first signal light is the same as the wavelength of the second signal light; the polarization direction of the first signal light is perpendicular to the polarization direction of the second signal light;
  • the polarization beam combiner is located on the light output path of the first light emitting chip and the second light emitting chip, and is configured to combine the first signal light and the second signal light into a first integrated signal light.
  • FIG1 is a partial architecture diagram of an optical communication system according to some embodiments.
  • FIG2 is a partial structural diagram of a host computer according to some embodiments.
  • FIG3 is a structural diagram of an optical module according to some embodiments.
  • FIG4 is an exploded view of an optical module according to some embodiments.
  • FIG5 is a schematic diagram of the exploded structure of a light emitting component provided by an embodiment of the present disclosure.
  • FIG6 is another exploded structural diagram of a light emitting component provided by an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a partial structure of a light emitting component provided in an embodiment of the present disclosure.
  • FIG8 is a second schematic diagram of a partial structure of a light emitting component provided in an embodiment of the present disclosure.
  • FIG9 is a schematic structural diagram of a polarization beam combiner of a light emitting component provided by an embodiment of the present disclosure.
  • FIG10 is a schematic diagram of a circuit structure of a light emitting component provided in an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of an equivalent circuit of a light emitting component provided in an embodiment of the present disclosure.
  • FIG12 is a first schematic diagram of a light emitting chip and substrate structure according to some embodiments.
  • FIG13 is a partial cross-sectional diagram of a substrate and a circuit board according to some embodiments.
  • FIG14 is an exploded schematic diagram of a light emitting chip and a substrate according to some embodiments.
  • FIG15 is a second structural diagram of a light emitting chip and a substrate according to some embodiments.
  • FIG16 is a fourth structural diagram of a light emitting chip and a substrate according to some embodiments.
  • FIG17 is a second exploded diagram of a light emitting chip and a substrate according to some embodiments.
  • FIG18 is a fifth structural diagram of a light emitting chip and a substrate according to some embodiments.
  • FIG19 is a schematic diagram of FIG18 from another angle
  • FIG20 is a sixth schematic diagram of a light emitting chip and substrate structure provided according to some embodiments.
  • Optical communication technology enables information transmission between information processing devices. It loads information onto light and uses the propagation of light to achieve this transmission. Light loaded with information is an optical signal. The propagation of optical signals within information transmission equipment reduces optical power loss, enabling high-speed, long-distance, and low-cost information transmission.
  • the information processed by information processing equipment exists in the form of electrical signals.
  • Optical network terminals/gateways, routers, switches, mobile phones, computers, servers, tablets, and televisions are common information processing devices, and optical fibers and optical waveguides are common information transmission devices.
  • optical modules The conversion of optical signals and electrical signals between information processing equipment and information transmission equipment is achieved through optical modules.
  • an optical fiber is connected to the optical signal input end and/or optical signal output end of the optical module, and an optical network terminal is connected to the electrical signal input end and/or electrical signal output end of the optical module.
  • a first optical signal from the optical fiber is transmitted into the optical module, and the optical module converts the first optical signal into a first electrical signal, which is then transmitted into the optical network terminal.
  • a second electrical signal from the optical network terminal is transmitted into the optical module, and the optical module converts the second electrical signal into a second optical signal, which is then transmitted into the optical fiber.
  • information processing devices can be connected to each other through an electrical signal network, at least one type of information processing device needs to be directly connected to the optical module, and not all types of information processing devices need to be directly connected to the optical module.
  • the information processing device directly connected to the optical module is called the host computer of the optical module.
  • Figure 1 is a partial architecture diagram of an optical communication system according to some embodiments. As shown in Figure 1 , the optical communication system partially comprises a remote information processing device 1000 , a local information processing device 2000 , a host computer 100 , an optical module 200 , an optical fiber 101 , and a network cable 103 .
  • optical fiber 101 extends toward remote information processing device 1000, and the other end connects to the optical interface of optical module 200.
  • Optical signals can undergo total internal reflection within optical fiber 101, maintaining nearly their original optical power as they propagate in the direction of total internal reflection.
  • Multiple total internal reflections within optical fiber 101 transmit optical signals from the direction of remote information processing device 1000 into optical module 200, or transmit light from optical module 200 toward remote information processing device 1000, enabling long-distance, low-power information transmission.
  • the number of optical fibers 101 may be one or more (two or more); the optical fiber 101 and the optical module 200 may be connected in a pluggable movable manner or in a fixed manner.
  • the host computer 100 has an optical module interface 102, which is configured to connect to the optical module 200, so that the host computer 100 establishes a unidirectional/bidirectional electrical signal connection with the optical module 200; the host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor and control the working status of the optical module 200.
  • Host computer 100 has an external electrical interface, such as a Universal Serial Bus (USB) interface and a network interface 104, which can be connected to an electrical signal network.
  • network interface 104 is configured to connect to a network cable 103, thereby establishing a unidirectional/bidirectional electrical signal connection between host computer 100 and network cable 103.
  • Optical network unit (ONU), optical line terminal (OLT), optical network equipment (ONT) and data center server are common host computers.
  • the network cable 103 establishes an electrical signal connection between the local information processing device 2000 and the host computer 100 .
  • the third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103.
  • the host computer 100 generates a second electrical signal based on the third electrical signal.
  • the second electrical signal from the host computer 100 is transmitted into the optical module 200.
  • the optical module 200 converts the second electrical signal into a second optical signal.
  • the optical module 200 transmits the second optical signal into the optical fiber 101.
  • the second optical signal is transmitted to the remote information processing device 1000 in the optical fiber 101.
  • a first optical signal from the direction of the remote information processing device 1000 propagates through the optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted into the optical module 200.
  • the optical module 200 converts the first optical signal into a first electrical signal.
  • the optical module 200 transmits the first electrical signal into the host computer 100.
  • the host computer 100 generates a fourth electrical signal based on the first electrical signal, and the host computer 100 transmits the fourth electrical signal to the local information processing device 2000.
  • Optical modules are tools for converting optical signals into electrical signals. During this conversion process, the information remains unchanged, but the encoding and decoding methods of the information can change.
  • FIG 2 is a partial structural diagram of a host computer according to some embodiments. To clearly illustrate the connection between the optical module 200 and the host computer 100, Figure 2 only shows the structure of the host computer 100 related to the optical module 200. As shown in Figure 2, the host computer 100 also includes a PCB circuit board 105 disposed within the housing, a cage 106 disposed on the surface of the PCB circuit board 105, a heat sink 107 disposed on the cage 106, and an electrical connector (not shown) disposed within the cage 106.
  • the heat sink 107 has a protruding structure that increases the heat dissipation area.
  • a fin-like structure is a common protruding structure.
  • Optical module 200 is inserted into cage 106 of host computer 100.
  • Cage 106 secures optical module 200, and heat generated by optical module 200 is transferred to cage 106 and then dissipated through heat sink 107.
  • the electrical interface of optical module 200 connects to the electrical connector inside cage 106.
  • Figure 3 is a structural diagram of an optical module according to some embodiments
  • Figure 4 is an exploded view of an optical module according to some embodiments.
  • the optical module 200 includes a housing, a circuit board 300 disposed within the housing, a light emitting component 400, and a light receiving component.
  • the present disclosure is not limited thereto.
  • the optical module 200 includes either the light emitting component 400 or the light receiving component.
  • the housing includes an upper housing 201 and a lower housing 202 .
  • the upper housing 201 covers the lower housing 202 to form the housing having two openings 204 and 205 .
  • the outer contour of the housing is generally a square.
  • the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicular to the base plate 2021; the upper shell 201 includes a cover plate 2011, and the cover plate 2011 covers the two lower side plates 2022 of the lower shell 202 to form the above-mentioned shell.
  • the lower shell 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and arranged perpendicularly to the base plate 2021;
  • the upper shell 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and arranged perpendicularly to the cover plate 2011. The two upper side plates are combined with the two lower side plates 2022 to achieve the upper shell 201 covering the lower shell 202.
  • the direction of the line connecting the two openings 204 and 205 can be consistent with the length direction of the optical module 200, or it can be inconsistent with the length direction of the optical module 200.
  • the opening 204 is located at the end of the optical module 200 (the right end in FIG3 ), and the opening 205 is also located at the end of the optical module 200 (the left end in FIG3 ).
  • the openings 204 and 205 can be arranged in a direction that is consistent with the length direction of the optical module 200.
  • Port 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200.
  • Opening 204 is an electrical interface, from which the gold fingers of circuit board 300 extend and plug into the electrical connector of the host computer.
  • Opening 205 is an optical port, configured to receive optical fiber 101, thereby connecting optical fiber 101 to the optical emitting component 400 and/or the optical receiving component in optical module 200.
  • the combined assembly of the upper and lower housings 201 and 202 facilitates the installation of components such as the circuit board 300, the light emitting component 400, and the light receiving component within the housing. These components are encapsulated and protected by the upper and lower housings 201 and 202. Furthermore, during assembly of the circuit board 300, the light emitting component 400, and the light receiving component, positioning components, heat dissipation components, and electromagnetic shielding components are easily positioned, facilitating automated production.
  • the upper shell 201 and the lower shell 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.
  • the optical module 200 further includes an unlocking component 600 located outside its housing.
  • the unlocking component 600 is configured to achieve a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.
  • the unlocking member 600 is located on the outside of the two lower side panels 2022 of the lower housing 202 and includes engaging components that mate with the cage 106 of the host computer.
  • the engaging components of the unlocking member 600 secure the optical module 200 within the cage 106.
  • the engaging components of the unlocking member 600 move accordingly, thereby changing the connection between the engaging components and the host computer, thereby releasing the fixed engagement between the optical module 200 and the host computer, allowing the optical module 200 to be removed from the cage 106.
  • the circuit board 300 includes circuit traces, electronic components, and chips.
  • the circuit traces connect the electronic components and chips according to the circuit design to achieve functions such as power supply, electrical signal transmission, and grounding.
  • Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs).
  • Chips may include, for example, microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers, clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.
  • MCUs microcontroller units
  • TIAs transimpedance amplifiers
  • CDRs clock and data recovery chips
  • DSP digital signal processing
  • the circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also realize the load-bearing function. For example, the rigid circuit board can stably carry the above-mentioned electronic components and chips; the rigid circuit board is also easy to insert into the electrical connector in the upper computer cage.
  • the circuit board 300 also includes gold fingers formed on its end surfaces.
  • the gold fingers are composed of multiple independent pins.
  • the circuit board 300 is inserted into the cage 106, and the gold fingers are electrically connected to the electrical connector inside the cage 106.
  • the gold fingers can be provided only on one side of the circuit board 300 (such as the top surface shown in FIG4 ), or they can be provided on both the top and bottom surfaces of the circuit board 300 to provide more pins.
  • the gold fingers are configured to establish an electrical connection with the host computer to achieve power supply, grounding, I2C signal transmission, data signal transmission, etc.
  • flexible circuit boards are also used in some optical modules.
  • Flexible circuit boards are generally used in conjunction with rigid circuit boards to supplement rigid circuit boards.
  • the light emitting component 400 and/or the light receiving component are located on the side of the circuit board 300 away from the gold finger; in some embodiments, the light emitting component 400 and the light receiving component are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors; in some embodiments, the light emitting component and/or the light receiving component can be directly set on the circuit board 300, can be set on the surface of the circuit board, and can also be set on the side of the circuit board.
  • FIG5 is a schematic diagram of the exploded structure of an optical emitting component provided in an embodiment of the present disclosure
  • FIG6 is another schematic diagram of the exploded structure of the optical emitting component provided in an embodiment of the present disclosure
  • the optical emitting component may include a cover plate 401 and a housing 402, and the cover plate 401 and the housing 402 are connected to each other.
  • the cover plate 401 covers the housing 402 from above, and one side wall of the housing 402 has an opening for inserting the circuit board 300, and the other side wall of the housing 402 has a through hole for inserting the optical fiber adapter 403.
  • the circuit board 300 extends into the housing 402 through the opening, and the circuit board 300 is fixed to the lower shell 202; the circuit board 300 is plated with metal traces, and the optical device can be electrically connected to the corresponding metal traces by bonding to achieve electrical connection between the optical device in the housing 402 and the circuit board 300.
  • the signal light emitted by the optical emitting component is injected into the through hole, and the optical fiber adapter 403 is inserted into the through hole to couple the received signal light.
  • This assembly structure design allows the optical fiber adapter 403 to move back and forth in the through hole, and the required size of the optical fiber between the optical emitting component and the optical fiber plug can be adjusted.
  • the optical fiber adapter can be moved backward (toward the outside of the cavity) in the through hole to meet the connection size requirements; when the optical fiber is long, the optical fiber adapter can be moved forward (toward the inside of the cavity) in the through hole to straighten the optical fiber and prevent it from bending.
  • the optical fiber adapter 403 is inserted into the through hole to achieve fixation with the optical emitting component; during the assembly process, the optical fiber adapter 403 can be moved in the through hole to select a fixed position.
  • one side wall of the housing 402 has an opening for inserting the circuit board 300
  • the other side wall of the housing 402 has a through hole for inserting the fiber optic adapter 403 .
  • the optical device in the housing 402 can optionally be connected to the circuit board 300 through pins, wherein the pins are designed to be compatible with the lower housing, one end of the pins is inserted into the interior of the lower housing, and a metal trace is plated on the end.
  • the optical device can be electrically connected to the corresponding metal trace by bonding.
  • the pins are placed at one end of the housing 402 and are provided with a plurality of pins electrically connected to the metal traces.
  • the pins are inserted into the circuit board 300 and welded together to achieve electrical connection between the optical device in the housing 402 and the circuit board 300.
  • the pins on the pins can also be directly welded to the circuit board 300 to achieve electrical connection between the optical device in the housing 402 and the circuit board 300.
  • the optical transmission subassembly in the housing 402 converts the electrical signal transmitted from the circuit board 300 into an optical signal after receiving the electrical signal.
  • the optical signal then enters the optical fiber adapter 403 and is transmitted to the outside of the optical module.
  • the optical emitting component includes a packaging structure to encapsulate the laser chip and other components.
  • Existing packaging structures include coaxial TO-CAN (coaxial optical fiber) packaging, silicon photonics packaging, COB-LENS (chip-on-board lens assembly) packaging, and micro-optics XMD (micro-optical micro-optical) packaging. These packaging structures can be either hermetic or non-hermetic. While providing a stable and reliable operating environment for the laser chip, the packaging also enables external electrical connections and optical output.
  • Figure 7 is a schematic diagram of a partial structure of a light emitting component provided in an embodiment of the present disclosure
  • Figure 8 is a schematic diagram of a partial structure of a light emitting component provided in an embodiment of the present disclosure.
  • Figures 8 and 7 show the interior of the housing of the light emitting component from different angles.
  • the light emitting component in the present disclosure may include: a light emitting assembly 410.
  • Light emitting assembly 410 is located inside housing 402 and can convert electrical signals into optical signals.
  • a first driver chip may be provided on the circuit board and may be integrated into the DSP chip.
  • the optical emission component 410 may include: a first optical emission chip 411, which may be connected to a first driver chip.
  • the first driver chip outputs a modulation signal to the first optical emission chip 411 to modulate the light emitted by the first optical emission chip 411 to form a first signal light.
  • the first light emitting chip 411 may be a first EML laser.
  • the first EML laser includes a first light emitter and a first modulator.
  • a first driver chip is connected to the first modulator, which encodes and modulates the light emitted by the first light emitter and outputs it, so that the output optical signal carries information.
  • the optical emission component 410 may include: a second optical emission chip 412, the second optical emission chip 412 can be connected to the first driver chip, the first driver chip outputs a modulation signal to the second optical emission chip 412, modulates the light emitted by the second optical emission chip 412, and forms a second signal light.
  • the second light emitting chip 412 may be a second EML laser.
  • the second EML laser includes a second light emitter and a second modulator.
  • the first driver chip is connected to the second modulator, and the second modulator modulates the light emitted by the second light emitter and then outputs it, so that the output optical signal carries information.
  • the wavelength of the first signal light is the same as the wavelength of the second signal light; the second light emitting chip 412 and the first light emitting chip 411 are connected to the first driving chip at the same time, the modulation signal of the second light emitting chip 412 is the same as that of the first light emitting chip 411, and the signal carried by the first signal light is the same as the signal carried by the second signal light.
  • the polarization direction of the signal light emitted by the first light emitting chip 411 may be consistent with the polarization direction of the signal light emitted by the second light emitting chip.
  • the polarization direction of the signal light emitted by the first light emitting chip 411 is changed, so that the changed signal light has a different polarization direction from the signal light emitted by the second light emitting chip.
  • the polarization direction of the signal light emitted by the first light emitting chip 411 may be consistent with the polarization direction of the signal light emitted by the second light emitting chip.
  • the polarization direction of the signal light emitted by the first light emitting chip 411 is changed so that the changed signal light is perpendicular to the polarization direction of the signal light emitted by the second light emitting chip.
  • the optical emitting assembly 410 may include a first collimating lens 421 located on the light-emitting path of the first optical emitting chip 411 .
  • the first signal light emitted by the first optical emitting chip 411 is divergent light, and the first collimating lens 421 collimates the first signal light.
  • the optical emitting assembly 410 may include a second collimating lens 422 located on the light-emitting path of the second optical emitting chip 412 .
  • the second signal light emitted by the second optical emitting chip 412 is divergent light, and the second collimating lens 422 collimates the second signal light.
  • the first polarization beam combiner 431 is located on the outgoing optical path of the first light emitting chip 411 and the second light emitting chip 412 .
  • the polarization beam combiner 431 can combine the first signal light and the second signal light into a first integrated signal light.
  • Figure 9 is a schematic diagram of the structure of a polarization beam combiner for a light emitting component provided by an embodiment of the present disclosure.
  • the first polarization beam combiner includes a first polarization reflector 4311 located in the light output path of the first light emitting chip.
  • the first polarization reflector 4311 reflects the collimated first signal light.
  • the angle between the normal line of the first polarizing reflector and the light emitting axis of the first light emitting chip is 45°.
  • the first polarization beam combiner may include a second polarization reflector 4312 located on the light output path of the second light emitting chip 412.
  • the second polarization reflector may reflect the collimated first signal light, and the second signal light may transmit through the second polarization reflector, thereby combining the first and second signal lights into a single beam.
  • the distance between the first light emitting chip 411 and the first polarization beam combiner is smaller than the distance between the second light emitting chip 412 and the first polarization beam combiner; this ensures that the optical path lengths of the first signal light and the second signal light at the exit of the first polarization beam combiner are consistent. That is, the optical path length of the first signal light from the exit of the first light emitting chip 411 to the exit of the first polarization beam combiner is equal to the optical path length of the second signal light from the exit of the second light emitting chip 411 to the exit of the first polarization beam combiner.
  • the optical emission component 410 may include: a third optical emission chip 413, the third optical emission chip 413 can be connected to the second driver chip, the second driver chip outputs a modulation signal to the third optical emission chip 413, modulates the light emitted by the third optical emission chip 413, and forms a third signal light.
  • the optical emission component 410 may include: a fourth optical emission chip 414, which may be connected to the second driver chip.
  • the second driver chip outputs a modulation signal to the fourth optical emission chip 414 to modulate the light emitted by the fourth optical emission chip 414 to form a fourth signal light.
  • the wavelength of the third signal light is the same as the wavelength of the fourth signal light; the third light emitting chip 413 and the fourth light emitting chip 414 are connected to the second driver chip at the same time, the modulation signals of the third light emitting chip 413 and the fourth light emitting chip 414 are the same, and the signal carried by the third signal light is the same as the signal carried by the fourth signal light.
  • the polarization direction of the third signal light is different from the polarization direction of the fourth signal light.
  • the polarization direction of the third signal light is perpendicular to the polarization direction of the fourth signal light.
  • the optical emitting assembly 410 may include a third collimating lens 423 located on the light-emitting path of the third optical emitting chip 413 .
  • the third signal light emitted by the third optical emitting chip 413 is divergent light, and the third collimating lens 423 collimates the third signal light.
  • the optical emitting assembly 410 may include: a fourth collimating lens 424 located on the light output path of the fourth optical emitting chip 414 .
  • the fourth signal light emitted by the fourth optical emitting chip 414 is divergent light, and the fourth collimating lens 424 collimates the fourth signal light.
  • the second polarization beam combiner 432 is located on the light output path of the third light emitting chip 413 and the fourth light emitting chip 414.
  • the second polarization beam combiner 432 can combine the third signal light and the fourth signal light into a second integrated signal light.
  • the structure of the second polarization beam combiner 432 can be shown in FIG9 .
  • the optical path of the third signal light from the outlet of the third light emitting chip 413 to the outlet of the second polarization beam combiner is equal to the optical path of the fourth signal light from the outlet of the fourth light emitting chip 414 to the outlet of the second polarization beam combiner.
  • the wavelength of the first integrated signal light is different from the wavelength of the second integrated signal light.
  • the optical transmission assembly 410 may include an optical wavelength division multiplexer 440.
  • the optical wavelength division multiplexer 440 may combine the first integrated signal light and the second integrated signal light into one beam.
  • the optical wavelength division multiplexer 440 can combine multiple integrated signal beams into one beam.
  • a first driver chip is connected to a first light emitting chip and a second light emitting chip.
  • the first driver chip provides a modulation signal to the first and second light emitting chips, so that the signal light emitted by the first and second light emitting chips carries the same signal.
  • the first signal light emitted by the first light emitting chip and the second signal light emitted by the second light emitting chip have the same wavelength but different polarization directions.
  • FIG 10 is a schematic diagram of a circuit structure of a light emitting component provided by an embodiment of the present disclosure.
  • a first drive signal line 461 may be provided on the surface of the circuit board 300, and one end of the first drive signal line 461 is connected to the first driver chip.
  • a second driving signal line 462 may be provided on the surface of the circuit board 300. One end of the second driving signal line 462 is connected to the first driving signal line 461. The other end of the second driving signal line 462 is connected to the first light emitting chip.
  • a third driving signal line 463 may be provided on the surface of the circuit board 300. One end of the third driving signal line 463 is connected to the first driving signal line 461. The other end of the third driving signal line 463 is connected to the first light emitting chip.
  • Figure 11 is a schematic diagram of an equivalent circuit of a light emitting component provided by an embodiment of the present disclosure.
  • the first driver chip 310 is connected to one end of the first drive signal line 461.
  • the other end of the first drive signal line 461 is connected to the second drive signal line 462 and the third drive signal line 463.
  • a first DC blocking capacitor 311 may be provided between the second driving signal line 462 and the first light emitting chip 411.
  • the first DC blocking capacitor 311 may block the direct current between the first driving chip and the first light emitting chip.
  • a second DC blocking capacitor 312 may be provided between the third driving signal line 463 and the second light emitting chip 412.
  • the second DC blocking capacitor 312 may block the direct current between the first driving chip and the second light emitting chip.
  • the first driving signal line 461 may be connected to the first power supply circuit 320 , and the first power supply circuit 320 may provide a power supply voltage for the first driving chip.
  • the first power supply circuit 320 is located between the first DC blocking capacitor 311 and the first driving chip 310.
  • the first DC blocking capacitor 311 can prevent the DC current of the first power supply circuit 320 from entering the first light emitting chip.
  • the second power supply circuit 330 provides power supply voltage to the first light emitting chip 411 and the second light emitting chip 412.
  • the second power supply circuit 330 includes a first branch 331 and a second branch 332.
  • the first branch 331 is connected to the first light emitting chip and provides power supply voltage to the first light emitting chip.
  • the first DC blocking capacitor 311 is located between the first power supply circuit 320 and the first branch 331 to ensure that the voltages of the power supply circuits of the first driver chip and the first light emitting chip do not interfere with each other.
  • the second branch 332 is connected to the second light emitting chip and can provide a power supply voltage for the second light emitting chip.
  • the second DC blocking capacitor 312 is located between the first power supply circuit 320 and the second branch 332, thereby ensuring that the voltages of the power supply circuit of the first driver chip and the power supply circuit of the second light emitting chip do not interfere with each other.
  • the second power supply circuit 330 may include a first inductor 3301 and a first resistor 3302.
  • the first inductor 3301 and the first resistor 3302 are connected in parallel to form a first RL filter.
  • the first RL filter can block AC signals and prevent the AC signals carried in the first drive signal line 461 from affecting the power supply.
  • the second power supply circuit 330 may include a first magnetic bead 3303, which may be connected in series with the power supply.
  • the first magnetic bead 3303 may be located between the first RL filter and the first drive signal line 461.
  • the first magnetic bead 3303 may prevent the high-frequency signal on the first drive signal line 461 from affecting the power supply.
  • the second power supply circuit 330 may include a second magnetic bead 3304, which may be located between the first magnetic bead 3303 and the first drive signal line 461.
  • the first magnetic bead 3303 and the second magnetic bead 3304 have different specifications and may block AC signals of different frequencies.
  • the second power supply circuit 330 may include a third magnetic bead 3305.
  • the second magnetic bead 3304 may be located between the first magnetic bead 3303 and the second drive signal line 462.
  • the first magnetic bead 3303 and the third magnetic bead 3305 have different specifications and can block AC signals of different frequencies.
  • the light emitting chip is located on a substrate, and a conductive region is provided on the substrate surface for connection to an external circuit.
  • the light emitting chip and substrate are hereinafter referred to as a light emitting assembly.
  • Figure 12 is a schematic diagram of a light emitting chip and substrate structure according to some embodiments. As shown in Figure 12, in the light emitting assembly provided in this embodiment, the light emitting chip is mounted on the top surface of a substrate 700, which also has signal traces. The anode of the light emitting chip is located at the top of the light emitting chip and is connected to the substrate 700 via bonding wires, through which high-frequency signals are received.
  • the light emitting chip 740 may be a first light emitting chip or a second light emitting chip.
  • the substrate 700 may be provided with a first platform 710 and a second platform 720 of different heights.
  • the first platform 710 is higher than the second platform.
  • the second platform 720 may be placed above the first platform 710, i.e., the upper surface of the second platform 720 is higher than the upper surface of the first platform.
  • the light emitting chip is located on the first platform.
  • the light emitting chip may be an EML laser, and the upper surface of the light emitting chip 740 may be provided with an EA pad 742 and a light emitting pad 741 ; the lower surface of the light emitting chip may be provided with a cathode pad.
  • the top surface of the light-emitting chip is flush with the top surface of the second platform, and the EA pads are connected to the EA signal lines on the second platform surface via wire bonding. This makes the connection between the EA pads and the EA signal lines on the second platform surface shorter, reducing parasitic resistance.
  • Figure 13 is a schematic partial cross-sectional view of a substrate and circuit board according to some embodiments. As shown in Figure 13 , the upper surface of the second platform is flush with the upper surface of the circuit board. The circuit board is connected to one end of the EA signal line via bonding wires. This flushness of the upper surface of the second platform with the upper surface of the circuit board shortens the bonding distance between the circuit board and the EA signal line, reducing parasitic resistance.
  • Figure 14 is an exploded schematic diagram of a light emitting chip and substrate according to some embodiments.
  • Figure 15 is a second schematic diagram of a light emitting chip and substrate structure according to some embodiments.
  • Figures 14 and 15 are structural diagrams from different angles. As shown in Figures 14 and 15, the upper surface of the second platform 720 may be provided with an EA signal line 721, one end of which is wire-bonded to an EA pad.
  • a first matching resistor 722 may be provided on the upper surface of the second platform 720.
  • the first matching resistor 722 is connected in series with the EA signal line 721.
  • the EA signal line 721 includes a first EA signal line 7211 and a second EA signal line 7212.
  • the first matching resistor 722 is connected across the first EA signal line 7211 and the second EA signal line 7212.
  • the first matching resistor 722 can be used for impedance matching.
  • the light emitting chip itself has a certain impedance.
  • the impedance rating of the driver chip after passing through the flexible printed circuit board is referred to herein as the characteristic impedance.
  • the characteristic impedance When the impedance output by the light emitting chip does not match this characteristic impedance, signal transmission between the driver chip and the light emitting chip will be lost, reducing signal integrity. Therefore, to ensure signal integrity, it is necessary to ensure that the impedance output by the light emitting chip matches this characteristic impedance.
  • matching here means ensuring that the impedance value output by the light emitting chip reaches the characteristic impedance value. In other words, the impedance value output by the signal line corresponding to the light emitting chip is consistent with the characteristic impedance value.
  • a ground conductive region 711 may be provided on the surface of the first platform 710 , and the light emitting chip is located above the ground conductive region 711 .
  • the cathode pad of the light emitting chip may be connected to the ground conductive region 711 .
  • a first resistive conductive area 712 may be provided on the surface of the first platform 710, and a second matching resistor 713 is provided between the first resistive conductive area 712 and the ground conductive area 711.
  • the first resistive conductive area 712 may be wire-bonded to the EA pad.
  • a second matching resistor 713 is connected between the first resistive conductive region 712 and the ground conductive region 711.
  • the first resistive conductive region 712 is connected to the EA pad of the optical transmitter chip via a wire bond.
  • the impedance of the second matching resistor 713 in parallel with the electro-absorption modulator is equal to the characteristic impedance of the driver chip and the transmitter chip, ensuring signal integrity.
  • the second platform 720 is located above the ground conductive region 711 .
  • the second matching resistor 713 provides impedance matching, ultimately aligning the impedance of the light-emitting chip with its characteristic impedance. Due to the limited space on the ceramic substrate, this second matching resistor 713 is typically a thin-film resistor sintered through a single area of the ceramic substrate. For ease of description, this disclosure refers to the circuit in which the second matching resistor 713 is connected in parallel with the electro-absorption modulator as an EA matching circuit.
  • a first matching resistor 722 may be provided on the upper surface of the second platform 720.
  • the first matching resistor 722 is connected in series with the EA signal line 721.
  • the EA signal line 721 includes a first EA signal line 7211 and a second EA signal line 7212.
  • the first matching resistor 722 is connected across the first EA signal line 7211 and the second EA signal line 7212.
  • the first matching resistor 722 can be used for impedance matching.
  • the first matching resistor 722 is connected in series with the electro-absorption modulator of the light emitting chip, and the second matching resistor 713 is connected in parallel with the electro-absorption modulator to achieve impedance matching.
  • the upper surface of the second platform may further be provided with a matching capacitor 723.
  • the matching capacitor 723 may be connected between the first EA signal line 7211 and the second EA signal line 7212, and the matching capacitor 723 is connected in parallel with the first matching resistor.
  • Figure 16 is a fourth schematic diagram of a light emitting chip and substrate structure according to some embodiments.
  • Figure 17 is a second exploded schematic diagram of a light emitting chip and substrate according to some embodiments.
  • Figure 17 is a disassembled schematic diagram of Figure 16.
  • the matching capacitor 723 may be located above the first matching resistor.
  • the projection of the matching capacitor 723 on the second platform may overlap the first matching resistor.
  • the projection of the matching capacitor 723 on the second platform may partially overlap the first matching resistor.
  • the first EA signal line 7211 is provided with a first capacitor connection area
  • the second EA signal line 7212 is provided with a second capacitor connection area
  • the matching capacitor can be connected across the first capacitor connection area and the second capacitor connection area.
  • the projection of the matching capacitor on the second platform does not cover the first matching resistor.
  • a first ground signal line 724 may be further provided on the upper surface of the second platform 720.
  • the first ground signal line 724 may be located on one side of the EA signal line 721.
  • One end of the first ground signal line 724 is positioned adjacent to the circuit board, facilitating bonding between the ground line on the circuit board and the first ground signal line 724.
  • the first ground signal line 724 provides a return path for high-frequency signals within the EA signal line 721, reducing loop area and circuit area, thereby reducing electromagnetic radiation.
  • a second ground signal line 725 may be further provided on the upper surface of the second platform 720.
  • the second ground signal line 725 may be located on the other side of the EA signal line 721.
  • One end of the second ground signal line 725 is positioned adjacent to the circuit board, facilitating bonding between the ground line on the circuit board and the second ground signal line 725.
  • the second ground signal line 725 provides a return path for high-frequency signals within the EA signal line 721, reducing loop area and circuit area, thereby reducing electromagnetic radiation.
  • the second ground signal line 725 and the first ground signal line 724 are respectively located on both sides of the EA signal line 721.
  • the first ground signal line 724 and the second ground signal line 725 can provide a return path for the high-frequency signal in the EA signal line 721, reducing the loop area and the loop area, and reducing electromagnetic radiation.
  • a first extension portion 726 may be provided on a sidewall of the second platform 720.
  • the first extension portion 726 is located on the sidewall of the second platform 720.
  • One end of the first extension portion 726 is connected to the first ground signal line 724, and the other end of the first extension portion 726 is connected to the ground conductive region 711.
  • a portion of the high-frequency signal within the EA signal line 721 flows to the circuit board via the first ground signal line 724, while the other portion flows to the ground conductive region 711 via the first ground signal line 724 and the first extension portion 726.
  • a sidewall of the second platform 720 is recessed inward to form a first avoidance portion 7201 to shorten the distance between the sidewall of the second platform 720 and the EA signal line 721.
  • the first extension portion 726 can cover the sidewall of the first avoidance portion 7201 to shorten the distance between the first extension portion 726 and the EA signal line 721, reducing the loop area and the loop area, thereby reducing electromagnetic radiation.
  • the first avoidance portion 7201 may be a rectangular structure, the first avoidance portion 7201 (specifically, the cross-sectional shape) may be a fan-shaped structure, or the first avoidance portion 7201 may be other shaped structures, which are not specifically limited here.
  • a second extension portion 727 may be provided on a sidewall of the second platform 720.
  • the second extension portion 727 is located on the sidewall of the second platform 720.
  • One end of the first extension portion 726 is connected to the second ground signal line 725, and the other end of the first extension portion 726 is connected to the ground conductive region 711.
  • a portion of the high-frequency signal in the EA signal line 721 flows to the circuit board via the second ground signal line 725, while the other portion flows to the ground conductive region 711 via the second ground signal line 725 and the second extension portion 727.
  • the other sidewall of the second platform 720 is recessed inward to form a second avoidance portion 7202, thereby shortening the distance between the sidewall of the second platform 720 and the EA signal line 721.
  • the second extension portion 727 can cover the sidewall of the second avoidance portion 7202 to shorten the distance between the second extension portion 727 and the EA signal line 721, reducing the loop area and the loop area, and reducing electromagnetic radiation.
  • the second avoidance portion 7202 may be a rectangular structure, a fan-shaped structure, or any other shape, which is not specifically limited herein.
  • Figure 18 is a fifth schematic diagram of a light emitting chip and substrate structure according to some embodiments.
  • Figure 19 is a schematic diagram from another angle of Figure 18.
  • the matching capacitor 723 can be composed of a metal strip spaced between the first EA signal line 7211 and the second EA signal line 7212.
  • a first metal arm 728 may be provided on one side of the first EA signal line 7211.
  • the first metal arm 728 is connected to the first EA signal line 7211.
  • a second metal arm 729 may be provided on one side of the second EA signal line 7212.
  • the second metal arm 729 is connected to the second EA signal line 7212.
  • a gap 750 is provided between the first metal arm 728 and the second metal arm 729, so that the first metal arm 728 and the second metal arm 729 form a capacitor structure.
  • the capacitor formed by the first metal arm 728 and the second metal arm 729 is connected in parallel with the first matching resistor 722, which can offset the parasitic inductance of the bonding wire, expand the bandwidth, and improve high-frequency performance.
  • a plurality of first metal layers 7281 and a plurality of second metal layers 7291 are provided within the gap 750.
  • first metal layer 7281 is electrically connected to the first metal arm 728, and the other end extends toward the second metal arm 729 but is not connected to the second metal arm 729.
  • the second metal layer 7291 is electrically connected to the second metal arm 729, and the other end extends toward the first metal arm 728 but is not connected to the first metal arm 728.
  • the first metal layers 7281 and the second metal layers 7291 are arranged in an alternating manner.
  • the first metal layer 7281 is not connected to the second metal layer 7291.
  • the second metal layer 7291 is disposed between adjacent first metal layers 7281, and the first metal layer 7281 is disposed between adjacent second metal layers 7291. That is, the first metal layers 7281 and the second metal layers 7291 are alternately disposed, so that there is a local area between the first metal layers 7281 and the second metal layers 7291 that is vertically opposite to each other as shown in Figures 18 and 19.
  • the plurality of first metal layers 7281 and the plurality of second metal layers 7291 are parallel to each other, that is, each first metal layer 7281 and each second metal layer 7291 are parallel to each other.
  • the first metal layer 7281 and the second metal layer 7291 which are alternately arranged with interdigitated fingers, form an equivalent capacitor, which is connected in parallel with the light emitting chip 740.
  • the light emitting chip 740 and the EA signal line form a parasitic inductance.
  • the equivalent capacitor and the parasitic inductance can form an LC resonance with a suitable amplitude to be able to
  • the bandwidth of the optical transmitter assembly is improved within an appropriate frequency range, and the flatness of the bandwidth curve is ensured.
  • the LC resonance effect within the optical transmitter assembly 410 can match the resonance effect at the connection between the optical transmitter device and the circuit board, effectively ensuring the high-frequency performance of the optical transmitter assembly 410 when used in an optical module.
  • the staggered arrangement of the first metal layer 7281 and the second metal layer 7291 can equivalently form a capacitor of 25-90fF.
  • the shapes of the first metal layer 7281 and the second metal layer 7291 can be changed as needed to obtain capacitors of other capacitance values, such as a capacitor of 70-85fF.
  • the shapes of the first metal layer 7281 and the second metal layer 7291 can be simulated and set as needed.
  • the width of the first metal layer 7281 is 15-80 ⁇ m
  • the width of the second metal layer 7291 is 15-80 ⁇ m
  • the interval between the first metal layer 7281 and the second metal layer 7291 is 15-80 ⁇ m
  • the lengths of the first metal layer 7281 and the second metal layer 7291 can be selected in combination with the width of the interval 630.
  • the width of the first metal layer 7281 is 20-60 ⁇ m
  • the width of the second metal layer 7291 is 20-60 ⁇ m
  • the interval between the first metal layer 7281 and the second metal layer 7291 is 20-60 ⁇ m.
  • the first metal arm 728 , the second metal arm 729 , the first metal layer 7281 , and the second metal layer 7291 may be formed on the main body of the second platform 720 by a metal thin film process.
  • the first metal layer 7281 and the second metal layer 7291 may have the same length.
  • the length of the first metal layer 7281 and the length of the second metal layer 7291 may also be different.
  • the number of the first metal layer 7281 and the second metal layer 7291 can be the same.
  • the number of the first metal layer 7281 and the second metal layer 7291 can also be different, which is not specifically limited here.
  • Figure 20 is a sixth schematic diagram of a light emitting chip and substrate structure according to some embodiments.
  • a first EA signal line 7211 is provided with a first metal pillar 751.
  • One end of the first metal pillar 751 is electrically connected to the first EA signal line 7211.
  • a second EA signal line 7212 is provided with a second metal pillar 752.
  • One end of the second metal pillar 752 is electrically connected to the second EA signal line 7212.
  • the first metal pillar 751 may be located above the first EA signal line 7211 .
  • the first metal pillar 751 may extend toward the inside of the second platform 720 .
  • the height of the first metal pillar 751 is smaller than that of the second platform 720 , so that the first metal pillar 751 is not connected to the ground conductive region 711 .
  • the second metal pillar 752 may be located above the second EA signal line 7212 .
  • the second metal pillar 752 may extend toward the inside of the second platform 720.
  • the height of the second metal pillar 752 is less than that of the second platform 720, so that the second metal pillar 752 is not connected to the ground conductive region 711.
  • the first metal pillar is not connected to the second metal pillar.
  • the distance between the first metal pillar 751 and the second metal pillar 752 can be set according to actual needs and is not limited here.

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Abstract

本公开提供一种光模块，包括：电路板、驱动芯片、第一光发射组件和第二光发射组件。第一光发射组件包括：基板和光发射芯片。基板包括：第一平台和第二平台，第二平台位于第一平台的上方。第二平台的表面设有第一EA信号线和第二EA信号线。第一匹配电阻跨接于第一EA信号线和第二EA信号线之间；匹配电容与第一匹配电阻并联后，与光发射芯片串联。驱动芯片同时为第一光发射芯片和第二光发射芯片提供调制信号。第一光发射芯片发出第一信号光；第二光发射芯片发出第二信号光。偏振合束器将第一信号光与第二信号光合并为第一综合信号光。第一信号光的波长与第二信号光的波长相同；第一信号光的偏振方向与第二信号光的偏振方向垂直。

Description

光模块
本申请要求在2024年4月12日提交中国专利局、申请号为202410444771.3的优先权；在2024年4月12日提交中国专利局、申请号为202420762007.6的优先权；其全部内容通过引用结合在本申请中。
技术领域
本公开涉及光纤通信技术领域，尤其涉及一种光模块。
背景技术
随着云计算、移动互联网、视频等新型业务和应用模式发展，光通信技术的发展进步变的愈加重要。而在光通信技术中，光模块是实现光电信号相互转换的工具，是光通信设备中的关键器件之一，并且随着光通信技术发展的需求光模块的传输距离不断提高。
发明内容
本公开实施例提供一种光模块，包括：
电路板；
第一光发射组件，包括：
基板，包括：
第一平台，其表面设有接地导电区、第一电阻导电区；
第二匹配电阻，位于所述接地导电区与所述第一电阻导电区之间；
第二平台，位于所述第一平台的上方；所述第二平台的上表面高于所述第一平台的上表面；
所述第二平台的表面设有EA信号线，所述EA信号线一端与所述电路板电连接；
第一匹配电阻，与所述EA信号线串接；
第一光发射芯片，位于所述第一平台，所述第一光发射芯片的负极与所述接地导电区电连接；所述第一光发射芯片的EA焊盘与所述EA信号线的另一端电连接；
驱动芯片，位于所述电路板上；
所述第一光发射芯片与所述驱动芯片电连接，所述第一光发射芯片被配置为发出第一信号光；
第二光发射组件，包括：第二光发射芯片，所述第二光发射芯片与所述驱动芯片电连接，所述第二光发射芯片被配置为发出第二信号光；
所述第一信号光的波长与所述第二信号光的波长相同；所述第一信号光的偏振方向与所述第二信号光的偏振方向垂直；
偏振合束器，位于所述第一光发射芯片和所述第二光发射芯片的出光光路上，所述偏振合束器被配置为将所述第一信号光与所述第二信号光合并为第一综合信号光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为根据一些实施例的一种光通信系统局部架构图；
图2为根据一些实施例的一种上位机的局部结构图；
图3为根据一些实施例的一种光模块的结构图；
图4为根据一些实施例的一种光模块的分解图；
图5为本公开实施例提供的一种光发射部件的分解结构示意图；
图6为本公开实施例提供的光发射部件的另一分解结构示意图；
图7为本公开实施例提供的一种光发射部件的局部结构示意图一；
图8为本公开实施例提供的一种光发射部件的局部结构示意图二；
图9为本公开实施例提供的一种光发射部件的偏振合束器结构示意图；
图10为本公开实施例提供的一种光发射部件的电路结构示意图；
图11为本公开实施例提供的一种光发射部件的等效电路示意图；
图12为根据一些实施例提供的一种光发射芯片与基板结构示意图一；
图13为根据一些实施例提供的一种基板与电路板局部剖面示意图；
图14为根据一些实施例提供的一种光发射芯片与基板分解示意图；
图15为根据一些实施例提供的一种光发射芯片与基板结构示意图二；
图16为根据一些实施例提供的一种光发射芯片与基板结构示意图四；
图17根据一些实施例提供的一种光发射芯片与基板分解示意图二；
图18为根据一些实施例提供的一种光发射芯片与基板结构示意图五；
图19为图18的其他角度示意图；
图20为根据一些实施例提供的一种光发射芯片与基板结构示意图六。
具体实施方式
光通信技术在信息处理设备之间建立信息传递，光通信技术将信息加载到光上，利用光的传播实现信息的传递，加载有信息的光就是光信号。光信号在信息传输设备中传播，可以减少光功率的损耗，实现高速度、远距离、低成本的信息传递。信息处理设备能够处理的信息以电信号的形态存在，光网络终端/网关、路由器、交换机、手机、计算机、服务器、平板电脑、电视机是常见的信息处理设备，光纤及光波导是常见的信息传输设备。
信息处理设备与信息传输设备之间的光信号、电信号相互转换，是通过光模块实现的。例如，在光模块的光信号输入端和/或光信号输出端连接有光纤，在光模块的电信号输入端和/或电信号输出端连接有光网络终端；来自光纤的第一光信号传输进光模块，光模块将第一光信号转换为第一电信号，光模块将第一电信号传输进光网络终端；来自光网络终端的第二电信号传输进光模块，光模块将第二电信号转换为第二光信号，光模块将第二光信号传输进光纤。由于信息处理设备之间可以通过电信号网络相互连接，所以至少需要一类信息处理设备直接与光模块连接，并不需要所有类型的信息处理设备均直接与光模块连接，直接连接光模块的信息处理设备被称为光模块的上位机。
图1为根据一些实施例的一种光通信系统局部架构图。如图1所示，光通信系统的局部呈现为远端信息处理设备1000、本地信息处理设备2000、上位机100、光模块200、光纤101以及网线103。
光纤101的一端向远端信息处理设备1000方向延伸，另一端接入光模块200的光接口。光信号可以在光纤101中发生全反射，光信号在全反射方向上的传播几乎可以维持原有光功率，光信号在光纤101中发生多次的全反射，将来自远端信息处理设备1000方向的光信号传输进光模块200中，或将来自光模块200的光向远端信息处理设备1000方向传播，实现远距离、功率损耗低的信息传递。
光纤101的数量可以是一根，也可以是多根(两根及以上)；光纤101与光模块200采用可插拔式的活动连接，也可采用固定连接。
上位机100具有光模块接口102，光模块接口102被配置为接入光模块200，从而使得上位机100与光模块200建立单向/双向的电信号连接；上位机100被配置为向光模块200提供数据信号，或从光模块200接收数据信号，或对光模块200的工作状态进行监测、控制。
上位机100具有对外电接口，如通用串行总线接口(Universal Serial Bus，USB)、网线接口104，对外电接口可以接入电信号网络。示例地，网线接口104被配置为接入网线103，从而使得上位机100与网线103建立单向/双向的电信号连接。
光网络终端(ONU，Optical Network Unit)、光线路终端(OLT，Optical Line Terminal)、光网络设备(ONT，Optical Network Terminal)及数据中心服务器为常见的上位机。
网线103的一端连接本地信息处理设备2000，另一端连接上位机100，网线103在本地信息处理设备2000与上位机100之间建立电信号连接。
示例地，本地信息处理设备2000发出的第三电信号通过网线103传入上位机100，上位机100基于第三电信号生成第二电信号，来自上位机100的第二电信号传输进光模块200，光模块200将第二电信号转换为第二光信号，光模块200将第二光信号传输进光纤101，第二光信号在光纤101中传向远端信息处理设备1000。
示例地，来自远端信息处理设备1000方向的第一光信号通过光纤101传播，来自光纤101的第一光信号传输进光模块200，光模块200将第一光信号转换为第一电信号，光模块200将第一电信号传输进上位机100，上位机100基于第一电信号生成第四电信号，上位机100将第四电信号传入本地信息处理设备2000。
光模块是实现光信号与电信号相互转换的工具，在上述光信号与电信号的转换过程中，信息并未发生变化，信息的编解码方式可以发生变化。
图2为根据一些实施例的一种上位机的局部结构图。为了清楚地显示光模块200与上位机100的连接关系，图2仅示出了上位机100与光模块200相关的结构。如图2所示，上位机100还包括设置于壳体内的PCB电路板105、设置在PCB电路板105的表面的笼子106、设置于笼子106上的散热器107、以及设置于笼子106内部的电连接器(图中未示出)，散热器107具有增大散热面积的凸起结构，翅片状结构是常见的凸起结构。
光模块200插入上位机100的笼子106中，由笼子106固定光模块200，光模块200产生的热量传导给笼子106，然后通过散热器107进行扩散。光模块200插入笼子106中后，光模块200的电接口与笼子106内部的电连接器连接。
图3为根据一些实施例的一种光模块的结构图，图4为根据一些实施例的一种光模块的分解图。如图3和图4所示，光模块200包括壳体(shell)、设置于壳体内的电路板300、光发射部件400和光接收部件。但本公开并不局限于此，在一些实施例中，光模块200包括光发射部件400和光接收部件之一。
壳体包括上壳体201和下壳体202，上壳体201盖合在下壳体202上，以形成具有两个开口204和205的上述壳体；壳体的外轮廓一般呈现方形体。
在一些实施例中，下壳体202包括底板2021以及位于底板2021两侧、与底板2021垂直设置的两个下侧板2022；上壳体201包括盖板2011，盖板2011盖合在下壳体202的两个下侧板2022上，以形成上述壳体。
在一些实施例中，下壳体202包括底板2021以及位于底板2021两侧、与底板2021垂直设置的两个下侧板2022；上壳体201包括盖板2011，以及位于盖板2011两侧、与盖板2011垂直设置的两个上侧板，由两个上侧板与两个下侧板2022结合，以实现上壳体201盖合在下壳体202上。
两个开口204和205的连线所在方向可以与光模块200的长度方向一致，也可以与光模块200的长度方向不一致。例如，开口204位于光模块200的端部(图3的右端)，开口205也位于光模块200的端部(图3的左端)。或者，开 口204位于光模块200的端部，而开口205则位于光模块200的侧部。开口204为电接口，电路板300的金手指从电接口伸出，插入上位机的电连接器中；开口205为光口，被配置为接入光纤101，以使光纤101连接光模块200中的光发射部件400和/或光接收部件。
采用上壳体201、下壳体202结合的装配方式，便于将电路板300、光发射部件400、光接收部件等组件安装到上述壳体中，由上壳体201、下壳体202可以对这些组件形状封装保护。此外，在装配电路板300、光发射部件400与光接收部件等组件时，便于这些器件的定位部件、散热部件以及电磁屏蔽部件的部署，有利于自动化地实施生产。
在一些实施例中，上壳体201及下壳体202采用金属材料制成，利于实现电磁屏蔽以及散热。
在一些实施例中，光模块200还包括位于其壳体外部的解锁部件600。解锁部件600被配置为实现光模块200与上位机之间的固定连接，或解除光模块200与上位机之间的固定连接。
例如，解锁部件600位于下壳体202的两个下侧板2022的外侧，包括与上位机的笼子106匹配的卡合部件。当光模块200插入笼子106里时，由解锁部件600的卡合部件将光模块200固定在笼子106里；拉动解锁部件600时，解锁部件600的卡合部件随之移动，进而改变卡合部件与上位机的连接关系，以解除光模块200与上位机的卡合固定连接，从而可以将光模块200从笼子106里抽出。
电路板300包括电路走线、电子元件及芯片等，通过电路走线将电子元件和芯片按照电路设计连接在一起，以实现供电、电信号传输及接地等功能。电子元件例如可以包括电容、电阻、三极管、金属氧化物半导体场效应管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)。芯片例如可以包括微控制单元(Microcontroller Unit，MCU)、激光驱动芯片、跨阻放大器(Transimpedance Amplifier，TIA)、限幅放大器(limiting amplifier)、时钟数据恢复芯片(Clock and Data Recovery，CDR)、电源管理芯片、数字信号处理(Digital Signal Processing，DSP)芯片。
电路板300一般为硬性电路板，硬性电路板由于其相对坚硬的材质，还可以实现承载作用，如硬性电路板可以平稳的承载上述电子元件和芯片；硬性电路板还便于插入上位机笼子中的电连接器中。
电路板300还包括形成在其端部表面的金手指，金手指由独立的多个引脚组成。电路板300插入笼子106中，由金手指与笼子106内的电连接器导通。金手指可以仅设置在电路板300一侧的表面(例如图4所示的上表面)，也可以设置在电路板300上下两侧的表面，以提供更多的引脚。金手指被配置为与上位机建立电连接，以实现供电、接地、I2C信号传递、数据信号传递等。
当然，部分光模块中也会使用柔性电路板，柔性电路板一般与硬性电路板配合使用，以作为硬性电路板的补充。
光发射部件400和/或光接收部件位于电路板300的远离金手指的一侧；在一些实施例中，光发射部件400及光接收部件分别与电路板300物理分离，然后分别通过相应的柔性电路板或电连接件与电路板300电连接；在一些实施例中，光发射部件和/或光接收部件可以直接设置在电路板300上，可以设置在电路板的表面，也可以设置在电路板的侧边。
图5为本公开实施例提供的一种光发射部件的分解结构示意图；图6为本公开实施例提供的光发射部件的另一分解结构示意图；下面结合图5和图6对本公开光模块的光发射部分的整体结构进行说明。如图5、图6所示，光发射部件可包括盖板401和外壳402，盖板401和外壳402盖合连接，具体盖板401从上方盖合外壳402，外壳402的一侧壁具有开口，用于电路板300的插入，外壳402的另一侧壁具有通孔，用于光纤适配器403的插入。
具体地，电路板300通过开口伸入外壳402中，电路板300与下壳体202固定；电路板300上镀有金属走线，光学器件可以通过打线的方式与对应的金属走线电连接，以实现外壳402内的光学器件与电路板300的电连接。
光发射部件发射的信号光射入该通孔，光纤适配器403伸入通孔中以耦合接收信号光，这种配装结构设计可以使得光纤适配器403在通孔中前后移动，可以调节光纤在光发射部件及光纤插头之间的需求尺寸，当光纤较短时，可以在通孔中将光纤适配器向后(向腔体外部方向)移动，以满足连接尺寸要求；当光纤较长时，可以在通孔中将光纤适配器向前(向腔体内部方向)移动，以拉直光纤，避免光纤弯曲。光纤适配器403插入通孔中以实现与光发射部件的固定；装配过程中，光纤适配器403可以在通孔中移动以选择固定位置。
在一些实施例中，外壳402的一侧壁具有开口，用于电路板300的插入，外壳402的另一侧壁具有通孔，用于光纤适配器403的插入。
本实施例设置外壳402内的光学器件可选地还可以通过引脚与电路板300连接，其中，引脚设计为与下壳体相适配的形状，引脚一端插入下壳体内部，并且在该端上镀有金属走线，光学器件可以通过打线的方式与对应的金属走线电连接，引脚置于外壳402的一端设有多个与金属走线电连接的管脚，通过将管脚插入电路板300中并焊接在一起，进而实现外壳402内的光学器件与电路板300的电连接，当然，也可以通过将引脚上的管脚直接与电路板300焊接在一起，以实现外壳402内的光学器件与电路板300的电连接。
在信号发射过程中，外壳402内的光发射子组件在接收到电路板300传输来的电信号后，会将该电信号转换成光信号，然后该光信号进入光纤适配器403后，发射至光模块外部。
在一些实施例中，光发射部件具有封装结构，以将激光芯片等封装起来，已有的封装结构包括同轴封装TO-CAN、硅光封装、板上芯片透镜组件封装COB-LENS、微光学XMD封装。封装还分为气密性封装及非气密性封装，封装一方面为激光芯片提供稳定、可靠的工作环境，另一方面形成对外的电连接及光输出。
图7为本公开实施例提供的一种光发射部件的局部结构示意图一；图8为本公开实施例提供的一种光发射部件的局部结构示意图二。图8和图7为不同角度下示出的光发射部件的外壳内部，如图7和图8所示，本公开实施例中光发射部件可以包括：光发射组件410。光发射组件410位于外壳402的内部，光发射组件410可将电信号转换为光信号。
在一些实施例中，电路板上可设有第一驱动芯片。第一驱动芯片可以集成于DSP芯片内部。
在一些实施例中，光发射组件410可以包括：第一光发射芯片411，第一光发射芯片411可与第一驱动芯片连接，第一驱动芯片输出调制信号至第一光发射芯片411，对第一光发射芯片411发出的光进行调制，形成第一信号光。
在一些实施例中，第一光发射芯片411可以是第一EML激光器。第一EML激光器包括：第一发光器和第一调制器。第一驱动芯片与第一调制器连接，第一调制器对第一发光器发出的光进行编码调制后输出，使得输出的光信号携带信息。
在一些实施例中，光发射组件410可以包括：第二光发射芯片412，第二光发射芯片412可与第一驱动芯片连接，第一驱动芯片输出调制信号至第二光发射芯片412，对第二光发射芯片412发出的光进行调制，形成第二信号光。
在一些实施例中，第二光发射芯片412可以是第二EML激光器。第二EML激光器包括：第二发光器和第二调制器。第一驱动芯片与第二调制器连接，第二调制器对第二发光器发出的光进行编码调制后输出，使得输出的光信号携带信息。
在本公开的一些实施例中，第一信号光的波长与第二信号光的波长相同；第二光发射芯片412与第一光发射芯片411同时与第一驱动芯片连接，第二光发射芯片412与第一光发射芯片411的调制信号相同，第一信号光携带的信号与第二信号光携带的信号相同。
在一些实施例中，第一光发射芯片411发出的信号光可与第二光发射芯片发出的信号光的偏振方向一致，通过在第一光发射芯片411的出光光路设置偏振片，改变第一光发射芯片411发出的信号光的偏振方向，使得改变后的信号光与第二光发射芯片发出的信号光的偏振方向不同。
在一些实施例中，第一光发射芯片411发出的信号光可与第二光发射芯片发出的信号光的偏振方向一致，通过在第一光发射芯片411的出光光路设置偏振片，改变第一光发射芯片411发出的信号光的偏振方向，使得改变后的信号光与第二光发射芯片发出的信号光的偏振方向垂直。
光发射组件410可以包括：第一准直透镜421，位于第一光发射芯片411的出光光路上，第一光发射芯片411发出的第一信号光为发散光，第一准直透镜421对第一信号光进行准直。
光发射组件410可以包括：第二准直透镜422，位于第二光发射芯片412的出光光路上，第二光发射芯片412发出的第二信号光为发散光，第二准直透镜422对第二信号光进行准直。
第一偏振合束器431，位于第一光发射芯片411和第二光发射芯片412的出光光路上，偏振合束器431可将所第一信号光与第二信号光合并为第一综合信号光。
图9为本公开实施例提供的一种光发射部件的偏振合束器结构示意图。如图9所示，第一偏振合束器包括：第一偏振反射片4311，位于第一光发射芯片的出光光路上。第一偏振反射片4311可将准直后的第一信号光反射。
在一些实施例中，第一偏振反射片的法线与第一光发射芯片的出光轴线夹角为45°。
在一些实施例中，第一偏振合束器可以包括：第二偏振反射片4312，位于第二光发射芯片412的出光光路上。第二偏振反射片可将准直后的第一信号光反射，第二信号光透射经过第二偏振反射片，将第一信号光与第二信号光合为一束。
在一些实施例中，为了使得第一信号光与第二信号光合束时光信号一致，避免因光路不同导致信号延迟，第一光发射芯片411与第一偏振合束器之间的距离，小于第二光发射芯片412与第一偏振合束器之间的距离；以使第一信号光与第二信号光在第一偏振合束器的出口处的光程一致。即，第一信号光由第一光发射芯片411的出口至第一偏振合束器的出口的光程，等于第二信号光由第二光发射芯片411的出口至第一偏振合束器的出口的光程。
如图8所示，光发射组件410可以包括：第三光发射芯片413，第三光发射芯片413可与第二驱动芯片连接，第二驱动芯片输出调制信号至第三光发射芯片413，对第三光发射芯片413发出的光进行调制，形成第三信号光。
光发射组件410可以包括：第四光发射芯片414，第四光发射芯片414可与第二驱动芯片连接，第二驱动芯片输出调制信号至第四光发射芯片414，对第四光发射芯片414发出的光进行调制，形成第四信号光。
在本公开的一些实施例中，第三信号光的波长与第四信号光的波长相同；第三光发射芯片413与第四光发射芯片414同时与第二驱动芯片连接，第三光发射芯片413与第四光发射芯片414的调制信号相同，第三信号光携带的信号与第四信号光携带的信号相同。
在一些实施例中，第三信号光的偏振方向与第四信号光的偏振方向不同，示例的，第三信号光的偏振方向与第四信号光的偏振方向垂直。
光发射组件410可以包括：第三准直透镜423，位于第三光发射芯片413的出光光路上，第三光发射芯片413发出的第三信号光为发散光，第三准直透镜423对第三信号光进行准直。
光发射组件410可以包括：第四准直透镜424，位于第四光发射芯片414的出光光路上，第四光发射芯片414发出的第四信号光为发散光，第四准直透镜424对第四信号光进行准直。
第二偏振合束器432位于第三光发射芯片413和第四光发射芯片414的出光光路上，第二偏振合束器432可将所第三信号光与第四信号光合并为第二综合信号光。第二偏振合束器432的结构可参照图9所示，当然，为了使得第三信号光与第四信号光合束时光信号一致，避免因光路不同导致信号延迟，参照上述示例可以理解，第三信号光由第三光发射芯片413的出口至第二偏振合束器的出口的光程，等于第四信号光由第四光发射芯片414的出口至第二偏振合束器的出口的光程。
由上述示例可以分析出，第一综合信号光的波长与第二综合信号光的波长不同。
在一些实施例中，光发射组件410可以包括：光波分复用器440。光波分复用器440可将第一综合信号光和第二综合信号光合为一束。
在一些实施例中，光波分复用器440可将多束综合信号光合为一束。
在本公开的一些实施例中，第一驱动芯片与第一光发射芯片、第二光发射芯片连接，第一驱动芯片为第一光发射芯片、第二光发射芯片提供调制信号，使得第一光发射芯片与第二光发射芯片发出的信号光携带的信号相同。第一光发射芯片发出的第一信号光与第二光发射芯片发出的第二信号光波长相同，偏振方向不同。通过偏振合束器将第一信号光与第二信号光合并为一束发射信号光，能够实现单个波长下获得最大程度的光强，具有光放大作用，可提高光的传播距离。
图10为本公开实施例提供的一种光发射部件的电路结构示意图。如图10中所示，电路板300的表面可设有第一驱动信号线461，第一驱动信号线461的一端与第一驱动芯片连接。
电路板300的表面可设有第二驱动信号线462，第二驱动信号线462的一端与第一驱动信号线461连接。第二驱动信号线462的另一端与第一光发射芯片连接。
电路板300的表面可设有第三驱动信号线463，第三驱动信号线463的一端与第一驱动信号线461连接。第三驱动信号线463的另一端与第一光发射芯片连接。
图11为本公开实施例提供的一种光发射部件的等效电路示意图。如图11所示，第一驱动芯片310与第一驱动信号线461的一端连接。第一驱动信号线461的另一端与第二驱动信号线462、第三驱动信号线463连接。
第二驱动信号线462与第一光发射芯片411之间可设有第一阻直电容311。第一阻直电容311可对第一驱动芯片与第一光发射芯片之间的直流电流进行隔断。
第三驱动信号线463与第二光发射芯片412之间可设有第二阻直电容312。第二阻直电容312可对第一驱动芯片与第二光发射芯片之间的直流电流进行隔断。
第一驱动信号线461可与第一供电电路320连接，第一供电电路320可为第一驱动芯片提供供电电压。
第一供电电路320位于第一阻直电容311与第一驱动芯片310之间。第一阻直电容311可避免第一供电电路320的直流电流进入第一光发射芯片。
第二供电电路330可为第一光发射芯片411、第二光发射芯片412提供供电电压。第二供电电路330可包括第一支路331和第二支路332。其中，第一支路331与第一光发射芯片连接，第一支路可为第一光发射芯片提供供电电压。第一阻直电容311位于第一供电电路320与第一支路331之间，从而保证第一驱动芯片的供电电路和第一光发射芯片的供电电路之间电压互不干扰。
第二支路332与第二光发射芯片连接，第二支路可为第二光发射芯片提供供电电压。第二阻直电容312位于第一供电电路320与第二支路332之间，从而保证第一驱动芯片的供电电路和第二光发射芯片的供电电路之间电压互不干扰。
在本公开的一些实施例中，第二供电电路330可以包括：第一电感3301、第一电阻3302。第一电感3301与第一电阻3302并联形成第一RL滤波器，第一RL滤波器可隔交流信号，避免第一驱动信号线461内携带的交流信号对电源形成影响。
第二供电电路330可以包括：第一磁珠3303，第一磁珠3303可与电源串联。第一磁珠3303可位于第一RL滤波器与第一驱动信号线461之间。第一磁珠3303可阻止第一驱动信号线461的高频信号对电源产生影响。
第二供电电路330可以包括：第二磁珠3304，第二磁珠3304可位于第一磁珠3303与第一驱动信号线461之间。第一磁珠3303与第二磁珠3304的规格不同，第一磁珠3303与第二磁珠3304可对不同频率的交流信号进行阻隔。
第二供电电路330可以包括：第三磁珠3305，第二磁珠3304可位于第一磁珠3303与第二驱动信号线462之间。第一磁珠3303与第三磁珠3305的规格不同，第一磁珠3303与第三磁珠3305可对不同频率的交流信号进行阻隔。
在一些实施例中，为实现对光发射芯片的驱动，光发射芯片位于基板上，基板表面设置导电区域，通过导电区域与外部电路连接。为了方便表述，以下将光发射芯片与基板称为光发射组件。
图12为根据一些实施例提供的一种光发射芯片与基板结构示意图一。如图12所示，本实施例提供的光发射组件中，光发射芯片设置在基板700的顶面上，基板700上设置信号走线；光发射芯片的正极位于光发射芯片的顶部，通过打线连接基板700，通过基板700接收高频信号。
在一些实施例中，光发射芯片740可以是第一光发射芯片，也可以是第二光发射芯片。
基板700可设有不同高度的第一平台710和第二平台720。其中，第一平台710的高度高于第二平台的高度。需要说明的是，第二平台720可以放置于第一平台710的上方，即，第二平台720的上表面高于第一平台的上表面。示例的，光发射芯片位于第一平台。
在一些实施例中，光发射芯片可以是EML激光器，光发射芯片740的上表面可设有EA焊盘742和发光焊盘741；光发射芯片的下表面可设有负极焊盘。
光发射芯片的上表面与第二平台的上表面平齐，EA焊盘经打线与第二平台表面的EA信号线连接。光发射芯片的上表面与第二平台的上表面平齐，使得EA焊盘与第二平台表面的EA信号线之间的连接线缩短，减少寄生电阻的产生。
图13为根据一些实施例提供的一种基板与电路板局部剖面示意图。如图13所示，第二平台的上表面与电路板上表面平齐。电路板通过打线与EA信号线的一端连接，第二平台的上表面与电路板上表面平齐，可缩短电路板与EA信号线的打线距离，减少寄生电阻的产生。
图14为根据一些实施例提供的一种光发射芯片与基板分解示意图。图15为根据一些实施例提供的一种光发射芯片与基板结构示意图二。图14和图15为不同角度的结构示意图，如图14和图15所示，第二平台720的上表面可设有EA信号线721，EA信号线721的一端与EA焊盘打线连接。
第二平台720的上表面可设有第一匹配电阻722，第一匹配电阻722与EA信号线721串联。示例的，EA信号线721包括第一EA信号线7211和第二EA信号线7212。第一匹配电阻722跨接于第一EA信号线7211和第二EA信号线7212之间。第一匹配电阻722可用于阻抗匹配。
光发射芯片本身具有一定的阻抗，由于驱动芯片经过柔性电路板后输出的阻抗额定，此处本公开中称之为特性阻抗。当光发射芯片输出的阻抗与该特性阻抗不匹配时，驱动芯片和光发射芯片之间传输信号会有损耗，降低信号的完整性，因此为了保证信号的完整性，需要保证光发射芯片输出的阻抗与该特性阻抗相匹配，需要说明的是，此处的匹配含义是指使光发射芯片输出的阻抗值达到特性阻抗值，也就是，光发射芯片相对应的信号线输出的阻抗值与特性阻抗值一致。
在一些实施例中，第一平台710表面可设有接地导电区711，光发射芯片位于接地导电区711的上方。光发射芯片的负极焊盘可与接地导电区711连接。
第一平台710表面可设有第一电阻导电区712，第一电阻导电区712与接地导电区711之间跨设有第二匹配电阻713。第一电阻导电区712可与EA焊盘打线连接。
第二匹配电阻713跨接于第一电阻导电区712与接地导电区711之间；第一电阻导电区712与光发射芯片的EA焊盘通过打线连接。第二匹配电阻713与电吸收调制器并联后的阻抗，等于驱动芯片和发射芯片的特性阻抗的值，保证信号的完整性。
在一些示例中，第二平台720位于接地导电区711的上方。
为方便制备，第二匹配电阻713具备阻抗匹配作用，最终使光发射芯片的阻抗与特性阻抗相一致；由于陶瓷基板的空间较小，一般第二匹配电阻713采用的是薄膜电阻，其通过陶瓷基板的一块区域烧结而成。为方便表述，本公开将第二匹配电阻713与电吸收调制器并联后的电路称为EA匹配电路。
第二平台720的上表面可设有第一匹配电阻722，第一匹配电阻722与EA信号线721串联。示例的，EA信号线721包括第一EA信号线7211和第二EA信号线7212。第一匹配电阻722跨接于第一EA信号线7211和第二EA信号线7212之间。第一匹配电阻722可用于阻抗匹配。
第一匹配电阻722与光发射芯片的电吸收调制器串联，第二匹配电阻713与电吸收调制器并联，实现阻抗匹配。
在一些实施例中，如图15中所示，第二平台的上表面还可设有匹配电容723。匹配电容723可以跨接于第一EA信号线7211和第二EA信号线7212之间，匹配电容723与第一匹配电阻并联。
图16为根据一些实施例提供的一种光发射芯片与基板结构示意图四。图17根据一些实施例提供的一种光发射芯片与基板分解示意图二。图17为图16的拆分示意图。在一些实施例中，如图16所示，匹配电容723可位于第一匹配电阻的上方。匹配电容723在第二平台的投影可覆盖第一匹配电阻。匹配电容723在第二平台的投影可部分覆盖第一匹配电阻。
如图17中所示，第一EA信号线7211设有第一电容连接区，第二EA信号线7212设有第二电容连接区，匹配电容可跨接于第一电容连接区与第二电容连接区之间。匹配电容在第二平台的投影不覆盖第一匹配电阻。
在一些实施例中，第二平台720的上表面还可设有第一接地信号线724。第一接地信号线724可位于EA信号线721的一侧。第一接地信号线724的一端邻近电路板设置，方便电路板上的接地线与第一接地信号线724打线连接。第一接地信号线724可为EA信号线721内的高频信号提供回流路径，减少回路面积和环路面积，减少电磁辐射。
在一些实施例中，第二平台720的上表面还可设有第二接地信号线725。第二接地信号线725可位于EA信号线721的另一侧。第二接地信号线725的一端邻近电路板设置，方便电路板上的接地线与第二接地信号线725打线连接。第二接地信号线725可为EA信号线721内的高频信号提供回流路径，减少回路面积和环路面积，减少电磁辐射。
在一些实施例中，第二接地信号线725与第一接地信号线724分别位于EA信号线721的两侧，第一接地信号线724和第二接地信号线725可为EA信号线721内的高频信号提供回流路径，减少回路面积和环路面积，减少电磁辐射。
如图14所示，在一些实施例中，为实现对第一接地信号线724与接地导电区711导电连接，第二平台720的一侧壁可设有第一延展部726。第一延展部726位于第二平台720的侧壁，第一延展部726的一端与第一接地信号线724连接，第一延展部726的另一端与接地导电区711连接。EA信号线721内的高频信号中一部分经第一接地信号线724流向电路板，另一部分经第一接地信号线724、第一延展部726流向接地导电区711。
在一些实施例中，第二平台720的一侧壁向内凹陷形成第一避让部7201，以缩短第二平台720的侧壁与EA信号线721的距离。第一延展部726可覆盖第一避让部7201的侧壁，以缩短第一延展部726与EA信号线721的距离，减少回路面积和环路面积，减少电磁辐射。
在一些实施例中，第一避让部7201可以是矩形结构，第一避让部7201(具体指截面形状)可以是扇形。第一避让部7201可以是其他形状结构，在此不做具体限定。
在一些实施例中，为实现对第二接地信号线725与接地导电区711导电连接，第二平台720的一侧壁可设有第二延展部727。第二延展部727位于第二平台720的侧壁，第一延展部726的一端与第二接地信号线725连接，第一延展部726的另一端与接地导电区711连接。EA信号线721内的高频信号中一部分经第二接地信号线725流向电路板，另一部分经第二接地信号线725、第二延展部727流向接地导电区711。
在一些实施例中，第二平台720的另一侧壁向内凹陷形成第二避让部7202，以缩短第二平台720的侧壁与EA信号线721的距离。第二延展部727可覆盖第二避让部7202的侧壁，以缩短第二延展部727与EA信号线721的距离，减少回路面积和环路面积，减少电磁辐射。
在一些实施例中，第二避让部7202可以是矩形结构，第二避让部7202可以是扇形。第二避让部7202可以是其他形状结构，在此不做具体限定。
图18为根据一些实施例提供的一种光发射芯片与基板结构示意图五。图19为图18的其他角度示意图。如图18和图19所示，匹配电容723可以是由第一EA信号线7211和第二EA信号线7212之间间隔设置的金属条组成。
在一些实施例中，第一EA信号线7211的一侧可设有第一金属臂728。第一金属臂728与第一EA信号线7211连接。第二EA信号线7212的一侧可设有第二金属臂729。第二金属臂729与第二EA信号线7212连接。第一金属臂728与第二金属臂729之间具有间隙750，使得第一金属臂728与第二金属臂729形成电容结构，第一金属臂728与第二金属臂729形成的电容与第一匹配电阻722并联，可抵消打线的寄生电感，拓展带宽，提高高频性能。在一些实施例中，间隙750内设置若干条第一金属层7281和若干条第二金属层7291。
第一金属层7281的一端电连接第一金属臂728、另一端向第二金属臂729延伸但不与第二金属臂729连接。第二金属层7291电连接第二金属臂729、另一端向第一金属臂728延伸但不与第一金属臂728连接，第一金属层7281与第二金属层7291交错设置。
在本公开一些实施例中，第一金属层7281与第二金属层7291不连接。示例地，相邻的第一金属层7281之间设置第二金属层7291，相邻的第二金属层7291之间设置第一金属层7281，即第一金属层7281与第二金属层7291交替设置，使第一金属层7281与第二金属层7291之间具有如图18和图19所示方向上下正对的局域。
在一些实施例中，若干条第一金属层7281和若干条第二金属层7291之间相互平行，即各第一金属层7281与各第二金属层7291相互平行。
因此，叉指交替设置的第一金属层7281与第二金属层7291形成等效电容，该等效电容与光发射芯片740并联，而光发射芯片740与EA信号线的打线形成寄生电感，该等效电容与寄生电感能够形成幅度合适的LC谐振，以能够在合 适的频率范围内提高光发射组件的带宽，并能保证带宽曲线的平整度。进而当光发射组件连接电路板300时，光发射组件410内的LC谐振效应能够与光发射器件与电路板连接处的谐振效应匹配，有效保证光发射组件410在光模块中使用的高频性能。
在一些实施例中，第一金属层7281与第二金属层7291交错设置可等效形成25-90fF的电容，当然可根据需要改变第一金属层7281与第二金属层7291的形状等获得其他容值的电容，如70-85fF的电容，具体可根据需要仿真设置第一金属层7281与第二金属层7291的形状。
在本公开一些实施例中，第一金属层7281的宽度为15-80μm，第二金属层7291的宽度为15-80μm，第一金属层7281与第二金属层7291之间的间隔为15-80μm，第一金属层7281与第二金属层7291的长度可结合间隔630的宽度进行选择。进一步，第一金属层7281的宽度为20-60μm，第二金属层7291的宽度为20-60μm，第一金属层7281与第二金属层7291之间的间隔为20-60μm
第一金属臂728、第二金属臂729、第一金属层7281与第二金属层7291可通过金属薄膜工艺在第二平台720的本体上形成。
在一些实施例中，第一金属层7281与第二金属层7291可具有相同的长度。第一金属层7281的长度与第二金属层7291的长度也可不同。
在一些实施例中，第一金属层7281与第二金属层7291数量可相同。第一金属层7281与第二金属层7291数量也可不同，在此不做具体限定。
图20为根据一些实施例提供的一种光发射芯片与基板结构示意图六。如图20所示，第一EA信号线7211设有第一金属柱751。第一金属柱751的一端与第一EA信号线7211电连接。第二EA信号线7212设有第二金属柱752。第二金属柱752的一端与第二EA信号线7212电连接。
在一些实施例中，第一金属柱751可位于第一EA信号线7211的上方。
在一些实施例中，第一金属柱751可向第二平台720的内部延伸。第一金属柱751的高度小于第二平台720的高度，以使第一金属柱751不与接地导电区711连接。
在一些实施例中，第二金属柱752可位于第二EA信号线7212的上方。
在一些实施例中，第二金属柱752可向第二平台720的内部延伸。第二金属柱752的高度小于第二平台720的高度，以使第二金属柱752不与接地导电区711连接。第一金属柱与所述第二金属柱不连接。
第一金属柱751与第二金属柱752之间的距离可根据实际需要进行设置，在此不做限定。
由于以上实施方式均是在其他方式之上引用结合进行说明，不同实施例之间均具有相同的部分，本说明书中各个实施例之间相同、相似的部分互相参见即可。在此不再详细阐述。
需要说明的是，在本说明书中，诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或暗示这些实体或操作之间存在任何这种实际的关系或顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的电路结构、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种电路结构、物品或者设备所固有的要素。在没有更多限制的情况下，有语句“包括一个……”限定的要素，并不排除在包括所述要素的电路结构、物品或者设备中还存在另外的相同要素。
本领域技术人员在考虑说明书及实践本公开的公开后，将容易想到本公开的其他实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求的内容指出。
以上所述的本公开实施方式并不构成对本公开保护范围的限定。

Claims (12)

  1. 一种光模块，包括：
    电路板；
    第一光发射组件，包括：
    基板，包括：
    第一平台，其表面设有接地导电区、第一电阻导电区；
    第二匹配电阻，位于所述接地导电区与所述第一电阻导电区之间；
    第二平台，位于所述第一平台的上方；所述第二平台的上表面高于所述第一平台的上表面；
    所述第二平台的表面设有EA信号线，所述EA信号线一端与所述电路板电连接；
    第一匹配电阻，与所述EA信号线串接；
    第一光发射芯片，位于所述第一平台，所述第一光发射芯片的负极与所述接地导电区电连接；所述第一光发射芯片的EA焊盘与所述EA信号线的另一端电连接；
    驱动芯片，位于所述电路板上；
    所述第一光发射芯片与所述驱动芯片电连接，所述第一光发射芯片被配置为发出第一信号光；
    第二光发射组件，包括：第二光发射芯片，所述第二光发射芯片与所述驱动芯片电连接，所述第二光发射芯片被配置为发出第二信号光；
    所述第一信号光的波长与所述第二信号光的波长相同；所述第一信号光的偏振方向与所述第二信号光的偏振方向垂直；
    偏振合束器，位于所述第一光发射芯片和所述第二光发射芯片的出光光路上，所述偏振合束器被配置为将所述第一信号光与所述第二信号光合并为第一综合信号光。
  2. 根据权利要求1所述的光模块，其中，所述EA信号线包括第一EA信号线和第二EA信号线，所述第一EA信号线与所述电路板电连接，所述第二EA信号线与所述第一光发射芯片的EA焊盘电连接；
    所述第一匹配电阻跨接于所述第一EA信号线和所述第二EA信号线之间。
  3. 根据权利要求2所述的光模块，其中，所述基板还包括匹配电容，所述匹配电容与所述第一匹配电阻并联，所述匹配电容跨接于所述第一EA信号线和所述第二EA信号线之间。
  4. 根据权利要求3所述的光模块，其中，所述第二平台的表面设有第一接地信号线和第二接地信号线；所述第一接地信号线和所述第二接地信号线位于所述第一EA信号线的两侧。
  5. 根据权利要求3所述的光模块，其中，所述偏振合束器包括：
    第一偏振反射片，位于所述第一光发射芯片的出光光路上，所述第一偏振反射片对所述第一信号光反射；
    第二偏振反射片，位于所述第二光发射芯片的出光光路上，所述第二信号光透射经过所述第二偏振反射片，所述第二信号光在所述第二偏振反射片处反射。
  6. 根据权利要求3所述的光模块，其中，所述光模块包括：
    第一准直透镜，位于所述第一光发射芯片与所述偏振合束器之间；
    第二准直透镜，位于所述第二光发射芯片与所述偏振合束器之间；
    第一驱动信号线，所述第一驱动信号线一端与所述驱动芯片连接；
    第二驱动信号线，所述第二驱动信号线一端与所述第一驱动信号线连接，另一端与所述第一光发射芯片连接，
    第三驱动信号线，所述第三驱动信号线一端与所述第一驱动信号线连接，另一端与所述第二光发射芯片连接。
  7. 根据权利要求6所述的光模块，其中，所述光模块包括：
    第一阻直电容，所述第一阻直电容位于所述第二驱动信号线与所述第一光发射芯片之间；
    第二阻直电容，所述第二阻直电容位于所述第三驱动信号线与所述第二光发射芯片之间。
  8. 根据权利要求7所述的光模块，其中，所述光模块包括：
    第一供电电路，位于所述第一阻直电容与所述驱动芯片之间；所述第一供电电路与所述第一驱动信号线连接；所述第一供电电路为所述驱动芯片提供电源；
    第二供电电路包括：
    第一支路，位于所述第一阻直电容与所述第一光发射芯片之间；所述第一支路与所述第二驱动信号线连接；所述第一支路为所述第一发射芯片提供电源；
    第二支路，位于所述第二阻直电容与所述第二光发射芯片之间；所述第二支路与所述第三驱动信号线连接；所述第二支路为所述第二发射芯片提供电源。
  9. 根据权利要求4所述的光模块，其中，所述第二平台的侧壁设有第一延展部，第一延展部一端与所述第一接地信号线连接，另一端与所述接地导电区连接；
    所述第二平台的另一侧壁设有第二延展部，第二延展部一端与所述第二接地信号线连接，另一端与所述接地导电区连接。
  10. 根据权利要求9所述的光模块，其中，所述第二平台的一侧壁向内凹陷形成第一避让部，所述第一延展部覆盖所述第一避让部；
    所述第二平台的另一侧壁向内凹陷形成第二避让部，所述第二延展部覆盖所述第二避让部。
  11. 根据权利要求4所述的光模块，其中，所述匹配电容包括：第一金属臂，所述第一金属臂的一端与所 述第一EA信号线连接；
    第二金属臂，所述第二金属臂的一端与所述第二EA信号线连接；所述第一金属臂与所述第二金属臂之间具有间隙。
  12. 根据权利要求11所述的光模块，其中，所述匹配电容包括：第一金属层，所述第一金属层的一端与所述第一金属臂连接，另一端向所述第二金属臂延伸但不与所述第二金属臂连接；
    第二金属层，所述第二金属层的一端与所述第二金属臂连接，另一端向所述第一金属臂延伸但不与所述第一金属臂连接；
    所述第一金属层与所述第二金属层位于所述间隙内。
PCT/CN2024/117452 2024-04-12 2024-09-06 光模块 Pending WO2025213701A1 (zh)

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CN202410444771.3A CN120630400A (zh) 2024-04-12 2024-04-12 一种光模块
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