WO2025201147A1 - 一种数模转换器 - Google Patents

一种数模转换器

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Publication number
WO2025201147A1
WO2025201147A1 PCT/CN2025/083553 CN2025083553W WO2025201147A1 WO 2025201147 A1 WO2025201147 A1 WO 2025201147A1 CN 2025083553 W CN2025083553 W CN 2025083553W WO 2025201147 A1 WO2025201147 A1 WO 2025201147A1
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WO
WIPO (PCT)
Prior art keywords
moscap
gate
drain
switch circuit
switch1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/083553
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English (en)
French (fr)
Inventor
罗豪
路昊炜
朱文涛
王东
武世明
李广
刘威
李炜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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Application filed by Sanechips Technology Co Ltd filed Critical Sanechips Technology Co Ltd
Publication of WO2025201147A1 publication Critical patent/WO2025201147A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/70—Automatic control for modifying converter range

Definitions

  • the embodiments of the present disclosure relate to the field of communication technology, and in particular to a digital-to-analog converter.
  • the core circuit of the current-steering digital-to-analog converter is divided into multiple units (Slices) for data reception.
  • the switching of the input data in the switching circuit will share the charge to the output of the digital-to-analog converter (DAC) through the gate-drain capacitance of the switching circuit.
  • DAC full-scale current that is, the sum of the current sources of all units in the DAC core circuit
  • the shared charge does not change linearly, resulting in the differential voltage amplitude of the DAC output not changing linearly with the DAC full-scale current. It will also cause the phase of the DAC differential output not to remain constant when the DAC full-scale current changes.
  • the DAC In the transmission chain of communication applications, in order to compensate for the power fluctuations of the DAC's post-stage power amplifier, the DAC needs to be adaptively adjusted within a wider full-scale current range, and the DAC output voltage is required to change linearly within this full-scale current range, and the output phase is required to be constant.
  • the traditional current-steering digital-to-analog converter core circuit structure cannot meet these requirements.
  • An embodiment of the present disclosure provides a digital-to-analog converter.
  • a digital-to-analog converter comprising: a data link and a digital-to-analog converter core circuit, wherein the digital-to-analog converter core circuit comprises a first switching circuit Switch1, a second switching circuit Switch2, a first charge compensation device, and a second charge compensation device, wherein the first switching circuit Switch1 is connected to the first charge compensation device, and the second switching circuit Switch2 is connected to the second charge compensation device;
  • the data link is configured to generate first data and second data, and input the first data into the first switch circuit Switch1, and input the second data into the second switch circuit Switch2;
  • the first switch circuit Switch1 and the second switch circuit Switch2 are configured to output a differential voltage Vout according to the first data and the second data, and share a first charge to an output terminal;
  • the first charge compensation device and the second charge compensation device are configured to share a second charge to the output end, wherein the second charge has a polarity opposite to that of the first charge, and the second charge and the first charge neutralize each other.
  • FIG1 is a block diagram of the core circuit structure of a current-steering digital-to-analog converter in the related art
  • FIG2 is a block diagram of a digital-to-analog converter according to an embodiment of the present disclosure
  • FIG3 is a first structural diagram of a core circuit of a current-steering digital-to-analog converter according to this embodiment
  • FIG4 is a second structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment.
  • FIG5 is a third structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment.
  • FIG6 is a fourth structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment.
  • FIG7 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present disclosure.
  • FIG8 is a fifth structural diagram of the core circuit of the current-steering digital-to-analog converter according to this embodiment.
  • the switching of input data at the gates of the switch circuits Switch1 and Switch2 will share charge with the DAC output through the gate-drain capacitance of the switch circuits.
  • the DAC full-scale current i.e., the sum of the currents of the current sources Current Source of all units in the DAC core circuit
  • the shared charge does not change linearly, resulting in the DAC differential output voltage amplitude not changing linearly with the DAC full-scale current.
  • This will also cause the DAC differential output phase to not remain constant when the DAC full-scale current changes.
  • the DAC needs to be adaptively adjusted within a wider full-scale current range.
  • the DAC output voltage is also required to change linearly within this full-scale current range, and the output phase is required to be constant.
  • the core circuit structure of the current-steering digital-to-analog converter cannot meet these requirements.
  • FIG2 is a block diagram of a digital-to-analog converter according to an embodiment of the present disclosure.
  • the digital-to-analog converter includes: a data link and a digital-to-analog converter core circuit, wherein the digital-to-analog converter core circuit includes a first switching circuit Switch1, a second switching circuit Switch2, a first charge compensation device, and a second charge compensation device.
  • the first switching circuit Switch1 is connected to the first charge compensation device
  • the second switching circuit Switch2 is connected to the second charge compensation device.
  • the data link is configured to generate first data and second data, and input the first data into the first switch circuit Switch1 and input the second data into the second switch circuit Switch2;
  • the first switch circuit Switch1 and the second switch circuit Switch2 are configured to output a differential voltage Vout according to the first data and the second data, and share the first charge to the output end;
  • the first charge compensation device and the second charge compensation device are configured to share a second charge to the output end, wherein the second charge has a polarity opposite to that of the first charge and the second charge and the first charge neutralize each other.
  • the digital-to-analog converter in this embodiment through charge sharing at the DAC output end by the first charge compensation device, the second charge compensation device, and the switching device, can solve the problem in the related art that the current-steering digital-to-analog converter cannot meet the requirements of linear voltage change and constant phase output within the full current range, and realizes linear voltage change and constant phase output of the DAC within the full current range.
  • the first charge compensation device is configured to invert the first data and share the second charge to the output terminal to neutralize the first charge shared by the first switch circuit Switch1 to the output terminal;
  • the second charge compensation device is configured to invert the second data and share the second charge to the output end to neutralize the first charge shared by the second switch circuit Switch2 to the output end.
  • the first charge compensation device and the second charge compensation device are one of the following: a metal oxide semiconductor capacitor (MOSCAP), a series-parallel combination of MOSCAPs, a metal oxide metal capacitor (MOMCAP), a series-parallel combination of MOMCAPs, a metal insulator metal capacitor (MIMCAP), and a series-parallel combination of MIMCAPs.
  • MOSCAP metal oxide semiconductor capacitor
  • MOMCAP metal oxide metal capacitor
  • MIMCAP metal insulator metal capacitor
  • first charge compensation device and the second charge compensation device are moscaps or a series-parallel combination of moscaps, they are configured to share the second charge to the output end through a gate-source capacitor or a gate-drain capacitor;
  • first charge compensation device and the second charge compensation device are one of the following: momcap, a series-parallel combination of momcaps, mimcap, and a series-parallel combination of mimcaps, they are configured to share the second charge to the output end through a capacitor.
  • FIG3 is a structural schematic diagram of the core circuit of the current steering digital-to-analog converter according to this embodiment. As shown in FIG3, two moscaps (named moscap1 and moscap2) are introduced. The gate of the first moscap is connected to the gate of the second switch circuit Switch2, the source of the first moscap is connected to the drain of the first switch circuit Switch1, and the gate of the second moscap is connected to the drain of the first switch circuit Switch2.
  • the gate of h1 is connected, the source of the second moscap is connected to the drain of the second switching circuit Switch2, and the drain of the first moscap and the drain of the second moscap are floating; or the gate of the first moscap is connected to the gate of the second switching circuit Switch2, the drain of the first moscap is connected to the drain of the first switching circuit Switch1, the gate of the second moscap is connected to the gate of the first switching circuit Switch1, the drain of the second moscap is connected to the drain of the second switching circuit Switch2, and the source of the first moscap and the source of the second moscap are floating.
  • the aspect ratio of moscap1 and moscap2 is consistent with that of DAC switches Switch1 and Switch2.
  • the data connected to the gate of moscap1 is the inverse of the data connected to Switch1
  • the data connected to the gate of moscap2 is the inverse of the data connected to Switch2.
  • One end of the source or drain of moscap1 is connected to the drain of Switch1, and the other end is floating.
  • One end of the source or drain of moscap2 is connected to the drain of Switch2, and the other end is floating (described).
  • Switch1 and Switch2 determine the output current of current source Current Source to the upper port of load resistor RL1 or RL2 (i.e., the positive or negative terminal of the DAC differential output) based on the input real data D ⁇ N:0> and Db ⁇ N:0>. Switching the gates of Switch1 and Switch2 will share charge with the DAC output through their own gate-drain capacitance. Switching the gates of the newly introduced moscap1 and moscap2 will share charge with the DAC output through the gate-source capacitance or gate-drain capacitance of moscap1 and moscap2. This shared charge has opposite polarity to the charge shared with the DAC output by the gate-drain capacitance of Switch1/Switch2, neutralizing each other and compensating for the impact of the original shared charge on the DAC output amplitude and phase.
  • first data and second data are generated through a data link, and the first data is input into the first switching circuit Switch1, and the second data is input into the second switching circuit Switch2; the first switching circuit Switch1 and the second switching circuit Switch2 output a differential voltage Vout according to the first data and the second data, and share a first charge to the output end; the first charge compensation device and the second charge compensation device share a second charge to the output end, wherein the second charge has an opposite polarity to the first charge and the second charge and the first charge neutralize each other, which can solve the problem in the related art that the current-steering digital-to-analog converter cannot meet the requirements of linear voltage change and constant phase output within the full current range.
  • the linear voltage change and constant phase output by the DAC within the full current range are achieved.
  • FIG5 is a third structural diagram of the core circuit of the current-steering DAC according to this embodiment. As shown in FIG5 , the source and drain of the MOSCAP are short-circuited and simultaneously connected to the drain of the switch, etc. Depending on the connection method, the aspect ratio of the MOSCAP can also be adjusted accordingly.
  • FIG6 is a structural schematic diagram of the core circuit of the current steering type digital-to-analog converter according to this embodiment. As shown in FIG6, moscap1 and moscap1' are connected in parallel and then connected to Switch1, and moscap2 and moscap2' are connected in parallel and then connected to Switch2. The specific connection method after parallel connection is similar to the first moscap and the second moscap in FIG3, and will not be repeated here.
  • the digital-to-analog converter core circuit in this embodiment includes multiple digital-to-analog converter core units, wherein the drains of the first switch circuits Switch1 of the multiple digital-to-analog converter core units are connected together, and the drains of the second switch circuits Switch2 of the multiple digital-to-analog converter core units are connected together.
  • the first switch circuit Switch1, the second switch circuit Switch2, the first MOSCAP (MOSCAP1) and the second MOSCAP (MOSCAP2) are on the same substrate. Furthermore, the first switch circuit Switch1, the second switch circuit Switch2, the first MOSCAP and the second MOSCAP have the same or different sizes.
  • FIG8 is a structural diagram of the core circuit of the current steering digital-to-analog converter according to the present embodiment.
  • the first charge compensation device is momcap1 or mimcap1 (corresponding to cap1)
  • the second charge compensation device is momcap2 or mimcap2 (corresponding to cap2)
  • the upper plate of the momcap1 or mimcap1 is connected to the drain of the first switch circuit Switch1
  • the lower plate of the momcap1 or mimcap1 is connected to the gate of the second switch circuit Switch2
  • the upper plate of the momcap2 or mimcap2 is connected to the drain of the second switch circuit Switch1.
  • the drain of ch2 is connected, and the lower plate of the momcap2 or mimcap2 is connected to the gate of the first switch circuit Switch1; or the lower plate of the momcap1 or mimcap1 is connected to the drain of the first switch circuit Switch1, and the upper plate of the momcap1 or mimcap1 is connected to the gate of the second switch circuit Switch2; the lower plate of the momcap2 or mimcap2 is connected to the drain of the second switch circuit Switch2, and the upper plate of the momcap2 or mimcap2 is connected to the gate of the first switch circuit Switch1.
  • the series and parallel connection of momcap and/or mimcap is also similar. After the series and parallel connection, they can be connected to Switch1 and Switch2, which will not be repeated here.
  • the decoder's primary function is to perform DAC segment encoding (typically thermometer code for the DAC's upper bits and binary encoding for the lower bits). Furthermore, the decoder can apply algorithms such as DEM, dithering, and rotation to the data. In these digital modules, each DAC bit is typically transmitted in multiple phases.
  • the serializer's primary function is to convert multi-phase data into a single phase or fewer phases.
  • the switch driver's primary function is to synchronize each bit of data and increase drive capability. The distinction between switch drivers and serializers can sometimes be blurred, as the switch driver may also perform some serialization.
  • the switch driver's output is fed into the digital-to-analog converter core unit, which performs the digital-to-analog conversion function.
  • the clock link's function is to provide clocks of various frequencies and phases to the data link.
  • the first switch circuit Switch1 and the second switch circuit Switch2 are PMOS transistors or NMOS transistors.
  • This embodiment introduces two MOSFETs (MOSFETs) with the same size as the DAC switches into the core circuit structure of a current-steering DAC.
  • the gates are connected to inverted data, sharing charges of opposite polarity with the source of the connected DAC switches. This compensates for the effect of the DAC switch gate-drain charge sharing on the DAC output amplitude and phase.
  • This overcomes the problem of related technologies that prevent linear output voltage variation and constant output phase over a wide full-scale current range.
  • the DAC output voltage amplitude varies by more than 29dB (very close to linear variation), with a phase deviation of less than 5 degrees.
  • the aspect ratio of the newly introduced moscap1 and moscap2 can be adjusted (not necessarily consistent with the aspect ratio of the DAC switches Switch1 and Switch2). This can adjust the charge neutralization effect, and thus adjust the impact of shared charge on the DAC output amplitude and phase.
  • the moscap connection method can have many variations, as long as it can provide a shared path to the DAC output. For example: as shown in Figure 4, the moscap gate connection method remains unchanged, the floating terminals of the original two moscaps are connected together, or the floating terminals are no longer floating but connected to a fixed potential, or as shown in Figure 5, the moscap source and drain are shorted and connected to the drain of the switch at the same time. Depending on the connection method, the aspect ratio of the moscap can also be adjusted accordingly.

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Abstract

本公开实施例提供了一种数模转换器，通过数据链路产生第一数据与第二数据，将第一数据输入第一开关电路Switch1，并将第二数据输入第二开关电路Switch2；第一开关电路Switch1、第二开关电路Switch2，根据第一数据与第二数据输出差分电压Vout，并向输出端分享第一电荷；第一电荷补偿器件、第二电荷补偿器件，向输出端分享第二电荷，第二电荷与第一电荷极性相反，第二电荷与第一电荷互相中和。

Description

一种数模转换器
相关公开的交叉引用
本公开基于2024年03月29日提交的发明名称为“一种数模转换器”的中国专利公开2024103799950，并且要求该专利公开的优先权，通过引用将其所公开的内容全部并入本公开。
技术领域
本公开实施例涉及通信技术领域，具体而言，涉及一种数模转换器。
背景技术
电流舵型数模转换器核心电路它分多个单元(Slice)进行数据接收。输入数据在开关电路的切换会通过开关电路的栅漏电容向数模转换器(Digtial-to-Analog Converter，简称为DAC)输出端分享电荷。当DAC满幅电流(即DAC核心电路中所有单元的电流源Current Source电流的总和)变化时，分享电荷并不会随着线性变化，导致DAC输出的差分电压幅度不会随着DAC满幅电流线性变化，同时也会导致DAC差分输出的相位不会在DAC满幅电流变化时保持恒定。在通讯应用的发射链路中，为了补偿DAC后级功率放大器的功率波动，DAC需要在一个较广泛的满幅电流范围内进行适应性地调整，且要求DAC在这个满幅电流范围内输出电压线性变化，输出相位恒定，传统的电流舵型数模转换器核心电路结构无法满足要求。
针对相关技术中电流舵型数模转换器无法满足在满幅电流范围内输出的电压线性变化、相位恒定的问题，尚未提出解决方案。
发明内容
本公开实施例提供了一种数模转换器。
根据本公开的一个实施例，提供了一种数模转换器，所述数模转换器包括：数据链路与数模转换器核心电路，其中，所述数模转换器核心电路包括第一开关电路Switch1、第二开关电路Switch2、第一电荷补偿器件及第二电荷补偿器件，所述第一开关电路Switch1与所述第一电荷补偿器件连接，所述第二开关电路Switch2与所述第二电荷补偿器件连接；
所述数据链路，设置为产生第一数据与第二数据，并将所述第一数据输入所述第一开关电路Switch1，并将所述第二数据输入所述第二开关电路Switch2；
所述第一开关电路Switch1、所述第二开关电路Switch2，设置为根据所述第一数据与所述第二数据输出差分电压Vout，并向输出端分享第一电荷；
所述第一电荷补偿器件、所述第二电荷补偿器件，设置为向所述输出端分享第二电荷，其中，所述第二电荷与所述第一电荷极性相反，所述第二电荷与所述第一电荷互相中和。
附图说明
图1是相关技术中电流舵型数模转换器的核心电路结构框图；
图2是根据本公开实施例的数模转换器的框图；
图3是根据本实施例的电流舵型数模转换器核心电路的结构示意图一；
图4根据本实施例的电流舵型数模转换器核心电路的结构示意图二；
图5根据本实施例的电流舵型数模转换器核心电路的结构示意图三；
图6根据本实施例的电流舵型数模转换器核心电路的结构示意图四；
图7是根据本公开实施例的数模转换器的结构示意图；
图8根据本实施例的电流舵型数模转换器核心电路的结构示意图五。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开的实施例。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
图1是相关技术中电流舵型数模转换器的核心电路结构框图，如图1所示，分多个单元(Slice)进行数据接收。开关驱动器输出的真实数据D<N：0>和Db<N：0>分别接到DAC核心电路中的开关电路Switch1和Switch2的栅极，设置为选择电流源Current Source的输出电流到负载电阻RL1或RL2的上端口(也即DAC差分输出的正端或负端)。Switch为PMOS管仅作为示意，也可以用NMOS管做开关电路。所有DAC核心电路单元的Switch1的漏极是连在一起的，所有Switch2的漏极是连在一起的。对于整个DAC核心电路而言，根据D<N：0>和Db<N：0>数据的不同，流到RL1的总电流和流到RL2的总电流是不同的，对应的差分输出电压Vout也是不同的，最终实现了输出差分电压Vout与输入数据的线性转换关系。
输入数据在开关电路Switch1和Switch2栅极的切换会通过开关电路的栅漏电容向DAC输出端分享电荷。当DAC满幅电流(即DAC核心电路中所有单元的电流源Current Source电流的总和)变化时，分享电荷并不会随着线性变化，导致DAC差分输出电压幅度不会随着DAC满幅电流线性变化，同时也会导致DAC差分输出的相位不会在DAC满幅电流变化时保持恒定。在通讯应用的发射链路中，为了补偿DAC后级功率放大器的功率波动，DAC需要在一个较广泛的满幅电流范围内进行适应性地调整，且要求DAC在这个满幅电流范围内输出电压线性变化，输出相位恒定，电流舵型数模转换器核心电路结构无法满足要求。
基于此，本实施例中提供了一种数模转换器，图2是根据本公开实施例的数模转换器的框图，如图2所示，所述数模转换器包括：数据链路与数模转换器核心电路，其中，所述数模转换器核心电路包括第一开关电路Switch1、第二开关电路Switch2、第一电荷补偿器件及第二电荷补偿器件，第一开关电路Switch1与第一电荷补偿器件连接，第二开关电路Switch2与第二电荷补偿器件连接；
所述数据链路，设置为产生第一数据与第二数据，并将第一数据输入第一开关电路Switch1，将第二数据输入第二开关电路Switch2；
第一开关电路Switch1、第二开关电路Switch2，设置为根据第一数据与第二数据输出差分电压Vout，并向输出端分享第一电荷；
第一电荷补偿器件、第二电荷补偿器件，设置为向所述输出端分享第二电荷，其中，第二电荷与第一电荷极性相反，第二电荷与第一电荷互相中和。
本实施例中的数模转换器，通过第一电荷补偿器件、第二电荷补偿器件中和开关器件对DAC输出端的电荷分享，可以解决相关技术中电流舵型数模转换器无法满足在满幅电流范围内输出的电压线性变化、相位恒定的问题，实现了在满幅电流范围内DAC输出的电压线性变化、相位恒定。
在一实施例中，第一电荷补偿器件，设置为对第一数据取反，向所述输出端分享第二电荷，以中和第一开关电路Switch1向所述输出端分享的第一电荷；
第二电荷补偿器件，设置为对第二数据取反，向所述输出端分享第二电荷，以中和第二开关电路Switch2向所述输出端分享的第一电荷。
在一实施例中，第一电荷补偿器件、第二电荷补偿器件为以下之一：金属-氧化物-硅电容器(metal oxide semiconductor capacitor，简称为moscap)、moscap的串并联组合、金属-氧化物-金属电容器(metal oxide metal capacitor，简称为momcap)、momcap的串并联组合、金属-绝缘体-金属电容器(metal insulator metal capacitor，简称为mimcap)、mimcap的串并联组合。
在一实施例中，第一电荷补偿器件、第二电荷补偿器件为moscap或moscap的串并联组合的情况下，设置为通过栅源电容或栅漏电容向所述输出端分享第二电荷；
第一电荷补偿器件、第二电荷补偿器件为以下之一：momcap、momcap的串并联组合、mimcap、mimcap的串并联组合的情况下，设置为通过电容向所述输出端分享第二电荷。
在第一电荷补偿器件为第一moscap(对应moscap1)，第二电荷补偿器件为第二moscap(对应moscap2)的情况下，图3是根据本实施例的电流舵型数模转换器核心电路的结构示意图一，如图3所示，引入了两个moscap(命名为moscap1和moscap2)，第一moscap的栅极与第二开关电路Switch2的栅极连接，第一moscap的源极与第一开关电路Switch1的漏极连接，第二moscap的栅极与第一开关电路Switch1的栅极连接，第二moscap的源极与第二开关电路Switch2的漏极连接，第一moscap的漏极、第二moscap的漏极浮空；或者第一moscap的栅极与第二开关电路Switch2的栅极连接，第一moscap的漏极与第一开关电路Switch1的漏极连接，第二moscap的栅极与第一开关电路Switch1的栅极连接，第二moscap的漏极与第二开关电路Switch2的漏极连接，第一moscap的源极、第二moscap的源极浮空。moscap1和moscap2的宽长比尺寸和DAC开关Switch1和Switch2宽长比尺寸一致，其中moscap1栅极接入的数据是Switch1接入数据的取反，moscap2栅极接入的数据是Switch2接入数据的取反，moscap1源极或漏极其中一端接到Switch1的漏极，另外一端浮空，moscap2源极或漏极其中一端接到Switch2的漏极，另外一端浮空(已描述)。
Switch1和Switch2会根据输入真实数据D<N：0>和Db<N：0>来决定电流源Current Source的输出电流到负载电阻RL1或RL2的上端口(也即DAC差分输出的正端或负端)。Switch1和Switch2栅极的切换会通过自身栅漏电容向DAC输出端分享电荷。新引入的moscap1和moscap2栅极的切换会通过moscap1和moscap2的栅源电容或栅漏电容向DAC输出端分享电荷，该分享电荷与Switch1/Switch2的栅漏电容向DAC输出端分享电荷极性相反，能够互相中和，补偿原先分享电荷对DAC输出幅度和相位的影响。
本公开实施例，通过数据链路产生第一数据与第二数据，并将所述第一数据输入所述第一开关电路Switch1，并将所述第二数据输入所述第二开关电路Switch2；所述第一开关电路Switch1、所述第二开关电路Switch2，根据所述第一数据与所述第二数据输出差分电压Vout，并向输出端分享第一电荷；所述第一电荷补偿器件、所述第二电荷补偿器件，向所述输出端分享第二电荷，其中，所述第二电荷与所述第一电荷极性相反，所述第二电荷与所述第一电荷互相中和，可以解决相关技术中电流舵型数模转换器无法满足在满幅电流范围内输出的电压线性变化、相位恒定的问题，通过第一电荷补偿器件、第二电荷补偿器件中和开关器件对DAC输出端的电荷分享，实现了在满幅电流范围内DAC输出的电压线性变化、相位恒定。
图4根据本实施例的电流舵型数模转换器核心电路的结构示意图二，如图4所示，moscap栅极接法不变，原本两个moscap的浮空端接在一起，又或者浮空端不再浮空，而是接某个固定电位。第一moscap(对应moscap1)的栅极与第二开关电路Swi tch2的栅极连接，第一moscap的源极与第一开关电路Switch1的漏极连接，第二moscap的栅极与第一开关电路Switch1的栅极连接，第二moscap(对应moscap2)的源极与第二开关电路Switch2的漏极连接，第一moscap的漏极与第二开关电路moscap2的漏极连接；或者第一moscap的栅极与第二开关电路Switch2的栅极连接，第一moscap的栅极与第一开关电路Switch1的漏极连接，第二moscap的栅极与第一开关电路Switch1的栅极连接，第二moscap的栅极与第二开关电路Switch2的漏极连接，第一moscap的源极与第二开关电路moscap2的源极连接。
图5根据本实施例的电流舵型数模转换器核心电路的结构示意图三，如图5所示，moscap源漏短接并同时接到switch的漏极等等。根据接法的不同，moscap的宽长比尺寸也可以针对性地调整。第一moscap(对应moscap1)的源极与第一开关电路Switch1的漏极连接，第二moscap(对应moscap2)的栅极与第一开关电路Switch1的栅极连接，第二moscap源极与第二开关电路Switch2的漏极连接，第一moscap的源极与第一moscap的漏极连接，第二moscap的源极与第二moscap的漏极连接；或者第一moscap的栅极与第二开关电路Switch2的栅极连接，第一moscap的漏极与第一开关电路Switch1的漏极连接，第二moscap的栅极与第一开关电路Switch1的栅极连接，第二moscap的漏极与第二开关电路Switch2的漏极连接，第一moscap的源极与第一moscap的漏极连接，第二moscap的源极与第二moscap的漏极连接。
在第一电荷补偿器件为moscap的并联(对应moscap1与moscap1′并联)，第二电荷补偿器件为moscap的并联(对应moscap2与moscap2′并联)的情况下，图6根据本实施例的电流舵型数模转换器核心电路的结构示意图四，如图6所示，moscap1与moscap1′并联之后与Switch1连接，moscap2与moscap2′并联之后与Switch2，并联后具体的连接方式与图3中第一moscap、第二moscap类似，在此不再赘述。第一电荷补偿器件为moscap的串联(对应moscap1与moscap1′串联)，第二电荷补偿器件为moscap的串联(对应moscap2与moscap2′串联)的与并联类似在，不再赘述。
图7是根据本公开实施例的数模转换器的结构示意图，如图7所示，包括数据链路(Data Path)、时钟链路(CLK)和数模转换器核心电路(DAC Core)。其中数据链路包括接口电路(Interface)、数字数据链路(Digital Data Path)、译码器(Decoder)、串行化器(Serializer)和开关驱动器(Switch Driver)，时钟链路包括时钟接收器(Clock Receiver)、延迟锁相环(DLL)、分频器(Divider)和一些时钟驱动器等，而数模转换器核心电路包括多个数模转换器核心单元(DAC Core Slices)。对于DAC而言，数模转换器核心电路的设计至关重要，影响到线性度、功耗、噪声、输出功率等多个指标。本实施例中的数模转换器核心电路包括多个数模转换器核心单元，其中，所述多个数模转换器核心单元的第一开关电路Switch1的漏极是连接在一起的，所述多个数模转换器核心单元的第二开关电路Switch2的漏极是连接在一起的。第一开关电路Switch1、第二开关电路Switch2、第一moscap(moscap1)及第二moscap(moscap2)在同一衬底上。进一步的，第一开关电路Switch1、第二开关电路Switch2、第一moscap及第二moscap的尺寸一致或不一致。
图8根据本实施例的电流舵型数模转换器核心电路的结构示意图五，如图8所示，第一电荷补偿器件为momcap1或mimcap1(对应cap1)、第二电荷补偿器件为momcap2或mimcap2(对应cap2)的情况下，所述momcap1或所述mimcap1的上极板与第一开关电路Switch1的漏极连接，所述momcap1或所述mimcap1的下极板与第二开关电路Switch2的栅极连接；所述momcap2或所述mimcap2的上极板与第二开关电路Switch2的漏极连接，所述momcap2或所述mimcap2的下极板与第一开关电路Switch1的栅极连接；或者所述momcap1或所述mimcap1的下极板与第一开关电路Switch1的漏极连接，所述momcap1或所述mimcap1的上极板与第二开关电路Switch2的栅极连接；所述momcap2或所述mimcap2的下极板与第二开关电路Switch2的漏极连接，所述momcap2或所述mimcap2的上极板与第一开关电路Switch1的栅极连接。momcap和/或mimcap的串并联方式也是类似的，串并联之后与Switch1、Switch2连接即可，在此不再赘述。
在数据链路中，输入数字信号首先通过接口电路和数字数据链路进行数据接收和处理，译码器的主要功能是完成DAC分段编码(DAC高位一般用温度计码，低位一般用二进制编码)，此外，译码器中可以对数据施加一些算法，例如DEM，dither，rotation等，在这些数字模块中DAC的每一位数据一般都会分为多相位传输。串行化器的主要功能是将多相位数据转变为单相位或较少相位的数据。而开关驱动器的主要功能是对每一位数据进行同步，并增加驱动能力。有时开关驱动器和串行化器的界限比较模糊，在开关驱动器中也可以做一些串行化的动作。开关驱动器的输出会送到数模转换器核心单元，设置为实现数模转换功能，而时钟链路的作用是给数据链路供给多种频率和相位的时钟。
本实施例中的第一开关电路Switch1、第二开关电路Switch2为PMOS管或NMOS管。
本实施例在电流舵型数模转换器核心电路结构引入两个与DAC开关尺寸一致的moscap，栅极接入数据取反，向相连的DAC开关源级分享极性相反的电荷，补偿原先DAC开关栅漏电荷分享对DAC输出幅度和相位的影响。解决了相关技术中存在的无法在一个较广泛的满幅电流范围内实现输出电压线性变化、输出相位恒定等问题，在0-30dB DAC满幅电流变化范围内，DAC输出电压幅度变化范围大于29dB(非常接近线性变化)，相位偏差小于5度。
新引入的moscap1和moscap2宽长比尺寸可以调整(不一定和DAC开关Switch1和Switch2宽长比尺寸保持一致)，这样可以调整电荷中和的效果，进而调整分享电荷对DAC输出幅度和相位的影响；moscap的接法可以有多种变型，只要能够向DAC输出提供分享路径即可，比如：如图4所示，moscap栅极接法不变，原本两个moscap的浮空端接在一起，又或者浮空端不再浮空，而是接某个固定电位，或者如图5所示，moscap源漏短接并同时接到switch的漏极等等。根据接法的不同，moscap的宽长比尺寸也可以针对性地调整；
尽管图4和图5的连接方式与图3有所不同，但基本工作原理是类似的，均为通过新引入的moscap向DAC输出端分享电荷，抵消Switch1/Switch2向DAC输出端分享电荷的影响。
本实施例中的电荷补偿器件可以是moscap，也可以是其它类型的电容器(capacitor，简称为cap)，比如：moscap的串并联组合、momcap、mimcap、moscap/momcap/mimcap的串并联组合，或者是其它类似的电容，也可以其它的能够提供分享路径的电路。比如：如图6所示的moscap并联的方式，或者momcap并联的方式。
本实施例中的具体示例可以参考上述实施例及示例性实施方式中所描述的示例，本实施例在此不再赘述。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (12)

  1. 一种数模转换器，所述数模转换器包括：数据链路与数模转换器核心电路，其中，所述数模转换器核心电路包括第一开关电路Switch1、第二开关电路Switch2、第一电荷补偿器件及第二电荷补偿器件，所述第一开关电路Switch1与所述第一电荷补偿器件连接，所述第二开关电路Switch2与所述第二电荷补偿器件连接；
    所述数据链路，设置为产生第一数据与第二数据，并将所述第一数据输入所述第一开关电路Switch1，将所述第二数据输入所述第二开关电路Switch2；
    所述第一开关电路Switch1、所述第二开关电路Switch2，设置为根据所述第一数据与所述第二数据输出差分电压Vout，并向输出端分享第一电荷；
    所述第一电荷补偿器件、所述第二电荷补偿器件，设置为向所述输出端分享第二电荷，其中，所述第二电荷与所述第一电荷极性相反，所述第二电荷与所述第一电荷互相中和。
  2. 根据权利要求1所述的数模转换器，其中，
    所述第一电荷补偿器件，设置为对所述第一数据取反，向所述输出端分享所述第二电荷，以中和所述第一开关电路Switch1向所述输出端分享的所述第一电荷；
    所述第二电荷补偿器件，设置为对所述第二数据取反，向所述输出端分享所述第二电荷，以中和所述第二开关电路Switch2向所述输出端分享的所述第一电荷。
  3. 根据权利要求2所述的数模转换器，其中，
    所述第一电荷补偿器件、所述第二电荷补偿器件为以下之一：金属-氧化物-硅电容器moscap、moscap的串并联组合、金属-氧化物-金属电容器momcap、momcap的串并联组合、金属-绝缘体-金属电容器mimcap、mimcap的串并联组合。
  4. 根据权利要求3所述的数模转换器，其中，
    所述第一电荷补偿器件、所述第二电荷补偿器件为moscap或moscap的串并联组合的情况下，设置为通过栅源电容或栅漏电容向所述输出端分享所述第二电荷；
    所述第一电荷补偿器件、所述第二电荷补偿器件为以下之一：momcap、momcap的串并联组合、mimcap、mimcap的串并联组合的情况下，设置为通过电容向所述输出端分享所述第二电荷。
  5. 根据权利要求4所述的数模转换器，其中，
    在所述第一电荷补偿器件为第一moscap，所述第二电荷补偿器件为第二moscap的情况下，所述第一moscap的栅极与所述第二开关电路Switch2的栅极连接，所述第一moscap的源极与所述第一开关电路Switch1的漏极连接，所述第二moscap的栅极与所述第一开关电路Switch1的栅极连接，所述第二moscap的源极与所述第二开关电路Switch2的漏极连接，所述第一moscap的漏极、所述第二moscap的漏极浮空；或者
    所述第一moscap的栅极与所述第二开关电路Switch2的栅极连接，所述第一moscap的漏极与所述第一开关电路Switch1的漏极连接，所述第二moscap的栅极与所述第一开关电路Switch1的栅极连接，所述第二moscap的漏极与所述第二开关电路Switch2的漏极连接，所述第一moscap的源极、所述第二moscap的源极浮空。
  6. 根据权利要求4所述的数模转换器，其中，
    在所述第一电荷补偿器件为第一moscap，所述第二电荷补偿器件为第二moscap的情况下，所述第一moscap的栅极与所述第二开关电路Switch2的栅极连接，所述第一moscap的源极与所述第一开关电路Switch1的漏极连接，所述第二moscap的栅极与所述第一开关电路Switch1的栅极连接，所述第二moscap源极与所述第二开关电路Switch2的漏极连接，所述第一moscap的漏极与所述第二开关电路moscap2的漏极连接；或者
    所述第一moscap的栅极与所述第二开关电路Switch2的栅极连接，所述第一moscap的栅极与所述第一开关电路Switch1的漏极连接，所述第二moscap的栅极与所述第一开关电路Switch1的栅极连接，所述第二moscap的栅极与所述第二开关电路Switch2的漏极连接，所述第一moscap的源极与所述第二开关电路moscap2的源极连接。
  7. 根据权利要求4所述的数模转换器，其中，
    在所述第一电荷补偿器件为第一moscap，所述第二电荷补偿器件为第二moscap的情况下，所述第一moscap的栅极与所述第二开关电路Switch2的栅极连接，所述第一moscap的源极与所述第一开关电路Switch1的漏极连接，所述第二moscap的栅极与所述第一开关电路Switch1的栅极连接，所述第二moscap源极与所述第二开关电路Switch2的漏极连接，所述第一moscap的源极与所述第一moscap的漏极连接，所述第二moscap的源极与所述第二moscap的漏极连接；或者
    所述第一moscap的栅极与所述第二开关电路Switch2的栅极连接，所述第一moscap的漏极与所述第一开关电路Switch1的漏极连接，所述第二moscap的栅极与所述第一开关电路Switch1的栅极连接，所述第二moscap的漏极与所述第二开关电路Switch2的漏极连接，所述第一moscap的源极与所述第一moscap的漏极连接，所述第二moscap的源极与所述第二moscap的漏极连接。
  8. 根据权利要求5至7中任一项所述的数模转换器，其中，
    所述第一开关电路Switch1、所述第二开关电路Switch2、所述第一moscap及所述第二moscap在同一衬底上。
  9. 根据权利要求5至7中任一项所述的数模转换器，其中，
    所述第一开关电路Switch1、所述第二开关电路Switch2、所述第一moscap及所述第二moscap的尺寸一致或不一致。
  10. 根据权利要求4所述的数模转换器，其中，
    所述第一电荷补偿器件为momcap1或mimcap1、所述第二电荷补偿器件为momcap2或mimcap2的情况下，所述momcap1或所述mimcap1的上极板与所述第一开关电路Switch1的漏极连接，所述momcap1或所述mimcap1的下极板与所述第二开关电路Switch2的栅极连接；所述momcap2或所述mimcap2的上极板与所述第二开关电路Switch2的漏极连接，所述momcap2或所述mimcap2的下极板与所述第一开关电路Switch1的栅极连接；或者
    所述momcap1或所述mimcap1的下极板与所述第一开关电路Switch1的漏极连接，所述momcap1或所述mimcap1的上极板与所述第二开关电路Switch2的栅极连接；所述momcap2或所述mimcap2的下极板与所述第二开关电路Switch2的漏极连接，所述momcap2或所述mimcap2的上极板与所述第一开关电路Switch1的栅极连接。
  11. 根据权利要求1至7、10中任一项所述的数模转换器，
    所述数模转换器核心电路包括多个数模转换器核心单元，其中，所述多个数模转换器核心单元的第一开关电路Switch1的漏极是连接在一起的，所述多个数模转换器核心单元的第二开关电路Switch2的漏极是连接在一起的。
  12. 根据权利要求1至7、10中任一项所述的数模转换器，
    所述第一开关电路Switch1、所述第二开关电路Switch2为PMOS管或NMOS管。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323158A (en) * 1993-04-06 1994-06-21 Analog Devices, Inc. Switched capacitor one-bit digital-to-analog converter
US20020140595A1 (en) * 2001-03-13 2002-10-03 Kabushiki Kaisha Toshiba Digital-analog converting circuit, display device, and digital-analog converting method
CN105187062A (zh) * 2015-09-07 2015-12-23 浪潮(北京)电子信息产业有限公司 一种数模转换器
CN114465621A (zh) * 2022-01-20 2022-05-10 复旦大学 一种具有差分电荷补偿功能的动态比较器
CN117674774A (zh) * 2022-08-26 2024-03-08 深圳市中兴微电子技术有限公司 一种差分锁存器电路、开关驱动器以及数模转换电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323158A (en) * 1993-04-06 1994-06-21 Analog Devices, Inc. Switched capacitor one-bit digital-to-analog converter
US20020140595A1 (en) * 2001-03-13 2002-10-03 Kabushiki Kaisha Toshiba Digital-analog converting circuit, display device, and digital-analog converting method
CN105187062A (zh) * 2015-09-07 2015-12-23 浪潮(北京)电子信息产业有限公司 一种数模转换器
CN114465621A (zh) * 2022-01-20 2022-05-10 复旦大学 一种具有差分电荷补偿功能的动态比较器
CN117674774A (zh) * 2022-08-26 2024-03-08 深圳市中兴微电子技术有限公司 一种差分锁存器电路、开关驱动器以及数模转换电路

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