WO2025200000A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置

Info

Publication number
WO2025200000A1
WO2025200000A1 PCT/CN2024/084985 CN2024084985W WO2025200000A1 WO 2025200000 A1 WO2025200000 A1 WO 2025200000A1 CN 2024084985 W CN2024084985 W CN 2024084985W WO 2025200000 A1 WO2025200000 A1 WO 2025200000A1
Authority
WO
WIPO (PCT)
Prior art keywords
peripheral control
line
control line
area
display substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/084985
Other languages
English (en)
French (fr)
Other versions
WO2025200000A9 (zh
Inventor
谢涛峰
于池
何帆
徐光华
魏玉龙
胡明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2024/084985 priority Critical patent/WO2025200000A1/zh
Priority to CN202480000666.9A priority patent/CN121058372A/zh
Publication of WO2025200000A1 publication Critical patent/WO2025200000A1/zh
Publication of WO2025200000A9 publication Critical patent/WO2025200000A9/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic light-emitting diodes
  • QLED quantum-dot light-emitting diodes
  • This embodiment provides a display substrate and a display device.
  • this embodiment provides a display substrate comprising: a display area and a frame area surrounding the display area.
  • the frame area comprises a first frame area and a second frame area that are interconnected, the first frame area including at least a bend area located on one side of the display area along a first direction.
  • the display substrate comprises: a substrate, a plurality of sub-pixels disposed on one side of the substrate and located in the display area, a plurality of gate drive circuits located in the second frame area, at least one first peripheral control line located in the first frame area, and a plurality of second peripheral control lines.
  • the plurality of gate drive circuits are electrically connected to the plurality of sub-pixels and configured to provide a plurality of pixel control signals to the plurality of sub-pixels.
  • At least one first peripheral control line is connected to the plurality of gate drive circuits.
  • a portion of the plurality of second peripheral control lines are connected to the plurality of gate drive circuits; the potential of the signal transmitted by each first peripheral control line is lower than the potential of the signal transmitted by each second peripheral control line.
  • at least one of the plurality of second peripheral control lines is located between the at least one first peripheral control line and a boundary of the display substrate.
  • the display substrate further includes: a plurality of peripheral data lines located in the first border area, the plurality of peripheral data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; in a second direction, the plurality of second peripheral control lines and the at least one first peripheral control line are located between the plurality of peripheral data lines and a boundary of the display substrate; the second direction intersects the first direction.
  • a minimum distance between the at least one first peripheral control line and a boundary of the display substrate is greater than or equal to 1250 micrometers.
  • the at least one first peripheral control line is configured to transmit a constant voltage signal, and a potential of the constant voltage signal is less than or equal to -6V.
  • At least one sub-pixel among the plurality of sub-pixels includes: a pixel circuit and a light-emitting element connected to the pixel circuit.
  • the pixel circuit includes at least: a driving transistor, a data writing transistor, and a compensation transistor; the gate of the data writing transistor is connected to the first scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor; the gate of the driving transistor is connected to the second electrode of the compensation transistor, the second electrode of the driving transistor is connected to the first electrode of the compensation transistor, and the gate of the compensation transistor is connected to the second scan line.
  • the plurality of gate driving circuits include: at least one first scanning driving circuit, and at least one second scanning driving circuit, the at least one first scanning driving circuit is configured to provide a first scanning signal to the first scanning line, and the at least one second scanning driving circuit is connected to the second scanning line.
  • the circuit is configured to provide a second scan signal to the second scan line.
  • the plurality of second peripheral control lines include at least a second start signal line and a second scan drive output line connected to the at least one second scan drive circuit; and the at least one first peripheral control line is located between the second start signal line and the second scan drive output line.
  • the pixel circuit further includes a first reset transistor, wherein a gate of the first reset transistor is connected to a first reset control line, a first electrode of the first reset transistor is configured to receive a first initial signal, and a second electrode of the first reset transistor is connected to a second electrode of the drive transistor.
  • a second peripheral control line of the plurality of second peripheral control lines that is closest to a boundary of the display substrate is configured to transmit the first initial signal.
  • a minimum distance between a second peripheral signal line among the plurality of second peripheral control lines closest to the boundary of the display substrate and the boundary of the display substrate is greater than or equal to 400 micrometers.
  • the first border region further includes: a first signal access region located on a side of the bending region away from the display region; the display substrate further includes: a plurality of first contact pads located in the first signal access region and arranged along a second direction; the second direction intersects the first direction; the plurality of first contact pads include: at least one first control contact pad connected to the at least one first peripheral control line, and a plurality of second control contact pads connected to the plurality of second peripheral control lines. In the second direction, at least one of the plurality of second control contact pads is located between the at least one first control contact pad and a boundary of the display substrate.
  • the at least one first peripheral control line is located between a first second peripheral control line and a second second peripheral control line.
  • the at least one first control contact pad is located between a second control contact pad connected to the first second peripheral control line and a second control contact pad connected to the second second peripheral control line.
  • the display substrate includes a plurality of first peripheral control lines, and the plurality of electrostatic discharge circuits are connected to one of the first peripheral control lines.
  • FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a schematic diagram illustrating the configuration of a gate drive circuit according to at least one embodiment of the present disclosure
  • FIG4A is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure
  • FIG4B is another partial cross-sectional schematic diagram of the display area of at least one embodiment of the present disclosure.
  • FIG5 is a schematic diagram of local wiring in a first border area according to at least one embodiment of the present disclosure
  • FIG6 is a partial schematic diagram of a first border area according to at least one embodiment of the present disclosure.
  • FIG7 is a partial enlarged schematic diagram of area S1 in FIG6 ;
  • FIG8 is another partial wiring diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG9 is another partial wiring diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG10 is another partial wiring diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG11 is another partial schematic diagram of the first border area according to at least one embodiment of the present disclosure.
  • FIG12 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • FIG13 is a partial enlarged schematic diagram of area S2 in FIG6 ;
  • FIG14 is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG13 ;
  • FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • connection can include “electrical connection”, and “electrical connection” can include the situation where constituent elements are connected together through an element with some electrical function.
  • elements with some electrical function There is no special restriction on “elements with some electrical function” as long as they can transmit electrical signals between connected constituent elements. Examples of “elements with some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to a device that includes at least three terminals: a gate (gate electrode), a drain, and a source.
  • a transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source.
  • the channel region refers to the region through which current primarily flows.
  • the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain.
  • the gate electrode can also be referred to as a control electrode.
  • parallel refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.
  • circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.
  • a extends along direction B means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions.
  • a extends along direction B means “the main portion of A extends along direction B.”
  • a and B are in the same layer
  • a and B are formed simultaneously through the same patterning process.
  • “Same layer” does not always mean that the thickness or height of the layer is the same in a cross-sectional view.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.
  • the lower bezel of the display substrate of flexible display products bends and narrows in the bending area. This bending area can cause reliability corrosion along the edge of the lower bezel, which can easily cause display problems.
  • This embodiment provides a display substrate, including: a display area and a frame area located around the display area, the frame area including: a first frame area and a second frame area connected to each other, the first frame area including at least: a bending area located on one side of the display area along a first direction.
  • the display substrate includes: a substrate, a plurality of sub-pixels, a plurality of gate drive circuits, At least one first peripheral control line and multiple second peripheral control lines. Multiple sub-pixels are arranged on one side of the substrate and located in the display area. Multiple gate drive circuits are located in the second frame area and electrically connected to the multiple sub-pixels, configured to provide multiple pixel control signals to the multiple sub-pixels.
  • At least one first peripheral control line is located in the first frame area and connected to the multiple gate drive circuits.
  • Multiple second peripheral control lines are located in the first frame area, and a portion of the multiple second peripheral control lines are connected to the multiple gate drive circuits; the potential of the signal transmitted by each first peripheral control line is lower than the potential of the signal transmitted by each second peripheral control line.
  • at least one of the multiple second peripheral control lines is located between the at least one first peripheral control line and the boundary of the display substrate.
  • the at least one second peripheral control line is located on the side of the at least one first peripheral control line closest to the boundary of the display substrate.
  • the at least one first peripheral control line is not the line closest to the boundary of the display substrate.
  • the display substrate provided in this embodiment increases the distance between the first peripheral control line and the boundary of the display substrate by arranging the first peripheral control line with a lower transmission potential on the side away from the boundary of the display substrate of at least one second peripheral control line with a higher transmission potential, which is beneficial to avoiding reliability corrosion of the first peripheral control line.
  • At least one first peripheral control line may be configured to transmit a constant voltage signal, and the potential of the constant voltage signal may be less than or equal to -6V. In some examples, the potential of the signal transmitted by at least one first peripheral control line may be less than or equal to -6V and greater than or equal to -12V. For example, the potential range of the signal transmitted by the first peripheral control line may be -7V to -8V.
  • the first peripheral control line of this example may be a trace that transmits the lowest potential in the first border area. This example prevents the first peripheral control line from being subjected to reliability corrosion by setting the first peripheral control line that transmits the lowest potential away from the boundary of the display substrate.
  • the first border region may further include: a first signal access region located on a side of the bending region away from the display region.
  • the display substrate may further include: a plurality of first contact pads located in the first signal access region and arranged along the second direction.
  • the plurality of first contact pads may include: at least one first control contact pad connected to the at least one first peripheral control line, and a plurality of second control contact pads connected to the plurality of second peripheral control lines.
  • at least one of the plurality of second control contact pads may be located between the at least one first control contact pad and a boundary of the display substrate.
  • at least one second control contact pad may be located between the at least one first control contact pad and a boundary of the display substrate.
  • the first frame region may further include: a first sub-region located on a side of the bending region close to the display region, the first sub-region being connected to the second frame region.
  • the plurality of electrostatic discharge circuits in the domain may be arranged adjacent to the plurality of gate drive circuits.
  • the plurality of electrostatic discharge circuits may be arranged in a plurality of rows along the first direction, and each row of electrostatic discharge circuits may include a plurality of electrostatic discharge circuits arranged along the second direction.
  • the at least one first peripheral signal line may be located between two adjacent rows of electrostatic discharge circuits. In this example, by arranging the first peripheral signal line between adjacent rows of electrostatic discharge circuits, the length of the first peripheral signal line may be reduced, which is beneficial to reducing the signal loading of the first peripheral signal line.
  • Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure.
  • the display substrate may include: a display area AA and a border area BB located around the display area AA.
  • the border area BB may include: a first border area B1 located on one side of the display area AA and a second border area B2 located on the other side of the display area AA.
  • the first border area B1 may be located on one side of the display area AA along the first direction D1.
  • the first border area B1 and the second border area B2 may be connected.
  • the first border area B1 may be the lower border area of the display substrate
  • the second border area B2 may include: a left border area B21, a right border area B22 and an upper border area B23 of the display substrate.
  • the display area AA may include: a display structure layer disposed on a substrate, or may include a display structure layer and a touch structure layer disposed sequentially on a substrate.
  • the display substrate may integrate a touch structure to form a touch structure on a thin film encapsulation (TFE).
  • Touch-on-TFE structures primarily include flexible multi-layer on-cell (FMLOC) structures and flexible single-layer on-cell (FSLOC) structures.
  • FMLOC structure operates based on the principle of mutual capacitance detection, generally using two layers of metal to form drive (Tx) electrodes and sense (Rx) electrodes.
  • the driver chip (IC) detects the mutual capacitance between the drive and sense electrodes to achieve touch control.
  • the FSLOC structure operates based on the principle of self-capacitance (or voltage) detection, generally using a single layer of metal to form touch electrodes.
  • the integrated circuit detects the self-capacitance (or voltage) of the touch electrodes to achieve touch control.
  • the display structure layer may include multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL.
  • the multiple gate lines GL may extend along the second direction D2 and be arranged along the first direction D1
  • the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2.
  • the first direction D1 and the second direction D2 may intersect; for example, the first direction D1 may be perpendicular to the second direction D2.
  • the orthographic projections of the multiple gate lines GL and the multiple data lines DL on the substrate may intersect to form multiple sub-pixel regions.
  • One sub-pixel PX may be disposed within one sub-pixel region.
  • the multiple data lines DL may be electrically connected to the multiple sub-pixels PX and may be configured to provide data signals to the multiple sub-pixels PX.
  • the multiple gate lines GL may be electrically connected to the multiple sub-pixels PX and may be configured to provide pixel control signals to the multiple sub-pixels PX.
  • the pixel control signals may include scan signals, or may include scan signals and light-emitting control signals, or may include scan signals, reset control signals, and light-emitting control signals.
  • a pixel unit in the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light).
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. sub-pixel, and two sub-pixels emitting green light.
  • Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure.
  • the pixel circuit of this example is illustrated using an 8T1C structure as an example.
  • the pixel circuit of this example may include eight pixel transistors (i.e., a first pixel transistor T1 to an eighth pixel transistor T8) and a storage capacitor Cst.
  • the first pixel transistor T1 may also be referred to as a first reset transistor
  • the second pixel transistor T2 may also be referred to as a compensation transistor
  • the third pixel transistor T3 may also be referred to as a drive transistor
  • the fourth pixel transistor T4 may also be referred to as a data write transistor
  • the fifth pixel transistor T5 may also be referred to as a first light-emitting control transistor
  • the sixth pixel transistor T6 may also be referred to as a second light-emitting control transistor
  • the seventh pixel transistor T7 may also be referred to as a second reset transistor
  • the eighth pixel transistor T8 may also be referred to as a third reset transistor.
  • the light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.
  • the first pixel transistor T1 and the third pixel transistor T3 to the eighth pixel transistor T8 may be first-type transistors, such as P-type transistors, and the second pixel transistor T2 may be a second-type transistor, such as N-type transistors.
  • this embodiment is not limited to this.
  • the plurality of pixel transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.
  • the first type of transistors in the pixel circuit (for example, including the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8) can be low-temperature polysilicon thin-film transistors
  • the second type of transistors in the pixel circuit (for example, including the second pixel transistor T2) can be oxide thin-film transistors.
  • the active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • oxide thin-film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current.
  • Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the pixel circuit can be connected to the first scan line GL1, the second scan line GL2,
  • the data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2 are electrically connected.
  • the first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit
  • the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS.
  • the first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit.
  • the second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit.
  • the data line DL can be configured to provide a data signal to the pixel circuit.
  • the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit.
  • the first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit.
  • the second reset control line can be configured to provide a second reset control signal RESET2 to the pixel circuit.
  • the gate of the third pixel transistor T3 is electrically connected to the first node N1, the first electrode of the third pixel transistor T3 is electrically connected to the second node N2, and the second electrode of the third pixel transistor T3 is electrically connected to the third node N3.
  • the gate of the fourth pixel transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth pixel transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth pixel transistor T4 is electrically connected to the second node N2.
  • the gate of the second pixel transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second pixel transistor T2 is electrically connected to the third node N3, and the second electrode of the second pixel transistor T2 is electrically connected to the first node N1.
  • the gate of the fifth pixel transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth pixel transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth pixel transistor T5 is electrically connected to the second node N2.
  • the gate of the sixth pixel transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth pixel transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth pixel transistor T6 is electrically connected to the fourth node N4.
  • the gate of the first pixel transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first pixel transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first pixel transistor T1 is electrically connected to the third node N3.
  • the first pixel transistor T1 can be configured to reset the third node N3.
  • the gate of the seventh pixel transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh pixel transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh pixel transistor T7 is electrically connected to the fourth node N4.
  • the seventh pixel transistor T7 can be configured to reset the fourth node N4.
  • the gate of the eighth pixel transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth pixel transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth pixel transistor T8 is electrically connected to the second node N2.
  • the eighth pixel transistor T8 can be configured to reset the second node N2.
  • the first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.
  • the first node N1 is the connection point of the storage capacitor Cst
  • the second pixel transistor T2 and the third pixel transistor T3 the second node N2 is the connection point of the fifth pixel transistor T5, the fourth pixel transistor T4, the eighth pixel transistor T8 and the third pixel transistor T3,
  • the third node N3 is the connection point of the first pixel transistor T1, the third pixel transistor T3, the second pixel transistor T2 and the sixth pixel transistor T6, and the fourth node N4 is the connection point of the sixth pixel transistor T6, the seventh pixel transistor T7 and the light-emitting element EL.
  • the operation process of the pixel circuit shown in Figure 2 is described below.
  • the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 are P-type transistors, and the second pixel transistor T2 is an N-type transistor.
  • the operation process of the pixel circuit may include at least: a first stage, a second stage, a third stage, and a fourth stage.
  • the first stage is called the first reset stage.
  • the second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, which turns on the seventh pixel transistor T7 and the eighth pixel transistor T8;
  • the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, which turns on the second pixel transistor T2.
  • the eighth pixel transistor T8 is turned on, so that the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2.
  • the seventh pixel transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth pixel transistor T8. Node N4 is initialized.
  • the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal
  • the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth pixel transistor T4, the first pixel transistor T1, the fifth pixel transistor T5, and the sixth pixel transistor T6.
  • the light-emitting element EL does not emit light.
  • the second stage is called the second reset stage.
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first pixel transistor T1;
  • the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor T2.
  • the first pixel transistor T1 and the second pixel transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1.
  • the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal
  • the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal
  • the light control signal EM provided by the light control line EML is a high-level signal, turning off the seventh pixel transistor T7, the eighth pixel transistor T8, the fourth pixel transistor T4, the fifth pixel transistor T5, and the sixth pixel transistor T6.
  • the light-emitting element EL does not emit light.
  • the third stage is called the data writing stage or the threshold compensation stage.
  • the first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth pixel transistor T4 is turned on.
  • the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor T2 is turned on.
  • the first electrode of the storage capacitor Cst is at a low level, and the third pixel transistor T3 is turned on.
  • the second pixel transistor T2, the fourth pixel transistor T4, and the third pixel transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third pixel transistor T3, the third node N3, and the turned-on second pixel transistor T2.
  • the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third pixel transistor T3 is charged into the storage capacitor Cst.
  • the voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-
  • the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal
  • the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal
  • the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the first pixel transistor T1, the seventh pixel transistor T7, the eighth pixel transistor T8, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected.
  • the first group of gate driving circuits may include: the first scan driving circuit 21a, the second scan driving circuit 22a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light-emitting driving circuit 25a; and the second group of gate driving circuits may include: the first scan driving circuit 21b, the second scan driving circuit 22b, the first reset driving circuit 23b, the second reset driving circuit 24b, and the light-emitting driving circuit 25b.
  • the second scan drive circuits 22a and 22b may each include a plurality of cascaded second scan drive units (e.g., including GN(1) to GN(4)). Each level of the second scan drive unit may be configured to provide a second scan signal to a row of pixel circuits in the display area AA.
  • the first level second scan drive unit GN(1) may be configured to provide a second scan signal to the first row of pixel circuits in the display area AA.
  • this embodiment is not limited to this.
  • each level of the second scan drive unit may be configured to provide a second scan signal to two adjacent rows of pixel circuits in the display area. Second scanning signal.
  • the light-emitting driving circuits 25a and 25b may each include a plurality of cascaded light-emitting driving units (e.g., including EM(1) to EM(4)). Each level of light-emitting driving units may be configured to provide a light-emitting control signal to a row of pixel circuits in the display area AA.
  • the first level of light-emitting driving unit EM(1) may be configured to provide a light-emitting control signal to the first row of pixel circuits in the display area AA.
  • this embodiment is not limited to this.
  • each level of light-emitting driving units may be configured to provide a light-emitting control signal to two adjacent rows of pixel circuits in the display area.
  • the first reset driving circuits 23a and 23b can each include a plurality of cascaded first reset driving units (e.g., including RP(1) to RP(4)). Each level of the first reset driving unit can be configured to provide a first reset control signal to a row of pixel circuits in the display area AA.
  • the first level of the first reset driving unit RP(1) can be configured to provide a first reset control signal to the first row of pixel circuits in the display area AA.
  • this embodiment is not limited to this.
  • each level of the first reset driving unit can be configured to provide a first reset control signal to two adjacent rows of pixel circuits in the display area.
  • the second reset driving circuits 24a and 24b can each include a plurality of cascaded second reset driving units (e.g., including RH(1) to RH(4)).
  • Each level of the second reset driving unit can be configured to provide a second reset control signal to a row of pixel circuits in the display area AA.
  • the first level of the second reset driving unit RH(1) can be configured to provide a second reset control signal to the first row of pixel circuits in the display area AA.
  • this embodiment is not limited to this.
  • each level of the second reset driving unit can be configured to provide a second reset control signal to two adjacent rows of pixel circuits in the display area.
  • FIG4A is a schematic partial cross-sectional view of a display region according to at least one embodiment of the present disclosure.
  • FIG4A illustrates the structure of a sub-pixel in the display region as an example.
  • the pixel circuit shown in FIG2 includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.
  • the display area of the display substrate may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on substrate 10.
  • Circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor.
  • Light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.
  • the display substrate may further include a touch structure layer located on the side of the encapsulation structure layer away from the substrate.
  • FIG4A illustrates an example of each sub-pixel including a first-type transistor 21, a second-type transistor 22, and a capacitor 23.
  • the first-type transistor 21 may be a low-temperature polysilicon thin-film transistor
  • the second-type transistor 22 may be an oxide thin-film transistor.
  • a first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, and a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source/drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarizing layer) may be disposed between the first source/drain metal layer and the second source/drain metal layer; the seventh insulating layer 107 may be located on a side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (also referred to as a second planarizing layer) may be
  • the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 may be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers.
  • this embodiment is not limited to this.
  • the first semiconductor layer is close to A buffer layer may also be provided on one side of the substrate, which may prevent harmful substances in the substrate from invading the interior of the display panel and may also increase the adhesion of the film layer in the display panel to the substrate.
  • the first semiconductor layer in the display area may include at least a first active layer 210 of the first-type transistor 21.
  • the first active layer 210 of the first-type transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102.
  • the first gate metal layer may include at least a first gate 213 of the first-type transistor 21 and a first plate 231 of the capacitor 23.
  • the orthographic projection of the first gate 213 of the first-type transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10.
  • the second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate 224 of the second-type transistor 22.
  • the orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap.
  • the second semiconductor layer may include at least a second active layer 220 of the second-type transistor 22.
  • the third gate metal layer may include at least a second gate 223 of the second-type transistor 22.
  • the orthographic projection of the second gate 223 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10.
  • the orthographic projection of the third gate 224 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10.
  • the third gate 224 may be the bottom gate of the second-type transistor 22, and the second gate 223 may be the top gate of the second-type transistor 22.
  • the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first-type transistor 21, and a second source 221 and a second drain 222 of the second-type transistor 22.
  • the fifth insulating layer 105 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area.
  • the fifth insulating layer 105, fourth insulating layer 104, and third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220.
  • the first source 211 of the first-type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via.
  • the second source 221 of the second-type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second-type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via.
  • the second source-drain metal layer can include at least a first connecting electrode 241.
  • the first connecting electrode 241 can be electrically connected to the first drain 212 of the first-type transistor 21 of the pixel circuit through a fifth pixel via defined between the sixth and seventh insulating layers 106 and 107.
  • the first switching electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.
  • the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer, the data lines of the display area may be located in the second source/drain metal layer, and the first power lines of the display area may be located in the second source/drain metal layer. This embodiment is not limited to this.
  • the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements.
  • each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132, and a second electrode 133.
  • the first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the eighth insulating layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via hole provided in the eighth insulating layer 108.
  • Pixel Definition The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108.
  • the pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131.
  • the second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first and second electrodes 131, 133, the organic light-emitting layer 132 may emit light of a corresponding color.
  • the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • HBL hole blocking layer
  • EBL electron blocking layer
  • EIL electron injection layer
  • ETL electron transport layer
  • the light-emitting layers of light-emitting elements of different colors may be different.
  • a red light-emitting element includes a red light-emitting layer
  • a green light-emitting element includes a green light-emitting layer
  • a blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be produced by a single process (a single evaporation process or a single inkjet printing process), and isolation can be achieved by means of a surface step difference of the formed film layer or by surface treatment.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated.
  • the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.
  • FMM fine metal mask
  • Open Mask open mask
  • the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143.
  • the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like.
  • the second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141, 143 to prevent external moisture from entering the light-emitting element.
  • the second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display panel and relieve stress on the first and third encapsulation layers 141, 143. It may also include a desiccant or other absorbent material to absorb intrusive moisture, oxygen, and other substances. However, this embodiment is not limited to this.
  • the encapsulation structure layer may have a five-layer stacked structure: inorganic/organic/inorganic/organic/inorganic.
  • Figure 4B is another partial cross-sectional schematic diagram of the display region of at least one embodiment of the present disclosure.
  • the multiple pixel transistors in the pixel circuit can be of the same transistor type, for example, all low-temperature polysilicon thin-film transistors.
  • Figure 4B illustrates an example of a first-type transistor 21 and a capacitor 23 included in each sub-pixel.
  • the seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers.
  • the remaining structure of the display area of the display substrate of this example can be referred to the description of the embodiment shown in FIG4A , and will not be repeated here.
  • FIG5 is a schematic diagram of a partial wiring diagram of the first frame area of at least one embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a partial wiring diagram of the first frame area
  • the area of the boundary XL near the left side of the display substrate is used as an example.
  • the first border area B1 may include: a first sub-area B01, a bending area B02, and a second sub-area B03 arranged in sequence along a side away from the display area AA in the first direction D1.
  • the first sub-area B01 can also be called a first fan-out area.
  • the first sub-area B01 can be connected to the left border area B21 and the right border area B22 of the second border area B2, and connected to the display area AA.
  • the bending area B02 can be connected between the first sub-area B01 and the second sub-area B03.
  • the second sub-area B03 may include at least: a first signal access area B034 and a second signal access area B035.
  • the first signal access area B034 can be located on the side of the second signal access area B035 away from the bending area B02.
  • the bending region B02 can be configured to bend the second sub-region B03 toward the back of the display area AA.
  • Multiple bending connection lines extending along the first direction D1 can be provided within the bending region B02 to electrically connect the traces transmitting the same signal within the first sub-region B01 and the second sub-region B03.
  • the multiple bending connection lines within the bending region B02 can be co-layered, for example, located in the second source/drain metal layer. However, this embodiment is not limited to this. In other examples, the multiple bending connections within the bending region can be located in the first source/drain metal layer.
  • the first signal access area B034 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to be bound and connected to an external flexible printed circuit (FPC).
  • the second signal access area B035 may be provided with a plurality of second contact pads, and the plurality of second contact pads may be configured to connect to a driver integrated circuit (IC). At least one first contact pad within the first signal access area B034 and at least one second contact pad within the second signal access area B035 may be connected by wiring.
  • a plurality of peripheral control lines may be provided in the first border area B1.
  • Each peripheral control line may include: a first routing segment located in the first sub-area B01, a control bending line located in the bending area B02, and a second routing segment located in the second sub-area B03; wherein the control bending line may connect the first routing segment and the second routing segment.
  • the first routing segment may extend at least along the first direction D1 and extend toward the second border area B2 along the edge shape of the display area AA.
  • the control bending line and the second routing segment may extend along the first direction D1.
  • FIG5 is illustrated by taking three peripheral control lines as an example.
  • the multiple peripheral control lines of the first border area B1 may include: a first peripheral control line L1, and multiple second peripheral control lines (for example, including a first second peripheral control line L2 and a second second peripheral control line L3).
  • the first peripheral control line L1 can be configured to transmit a constant voltage signal.
  • the potential of the signal transmitted by the first peripheral control line L1 can be lower than the potential of the signal transmitted by each second peripheral control line.
  • the potential of the signal transmitted by the first peripheral control line L1 can be the lowest potential of the signals transmitted by the multiple peripheral control lines.
  • the potential of the signal transmitted by the first peripheral control line L1 can be less than or equal to -6V.
  • the first second peripheral control line L2 and the second peripheral control line L3 can be peripheral control lines adjacent to the first peripheral control line L1.
  • the first peripheral control line L1 may include a first routing segment 41-1 located in the first sub-region B01, a control bending line 42-1 located in the bending region B02, and a second routing segment 43-1 located in the second sub-region B03.
  • the control bending line 42-1 may connect the first routing segment 41-1 and the second routing segment 43-1.
  • the control bending line 42-1 and the second routing segment 43-1 may extend along a first direction D1.
  • the second routing segment 43-1 may connect to a third routing segment 44-1 that extends approximately along the second direction D2, and the third routing segment 44-1 may connect to a fourth routing segment 45-1 that extends approximately along the first direction D1.
  • the second routing segment 43-1 and the third routing segment 44-1 can be interconnected and integrally formed, for example, located in the first gate metal layer or the second gate metal layer.
  • the fourth routing segment 45-1 and the third routing segment 44-1 can be located in different conductive layers, for example, the fourth routing segment 45-1 can be located in the first source/drain metal layer.
  • this embodiment is not limited to this.
  • the second routing segment 43-1 and the third routing segment 44-1 can be located in different conductive layers.
  • the second routing segment 43-2 and the third routing segment 44-2 can be an interconnected integral structure, for example, they can be located in the first gate metal layer or the second gate metal layer; the fourth routing segment 45-2 and the third routing segment 44-2 can be located in different conductive layers, for example, the fourth routing segment 45-2 can be located in the first source and drain metal layer.
  • this embodiment is not limited to this.
  • the second routing segment 43-2 and the third routing segment 44-2 can be located in different conductive layers.
  • the second routing segment 43-3 and the third routing segment 44-3 can be interconnected and integrally formed, for example, located in the first gate metal layer or the second gate metal layer.
  • the fourth routing segment 45-3 and the third routing segment 44-3 can be located in different conductive layers, for example, the fourth routing segment 45-3 can be located in the first source/drain metal layer.
  • this embodiment is not limited to this.
  • the second routing segment 43-3 and the third routing segment 44-3 can be located in different conductive layers.
  • first routing segment 41-1 of the first peripheral control line L1, the first routing segment 41-2 of the first second peripheral control line L2, and the first routing segment 41-3 of the second second peripheral control line L3 can be a same-layer structure, for example, they can all be located in the first gate metal layer, or in the second gate metal layer, or can be a double-layer routing structure located in the first gate metal layer and the second gate metal layer.
  • the second routing segment 43-1 of the first peripheral control line L1, the second routing segment 43-2 of the first second peripheral control line L2, and the second routing segment 43-3 of the second second peripheral control line L3 can be a same-layer structure, for example, they can all be located in the first gate metal layer or the second gate metal layer.
  • third routing segments 44-1, 44-2, and 44-3 may be co-layered, for example, located in the first gate metal layer or the second gate metal layer.
  • Fourth routing segments 45-1, 45-2, and 45-3 may be co-layered, for example, located in the first source/drain metal layer.
  • the first peripheral control line L1 may be located between the first second peripheral control line L2 and the second second peripheral control line L3, the first second peripheral control line L2 may be located on a side of the first peripheral control line L1 that is closer to the boundary XL of the display substrate, and the second second peripheral control line L3 may be located on a side of the first peripheral control line L1 that is farther from the boundary XL of the display substrate.
  • the plurality of first contact pads of the first signal access area B034 may include: a plurality of control contact pads (e.g., a first control contact pad 511, a second control contact pad 512, and a second control contact pad 513) arranged along the second direction D2.
  • the first control contact pad 511, the second control contact pad 512, and the second control contact pad 513 may be arranged sequentially along the second direction D2.
  • the first control contact pad 511 may be located on a side of the second control contact pad 512 that is close to the boundary XL of the display substrate.
  • the first control contact pad 511 may be the contact pad closest to the boundary XL of the display substrate among the plurality of first contact pads.
  • the second routing segment 43-1 of the first peripheral control line L1 can be connected to the first control contact pad 511 through the third routing segment 44-1 and the fourth routing segment 45-1.
  • the second routing segment 43-2 of the first second peripheral control line L2 can be connected to the second control contact pad 512 through the third routing segment 44-2 and the fourth routing segment 45-2.
  • the third routing segment 44-2 can also extend to the second signal access area B035 and connect to the second contact pad in the second signal access area B035.
  • the second routing segment 43-3 of the second second peripheral control line L3 can be connected to the second control contact pad 512 through the third routing segment 44-3 and the fourth routing segment 45-2.
  • the fourth routing segment 45-3 is connected to the second control contact pad 513, and the third routing segment 44-3 can also extend to the second signal access area B035 and connect to the second contact pad within the second signal access area B035.
  • this embodiment is not limited to this.
  • the second peripheral control line adjacent to the first peripheral control line can be connected only to the first contact pad within the first signal access area.
  • the material of multiple peripheral control lines includes metal aluminum (Al)
  • the metal Al reacts with H + to form Al3 +
  • Al3 + reacts with F- / S2- to form a compound, which can easily cause edge line corrosion.
  • the OH- concentration in the environment is high, and the metal Al reacts with OH- to form AlO2- , but cannot form a compound, which can effectively prevent line corrosion.
  • the distance between the first peripheral control line and the edge of the display substrate can be increased, thereby preventing the first peripheral control line from experiencing reliability corrosion.
  • Figure 6 is a partial schematic diagram of the first border area of at least one embodiment of the present disclosure.
  • the second sub-area B03 may include: a second fan-out area B031, a circuit setting area B032, a third fan-out area B033, a second signal access area B035, and a first signal access area B034 arranged in sequence along the first direction D1 away from the bending area B02.
  • this embodiment is not limited to this.
  • the second sub-area of the first border area may include: a second fan-out area, a first signal access area, and a second signal access area arranged in sequence along the side away from the bending area in the first direction.
  • the circuit arrangement area B032 may be provided with at least a plurality of test circuits arranged along the second direction D2.
  • a plurality of anti-static circuits may be provided on a side of the plurality of test circuits close to the bending area B02, and a plurality of data selection circuits may be provided on a side of the plurality of test circuits away from the bending area B02.
  • this embodiment is not limited to this.
  • the multiple bending connection lines in the bending area B02 may include: multiple data bending lines (for example, including a first group of data bending lines 312a, a second group of data bending lines 312b, a third group of data bending lines 312c and a fourth group of data bending lines 312d), multiple first power bending lines (for example, including a first group of first power bending lines 321a, a second group of first power bending lines 321b, a third group of first power bending lines 321c), multiple second power bending lines (for example, including a first group of second power bending lines 331a, a second group of second power bending lines 331b, a third group of second power bending lines 331c and a fourth group of second power bending lines 331d), multiple control bending lines (for example, including a first group of control bending lines 42a and a second group of control bending lines 42b), and multiple touch bending lines (for example, including a first group of touch bending
  • the plurality of data meandering lines can be configured to transmit data signals.
  • the plurality of first power meandering lines can be configured to transmit a first voltage signal VDD, and the plurality of second power meandering lines can be configured to transmit a second voltage signal VSS.
  • FIG6 illustrates an overall diagram of each group of meandering connection lines within the bend region B02.
  • the first border area B1 may be provided with a plurality of peripheral data lines.
  • the plurality of peripheral data lines may include: a plurality of first data fan-out lines (for example, a first group of first data fan-out lines 311a and a second group of first data fan-out lines 311b) located in the first sub-area B01, a plurality of second data fan-out lines (for example, a first group of second data fan-out lines 313a and a second group of second data fan-out lines 313b) located in the second fan-out area B031, and a plurality of peripheral data fan-out lines (for example, a first group of second data fan-out lines 313a and a second group of second data fan-out lines 313b) located in the bending area.
  • multiple first data fan-out lines can be connected to multiple data lines in display area AA, for example, in a one-to-one correspondence.
  • a first group of first data fan-out lines 311a can be connected to a first group of second data fan-out lines 313a via a first group of data bending lines 312a and a second group of data bending lines 312b
  • a second group of first data fan-out lines 311b can be connected to a second group of second data fan-out lines 313b via a third group of data bending lines 312c and a fourth group of data bending lines 312d.
  • multiple first data fan-out lines can be connected to multiple data bending lines in a one-to-one correspondence
  • multiple data bending lines can be connected to multiple second data fan-out lines in a one-to-one correspondence
  • a first group of second data fan-out lines 313a can be connected to a first group of third data fan-out lines 314a
  • a second group of second data fan-out lines 313b can be connected to a second group of third data fan-out lines 314b.
  • a single third data fan-out line can be connected to multiple second data fan-out lines. This embodiment is not limited to this.
  • the plurality of second contact pads of the second signal access region B035 may include a plurality of data contact pads 315.
  • the plurality of third data fan-out lines may be electrically connected to the plurality of data contact pads 315 in the second signal access region B035.
  • the first border area B1 may be provided with a plurality of peripheral control lines extending at least along the first direction D1.
  • the plurality of peripheral control lines may include a first group of peripheral control lines and a second group of peripheral control lines, and the first group of peripheral control lines and the second group of peripheral control lines may be located on both sides of the plurality of peripheral data lines along the second direction D2.
  • the plurality of peripheral data lines may be located in the middle of the plurality of peripheral control lines in the second direction D2.
  • Each peripheral control line may include: a first routing segment located in the first sub-area B01, a control bending line located in the bending area B02, and a second routing segment located in the second sub-area B03.
  • the multiple first routing segments of the first sub-area B01 may include: a first group of first routing segments 41a and a second group of first routing segments 41b.
  • Figure 6 is illustrated by taking the multiple first routing segments of the first sub-area B01 as an example. This embodiment does not limit the number of first routing segments.
  • the first group of first routing segments 41a and the second group of first routing segments 41b can be located on both sides of the multiple first data fan-out lines in the second direction D2.
  • the plurality of second routing segments of the second sub-area B03 may include: a first group of second routing segments 43a and a second group of second routing segments 43b.
  • FIG6 is illustrated by taking the plurality of second routing segments of the second sub-area B03 as an example. This embodiment does not limit the number of second routing segments.
  • the first group of second routing segments 43a and the second group of second routing segments 43b may be located on both sides of the plurality of second data fan-out lines and the plurality of third data fan-out lines in the second direction D2.
  • the first group of first routing segments 41a in the first sub-area B01 can be connected to the first group of second routing segments 43a in the second sub-area B03 through the first group of control bending lines 42a in the bending area B02; the second group of first routing segments 41b in the first sub-area B01 can be connected to the second group of second routing segments 43b in the second sub-area B03 through the second group of control bending lines 42b in the bending area B02.
  • the second sub-area B03 may further be provided with a plurality of third routing segments (e.g., including a first group of third routing segments 44a and a second group of third routing segments 44b) and a plurality of fourth routing segments (e.g., including a first group of fourth routing segments 45a and a second group of fourth routing segments 45b).
  • the second routing segments of a portion of the plurality of peripheral control lines may be connected to the first contact pad in the second signal access area B035 via the third routing segments extending along the second direction D2, and may also be connected to the first contact pad in the first signal access area B034 via the third routing segments extending along the second direction D2 and the fourth routing segments extending along the first direction D1.
  • the second routing segments of another portion of the plurality of peripheral control lines may not be connected to the second contact pad in the second signal access area B035, but may be connected to the first contact pad in the first signal access area B034 via the third routing segments extending along the second direction D2 and the fourth routing segments extending along the first direction D1.
  • at least one peripheral control line in the other part of the peripheral control lines may also be connected to the test circuit located in the circuit arrangement area through a third routing segment extending along the second direction D2.
  • the arrangement of the plurality of gate drive circuits located in the second border area B2 can be as shown in Figure 3, and the number and arrangement of the first group of gate drive circuits in the left border area B21 and the second group of gate drive circuits in the right border area B22 are the same.
  • a portion of the peripheral control lines in the first group of peripheral control lines can be connected to the first group of gate drive circuits, and a portion of the peripheral control lines in the second group of peripheral control lines can be connected to the second group of gate drive circuits.
  • the number and type of the first group of peripheral control lines and the second group of peripheral control lines located on both sides of the plurality of peripheral data lines can be the same.
  • the first group of peripheral control lines and the second group of peripheral control lines can be arranged roughly symmetrically about the center line of the first border area B1 parallel to the first direction D1.
  • this embodiment is not limited to this.
  • the number or type of gate drive circuits in the first group of gate drive circuits and the second group of gate drive circuits are different, the number or type of routing of the first group of peripheral control lines and the second group of peripheral control lines can be different.
  • Figure 7 is a partially enlarged schematic diagram of area S1 in Figure 6.
  • Figure 7 uses the first set of peripheral control lines as an example for explanation.
  • the description of the second set of peripheral control lines can refer to the description of the first set of peripheral control lines, so it is not repeated here.
  • the first group of peripheral control lines may include: a first initial control line VI1, a second initial control line VI2, a third initial control line VI3, a fifth voltage control line VGH-N, a fourth voltage control line VGH, a light-emitting drive output line Eout, a fifth start signal line ESTV, a thirteenth clock signal line ECB, a twelfth clock signal line ECK, a fourteenth clock signal line ECX, a tenth clock signal line HCB, a ninth clock signal line HCK, a fourth start signal line HSTV, a second reset drive output line Hout, a first reset drive output line Pout, and a third start signal line PS TV, seventh clock signal line PCB, sixth clock signal line PCK, eighth clock signal line PCX, fourth clock signal line NCB, third clock signal line NCK, second start signal line NSTV, first voltage control line VGL1, second voltage control line VGL2, third voltage control line VGL3, second scan drive output line Nout
  • the light-emitting drive output line Eout, the second reset drive output line Hout, the first reset drive output line Pout, the second scan drive output line Nout, the first scan drive output line Gout, the first panel detection line PCD1, and the second panel detection line PCD2 can be single-layer routing located in the first gate metal layer.
  • the first start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, and the first scan driver output line Gout can be electrically connected to the first scan driver circuit 21a located in the left border area B21.
  • the first start signal line GSTV can be configured to provide a start signal to the first scan driver circuit 21a
  • the first clock signal line GCK and the second clock signal line GCB can be configured to provide a clock signal to the first scan driver circuit 21a
  • the first scan driver output line Gout can be configured to be connected to the output end of the last stage first scan driver unit of the first scan driver circuit 21a.
  • the second start signal line NSTV, the third clock signal line NCK, the fourth clock signal line NCB, the fifth clock signal line NCX, and the second scan drive output line Nout can be electrically connected to the second scan drive circuit 22a in the left border area B21.
  • the second start signal line NSTV can be configured to provide a start signal to the second scan drive circuit 22a
  • the third clock signal line NCK, the fourth clock signal line NCB, and the fifth clock signal line NCK can be configured to provide a clock signal to the second scan drive circuit 22a
  • the second scan drive output line Nout can be configured to be connected to the output end of the second scan drive unit of the last stage of the second scan drive circuit 22a.
  • the fifth start signal line ESTV, the twelfth clock signal ECK, the thirteenth clock signal ECB, the fourteenth clock signal ECX, and the light-emitting drive output line Eout can be electrically connected to the light-emitting drive circuit 25a in the left border area B21.
  • the fifth start signal line ESTV can be configured to provide a start signal to the light-emitting drive circuit 25a
  • the twelfth clock signal ECK, the thirteenth clock signal ECB, and the fourteenth clock signal ECX can be configured to provide a clock signal to the light-emitting drive circuit 25a
  • the light-emitting drive output line Eout can be configured to be connected to the output end of the last stage light-emitting drive unit of the light-emitting drive circuit 25a.
  • the fifth voltage control line VGH-N can be electrically connected to the second scan driver circuit 22a in the left frame area B21 and configured to provide a seventh voltage signal to the second scan driver circuit 22a.
  • the fourth voltage control line VGH can be electrically connected to the first scan driver circuit 21a, the first reset driver circuit 23a, the second reset driver circuit 24a, and the light-emitting driver circuit 25a in the left frame area B21 and configured to provide a sixth voltage signal.
  • the fifth and sixth voltage signals can be constant voltage signals, and the sixth voltage signal can be different from the fifth voltage signal.
  • the first voltage control line VGL1 can be electrically connected to the first scan driving circuit 21a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light-emitting driving circuit 25a in the left frame area B21, and configured to provide a third voltage signal.
  • the second voltage control line VGL2 can be electrically connected to the second scan driving circuit 22a in the left frame area B21, and configured to provide a fourth voltage signal.
  • the third voltage control line VGL3 can be electrically connected to the second scan driving circuit 22a in the left frame area B21, and configured to provide a fifth voltage signal.
  • the potential range of the third voltage signal and the fifth voltage signal can both be between -6V and -10V, and the potential range of the fourth voltage signal can be between -6V and -12V. This example can help ensure the performance of the second scan driver circuit by providing two low-potential constant voltage signals to the second scan driver circuit.
  • the first initial control line VI1 can be configured to provide a first initial signal
  • the second initial control line VI2 can be configured to provide a second initial signal
  • the third initial control line VI3 can be configured to provide a third initial signal.
  • the first initial control line VI1 can be connected to the first initial signal line of the display area and configured to provide the first initial signal to the first reset transistor of the pixel circuit.
  • the second initial control line VI2 can be connected to the second initial signal line of the display area and configured to provide the second initial signal to the second reset transistor of the pixel circuit.
  • the third initial control line VI3 can be connected to the third initial signal line of the display area and configured to provide the third initial signal to the third reset transistor of the pixel circuit.
  • the first panel inspection line PCD1 and the second panel inspection line PCD2 may be configured to transmit a signal for detecting whether a crack exists on a periphery of the display substrate.
  • the first initial control line VI1, the second initial control line VI2, the third initial control line VI3, the first panel detection line PCD1, and the second panel detection line PCD2 in the first group of peripheral control lines are not directly electrically connected to the multiple gate drive circuits, and the remaining lines are electrically connected to the multiple gate drive circuits.
  • first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 may be located between the remaining second peripheral control lines, for example, between the first scan drive output line Gout and the first panel detection line PCD1, or between the first reset drive output line Pout and the second reset drive output line Hout.
  • first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 may be located on a side of the plurality of second peripheral control lines close to the peripheral data lines, for example, on a side of the second panel detection line PCD2 away from the first panel detection line PCD1.
  • the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 are sequentially arranged in a direction away from the boundary of the display substrate.
  • the minimum distance between the boundaries of the display substrate and the first voltage control line VGL1 may be the minimum distance between the first voltage control line VGL1 and the boundary of the display substrate.
  • the minimum distance W2 between the first voltage control line VGL1 and the boundary of the display substrate may be the distance between the edge of the first voltage control line VGL1 closest to the boundary of the display substrate and the boundary of the display substrate.
  • W2 may be greater than or equal to 1250 microns, for example, approximately 2067 microns.
  • the line closest to the boundary of the display substrate in the first group of peripheral control lines is the first initial control line VI1.
  • the minimum distance W1 between the first initial control line VI1 and the boundary of the display substrate may be the distance between an edge of the first initial control line VI1 close to the boundary of the display substrate and the boundary of the display substrate.
  • W1 may be greater than or equal to 400 microns, for example, approximately 535 microns.
  • the potential of the signal transmitted by the first initial control line VI1 is higher than the potential of the signals transmitted by the first voltage control line VGL1, the second voltage control line VGL2 and the third voltage control line VGL3.
  • the potential range of the signal transmitted by the first initial control line VI1 can be -3V to -4V.
  • At least two of the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 can be interposed between different second peripheral traces.
  • the second voltage control line VGL2 and the third voltage control line VGL3 can be located between the second start signal line NSTV and the second scan drive output line Nout
  • the first voltage control line VGL1 can be located between the first reset drive output line Pout and the second reset drive output line Hout. This embodiment is not limited to this. It is sufficient to ensure that the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 are not located closest to the edge of the display substrate.
  • FIG8 is another partial routing diagram of the first border region of at least one embodiment of the present disclosure.
  • FIG8 is illustrated using the region of the first border region near the boundary XL on the left side of the display substrate as an example.
  • the first peripheral control line L1 is connected to the first control contact pad 511
  • the first second peripheral control line L2 is connected to the second control contact pad 512
  • the second second peripheral control line L3 is connected to the second control contact pad 513.
  • the first control contact pad 511 can be located between the second control contact pads 512 and 513.
  • This example facilitates the arrangement of the first and second peripheral control lines by placing the first control contact pads connected to the first peripheral control lines between the second control contact pads connected to the adjacent second peripheral control lines.
  • the remaining description of this example can be found in the description of the embodiment shown in FIG5 , and will not be repeated here.
  • FIG9 is another partial routing diagram of the first border region of at least one embodiment of the present disclosure.
  • FIG9 is illustrated using the region of the first border region near the boundary XL on the left side of the display substrate as an example.
  • the first peripheral control line L1 is connected to the first control contact pad 511
  • the first second peripheral control line L2 is connected to the second control contact pad 512
  • the second second peripheral control line L3 is connected to the second control contact pad 513.
  • the first control contact pad 511 can be located on the side of the second control contact pad 513 away from the boundary of the display substrate.
  • this example by disposing the first control contact pad connected to the first peripheral control line on a side away from the boundary of the display substrate where the second control contact pad connected to the adjacent second peripheral control line is located, this helps ensure signal transmission of the first peripheral control line and prevents interference between the signal transmitted by the adjacent second peripheral control line and the signal transmitted by the first peripheral control line.
  • the remaining description of this example can be found in the description of the embodiment shown in FIG5 , and will not be repeated here.
  • Figure 10 is another partial routing diagram of the first border area of at least one embodiment of the present disclosure.
  • Figure 10 is illustrated by taking the area of the first border area close to the boundary XL on the left side of the display substrate as an example.
  • the third routing segment 44-3 connected to the first peripheral control line L1 can be located on the side of the third routing segment 44-3 connected to the second second peripheral control line L3 close to the bending area B02.
  • the third routing segments 44-1, 44-3, and 44-2 can be arranged in a direction away from the bending area B02.
  • This example facilitates the connection between the first peripheral control line and the first control contact pad by adjusting the routing arrangement within the second sub-area, thereby avoiding interference between the signal transmitted by the second peripheral control line and the signal transmitted by the first peripheral control line.
  • the rest of the description of this example can refer to the description of the embodiment shown in Figure 9, so it will not be repeated here.
  • the multiple electrostatic discharge circuits within the first sub-area B01 can be arranged in multiple rows along the first direction D1, and each row of electrostatic discharge circuits can include multiple electrostatic discharge circuits arranged along the second direction D2.
  • the multiple electrostatic discharge circuits can be arranged as a first row of electrostatic discharge circuits 61a, a second row of electrostatic discharge circuits 61b, and a third row of electrostatic discharge circuits 61c.
  • the first row of electrostatic discharge circuits 61a, the second row of electrostatic discharge circuits 61b, and the third row of electrostatic discharge circuits 61c can be arranged sequentially in a direction away from the display area.
  • the first routing segment 41-1 of the first peripheral control line L1 located within the first sub-region B01 can be connected to multiple electrostatic discharge circuits.
  • the first routing segment 41-1 of the first peripheral control line L1 can extend approximately along the curved edge of the display area toward the left border region B21 of the second border region.
  • the first routing segment 41-1 of the first peripheral control line L1 can be located between the first row of electrostatic discharge circuits 61a and the second row of electrostatic discharge circuits 61b.
  • the routing method of the first peripheral control line in this example can adapt to the position of the first peripheral control line away from the boundary of the display substrate, which can reduce the length of the first peripheral control line, thereby facilitating load reduction.
  • FIG12 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure.
  • the electrostatic discharge circuit can be connected to a peripheral control line CL and configured to discharge static electricity from the peripheral control line CL to which it is connected.
  • the electrostatic discharge circuit can include: first to fourth release transistors ST1 to ST4.
  • the first electrode of the first release transistor ST1 can be electrically connected to the third voltage control line VGL1, the gate and second electrode of the first release transistor ST1 are electrically connected to the first electrode of the second release transistor ST2, the gate and second electrode of the second release transistor ST2 are electrically connected to the peripheral control line CL corresponding to the first electrostatic discharge circuit, the first electrode of the third release transistor ST3 is electrically connected to the peripheral control line CL corresponding to the first electrostatic discharge circuit, the gate and second electrode of the third release transistor ST3 are electrically connected to the first electrode of the fourth release transistor ST4, and the gate and second electrode of the fourth release transistor ST4 are electrically connected to the fourth voltage line VGH.
  • the electrostatic discharge circuit may include two discharge transistors, each with one electrode connected to its own gate, thereby forming an equivalent diode connection.
  • the signal line to be protected is connected between the two "diodes," and the other two ends of the two “diodes” are connected to the fourth voltage control line VGH and the first voltage control line VGL1, respectively.
  • a transient high voltage e.g., 100V
  • a transient low voltage e.g., -100V
  • the other "diode” conducts, releasing the negative charge in the signal line.
  • Figure 13 is a partially enlarged schematic diagram of region S2 in Figure 6.
  • Figure 14 is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 13.
  • Figures 13 and 14 illustrate the arrangement of multiple electrostatic discharge circuits in the first corner region of the first subregion as an example.
  • first release transistor to the fourth release transistor of the first electrostatic release circuit in the first row of electrostatic release circuits in the second direction D2 are arranged along the second direction D2, and the fourth release transistor to the first release transistor of the second electrostatic release circuit can be arranged along the second direction D2.
  • the first row of electrostatic discharge circuits 61a, the second row of electrostatic discharge circuits 61b, and the third row of electrostatic discharge circuits 61c can be connected to the first voltage control line VGL1 via a first connection line 621, a second connection line 622, a third connection line 623, and a fourth connection line 624.
  • the first connection line 621, the second connection line 622, the third connection line 623, and the fourth connection line 624 can extend along the first direction D1 and be arranged along the second direction D2.
  • the fourth voltage control line VGH can be located on a side of the third row of electrostatic discharge circuits 61c away from the second row of electrostatic discharge circuits 61b and can be electrically connected to the three rows of electrostatic discharge circuits via four connection lines extending along the first direction D1.
  • the first row of electrostatic release circuits 61a can include six electrostatic release circuits.
  • the six electrostatic release circuits arranged along the second direction D2 can be connected to the second start signal line NSTV, the third clock signal line NCK, the second clock signal line GCB, the first clock signal line GCK, the first start signal line GSTV and the eleventh clock signal line HCX in sequence to play an electrostatic protection role.
  • the third row of electrostatic discharge circuits 61c may include seven electrostatic discharge circuits, six of which may be aligned with the six electrostatic discharge circuits of the first row of electrostatic discharge circuits 61a in the first direction D1.
  • the seven electrostatic discharge circuits of the third row of electrostatic discharge circuits 61c arranged along the second direction D2 may be sequentially connected to the ninth clock signal line HCK, the twelfth clock signal line ECK, the tenth clock signal line HCB, the fourteenth clock signal line ECX, the thirteenth clock signal line ECB, the fifth start signal line ESTV, and the fifth clock signal line NCX, thereby providing electrostatic protection.
  • the first panel detection line PCD1 can be connected to the second detection connection line 631 located on the first gate metal layer via a first detection connection line 633 located on the first source/drain metal layer.
  • the second panel detection line PCD2 can be connected to the fourth detection connection line 632 located on the first gate metal layer via a third detection connection line 634 located on the first source/drain metal layer.
  • the structure of the second corner region of the first sub-region is similar to that of the first corner region, and therefore will not be described in detail here.
  • FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • display substrate 910 may be an OLED display substrate.
  • Display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited to this.
  • the reference terms "one embodiment”, “some embodiments”, “example” or “some examples” and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.
  • the schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
  • those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

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Abstract

一种显示基板，包括相互连通的第一边框区域(B1)和第二边框区域(B2)，第一边框区域(B1)包括沿第一方向(D1)位于显示区域(AA)一侧的弯折区域(B02)。显示基板包括：衬底(10)、设置在衬底(10)上且位于显示区域(AA)的多个子像素(PX)、位于第二边框区域(B2)的多个栅极驱动电路、位于第一边框区域(B1)的至少一条第一周边控制线(L1)和多条第二周边控制线(L2、L3)。每条第一周边控制线(L1)所传输信号的电位低于每条第二周边控制线(L2、L3)所传输信号的电位。在弯折区域(B02)，至少一条第二周边控制线(L2)位于至少一条第一周边控制线(L1)与显示基板的边界之间。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：显示区域和位于所述显示区域周围的边框区域，所述边框区域包括：相互连通的第一边框区域和第二边框区域，所述第一边框区域至少包括：沿第一方向位于所述显示区域一侧的弯折区域。所述显示基板包括：衬底、设置在所述衬底的一侧且位于所述显示区域的多个子像素、位于所述第二边框区域的多个栅极驱动电路、位于第一边框区域的至少一条第一周边控制线和多条第二周边控制线。多个栅极驱动电路与所述多个子像素电连接，配置为向所述多个子像素提供多种像素控制信号。至少一条第一周边控制线与所述多个栅极驱动电路连接。所述多条第二周边控制线中的一部分第二周边控制线与所述多个栅极驱动电路连接；每条第一周边控制线所传输信号的电位低于每条第二周边控制线所传输信号的电位。在所述弯折区域，所述多条第二周边控制线中的至少一条第二周边控制线位于所述至少一条第一周边控制线与所述显示基板的边界之间。
在一些示例性实施方式中，显示基板还包括：位于所述第一边框区域的多条周边数据线，所述多条周边数据线与所述多个子像素电连接，配置为给所述多个子像素提供数据信号；在第二方向上，所述多条第二周边控制线和所述至少一条第一周边控制线位于所述多条周边数据线与所述显示基板的边界之间；所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，在所述弯折区域，所述至少一条第一周边控制线与所述显示基板的边界之间的最小距离大于或等于1250微米。
在一些示例性实施方式中，所述至少一条第一周边控制线配置为传输恒压信号，所述恒压信号的电位小于或等于-6V。
在一些示例性实施方式中，所述多个子像素中的至少一个子像素包括：像素电路以及与所述像素电路连接的发光元件。所述像素电路至少包括：驱动晶体管、数据写入晶体管和补偿晶体管；所述数据写入晶体管的栅极与第一扫描线连接，所述数据写入晶体管的第一极与数据线连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极连接；所述驱动晶体管的栅极与所述补偿晶体管的第二极连接，所述驱动晶体管的第二极与所述补偿晶体管的第一极连接，所述补偿晶体管的栅极与第二扫描线连接。所述多个栅极驱动电路包括：至少一个第一扫描驱动电路、以及至少一个第二扫描驱动电路，所述至少一个第一扫描驱动电路配置为给所述第一扫描线提供第一扫描信号，所述至少一个第二扫描驱动电 路配置为给所述第二扫描线提供第二扫描信号。所述多条第二周边控制线至少包括：与所述至少一个第二扫描驱动电路连接的第二起始信号线和第二扫描驱动输出线；所述至少一条第一周边控制线位于所述第二起始信号线和所述第二扫描驱动输出线之间。
在一些示例性实施方式中，所述像素电路还包括：第一复位晶体管，所述第一复位晶体管的栅极与第一复位控制线连接，所述第一复位晶体管的第一极配置为接收第一初始信号，所述第一复位晶体管的第二极与所述驱动晶体管的第二极连接。在所述弯折区域，所述多条第二周边控制线中最靠近所述显示基板的边界的第二周边控制线配置为传输所述第一初始信号。
在一些示例性实施方式中，在所述弯折区域，所述多条第二周边控制线中最靠近所述显示基板的边界的第二周边信号线与所述显示基板的边界之间的最小距离大于或等于400微米。
在一些示例性实施方式中，所述第一边框区域还包括：位于所述弯折区域远离所述显示区域一侧的第一信号接入区域；所述显示基板还包括：位于所述第一信号接入区域且沿第二方向排布的多个第一接触垫；所述第二方向与所述第一方向交叉；所述多个第一接触垫包括：与所述至少一条第一周边控制线连接的至少一个第一控制接触垫、以及与所述多条第二周边控制线连接的多个第二控制接触垫。在所述第二方向上，所述多个第二控制接触垫中的至少一个第二控制接触垫位于所述至少一个第一控制接触垫与所述显示基板的边界之间。
在一些示例性实施方式中，所述至少一条第一周边控制线位于第一条第二周边控制线和第二条第二周边控制线之间。在所述第二方向上，所述至少一个第一控制接触垫位于所述第一条第二周边控制线所连接的第二控制接触垫与所述第二条第二周边控制线所连接的第二控制接触垫之间。
在一些示例性实施方式中，所述至少一条第一周边控制线位于第一条第二周边控制线和第二条第二周边控制线之间；所述第一条第二周边控制线位于所述至少一条第一周边控制线靠近所述显示基板的边界的一侧。在所述第二方向上，所述至少一个第一控制接触垫位于所述第二条第二周边控制线所连接的第二控制接触垫远离所述显示基板的边界的一侧。
在一些示例性实施方式中，所述第一边框区域还包括：位于所述弯折区域靠近所述显示区域一侧的第一子区域，所述第一子区域与所述第二边框区域连通。所述显示基板还包括：位于所述第一子区域的多个静电释放电路，所述多个静电释放电路与所述多个栅极驱动电路邻近设置。所述多个静电释放电路沿所述第一方向排布为多行，每行静电释放电路包括沿第二方向设置的多个静电释放电路；所述第二方向与所述第一方向交叉。所述至少一条第一周边信号线位于相邻两行静电释放电路之间。
在一些示例性实施方式中，所述多个静电释放电路按照远离所述显示区域的方向排布为第一行静电释放电路、第二行静电释放电路和第三行静电释放电路，所述至少一条第一周边信号线位于所述第一行静电释放电路和所述第二行静电释放电路之间。
在一些示例性实施方式中，显示基板包括多条第一周边控制线，所述多个静电释放电路与其中一条第一周边控制线连接。
在一些示例性实施方式中，所述多个栅极驱动电路包括沿第二方向位于所述显示区域两侧的第一组栅极驱动电路和第二组栅极驱动电路，所述第二方向与所述第一方向交叉。所述第一组栅极驱动电路与至少一条第一周边控制线连接，所述第二组栅极驱动电路与至少一条第一周边控制线连接；所述第一组栅极驱动电路包括的栅极驱动电路的数目与所述 第二组栅极驱动电路包括的栅极驱动电路的数目相同。
另一方面，本实施例提供一种显示装置，包括如前所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的像素电路的等效电路图；
图3为本公开至少一实施例的栅极驱动电路的设置示意图；
图4A为本公开至少一实施例的显示区域的局部剖面示意图；
图4B为本公开至少一实施例的显示区域的另一局部剖面示意图；
图5为本公开至少一实施例的第一边框区域的局部走线示意图；
图6为本公开至少一实施例的第一边框区域的局部示意图；
图7为图6中区域S1的局部放大示意图；
图8为本公开至少一实施例的第一边框区域的另一局部走线示意图；
图9为本公开至少一实施例的第一边框区域的另一局部走线示意图；
图10为本公开至少一实施例的第一边框区域的另一局部走线示意图；
图11为本公开至少一实施例的第一边框区域的另一局部示意图；
图12为本公开至少一实施例的静电释放电路的等效电路图；
图13为图6中区域S2的局部放大示意图；
图14为图13中第一半导体层、第一栅金属层和第二栅金属层的示意图；
图15为本公开至少一实施例的显示装置的示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水 平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“连接”可以包括“电连接”，“电连接”可以包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极(栅电极)、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。另外，栅极还可以称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“相同”包括数值相差10％以内的情况，比如数值相差5％以内的情况。
在本说明书中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本说明书中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本说明书中所说的“A和B为同层结构”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
随着显示技术的发展，柔性显示产品得到的关注越来越多。柔性显示产品的显示基板的下边框会在弯折区域弯折收窄，下边框的弯折区域的边缘走线存在信赖性腐蚀的情况，容易造成显示产品的显示问题。
本实施例提供一种显示基板，包括：显示区域和位于显示区域周围的边框区域，边框区域包括：相互连通的第一边框区域和第二边框区域，第一边框区域至少包括：沿第一方向位于显示区域一侧的弯折区域。显示基板包括：衬底、多个子像素、多个栅极驱动电路、 至少一条第一周边控制线和多条第二周边控制线。多个子像素设置在衬底的一侧且位于显示区域。多个栅极驱动电路位于第二边框区域，并与多个子像素电连接，配置为向所述多个子像素提供多种像素控制信号。至少一条第一周边控制线位于第一边框区域，并与多个栅极驱动电路连接。多条第二周边控制线位于第一边框区域，所述多条第二周边控制线中的一部分第二周边控制线与所述多个栅极驱动电路连接；每条第一周边控制线所传输信号的电位低于每条第二周边控制线所传输信号的电位。在弯折区域，所述多条第二周边控制线中的至少一条第二周边控制线位于所述至少一条第一周边控制线与显示基板的边界之间。换言之，至少一条第二周边控制线位于所述至少一条第一周边控制线靠近显示基板的边界的一侧。所述至少一条第一周边控制线不是最靠近显示基板的边界的走线。
本实施例提供的显示基板，通过将传输电位较低的第一周边控制线设置在传输电位较高的至少一条第二周边控制线远离显示基板的边界的一侧，可以增加第一周边控制线与显示基板的边界之间的距离，有利于避免第一周边控制线发生信赖性腐蚀情况。
在一些示例性实施方式中，显示基板还可以包括：位于第一边框区域的多条周边数据线，所述多条周边数据线与所述多个子像素电连接，配置为给所述多个子像素提供数据信号。在第二方向上，所述多条第二周边控制线和所述至少一条第一周边控制线位于所述多条周边数据线与显示基板的边界之间。其中，第二方向与第一方向交叉；例如，第二方向可以垂直于第一方向。在一些示例中，多条第二周边控制线可以位于多条周边数据线在第二方向的两侧，至少一条第一周边控制线可以位于多条周边数据线靠近至少一条第二周边控制线的一侧。本实施例对此并不限定。
在一些示例性实施方式中，至少一条第一周边控制线可以配置为传输恒压信号，所述恒压信号的电位可以小于或等于-6V。在一些示例中，至少一条第一周边控制线所传输信号的电位可以小于或等于-6V且大于或等于-12V。例如，第一周边控制线所传输信号的电位范围可以为-7V至-8V。本示例的第一周边控制线可以为第一边框区域内传输最低电位的走线。本示例通过将传输最低电位的第一周边控制线远离显示基板的边界设置，可以防止第一周边控制线发生信赖性腐蚀的情况。
在一些示例性实施方式中，第一边框区域还可以包括：位于弯折区域远离显示区域一侧的第一信号接入区域。显示基板还可以包括：位于第一信号接入区域且沿第二方向排布的多个第一接触垫。所述多个第一接触垫可以包括：与所述至少一条第一周边控制线连接的至少一个第一控制接触垫、以及与所述多条第二周边控制线连接的多个第二控制接触垫。在第二方向上，所述多个第二控制接触垫中的至少一个第二控制接触垫可以位于所述至少一个第一控制接触垫与所述显示基板的边界之间。换言之，在第二方向上，至少一个第二控制接触垫可以位于至少一个第一控制接触垫靠近显示基板的边界之间。在一些示例中，至少一条第一周边控制线可以位于第一条第二周边控制线和第二条第二周边控制线之间；在第二方向上，所述至少一个第一控制接触垫可以位于所述第一条第二周边控制线所连接的第二控制接触垫与所述第二条第二周边控制线所连接的第二控制接触垫之间。在另一些示例中，至少一条第一周边控制线可以位于第一条第二周边控制线和第二条第二周边控制线之间；所述第一条第二周边控制线位于所述至少一条第一周边控制线靠近所述显示基板的边界的一侧；在所述第二方向上，所述至少一个第一控制接触垫可以位于所述第二条第二周边控制线所连接的第二控制接触垫远离所述显示基板的边界的一侧。本示例通过将第一周边控制线连接的第一控制接触垫远离显示基板的边界设置，可以保证第一周边控制线的信号传输以及在第一边框区域内的合理排布。
在一些示例性实施方式中，第一边框区域还可以包括：位于弯折区域靠近显示区域一侧的第一子区域，第一子区域与第二边框区域连通。显示基板还可以包括：位于第一子区 域的多个静电释放电路，所述多个静电释放电路可以与多个栅极驱动电路邻近设置。所述多个静电释放电路可以沿第一方向排布为多行，每行静电释放电路包括沿第二方向设置的多个静电释放电路。所述至少一条第一周边信号线可以位于相邻两行静电释放电路之间。本示例通过在相邻行静电释放电路之间排布第一周边信号线，可以减少第一周边信号线的长度，有利于降低第一周边信号线的信号负载(loading)。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例中，如图1所示，显示基板可以包括：显示区域AA以及位于显示区域AA周围的边框区域BB。边框区域BB可以包括：位于显示区域AA一侧的第一边框区域B1以及位于显示区域AA其余侧的第二边框区域B2。例如，第一边框区域B1可以沿第一方向D1位于显示区域AA的一侧。第一边框区域B1和第二边框区域B2可以连通。例如，第一边框区域B1可以为显示基板的下边框区域，第二边框区域B2可以包括：显示基板的左边框区域B21、右边框区域B22和上边框区域B23。
在一些示例中，如图1所示，显示区域AA可以是平坦的区域，包括组成像素阵列的多个子像素PX。多个子像素PX可以被配置为显示动态图片或静止图像。显示区域AA可以称为有效区域(Active Area)。在一些示例中，显示区域AA可以为矩形，例如圆角矩形。然而，本实施例对此并不限定。例如，显示区域可以为圆形、椭圆形等其它形状。在一些示例中，显示基板可以为柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例中，显示区域AA可以包括：设置在衬底上的显示结构层，或者可以包括依次设置在衬底上的显示结构层和触控结构层。例如，显示基板可以集成触控结构，形成触控结构在薄膜封装(Touch on Thin Film Encapsulation，简称Touch on TFE)上的结构。Touch on TFE结构主要包括柔性多层覆盖表面式(FMLOC，Flexible Multi-Layer On Cell)结构和柔性单层覆盖表面式(FSLOC，Flexible Single-Layer On Cell)结构。FMLOC结构是基于互容检测的工作原理，一般采用两层金属形成驱动(Tx)电极和感应(Rx)电极，驱动芯片(IC)通过检测驱动电极和感应电极间的互容来实现触控动作。FSLOC结构是基于自容(或电压)检测的工作原理，一般采用单层金属形成触控电极，集成电路通过检测触控电极自容(或电压)来实现触控动作。
在一些示例中，显示结构层可以包括多个子像素PX、多条栅线GL和多条数据线DL。多条栅线GL可以沿第二方向D2延伸并沿第一方向D1排布，多条数据线DL可以沿第一方向D1延伸并沿第二方向D2排布。第一方向D1与第二方向D2可以交叉，例如，第一方向D1可以垂直于第二方向D2。多条栅线GL和多条数据线DL在衬底的正投影可以交叉形成多个子像素区域。一个子像素PX可以设置在一个子像素区域内。多条数据线DL可以与多个子像素PX电连接，多条数据线DL可以被配置为向多个子像素PX提供数据信号。多条栅线GL可以与多个子像素PX电连接，多条栅线GL可以被配置为向多个子像素PX提供像素控制信号。例如，像素控制信号可以包括扫描信号，或者可以包括扫描信号和发光控制信号，或者可以包括扫描信号、复位控制信号和发光控制信号。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素可以分别为出射第一颜色光(例如，红光)的第一子像素、出射第二颜色光(例如，绿光)的第二子像素和出射第三颜色光(例如，蓝光)的第三子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为出射红光的子像素、出射绿光的子像素、出射蓝光的子像素和出射白光的子像素。又如，一个像素单元可以包括四个子像素，四个子像素可以包括一个出射红光的子像素、一个出射蓝光的 子像素、以及两个出射绿光的子像素。
在一些示例中，一个子像素PX可以包括：像素电路以及与像素电路电连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。在另一些示例中，像素电路中的多个晶体管可以为P型晶体管或者可以为N型晶体管，像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。
在一些示例中，子像素的发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图2为本公开至少一实施例的像素电路的等效电路图。本示例的像素电路以8T1C结构为例进行说明。在一些示例中，如图2所示，本示例的像素电路可以包括八个像素晶体管(即第一像素晶体管T1至第八像素晶体管T8)和一个存储电容Cst。第一像素晶体管T1还可以称为第一复位晶体管，第二像素晶体管T2还可以称为补偿晶体管，第三像素晶体管T3还可以称为驱动晶体管，第四像素晶体管T4还可以称为数据写入晶体管，第五像素晶体管T5还可以称为第一发光控制晶体管，第六像素晶体管T6还可以称为第二发光控制晶体管，第七像素晶体管T7还可以称为第二复位晶体管，第八像素晶体管T8还可以称为第三复位晶体管。发光元件EL可以包括阳极、阴极和设置在阳极和阴极之间的有机发光层。
在一些示例中，第一像素晶体管T1、第三像素晶体管T3至第八像素晶体管T8可以为第一类型晶体管，例如可以为P型晶体管，第二像素晶体管T2可以为第二类型晶体管，例如可以为N型晶体管。然而，本实施例对此并不限定。例如，像素电路的多个像素晶体管可以均是P型晶体管，或者可以均是N型晶体管。
在一些示例中，像素电路的第一类型晶体管(例如包括第一像素晶体管T1、第三像素晶体管T3至第八像素晶体管T8)可以采用低温多晶硅薄膜晶体管，像素电路的第二类型晶体管(例如包括第二像素晶体管T2)可以采用氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPS+Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例中，如图2所示，像素电路可以与第一扫描线GL1、第二扫描线GL2、 数据线DL、第一电源线PL1、第二电源线PL2、发光控制线EML、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线INIT3、第一复位控制线RST1以及第二复位控制线RST2电连接。第一电源线PL1可以配置为向像素电路提供恒定的第一电压信号VDD，第二电源线PL2可以配置为向像素电路提供恒定的第二电压信号VSS，并且第一电压信号VDD大于第二电压信号VSS。第一扫描线GL1可以配置为向像素电路提供第一扫描信号SCAN1。第二扫描线GL2可以配置为向像素电路提供第二扫描信号SCAN2。数据线DL可以配置为向像素电路提供数据信号。发光控制线EML可以配置为向像素电路提供发光控制信号EM。第一复位控制线RST1可以配置为向像素电路提供第一复位控制信号RESET1。第二复位控制线可以配置为向像素电路提供第二复位控制信号RESET2。
在一些示例中，如图2所示，第三像素晶体管T3的栅极与第一节点N1电连接，第三像素晶体管T3的第一极与第二节点N2电连接，第三像素晶体管T3的第二极与第三节点N3电连接。第四像素晶体管T4的栅极与第一扫描线GL1电连接，第四像素晶体管T4的第一极与数据线DL电连接，第四像素晶体管T4的第二极与第二节点N2电连接。第二像素晶体管T2的栅极与第二扫描线GL2电连接，第二像素晶体管T2的第一极与第三节点N3电连接，第二像素晶体管T2的第二极与第一节点N1电连接。第五像素晶体管T5的栅极与发光控制线EML电连接，第五像素晶体管T5的第一极与第一电源线PL1电连接，第五像素晶体管T5的第二极与第二节点N2电连接。第六像素晶体管T6的栅极与发光控制线EML电连接，第六像素晶体管T6的第一极与第三节点N3电连接，第六像素晶体管T6的第二极与第四节点N4电连接。第一像素晶体管T1的栅极与第一复位控制线RST1电连接，第一像素晶体管T1的第一极与第一初始信号线INIT1电连接，第一像素晶体管T1的第二极与第三节点N3电连接。第一像素晶体管T1可以配置为对第三节点N3进行复位。第七像素晶体管T7的栅极与第二复位控制线RST2电连接，第七像素晶体管T7的第一极与第二初始信号线INIT2电连接，第七像素晶体管T7的第二极与第四节点N4电连接。第七像素晶体管T7可以配置为对第四节点N4进行复位。第八像素晶体管T8的栅极与第二复位控制线RST2电连接，第八像素晶体管T8的第一极与第三初始信号线INIT3电连接，第八像素晶体管T8的第二极与第二节点N2电连接。第八像素晶体管T8可以配置为对第二节点N2进行复位。存储电容Cst的第一电极与第一节点N1电连接，存储电容Cst的第二电极与第一电源线PL1电连接。
在本示例中，第一节点N1为存储电容Cst、第二像素晶体管T2和第三像素晶体管T3的连接点，第二节点N2为第五像素晶体管T5、第四像素晶体管T4、第八像素晶体管T8和第三像素晶体管T3的连接点，第三节点N3为第一像素晶体管T1、第三像素晶体管T3、第二像素晶体管T2和第六像素晶体管T6的连接点，第四节点N4为第六像素晶体管T6、第七像素晶体管T7和发光元件EL的连接点。
下面对图2所示的像素电路的工作过程进行说明。其中，像素电路的第一像素晶体管T1、第三像素晶体管T3至第八像素晶体管T8为P型晶体管，第二像素晶体管T2为N型晶体管。
在一些示例中，在一帧显示时间段，像素电路的工作过程可以至少包括：第一阶段、第二阶段、第三阶段以及第四阶段。
第一阶段，称为第一复位阶段。第二复位控制线RST2提供的第二复位控制信号RESET2为低电平信号，使第七像素晶体管T7和第八像素晶体管T8导通；第二扫描线GL2提供的第二扫描信号SCAN2为高电平信号，使第二像素晶体管T2导通。第八像素晶体管T8导通，使得第三初始信号线INIT3提供的第三初始信号被提供至第二节点N2。第七像素晶体管T7导通，使得第二初始信号线INIT2提供的第二初始信号被提供至第四 节点N4，对第四节点N4进行初始化。第一扫描线GL1提供的第一扫描信号SCAN1为高电平信号，第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使第四像素晶体管T4、第一像素晶体管T1、第五像素晶体管T5和第六像素晶体管T6断开。此阶段发光元件EL不发光。
第二阶段，称为第二复位阶段。第一复位控制线RST1提供的第一复位控制信号RESET1为低电平信号，第一像素晶体管T1导通；第二扫描线GL2提供的第二扫描信号SCAN2为高电平信号，第二像素晶体管T2导通。第一像素晶体管T1和第二像素晶体管T2导通，使得第一初始信号线INIT1提供的第一初始信号线被提供至第一节点N1，对第一节点N1进行初始化。第二复位控制线RST2提供的第二复位控制信号RESET2为高电平信号，第一扫描线GL1提供的第一扫描信号SCAN1为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使得第七像素晶体管T7、第八像素晶体管T8、第四像素晶体管T4、第五像素晶体管T5和第六像素晶体管T6断开。此阶段发光元件EL不发光。
第三阶段，称为数据写入阶段或者阈值补偿阶段。第一扫描线GL1提供的第一扫描信号SCAN1为低电平信号，第四像素晶体管T4导通；第二扫描线GL2提供的第二扫描信号SCAN2为高电平信号，第二像素晶体管T2导通。此阶段存储电容Cst的第一电极为低电平，第三像素晶体管T3导通。第二像素晶体管T2、第四像素晶体管T4和第三像素晶体管T3导通，使得数据线DL输出的数据电压Vdata经过第二节点N2、导通的第三像素晶体管T3、第三节点N3和导通的第二像素晶体管T2提供至第一节点N1，并将数据线DL输出的数据电压Vdata与第三像素晶体管T3的阈值电压之差充入存储电容Cst，存储电容Cst的第一电极(即第一节点N1)的电压为Vdata-|Vth|，其中，Vdata为数据线DL输出的数据电压，Vth为第三像素晶体管T3的阈值电压。第一复位控制线RST1提供的第一复位控制信号RESET1为高电平信号，第二复位控制线RST2提供的第二复位控制信号RESET2为高电平信号，发光控制线EML提供的发光控制信号EM为高电平信号，使第一像素晶体管T1、第七像素晶体管T7、第八像素晶体管T8、第五像素晶体管T5和第六像素晶体管T6断开。
第四阶段，发光控制线EML提供的发光控制信号EM可以从高电平信号切换为低电平信号，使第五像素晶体管T5和第六像素晶体管T6导通。第二扫描线GL2提供的第二扫描信号SCAN2为低电平信号，使第二像素晶体管T2断开。第一扫描线GL1提供的第一扫描信号SCAN1、第一复位控制线RST1提供的第一复位控制信号RESET1和第二复位控制线RST2提供的第二复位控制信号RESET2为高电平信号，使第四像素晶体管T4、第一像素晶体管T1、第七像素晶体管T7和第八像素晶体管T8断开。第一电源线PL1输出的第一电压信号VDD可以通过导通的第五像素晶体管T5、第三像素晶体管T3和第六像素晶体管T6向发光元件EL的阳极提供驱动电压，驱动发光元件EL发光。
在像素电路的驱动过程中，流过第三像素晶体管T3的驱动电流由其栅极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而第三像素晶体管T3的驱动电流为：
I＝K×(Vgs-Vth)2＝K×[(VDD-Vdata+|Vth|)-Vth]2＝K×[VDD-Vdata]2；
其中，I为流过第三像素晶体管T3的驱动电流，也就是驱动发光元件的驱动电流，K为常数，Vgs为第三像素晶体管T3的栅极和第一极之间的电压差，Vth为第三像素晶体管T3的阈值电压，Vdata为数据线DL输出的数据电压，VDD为第一电源线PL1输出的第一电压信号。
由上式中可以看到流经发光元件的电流与第三像素晶体管T3的阈值电压无关。因此，本实施例的像素电路可以较好地补偿第三像素晶体管T3的阈值电压。而且，本实施例提供的像素电路可以改善由于低频导致的显示不良情况，提高发光元件的显示效果。
图3为本公开至少一实施例的栅极驱动电路的设置示意图。在一些示例中，如图3所示，第二边框区域B2可以设置多个栅极驱动电路。例如，多个栅极驱动电路可以包括第一组栅极驱动电路和第二组栅极驱动电路，第一组栅极驱动电路可以位于第二边框区域B2的左边框区域B21，第二组栅极驱动电路可以位于第二边框区域B2的右边框区域B22。第一组栅极驱动电路内的栅极驱动电路的数目与第二组栅极驱动电路内的栅极驱动电路的数目可以相同。然而，本实施例对此并不限定。
在一些示例中，如图3所示，多个栅极驱动电路可以包括：两个第一扫描驱动电路21a和21b、两个第二扫描驱动电路22a和22b、两个第一复位驱动电路23a和23b、两个第二复位驱动电路24a和24b、以及两个发光驱动电路25a和25b。第一组栅极驱动电路可以包括：第一扫描驱动电路21a、第二扫描驱动电路22a、第一复位驱动电路23a、第二复位驱动电路24a和发光驱动电路25a；第二组栅极驱动电路可以包括：第一扫描驱动电路21b、第二扫描驱动电路22b、第一复位驱动电路23b、第二复位驱动电路24b和发光驱动电路25b。例如，在第二边框区域B2的左边框区域B21内，第一扫描驱动电路21a、第二扫描驱动电路22a、第一复位驱动电路23a、第二复位驱动电路24a和发光驱动电路25a可以沿着远离显示区域AA的方向依次设置；在第二边框区域B2的右边框区域B22内，第一扫描驱动电路21b、第二扫描驱动电路22b、第一复位驱动电路23b、第二复位驱动电路24b和发光驱动电路25b可以沿着远离显示区域AA的方向依次设置。
在一些示例中，多个栅极驱动电路给显示区域的多个子像素提供的多种像素控制信号可以包括：第一扫描信号、第二扫描信号、第一复位控制信号、第二复位控制信号以及发光控制信号。第一扫描驱动电路21a和21b可以配置为给显示区域AA的多个像素电路提供第一扫描信号。第二扫描驱动电路22a和22b可以配置为给显示区域AA的多个像素电路提供第二扫描信号。发光驱动电路25a和25b可以配置为给显示区域AA的多个像素电路提供发光控制信号。第一复位驱动电路23a和23b可以配置为给显示区域AA的多个像素电路提供第一复位控制信号。第二复位驱动电路24a和24b可以配置为给显示区域AA的多个像素电路提供第二复位控制信号。本示例中，第一扫描信号、第二扫描信号、发光控制信号、第一复位控制信号和第二复位控制信号可以均采用双边驱动。然而，本实施例对此并不限定。在另一些示例中，第一扫描信号、第二扫描信号、发光控制信号、第一复位控制信号和第二复位控制信号中的至少之一可以采用单边驱动。
在一些示例，以显示区域AA包括M行像素电路为例进行说明，其中，M为正整数。显示区域AA内的多行像素电路可以沿着从上边框区域B23到第一边框区域B1的方向上依次标记为第1行至第M行。
在一些示例中，第一扫描驱动电路21a和21b可以各自包括多个级联的第一扫描驱动单元(例如包括GP(1)至GP(4))。每一级第一扫描驱动单元可以配置为给显示区域AA的一行像素电路提供第一扫描信号。例如，第一级第一扫描驱动单元GP(1)可以配置为给显示区域AA的第1行像素电路提供第一扫描信号。
在一些示例中，第二扫描驱动电路22a和22b可以各自包括多个级联的第二扫描驱动单元(例如包括GN(1)至GN(4))。每一级第二扫描驱动单元可以配置为给显示区域AA的一行像素电路提供第二扫描信号。例如，第一级第二扫描驱动单元GN(1)可以配置为给显示区域AA的第1行像素电路提供第二扫描信号。然而，本实施例对此并不限定。在另一些示例中，每一级第二扫描驱动单元可以配置为给显示区域的相邻两行像素电路提供第 二扫描信号。
在一些示例中，发光驱动电路25a和25b可以各自包括多个级联的发光驱动单元(例如包括EM(1)至EM(4))。每一级发光驱动单元可以配置为给显示区域AA的一行像素电路提供发光控制信号。例如，第一级发光驱动单元EM(1)可以配置为给显示区域AA的第1行像素电路提供发光控制信号。然而，本实施例对此并不限定。在另一些示例中，每一级发光驱动单元可以配置为给显示区域的相邻两行像素电路提供发光控制信号。
在一些示例中，第一复位驱动电路23a和23b可以各自包括多个级联的第一复位驱动单元(例如包括RP(1)至RP(4))。每一级第一复位驱动单元可以配置为给显示区域AA的一行像素电路提供第一复位控制信号。例如，第一级第一复位驱动单元RP(1)可以配置为给显示区域AA的第1行像素电路提供第一复位控制信号。然而，本实施例对此并不限定。在另一些示例中，每一级第一复位驱动单元可以配置为给显示区域的相邻两行像素电路提供第一复位控制信号。
在一些示例中，第二复位驱动电路24a和24b可以各自包括多个级联的第二复位驱动单元(例如包括RH(1)至RH(4))。每一级第二复位驱动单元可以配置为给显示区域AA的一行像素电路提供第二复位控制信号。例如，第一级第二复位驱动单元RH(1)可以配置为给显示区域AA的第1行像素电路提供第二复位控制信号。然而，本实施例对此并不限定。在另一些示例中，每一级第二复位驱动单元可以配置为给显示区域的相邻两行像素电路提供第二复位控制信号。
图4A为本公开至少一实施例的显示区域的局部剖面示意图。图4A中以显示区域的一个子像素的结构为例进行示意。在本示例中，以图2所示的像素电路包括低温多晶硅薄膜晶体管和氧化物薄膜晶体管为例进行说明。
在一些示例中，如图4A所示，在垂直于显示基板的方向上，显示基板的显示区域可以至少包括：衬底10、以及依次设置在衬底10上的电路结构层12、发光结构层13以及封装结构层14。电路结构层12可以至少包括：多个子像素的像素电路，每个子像素的像素电路可以包括多个晶体管和至少一个电容。发光结构层13可以至少包括：多个子像素的发光元件。在另一些示例中，显示基板还可以包括位于封装结构层远离衬底一侧的触控结构层。
在一些示例中，图4A中以每个子像素包括的一个第一类型晶体管21、一个第二类型晶体管22和一个电容23为例进行示意。其中，第一类型晶体管21可以为低温多晶硅薄膜晶体管，第二类型晶体管22可以为氧化物薄膜晶体管。
在一些示例中，显示区域的电路结构层12可以包括：设置在衬底10上的第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层和第二源漏金属层。第一半导体层和第一栅金属层之间可以设置有第一绝缘层101，第一栅金属层和第二栅金属层之间可以设置有第二绝缘层102；第二栅金属层和第二半导体层之间可以设置有第三绝缘层103；第二半导体层和第三栅金属层之间可以设置有第四绝缘层104；第三栅金属层和第一源漏金属层之间可以设置有第五绝缘层105；第一源漏金属层和第二源漏金属层之间可以设置有第六绝缘层106(还可以称为钝化层)和第七绝缘层107(还可以称为第一平坦层)，第七绝缘层107可以位于第六绝缘层106远离衬底10的一侧；第二源漏金属层远离衬底10的一侧可以设置有第八绝缘层108(还可以称为第二平坦层)。其中，第一绝缘层101、第二绝缘层102、第三绝缘层103、第四绝缘层104、第五绝缘层105以及第六绝缘层106可以为无机绝缘层，第七绝缘层107和第八绝缘层108可以为有机绝缘层。然而，本实施例对此并不限定。在另一些示例中，第一半导体层靠近 衬底一侧还可以设置缓冲层，缓冲层可以防止衬底中的有害物质侵入显示面板的内部，还可以增加显示面板中的膜层在衬底上的附着力。在另一些示例中，在缓冲层靠近衬底一侧还可以设置底部遮光金属层(BSM，Bottom Shielding Metal)，底部遮光金属层可以被配置为至少部分覆盖像素电路的晶体管的有源层，以避免外部光线对晶体管的性能产生影响。另一些示例中，第一源漏金属层和第二源漏金属层之间可以省略第六绝缘层，第一源漏金属层和第二源漏金属层之间可以仅设置第七绝缘层。
在一些示例中，如图4A所示，显示区域的第一半导体层可以至少包括：第一类型晶体管21的第一有源层210。第一类型晶体管21的第一有源层210可以包括：第一区2101、第二区2102以及位于第一区2101和第二区2102之间的沟道区2100。第一栅金属层可以至少包括：第一类型晶体管21的第一栅极213、以及电容23的第一极板231。第一类型晶体管21的第一栅极213在衬底10的正投影可以覆盖第一有源层210的沟道区2100在衬底10的正投影。第二栅金属层可以至少包括：电容23的第二极板232、第二类型晶体管22的第三栅极224。电容23的第二极板232和第一极板231在衬底10的正投影可以至少部分交叠，例如，两者可以重合。第二半导体层可以至少包括：第二类型晶体管22的第二有源层220。第三栅金属层可以至少包括：第二类型晶体管22的第二栅极223。第二类型晶体管22的第二栅极223在衬底10的正投影与第二有源层220在衬底10的正投影可以部分交叠。第二类型晶体管22的第三栅极224在衬底10的正投影与第二有源层220在衬底10的正投影可以部分交叠。第三栅极224可以为第二类型晶体管22的底栅，第二栅极223可以为第二类型晶体管22的顶栅。
在一些示例中，如图4A所示，显示区域的第一源漏金属层可以至少包括：第一类型晶体管21的第一源极211和第一漏极212、第二类型晶体管22的第二源极221和第二漏极222。第五绝缘层105在显示区域可以开设有多个像素过孔(例如，包括第一像素过孔、第二像素过孔、第三像素过孔和第四像素过孔)，第一像素过孔内的第五绝缘层105、第四绝缘层104、第三绝缘层103、第二绝缘层102和第一绝缘层101可以被去掉，暴露出第一有源层210的第一区2101的至少部分表面；第二像素过孔内的第五绝缘层105、第四绝缘层104、第三绝缘层103、第二绝缘层102和第一绝缘层101可以被去掉，暴露出第一有源层210的第二区2102的至少部分表面。第三像素过孔和第四像素过孔内的第五绝缘层105、第四绝缘层104和第三绝缘层103可以被去掉，暴露出第二有源层220的两端的至少部分表面。第一类型晶体管21的第一源极211可以通过第一像素过孔与第一有源层210的第一区2101电连接，第一漏极212可以通过第二像素过孔与第一有源层210的第二区2102电连接。第二类型晶体管22的第二源极221可以通过第三像素过孔与第二有源层220的一端电连接，第二类型晶体管22的第二漏极222可以通过第四像素过孔与第二有源层220的另一端电连接。第二源漏金属层可以至少包括：第一转接电极241。第一转接电极241可以通过第六绝缘层106和第七绝缘层107开设的第五像素过孔与像素电路的第一类型晶体管21的第一漏极212电连接。本示例可以通过第一转接电极241实现像素电路与发光元件之间的电连接。
在一些示例中，显示区域的栅线例如可以位于第一栅金属层和第三栅金属层，显示区域的数据线例如可以位于第二源漏金属层，显示区域的第一电源线例如可以位于第二源漏金属层。本实施例对此并不限定。
在一些示例中，如图4A所示，发光结构层13可以包括：像素定义层134和多个发光元件。例如，每个发光元件可以包括：叠设的第一电极131、有机发光层132和第二电极133。发光元件的第一电极131可以为阳极，第一电极131可以设置在第八绝缘层108上，并通过第八绝缘层108开设的第六像素过孔，与第一转接电极241电连接。像素定义 层134设置在第一电极131和第八绝缘层108上，像素定义层134可以开设有多个像素开口，一个像素开口可以暴露出对应的一个第一电极131的至少部分表面。有机发光层132的至少部分可以设置在一个像素开口内，并与对应的第一电极131连接。第二电极133可以设置在有机发光层132上，并与有机发光层132连接。有机发光层132在第一电极131和第二电极133的驱动下可以出射相应颜色的光线。
在一些示例中，发光元件的有机发光层132可以包括发光层(EML，Emitting Layer)，以及包括以下至少一个膜层：空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer)。在第一电极131和第二电极133的电压驱动下，可以利用有机材料的发光特性根据需要的灰度发光。
在一些示例中，不同颜色的发光元件的发光层可以不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例中，如图4A所示，封装结构层14可以包括叠设的第一封装层141、第二封装层142和第三封装层143。其中，第一封装层141和第三封装层143可以采用无机材料，例如氮化硅、氧化硅、氮氧化硅等，无机材料的致密性高，可以防止水、氧等的侵入。第二封装层142可以设置在第一封装层141和第三封装层143之间，以保证外界水汽无法进入发光元件。第二封装层142可以采用有机材料，例如，可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，或者可以为高分子树脂等以对显示面板的表面进行平坦化处理，并且可以缓解第一封装层141和第三封装层143的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。然而，本实施例对此并不限定。例如，封装结构层可以采用无机/有机/无机/有机/无机的五层叠设结构。
图4B为本公开至少一实施例的显示区域的另一局部剖面示意图。在一些示例中，像素电路中的多个像素晶体管的晶体管类型可以相同，例如可以均为低温多晶硅薄膜晶体管。图4B中以每个子像素包括的一个第一类型晶体管21和一个电容23为例进行示意。
在一些示例中，如图4B所示，显示区域的电路结构层12可以包括：设置在衬底10上的第一半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层。第一半导体层和第一栅金属层之间可以设置第一绝缘层101，第一栅金属层和第二栅金属层之间可以设置第二绝缘层102，第二栅金属层和第一源漏金属层之间可以设置第三绝缘层103，第一源漏金属层和第二源漏金属层之间可以设置第六绝缘层106和第七绝缘层107，第二源漏金属层远离衬底10的一侧可以设置第八绝缘层108。第七绝缘层107和第八绝缘层108可以为有机绝缘层，第一绝缘层101、第二绝缘层102和第三绝缘层103可以为无机绝缘层。关于本示例的显示基板的显示区域的其余结构可以参照图4A所示实施例的描述，故于此不再赘述。
图5为本公开至少一实施例的第一边框区域的局部走线示意图。图5以第一边框区域 靠近显示基板的左侧的边界XL的区域为例进行说明。在一些示例中，如图1和图5所示，第一边框区域B1可以包括：在第一方向D1上沿着远离显示区域AA的一侧依次排布的第一子区域B01、弯折区域B02和第二子区域B03。第一子区域B01还可以称为第一扇出区域。第一子区域B01可以与第二边框区域B2的左边框区域B21和右边框区域B22连通，并与显示区域AA连接。弯折区域B02可以连接在第一子区域B01和第二子区域B03之间。第二子区域B03可以至少包括：第一信号接入区域B034以及第二信号接入区域B035。第一信号接入区域B034可以位于第二信号接入区域B035远离弯折区域B02的一侧。
在一些示例中，弯折区域B02可以配置为使第二子区域B03弯折到显示区域AA的背面。弯折区域B02内可以设置有沿第一方向D1延伸的多条弯折连接线，以实现第一子区域B01和第二子区域B03内传输相同信号的走线之间的电连接。弯折区域B02内的多条弯折连接线可以为同层结构，例如可以位于第二源漏金属层。然而，本实施例对此并不限定。在另一些示例中，弯折区域的多条弯折连接可以位于第一源漏金属层。
在一些示例中，第一信号接入区域B034可以设置有多个第一接触垫，多个第一接触垫可以配置为与外部的柔性电路板(FPC)绑定连接。第二信号接入区域B035可以设置有多个第二接触垫，多个第二接触垫可以配置为连接驱动集成电路(IC)。第一信号接入区域B034内的至少一个第一接触垫和第二信号接入区域B035内的至少一个第二接触垫可以通过走线连接。
在一些示例中，如图5所示，第一边框区域B1可以设置有多条周边控制线。每条周边控制线可以包括：位于第一子区域B01的第一走线段、位于弯折区域B02的控制弯折线、以及位于第二子区域B03的第二走线段；其中，控制弯折线可以连接第一走线段和第二走线段。第一走线段可以至少沿第一方向D1延伸，并沿着显示区域AA的边缘形状向第二边框区域B2延伸。控制弯折线和第二走线段可以沿第一方向D1延伸。图5中以三条周边控制线为例进行示意。
在一些示例中，第一边框区域B1的多条周边控制线可以包括：第一周边控制线L1、以及多条第二周边控制线(例如包括第一条第二周边控制线L2和第二条第二周边控制线L3)。第一周边控制线L1可以配置为传输恒压信号。第一周边控制线L1所传输信号的电位可以低于每条第二周边控制线所传输信号的电位。例如，第一周边控制线L1所传输信号的电位可以为多条周边控制线所传输信号的最低电位。比如，第一周边控制线L1所传输信号的电位可以小于或等于-6V。第一条第二周边控制线L2和第二条第二周边控制线L3可以为与第一周边控制线L1相邻的周边控制线。
在一些示例中，如图5所示，第一周边控制线L1可以包括：位于第一子区域B01的第一走线段41-1、位于弯折区域B02的控制弯折线42-1、以及位于第二子区域B03的第二走线段43-1。控制弯折线42-1可以连接第一走线段41-1和第二走线段43-1。控制弯折线42-1和第二走线段43-1可以沿第一方向D1延伸。第二走线段43-1可以与大致沿第二方向D2延伸的第三走线段44-1连接，第三走线段44-1可以与大致沿第一方向D1延伸的第四走线段45-1连接。例如，第二走线段43-1与第三走线段44-1可以为相互连接的一体结构，例如可以位于第一栅金属层或第二栅金属层；第四走线段45-1与第三走线段44-1可以位于不同导电层，比如第四走线段45-1可以位于第一源漏金属层。然而，本实施例对此并不限定。例如，第二走线段43-1与第三走线段44-1可以位于不同导电层。
在一些示例中，如图5所示，第一条第二周边控制线L2可以包括：位于第一子区域B01的第一走线段41-2、位于弯折区域B02的控制弯折线42-2和位于第二子区域B03的第二走线段43-2。控制弯折线42-2可以连接第一走线段41-2和第二走线段43-2。控制弯 折线42-2和第二走线段43-2可以沿第一方向D1延伸。第二走线段43-2可以与大致沿第二方向D2延伸的第三走线段44-2连接，第三走线段44-2可以与大致沿第一方向D1延伸的第四走线段45-2连接。例如，第二走线段43-2与第三走线段44-2可以为相互连接的一体结构，例如可以位于第一栅金属层或第二栅金属层；第四走线段45-2与第三走线段44-2可以位于不同导电层，比如第四走线段45-2可以位于第一源漏金属层。然而，本实施例对此并不限定。例如，第二走线段43-2与第三走线段44-2可以位于不同导电层。
在一些示例中，如图5所示，第二周边控制线L3可以包括：位于第一子区域B01的第一走线段41-3、位于弯折区域B02的控制弯折线42-3和位于第二子区域B03的第二走线段43-3。控制弯折线42-3可以连接第一走线段41-3和第二走线段43-3。控制弯折线42-3和第二走线段43-3可以沿第一方向D1延伸。第二走线段43-3可以与大致沿第二方向D2延伸的第三走线段44-3连接，第三走线段44-3可以与大致沿第一方向D1延伸的第四走线段45-3连接。例如，第二走线段43-3与第三走线段44-3可以为相互连接的一体结构，例如可以位于第一栅金属层或第二栅金属层；第四走线段45-3与第三走线段44-3可以位于不同导电层，比如第四走线段45-3可以位于第一源漏金属层。然而，本实施例对此并不限定。例如，第二走线段43-3与第三走线段44-3可以位于不同导电层。
在一些示例中，第一周边控制线L1的第一走线段41-1、第一条第二周边控制线L2的第一走线段41-2和第二条第二周边控制线L3的第一走线段41-3可以为同层结构，例如可以均位于第一栅金属层、或者位于第二栅金属层，或者可以为位于第一栅金属层和第二栅金属层的双层走线结构。
在一些示例中，第一周边控制线L1的控制弯折线42-1、第一条第二周边控制线L2的控制弯折线42-2和第二条第二周边控制线L3的控制弯折线42-3可以为同层结构，例如可以均位于第一源漏金属层或第二源漏金属层。
在一些示例中，第一周边控制线L1的第二走线段43-1、第一条第二周边控制线L2的第二走线段43-2和第二条第二周边控制线L3的第二走线段43-3可以为同层结构，例如可以均位于第一栅金属层或第二栅金属层。
在一些示例中，第三走线段44-1、44-2和44-3可以为同层结构，例如可以均位于第一栅金属层或第二栅金属层。第四走线段45-1、45-2和45-3可以为同层结构，例如可以位于第一源漏金属层。
在一些示例中，第一周边控制线L1可以位于第一条第二周边控制线L2和第二条第二周边控制线L3之间，第一条第二周边控制线L2可以位于第一周边控制线L1靠近显示基板的边界XL的一侧。第二条第二周边控制线L3可以位于第一周边控制线L1远离显示基板的边界XL的一侧。
在一些示例中，第一信号接入区域B034的多个第一接触垫可以包括：沿第二方向D2排布的多个控制接触垫(例如包括第一控制接触垫511、第二控制接触垫512和513)。第一控制接触垫511、第二控制接触垫512和513可以沿第二方向D2依次排布。第一控制接触垫511可以位于第二控制接触垫512靠近显示基板的边界XL的一侧。例如，第一控制接触垫511可以为多个第一接触垫中最靠近显示基板的边界XL的接触垫。
在一些示例中，第一周边控制线L1的第二走线段43-1可以通过第三走线段44-1和第四走线段45-1与第一控制接触垫511连接。第一条第二周边控制线L2的第二走线段43-2可以通过第三走线段44-2和第四走线段45-2与第二控制接触垫512连接，第三走线段44-2还可以延伸至第二信号接入区域B035，并与第二信号接入区域B035内的第二接触垫连接。第二条第二周边控制线L3的第二走线段43-3可以通过第三走线段44-3和第 四走线段45-3与第二控制接触垫513连接，第三走线段44-3还可以延伸至第二信号接入区域B035，并与第二信号接入区域B035内的第二接触垫连接。然而，本实施例对此并不限定。在另一些示例中，与第一周边控制线相邻的第二周边控制线可以仅与第一信号接入区域内的第一接触垫连接。
在一些示例中，以多条周边控制线的材料包括金属铝(Al)为例，当靠近显示基板的边界的走线所输出的信号的电位为低电位，环境中的H+浓度高，金属Al与H+发生反应生成Al3+，Al3+与F-/S2-反应生成化合物，从而容易出现边缘走线腐蚀的情况。而针对传输信号的电位为高电位的走线，环境中的OH-浓度高，金属Al与OH-发生反应生成AlO2-，不能生成化合物，可以有效避免走线腐蚀的情况。本示例通过将传输电位最低的第一周边控制线设置在传输电位较高的至少一条第二周边控制线远离显示基板的边界的一侧，可以增加第一周边控制线与显示基板的边界之间的距离，从而防止第一周边控制线发生信赖性腐蚀。
图6为本公开至少一实施例的第一边框区域的局部示意图。在一些示例中，如图6所示，第二子区域B03可以包括：在第一方向D1上沿着远离弯折区域B02依次排布的第二扇出区域B031、电路设置区域B032、第三扇出区域B033、第二信号接入区域B035以及第一信号接入区域B034。然而，本实施例对此并不限定。在另一些示例中，第一边框区域的第二子区域可以包括：在第一方向上沿着远离弯折区域的一侧依次排布的第二扇出区域、第一信号接入区域和第二信号接入区域。
在一些示例中，电路设置区域B032可以至少设置沿第二方向D2排布的多个测试电路。在另一些示例中，在多个测试电路靠近弯折区域B02的一侧可以设置多个防静电电路，在多个测试电路远离弯折区域B02的一侧可以设置多个数据选择电路。然而，本实施例对此并不限定。
在一些示例中，弯折区域B02的多条弯折连接线可以包括：多条数据弯折线(例如包括第一组数据弯折线312a、第二组数据弯折线312b、第三组数据弯折线312c和第四组数据弯折线312d)、多条第一电源弯折线(例如包括第一组第一电源弯折线321a、第二组第一电源弯折线321b、第三组第一电源弯折线321c)、多条第二电源弯折线(例如包括第一组第二电源弯折线331a、第二组第二电源弯折线331b、第三组第二电源弯折线331c和第四组第二电源弯折线331d)、多条控制弯折线(例如包括第一组控制弯折线42a和第二组控制弯折线42b)、多条触控弯折线(例如包括第一组触控弯折线341a和第二组触控弯折线341b)。其中，多条数据弯折线可以配置为传输数据信号。多条第一电源弯折线可以配置为传输第一电压信号VDD，多条第二电源弯折线可以配置为传输第二电压信号VSS。图6中对弯折区域B02内的每组弯折连接线进行了整体示意。
在一些示例中，第一组控制弯折线42a、第一组第二电源弯折线331a、第一组触控弯折线341a、第二组第二电源弯折线331b、第一组数据弯折线312a、第一组第一电源弯折线321a、第二组数据弯折线312b、第二组第一电源弯折线321b、第三组数据弯折线312c、第三组第一电源弯折线321c、第四组数据弯折线312d、第三组第二电源弯折线331c、第二组触控弯折线341b、第四组第二电源弯折线331d、以及第二组控制弯折线42b可以沿第二方向D2依次排布。然而，本实施例对此并不限定。在另一些示例中，弯折区域可以省略设置多条触控弯折线；或者，弯折区域可以设置一组或五组第一电源弯折线。
在一些示例中，第一边框区域B1可以设置有多条周边数据线。多条周边数据线可以包括：位于第一子区域B01内的多条第一数据扇出线(例如包括第一组第一数据扇出线311a和第二组第一数据扇出线311b)、位于第二扇出区域B031内的多条第二数据扇出线(例如包括第一组第二数据扇出线313a和第二组第二数据扇出线313b)、位于弯折区 域B02的多条数据弯折线(例如包括第一组数据弯折线312a、第二组数据弯折线312b、第三组数据弯折线312c和第四组数据弯折线312d)、以及位于第三扇出区域B03内的多条第三数据扇出线(例如包括第一组第三数据扇出线314a和第二组第三数据扇出线314b)。图6中对多条数据弯折线、多条第一数据扇出线、多条第二数据扇出线和多条第三数据扇出线进行了整体示意，本示例对于数据弯折线、第一数据扇出线、第二数据扇出线和第三数据扇出线的数目并不限定。
在一些示例中，多条第一数据扇出线可以与显示区域AA的多条数据线连接，例如，可以一一对应连接。第一组第一数据扇出线311a可以通过第一组数据弯折线312a和第二组数据弯折线312b与第一组第二数据扇出线313a连接，第二组第一数据扇出线311b可以通过第三组数据弯折线312c和第四组数据弯折线312d与第二组第二数据扇出线313b连接。例如，多条第一数据扇出线与多条数据弯折线可以一一对应连接，多条数据弯折线可以与多条第二数据扇出线一一对应连接。第一组第二数据扇出线313a可以与第一组第三数据扇出线314a连接，第二组第二数据扇出线313b可以与第二组第三数据扇出线314b连接。例如，一条第三数据扇出线可以与多条第二数据扇出线连接。本实施例对此并不限定。
在一些示例中，第二信号接入区域B035的多个第二接触垫可以包括：多个数据接触垫315。多条第三数据扇出线可以与第二信号接入区域B035内的多个数据接触垫315电连接。
在一些示例中，第一边框区域B1可以设置有至少沿第一方向D1延伸的多条周边控制线。多条周边控制线可以包括第一组周边控制线和第二组周边控制线，第一组周边控制线和第二组周边控制线可以沿第二方向D2位于多条周边数据线的两侧。换言之，多条周边数据线在第二方向D2上可以位于多条周边控制线的中间。每条周边控制线可以包括：位于第一子区域B01的第一走线段、位于弯折区域B02的控制弯折线以及位于第二子区域B03的第二走线段。
在一些示例中，第一子区域B01的多条第一走线段可以包括：第一组第一走线段41a和第二组第一走线段41b。图6中以第一子区域B01的若干条第一走线段为例进行示意。本实施例对于第一走线段的数目并不限定。第一组第一走线段41a和第二组第一走线段41b在第二方向D2上可以位于多条第一数据扇出线的两侧。其中，第一组第一走线段41a在第二方向D2上可以位于第一组第一数据扇出线311a靠近显示基板的边界的一侧，第二组第一走线段41b在第二方向D2上可以位于第二组第一数据扇出线311b靠近显示基板的边界的一侧。
在一些示例中，第二子区域B03的多条第二走线段可以包括：第一组第二走线段43a和第二组第二走线段43b。图6中以第二子区域B03的若干条第二走线段为例进行示意。本实施例对于第二走线段的数目并不限定。第一组第二走线段43a和第二组第二走线段43b在第二方向D2上可以位于多条第二数据扇出线和多条第三数据扇出线的两侧。其中，第一组第二走线段43a在第二方向D2上可以位于第一组第二数据扇出线313a和第一组第三数据扇出线314a靠近显示基板的边界的一侧，第二组第二走线段43b在第二方向D2上可以位于第二组第二数据扇出线313b和第二组第三数据扇出线314b靠近显示基板的边界的一侧。
在一些示例中，第一子区域B01内的第一组第一走线段41a可以通过弯折区域B02内的第一组控制弯折线42a与第二子区域B03内的第一组第二走线段43a连接；第一子区域B01内的第二组第一走线段41b可以通过弯折区域B02内的第二组控制弯折线42b与第二子区域B03内的第二组第二走线段43b连接。
在一些示例中，第二子区域B03还可以设置有多条第三走线段(例如包括第一组第三走线段44a和第二组第三走线段44b)和多条第四走线段(例如包括第一组第四走线段45a和第二组第四走线段45b)。多条周边控制线中的一部分周边控制线的第二走线段可以通过沿第二方向D2延伸的第三走线段与第二信号接入区域B035内的第一接触垫连接，还可以通过沿第二方向D2延伸的第三走线段和沿第一方向D1延伸的第四走线段与第一信号接入区域B034内的第一接触垫连接。多条周边控制线中的另一部分周边控制线的第二走线段可以不与第二信号接入区域B035内的第二接触垫连接，而是通过沿第二方向D2延伸的第三走线段和沿第一方向D1延伸的第四走线段与第一信号接入区域B034内的第一接触垫连接。例如，所述另一部分周边控制线中的至少一条周边控制线还可以通过沿第二方向D2延伸的第三走线段与位于电路设置区域内的测试电路连接。
在一些示例中，位于第二边框区域B2的多个栅极驱动电路的排布方式可以如图3所示，左边框区域B21内的第一组栅极驱动电路和右边框区域B22内的第二组栅极驱动电路的数目和排布方式都相同。第一组周边控制线中的一部分周边控制线可以与第一组栅极驱动电路连接，第二组周边控制线中的一部分周边控制线可以与第二组栅极驱动电路连接。位于多条周边数据线两侧的第一组周边控制线和第二组周边控制线的数目和类型可以相同。例如，第一组周边控制线和第二组周边控制线可以关于第一边框区域B1的平行于第一方向D1的中线大致对称设置。然而，本实施例对此并不限定。在另一些示例中，在第一组栅极驱动电路和第二组栅极驱动电路内的栅极驱动电路的数目或类型不同时，第一组周边控制线和第二组周边控制线的走线数目或类型可以不同。
图7为图6中区域S1的局部放大示意图。图7以第一组周边控制线为例进行说明。关于第二组周边控制线的说明可以参照第一组周边控制线的描述，故于此不再赘述。
在一些示例中，如图7所示，第一组周边控制线可以包括：第一初始控制线VI1、第二初始控制线VI2、第三初始控制线VI3、第五电压控制线VGH-N、第四电压控制线VGH、发光驱动输出线Eout、第五起始信号线ESTV、第十三时钟信号线ECB、第十二时钟信号线ECK、第十四时钟信号线ECX、第十时钟信号线HCB、第九时钟信号线HCK、第四起始信号线HSTV、第二复位驱动输出线Hout、第一复位驱动输出线Pout、第三起始信号线PSTV、第七时钟信号线PCB、第六时钟信号线PCK、第八时钟信号线PCX、第四时钟信号线NCB、第三时钟信号线NCK、第二起始信号线NSTV、第一电压控制线VGL1、第二电压控制线VGL2、第三电压控制线VGL3、第二扫描驱动输出线Nout、第二时钟信号线GCB、第一时钟信号线GCK、第一起始信号线GSTV、第十一时钟信号线HCX、第五时钟信号线NCX、第一扫描驱动输出线Gout、第一面板检测线PCD1、第二面板检测线PCD2。
在一些示例中，在第一子区域内，第一初始控制线VI1、第二初始控制线VI2、第三初始控制线VI3、第五电压控制线VGH-N、第四电压控制线VGH、第五起始信号线ESTV、第十三时钟信号线ECB、第十二时钟信号线ECK、第十四时钟信号线ECX、第十时钟信号线HCB、第九时钟信号线HCK、第四起始信号线HSTV、第三起始信号线PSTV、第七时钟信号线PCB、第六时钟信号线PCK、第八时钟信号线PCX、第四时钟信号线NCB、第三时钟信号线NCK、第二起始信号线NSTV、第一电压控制线VGL1、第二电压控制线VGL2、第三电压控制线VGL3、第二时钟信号线GCB、第一时钟信号线GCK、第一起始信号线GSTV、第十一时钟信号线HCX、第五时钟信号线NCX可以均采用位于第一栅金属层和第二栅金属层的双层走线设计。发光驱动输出线Eout、第二复位驱动输出线Hout、第一复位驱动输出线Pout、第二扫描驱动输出线Nout、第一扫描驱动输出线Gout、第一面板检测线PCD1、第二面板检测线PCD2可以为位于第一栅金属层的单层走线。
在一些示例中，第一起始信号线GSTV、第一时钟信号线GCK、第二时钟信号线GCB和第一扫描驱动输出线Gout可以与位于左边框区域B21内的第一扫描驱动电路21a电连接。第一起始信号线GSTV可以配置为给第一扫描驱动电路21a提供起始信号，第一时钟信号线GCK和第二时钟信号线GCB可以配置为给第一扫描驱动电路21a提供时钟信号，第一扫描驱动输出线Gout可以配置与第一扫描驱动电路21a的最后一级第一扫描驱动单元的输出端连接。
在一些示例中，第二起始信号线NSTV、第三时钟信号线NCK、第四时钟信号线NCB、第五时钟信号线NCX和第二扫描驱动输出线Nout可以与左边框区域B21内的第二扫描驱动电路22a电连接。第二起始信号线NSTV可以配置为给第二扫描驱动电路22a提供起始信号，第三时钟信号线NCK、第四时钟信号线NCB和第五时钟信号线NCK可以配置为给第二扫描驱动电路22a提供时钟信号，第二扫描驱动输出线Nout可以配置为与第二扫描驱动电路22a的最后一级第二扫描驱动单元的输出端连接。
在一些示例中，第三起始信号线PSTV、第六时钟信号线PCK、第七时钟信号线PCB、第八时钟信号线PCX和第一复位驱动输出线Pout可以与左边框区域B21内的第一复位驱动电路23a电连接。第三起始信号线PSTV可以配置为给第一复位驱动电路23a提供起始信号，第六时钟信号线PCK、第七时钟信号线PCB和第八时钟信号线PCX可以配置为给第一复位驱动电路23a提供时钟信号，第一复位驱动输出线Pout可以配置为与第一复位驱动电路23a的最后一级第一复位驱动单元的输出端连接。
在一些示例中，第四起始信号线HSTV、第九时钟信号HCK、第十时钟信号HCB、第十一时钟信号HCX和第二复位驱动输出线Hout可以与左边框区域B21内的第二复位驱动电路24a电连接。第四起始信号线HSTV可以配置为给第二复位驱动电路24a提供起始信号，第九时钟信号HCK、第十时钟信号HCB和第十一时钟信号HCX可以配置为给第二复位驱动电路24a提供时钟信号，第二复位驱动输出线Hout可以配置为与第二复位驱动电路24a的最后一级第二复位驱动单元的输出端连接。
在一些示例中，第五起始信号线ESTV、第十二时钟信号ECK、第十三时钟信号ECB、第十四时钟信号ECX和发光驱动输出线Eout可以与左边框区域B21内的发光驱动电路25a电连接。第五起始信号线ESTV可以配置为给发光驱动电路25a提供起始信号，第十二时钟信号ECK、第十三时钟信号ECB、第十四时钟信号ECX可以配置为发光驱动电路25a提供时钟信号，发光驱动输出线Eout可以配置为与发光驱动电路25a的最后一级发光驱动单元的输出端连接。
在一些示例中，第五电压控制线VGH-N可以与左边框区域B21内的第二扫描驱动电路22a电连接，配置为给第二扫描驱动电路22a提供第七电压信号。第四电压控制线VGH可以与左边框区域B21内的第一扫描驱动电路21a、第一复位驱动电路23a、第二复位驱动电路24a和发光驱动电路25a电连接，配置为提供第六电压信号。第五电压信号和第六电压信号可以为恒压信号，且第六电压信号可以不同于第五电压信号。
在一些示例中，第一电压控制线VGL1可以与左边框区域B21内的第一扫描驱动电路21a、第一复位驱动电路23a、第二复位驱动电路24a和发光驱动电路25a电连接，配置为提供第三电压信号。第二电压控制线VGL2可以与左边框区域B21内的第二扫描驱动电路22a电连接，配置为提供第四电压信号。第三电压控制线VGL3可以与左边框区域B21内的第二扫描驱动电路22a电连接，配置为提供第五电压信号。
在一些示例中，第三电压信号、第四电压信号和第五电压信号可以为恒压信号，且第三电压信号、第四电压信号和第五电压信号的电位可以均小于或等于-6V。第一电压控制 线VGL1提供的第三电压信号与第三电压控制线VGL3提供的第五电压信号可以大致相同，第二电压控制线VGL2提供的第四电压信号可以不同于第三电压控制线VGL3提供的第五电压信号。例如，第四电压信号的电位可以小于或等于第五电压信号的电位。在一些示例中，第三电压信号和第五电压信号的电位范围可以均为-6V至-10V，第四电压信号的电位范围可以为-6V至-12V。本示例通过给第二扫描驱动电路提供两路低电位的恒压信号，可以有利于保证第二扫描驱动电路的性能。
在一些示例中，第一初始控制线VI1可以配置为提供第一初始信号，第二初始控制线VI2可以配置为提供第二初始信号，第三初始控制线VI3可以配置为提供第三初始信号。第一初始控制线VI1可以与显示区域的第一初始信号线连接，配置为给像素电路的第一复位晶体管提供第一初始信号。第二初始控制线VI2可以与显示区域的第二初始信号线连接，配置为给像素电路的第二复位晶体管提供第二初始信号。第三初始控制线VI3可以与显示区域的第三初始信号线连接，配置为给像素电路的第三复位晶体管提供第三初始信号。
在一些示例中，第一面板检测线PCD1和第二面板检测线PCD2可以配置为传输检测显示基板的周边是否存在裂纹的信号。
在一些示例中，第一组周边控制线中的第一初始控制线VI1、第二初始控制线VI2、第三初始控制线VI3、第一面板检测线PCD1和第二面板检测线PCD2与多个栅极驱动电路没有直接电连接，其余走线与多个栅极驱动电路存在电连接。
在一些示例中，如图7所示，第一初始控制线VI1、第二初始控制线VI2、第三初始控制线VI3、第五电压控制线VGH-N、第四电压控制线VGH、发光驱动输出线Eout、第五起始信号线ESTV、第十三时钟信号线ECB、第十二时钟信号线ECK、第十四时钟信号线ECX、第十时钟信号线HCB、第九时钟信号线HCK、第四起始信号线HSTV、第二复位驱动输出线Hout、第一复位驱动输出线Pout、第三起始信号线PSTV、第七时钟信号线PCB、第六时钟信号线PCK、第八时钟信号线PCX、第四时钟信号线NCB、第三时钟信号线NCK、第二起始信号线NSTV、第一电压控制线VGL1、第二电压控制线VGL2、第三电压控制线VGL3、第二扫描驱动输出线Nout、第二时钟信号线GCB、第一时钟信号线GCK、第一起始信号线GSTV、第十一时钟信号线HCK、第五时钟信号线NCK、第一扫描驱动输出线Gout、第一面板检测线PCD1、第二面板检测线PCD2可以沿着远离显示基板的边界的方向依次排布。
在本示例中，多条第一周边控制线可以包括：第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3，其余周边控制线均为前述实施例所述的第二周边控制线。本示例中，第一条第二周边控制线可以为第二起始信号线NSTV，第二条第二周边控制线可以为第二扫描驱动输出线Nout，三条第一周边控制线可以位于第二起始信号线NSTV和第二扫描驱动输出线Nout之间。第二起始信号线NSTV和第二扫描驱动输出线Nout所传输信号较为稳定，对三条第一周边控制线所传输信号的影响较小。然而，本实施例对此并不限定。在另一些示例中，第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3可以位于其余第二周边控制线之间，例如可以位于第一扫描驱动输出线Gout和第一面板检测线PCD1之间，或者，可以位于第一复位驱动输出线Pout和第二复位驱动输出线Hout之间。在另一些示例中，第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3可以位于多条第二周边控制线靠近周边数据线的一侧，例如，可以位于第二面板检测线PCD2远离第一面板检测线PCD1的一侧。
在一些示例中，第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3沿着远离显示基板的边界的方向依次排布。本示例的多条第一周边控制线与显示基 板的边界之间的最小距离可以为第一电压控制线VGL1与显示基板的边界之间的最小距离。第一电压控制线VGL1与显示基板的边界之间的最小距离W2可以为第一电压控制线VGL1靠近显示基板的边界的边缘与显示基板的边界之间的距离。W2可以大于或等于1250微米，例如可以约为2067微米。
在一些示例中，第一组周边控制线中最靠近显示基板的边界的走线是第一初始控制线VI1，第一初始控制线VI1与显示基板的边界之间的最小距离W1可以为第一初始控制线VI1靠近显示基板的边界的边缘与显示基板的边界之间的距离。W1可以大于或等于400微米，例如可以约为535微米。
在一些示例中，第一初始控制线VI1所传输信号的电位高于第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3所传输信号的电位，例如，第一初始控制线VI1所传输信号的电位范围可以为-3V至-4V。
本示例通过将多条第一周边控制线(包括第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3)远离显示基板的边界设置，可以防止第一周边控制线发生信赖性腐蚀情况，有利于避免显示基板产生黑屏、黄屏等显示问题。
在另一些示例中，第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3中的至少两条可以插设在不同的第二周边走线之间。例如，第二电压控制线VGL2和第三电压控制线VGL3可以位于第二起始信号线NSTV和第二扫描驱动输出线Nout之间，第一电压控制线VGL1可以位于第一复位驱动输出线Pout和第二复位驱动输出线Hout之间。本实施例对此并不限定。只要保证第一电压控制线VGL1、第二电压控制线VGL2和第三电压控制线VGL3不位于最靠近显示基板的边界的位置即可。
图8为本公开至少一实施例的第一边框区域的另一局部走线示意图。图8以第一边框区域靠近显示基板的左侧的边界XL的区域为例进行说明。在一些示例中，如图8所示，第一周边控制线L1与第一控制接触垫511连接，第一条第二周边控制线L2与第二控制接触垫512连接，第二条第二周边控制线L3与第二控制接触垫513连接。在第一信号接入区域B034内，第一控制接触垫511可以位于第二控制接触垫512和513之间。
本示例通过将第一周边控制线所连接的第一控制接触垫设置在相邻第二周边控制线所连接的第二控制接触垫之间，可以便于第一周边控制线和第二周边控制线的排布。关于本示例的其余说明可以参照图5所示实施例的描述，故于此不再赘述。
图9为本公开至少一实施例的第一边框区域的另一局部走线示意图。图9以第一边框区域靠近显示基板的左侧的边界XL的区域为例进行说明。在一些示例中，如图9所示，第一周边控制线L1与第一控制接触垫511连接，第一条第二周边控制线L2与第二控制接触垫512连接，第二条第二周边控制线L3与第二控制接触垫513连接。在第一信号接入区域B034内，第一控制接触垫511可以位于第二控制接触垫513远离显示基板的边界的一侧。
本示例通过将第一周边控制线所连接的第一控制接触垫设置在相邻的第二条第二周边控制线所连接的第二控制接触垫远离显示基板的边界的一侧，可以有利于保证第一周边控制线的信号传输，避免相邻的第二周边控制线传输的信号对第一周边控制线所传输信号产生干扰。关于本示例的其余说明可以参照图5所示实施例的描述，故于此不再赘述。
在另一些示例中，第一组周边控制线中的第一周边控制线所连接的第一控制接触垫可以位于其余所有第二周边控制线所连接的第二控制接触垫远离显示基板的边界的一侧。换言之，第一控制接触垫可以不插设在多个第二控制接触垫内，而是位于第一组周边控制线所连接的多个第二控制接触垫远离显示基板的边界的一侧。
图10为本公开至少一实施例的第一边框区域的另一局部走线示意图。图10以第一边框区域靠近显示基板的左侧的边界XL的区域为例进行说明。在一些示例中，如图10所示，第一周边控制线L1所连接的第三走线段44-3可以位于第二条第二周边控制线L3所连接的第三走线段44-3靠近弯折区域B02的一侧。第三走线段44-1、44-3、44-2可以沿着远离弯折区域B02的方向排布。本示例通过调整第二子区域内的走线排布，可以便于第一周边控制线与第一控制接触垫的连接，避免第二周边控制线传输的信号对第一周边控制线传输的信号产生干扰。关于本示例的其余说明可以参照图9所示实施例的描述，故于此不再赘述。
图11为本公开至少一实施例的第一边框区域的另一局部示意图。在一些示例中，第一子区域B01可以设置有多个静电释放电路。多个静电释放电路可以与第二边框区域B2内的多个栅极驱动电路邻近。比如，第一子区域B01可以包括与左边框区域B21连通的第一拐角区域、以及与右边框区域B22连通的第二拐角区域。多个静电释放电路可以位于第一拐角区域和第二拐角区域。图11以第一拐角区域的多个静电释放电路的排布为例进行说明。
在一些示例中，如图11所示，第一子区域B01内的多个静电释放电路可以沿第一方向D1排布为多行，每行静电释放电路可以包括沿第二方向D2排布的多个静电释放电路。例如，多个静电释放电路可以排布为第一行静电释放电路61a、第二行静电释放电路61b和第三行静电释放电路61c。第一行静电释放电路61a、第二行静电释放电路61b和第三行静电释放电路61c可以沿着远离显示区域的方向依次设置。
在一些示例中，第一周边控制线L1的位于第一子区域B01内的第一走线段41-1可以与多个静电释放电路连接。第一周边控制线L1的第一走线段41-1可以大致沿着显示区域的弧形边缘向第二边框区域的左边框区域B21延伸。第一周边控制线L1的第一走线段41-1可以位于第一行静电释放电路61a和第二行静电释放电路61b之间。相较于第一周边控制线从多行静电释放电路的同一侧绕过，本示例中第一周边控制线的走线方式可以适应于第一周边控制线远离显示基板的边界的位置，可以减少第一周边控制线的长度，从而有利于降低负载。
图12为本公开至少一实施例的静电释放电路的等效电路图。在一些示例中，如图12所示，静电释放电路可以与一条周边控制线CL连接，且配置为释放其连接的周边控制线CL中的静电。静电释放电路可以包括：第一释放晶体管ST1至第四释放晶体管ST4。第一释放晶体管ST1的第一极可以与第三电压控制线VGL1电连接，第一释放晶体管ST1的栅极和第二极与第二释放晶体管ST2的第一极电连接，第二释放晶体管ST2的栅极和第二极与第一静电释放电路对应的周边控制线CL电连接，第三释放晶体管ST3的第一极与第一静电释放电路对应的周边控制线CL电连接，第三释放晶体管ST3的栅极和第二极与第四释放晶体管ST4的第一极电连接，第四释放晶体管ST4的栅极和第二极与第四电压线VGH电连接。
在一种示例中，设置静电释放电路可以防止周边控制线中的静电积累而引起放电击穿导致损坏，以释放周边控制线中积累的静电，实现对周边控制线的保护。
在另一种示例中，静电释放电路可以包括两个释放晶体管，其中，每个释放晶体管的一极都和自身的栅极连接，从而形成等效的二极管连接；而两个“二极管”之间连接要保护的信号线，两个“二极管”的另外两端分别连接第四电压控制线VGH和第一电压控制线VGL1。由此，当信号线中因积累正电荷出现瞬时高压(如100V)时，其中一个“二极管”导通，释放信号线中的正电荷；而当信号线中因积累负电荷出现瞬时低压(如-100V)时，另一个“二极管”导通，释放信号线中的负电荷。
图13为图6中区域S2的局部放大示意图。图14为图13中第一半导体层、第一栅金属层和第二栅金属层的示意图。图13和图14以第一子区域的第一拐角区域的多个静电释放电路的排布为例进行说明。
在一些示例中，如图13和图14所示，第一子区域内的多个静电释放电路包括：第一行静电释放电路61a、第二行静电释放电路61b和第三行静电释放电路61c。位于同一行的多个静电释放电路的释放晶体管的有源层可以为相互连接的一体结构。例如，该一体结构可以为沿第二方向D2延伸的条状结构。多个释放晶体管的有源层可以位于第一半导体层。位于同一行中的相邻静电释放电路的四个释放晶体管的排布顺序可以相反，例如，第一行静电释放电路中在第二方向D2上的第一个静电释放电路的第一释放晶体管至第四释放晶体管沿第二方向D2排布，第二个静电释放电路的第四释放晶体管至第一释放晶体管可以沿第二方向D2排布。
在一些示例中，如图13和图14所示，第三电压控制线VGL3、第二电压控制线VGL2、第一电压控制线VGL1可以位于第一行静电释放电路61a和第二行静电释放电路61b之间，且可以在第一方向D1上沿着远离第一行静电释放电路61a的方向依次排布。
在一些示例中，第一行静电释放电路61a、第二行静电释放电路61b和第三行静电释放电路61c可以通过第一连接线621、第二连接线622、第三连接线623和第四连接线624与第一电压控制线VGL1连接。第一连接线621、第二连接线622、第三连接线623和第四连接线624可以沿第一方向D1延伸，并沿第二方向D2排布。第四电压控制线VGH可以位于第三行静电释放电路61c远离第二行静电释放电路61b的一侧，并可以通过沿第一方向D1延伸的四条连接线与三行静电释放电路电连接。
在一些示例中，第一行静电释放电路61a可以包括六个静电释放电路，沿着第二方向D2排布的六个静电释放电路可以依次与第二起始信号线NSTV、第三时钟信号线NCK、第二时钟信号线GCB、第一时钟信号线GCK、第一起始信号线GSTV和第十一时钟信号线HCX连接，起到静电防护作用。
在一些示例中，第二行静电释放电路61b可以包括六个静电释放电路，第二行静电释放电路61b的六个静电释放电路可以与第一行静电释放电路61a的六个静电释放电路在第一方向D1上对齐设置。第二行静电释放电路61b的沿着第二方向D2排布的六个静电释放电路可以依次与第七时钟信号线PCB、第六时钟信号线PCK、第四时钟信号线NCB、第八时钟信号线PCX、第七时钟信号线PCB、第四起始信号线HSTV连接，起到静电防护作用。
在一些示例中，第三行静电释放电路61c可以包括七个静电释放电路，其中六个静电释放电路可以与第一行静电释放电路61a的六个静电释放电路在第一方向D1上对齐设置。第三行静电释放电路61c的沿着第二方向D2排布的七个静电释放电路可以依次与第九时钟信号线HCK、第十二时钟信号线ECK、第十时钟信号线HCB、第十四时钟信号线ECX、第十三时钟信号线ECB、第五起始信号线ESTV、第五时钟信号线NCX连接，起到静电防护作用。
在一些示例中，第一面板检测线PCD1可以通过位于第一源漏金属层的第一检测连接线633与位于第一栅金属层的第二检测连接线631连接。第二面板检测线PCD2可以通过位于第一源漏金属层的第三检测连接线634与位于第一栅金属层的第四检测连接线632连接。
在一些示例中，第一子区域还可以设置位于第一源漏金属层的第二电源边框线342，第二电源边框线342可以与弯折区域的第一组第二电源弯折线331a和第二组第二电源弯 折线331b连接，以配置为传输第二电压信号VSS。
关于第一子区域的第二拐角区域的结构与第一拐角区域的结构类似，故于此不再赘述。
图15为本公开至少一实施例的显示装置的示意图。在一些示例中，如图15所示，显示基板910可以为OLED显示基板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (15)

  1. 一种显示基板，包括显示区域和位于所述显示区域周围的边框区域，所述边框区域包括：相互连通的第一边框区域和第二边框区域，所述第一边框区域至少包括：沿第一方向位于所述显示区域一侧的弯折区域；
    所述显示基板包括：
    衬底；
    多个子像素，设置在所述衬底的一侧且位于所述显示区域；
    多个栅极驱动电路，位于所述第二边框区域，并与所述多个子像素电连接，配置为向所述多个子像素提供多种像素控制信号；
    至少一条第一周边控制线，位于所述第一边框区域，并与所述多个栅极驱动电路连接；
    多条第二周边控制线，位于所述第一边框区域，所述多条第二周边控制线中的一部分第二周边控制线与所述多个栅极驱动电路连接；每条第一周边控制线所传输信号的电位低于每条第二周边控制线所传输信号的电位；
    在所述弯折区域，所述多条第二周边控制线中的至少一条第二周边控制线位于所述至少一条第一周边控制线与所述显示基板的边界之间。
  2. 根据权利要求1所述的显示基板，还包括：位于所述第一边框区域的多条周边数据线，所述多条周边数据线与所述多个子像素电连接，配置为给所述多个子像素提供数据信号；在第二方向上，所述多条第二周边控制线和所述至少一条第一周边控制线位于所述多条周边数据线与所述显示基板的边界之间；所述第二方向与所述第一方向交叉。
  3. 根据权利要求1所述的显示基板，其中，在所述弯折区域，所述至少一条第一周边控制线与所述显示基板的边界之间的最小距离大于或等于1250微米。
  4. 根据权利要求1所述的显示基板，其中，所述至少一条第一周边控制线配置为传输恒压信号，所述恒压信号的电位小于或等于-6V。
  5. 根据权利要求1所述的显示基板，其中，所述多个子像素中的至少一个子像素包括：像素电路以及与所述像素电路连接的发光元件；
    所述像素电路至少包括：驱动晶体管、数据写入晶体管和补偿晶体管；
    所述数据写入晶体管的栅极与第一扫描线连接，所述数据写入晶体管的第一极与数据线连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极连接；
    所述驱动晶体管的栅极与所述补偿晶体管的第二极连接，所述驱动晶体管的第二极与所述补偿晶体管的第一极连接，所述补偿晶体管的栅极与第二扫描线连接；
    所述多个栅极驱动电路包括：至少一个第一扫描驱动电路、以及至少一个第二扫描驱动电路，所述至少一个第一扫描驱动电路配置为给所述第一扫描线提供第一扫描信号，所述至少一个第二扫描驱动电路配置为给所述第二扫描线提供第二扫描信号；
    所述多条第二周边控制线至少包括：与所述至少一个第二扫描驱动电路连接的第二起始信号线和第二扫描驱动输出线；
    所述至少一条第一周边控制线位于所述第二起始信号线和所述第二扫描驱动输出线之间。
  6. 根据权利要求5所述的显示基板，其中，所述像素电路还包括：第一复位晶体管， 所述第一复位晶体管的栅极与第一复位控制线连接，所述第一复位晶体管的第一极配置为接收第一初始信号，所述第一复位晶体管的第二极与所述驱动晶体管的第二极连接；
    在所述弯折区域，所述多条第二周边控制线中最靠近所述显示基板的边界的第二周边控制线配置为传输所述第一初始信号。
  7. 根据权利要求1或6所述的显示基板，其中，在所述弯折区域，所述多条第二周边控制线中最靠近所述显示基板的边界的第二周边信号线与所述显示基板的边界之间的最小距离大于或等于400微米。
  8. 根据权利要求1所述的显示基板，其中，所述第一边框区域还包括：位于所述弯折区域远离所述显示区域一侧的第一信号接入区域；
    所述显示基板还包括：位于所述第一信号接入区域且沿第二方向排布的多个第一接触垫；所述第二方向与所述第一方向交叉；
    所述多个第一接触垫包括：与所述至少一条第一周边控制线连接的至少一个第一控制接触垫、以及与所述多条第二周边控制线连接的多个第二控制接触垫；
    在所述第二方向上，所述多个第二控制接触垫中的至少一个第二控制接触垫位于所述至少一个第一控制接触垫与所述显示基板的边界之间。
  9. 根据权利要求8所述的显示基板，其中，所述至少一条第一周边控制线位于第一条第二周边控制线和第二条第二周边控制线之间；
    在所述第二方向上，所述至少一个第一控制接触垫位于所述第一条第二周边控制线所连接的第二控制接触垫与所述第二条第二周边控制线所连接的第二控制接触垫之间。
  10. 根据权利要求8所述的显示基板，其中，所述至少一条第一周边控制线位于第一条第二周边控制线和第二条第二周边控制线之间；所述第一条第二周边控制线位于所述至少一条第一周边控制线靠近所述显示基板的边界的一侧；
    在所述第二方向上，所述至少一个第一控制接触垫位于所述第二条第二周边控制线所连接的第二控制接触垫远离所述显示基板的边界的一侧。
  11. 根据权利要求1所述的显示基板，其中，所述第一边框区域还包括：位于所述弯折区域靠近所述显示区域一侧的第一子区域，所述第一子区域与所述第二边框区域连通；
    所述显示基板还包括：位于所述第一子区域的多个静电释放电路，所述多个静电释放电路与所述多个栅极驱动电路邻近设置；
    所述多个静电释放电路沿所述第一方向排布为多行，每行静电释放电路包括沿第二方向设置的多个静电释放电路；所述第二方向与所述第一方向交叉；
    所述至少一条第一周边信号线位于相邻两行静电释放电路之间。
  12. 根据权利要求11所述的显示基板，其中，所述多个静电释放电路按照远离所述显示区域的方向排布为第一行静电释放电路、第二行静电释放电路和第三行静电释放电路，所述至少一条第一周边信号线位于所述第一行静电释放电路和所述第二行静电释放电路之间。
  13. 根据权利要求11或12所述的显示基板，包括多条第一周边控制线，所述多个静电释放电路与其中一条第一周边控制线连接。
  14. 根据权利要求1所述的显示基板，其中，所述多个栅极驱动电路包括沿第二方向位于所述显示区域两侧的第一组栅极驱动电路和第二组栅极驱动电路，所述第二方向与所述第一方向交叉；
    所述第一组栅极驱动电路与至少一条第一周边控制线连接，所述第二组栅极驱动电路与至少一条第一周边控制线连接；
    所述第一组栅极驱动电路包括的栅极驱动电路的数目与所述第二组栅极驱动电路包括的栅极驱动电路的数目相同。
  15. 一种显示装置，包括如权利要求1至14中任一项所述的显示基板。
PCT/CN2024/084985 2024-03-29 2024-03-29 显示基板及显示装置 Pending WO2025200000A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019101062A (ja) * 2017-11-28 2019-06-24 株式会社ジャパンディスプレイ 表示装置
CN113589600A (zh) * 2021-06-24 2021-11-02 上海中航光电子有限公司 一种显示面板及显示装置
CN115294889A (zh) * 2022-08-30 2022-11-04 京东方科技集团股份有限公司 显示基板、显示面板及显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019101062A (ja) * 2017-11-28 2019-06-24 株式会社ジャパンディスプレイ 表示装置
CN113589600A (zh) * 2021-06-24 2021-11-02 上海中航光电子有限公司 一种显示面板及显示装置
CN115294889A (zh) * 2022-08-30 2022-11-04 京东方科技集团股份有限公司 显示基板、显示面板及显示装置

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