WO2025199863A1 - 显示模组及其制备方法、显示面板 - Google Patents

显示模组及其制备方法、显示面板

Info

Publication number
WO2025199863A1
WO2025199863A1 PCT/CN2024/084393 CN2024084393W WO2025199863A1 WO 2025199863 A1 WO2025199863 A1 WO 2025199863A1 CN 2024084393 W CN2024084393 W CN 2024084393W WO 2025199863 A1 WO2025199863 A1 WO 2025199863A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
display module
touch
trace
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/084393
Other languages
English (en)
French (fr)
Inventor
张元其
李伟
刘庭良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2024/084393 priority Critical patent/WO2025199863A1/zh
Priority to CN202480000633.4A priority patent/CN121220222A/zh
Publication of WO2025199863A1 publication Critical patent/WO2025199863A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the present application relates to the field of display technology, and in particular to a display module and a preparation method thereof, and a display panel.
  • This application provides a display module and a manufacturing method thereof, and a display panel.
  • the technical solutions are as follows:
  • the base substrate having a display area and a peripheral area surrounding the display area, the peripheral area including a binding area located on one side of the display area;
  • the plurality of binding interfaces being located in the binding area and connected to the touch electrodes;
  • first ends of the connecting traces are connected to the binding interface, a width of a first target portion of the connecting traces is smaller than a width of the binding interface, and a distance between adjacent first target portions of the connecting traces is greater than a distance between adjacent binding interfaces;
  • the width of the first end of the connecting line is greater than the first target portion of the connecting line. width.
  • the first target portion of the connecting line has a first boundary and a second boundary that are opposite to each other, and the first end of the connecting line has a third boundary and a fourth boundary that are opposite to each other;
  • the first boundary and the third boundary are collinear and constitute a common boundary of the connecting trace, and the second boundary is closer to the common boundary than the fourth boundary;
  • the first boundary, the second boundary, the third boundary, and the fourth boundary all extend along the extending direction of the connecting line.
  • the width of the transition portion close to the first end of the connecting trace is equal to the width of the first end of the connecting trace
  • the width of the transition portion close to the first target portion is equal to the width of the first target portion
  • the width of the transition portion decreases as the distance from the first end increases.
  • the transition portion has a fifth boundary and a sixth boundary opposite to each other;
  • the fifth boundary and the sixth boundary are both straight lines, and the angle between the boundary of the fifth boundary and the sixth boundary that intersects with the extension direction of the connecting line and the extension direction of the connecting line is an obtuse angle.
  • the display module includes an active layer, a gate insulating layer, and a gate layer stacked on the base substrate; the connecting wire is located in the gate layer;
  • the switching transistor includes an active pattern located in the active layer; an orthographic projection of a first end of the active pattern on the base substrate overlaps with an orthographic projection of the first sub-route on the base substrate, and the first end of the active pattern serves as a first electrode of the switching transistor and is connected to the first sub-route through a first via in the gate insulating layer; an orthographic projection of a second end of the active pattern on the base substrate overlaps with an orthographic projection of the second sub-route on the base substrate, and the second end of the active pattern serves as a second electrode of the switching transistor and is connected to the second sub-route through a second via in the gate insulating layer;
  • the switching transistor further includes a gate pattern located in the gate layer, the orthographic projection of the gate pattern on the base substrate overlaps with the orthographic projection of the active pattern on the base substrate, and the gate pattern serves as the gate of the switching transistor and is connected to the signal transmission line.
  • An orthographic projection of the signal transmission line on the base substrate overlaps with an orthographic projection of the gate pattern on the base substrate, and the gate pattern is connected to the signal transmission line through a third via hole in the interlayer dielectric layer.
  • the anode layer, the light-emitting layer, and the cathode layer are used to constitute the plurality of pixel units;
  • the display module further includes a first connecting portion located on the first source-drain electrode layer, and a second connecting portion located on the second source-drain electrode layer;
  • the first end of the connecting trace is connected to the first connecting portion through a via in the interlayer dielectric layer, the first connecting portion and the second connecting portion are connected through a via in the first flat layer, and the second connecting portion is connected through a via in the second flat layer, the pixel defining layer, the encapsulation layer and the touch insulating layer.
  • a touch film layer is located on a side of the plurality of pixel units away from the base substrate, and the touch film layer at least includes a touch electrode;
  • the display module also includes: a switching transistor and a signal transmission line, the first electrode of the switching transistor is connected to the first sub-line, the second electrode of the switching transistor is connected to the second sub-line, and the gate of the switching transistor is connected to the signal transmission line.
  • the switching transistor is used to receive a shutdown signal provided from the signal transmission line during the display stage and is in an off state under the action of the shutdown signal.
  • a method for preparing a display module for preparing the display module described in the above aspect; the method comprising:
  • an initial display module comprising: an initial base substrate, wherein the initial base substrate has a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area located on one side of the display area and an area to be cut located on a side of the binding area away from the display area; a plurality of pixel units, wherein the plurality of pixel units are located in the display area; a touch film layer, wherein the touch film layer is located on a side of the plurality of pixel units away from the base substrate;
  • the touch film layer includes at least touch electrodes; a plurality of binding interfaces, the plurality of binding interfaces being located in the binding area and connected to the touch electrodes; a plurality of initial connection traces, the first ends of the initial connection traces and the first target portion being located in the binding area, the first ends of the initial connection traces being connected to the binding interfaces; a plurality of test circuits and a plurality of test interfaces, the plurality of test circuits, the plurality of test circuits,
  • test device to sequentially provide a detection signal to the touch electrode through the test interface, the test circuit, the initial connection line, and the binding interface to test the touch performance of the display module;
  • a cutting device is used to cut along the cutting path between the first end of the initial connecting trace and the second end of the initial connecting trace, and the area to be cut of the initial substrate, the test circuit, the test interface and the portion of the initial connecting trace located in the area to be cut are cut off.
  • the portion of the initial connecting trace that is not cut off is the connecting trace, and the first end of the initial connecting trace is the first end of the connecting trace.
  • the first target portion and the second target portion are directly connected, and the width of the first target portion is equal to the width of the second target portion.
  • a display panel comprising: a flexible circuit board, and the display module according to the above aspect;
  • FIG1 is a partial schematic diagram of a display module in the related art
  • FIG2 is a schematic diagram of a short circuit of a connection line provided in an embodiment of the present application.
  • FIG5 is a partial schematic diagram of a display module before being cut into pieces according to an embodiment of the present application.
  • FIG6 is a partial schematic diagram of another display module provided in an embodiment of the present application.
  • FIG7 is a partial schematic diagram of another display module provided in an embodiment of the present application.
  • FIG9 is a schematic diagram of another connection wiring provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of a touch electrode provided in an embodiment of the present application.
  • FIG15 is a cross-sectional view taken along the BB′ direction in FIG14 ;
  • FIG20 is a top view of an initial display module provided in an embodiment of the present application.
  • FIG21 is a partial schematic diagram of an initial display module provided in an embodiment of the present application.
  • FIG24 is a partial schematic diagram of another initial display module provided in an embodiment of the present application.
  • FIG25 is a partial schematic diagram of another initial display module provided in an embodiment of the present application.
  • the display panel is obtained by binding a flexible circuit board to a display module after the display module is prepared.
  • a performance test on the display module before binding the flexible circuit board, such as a touch performance test or a display performance test.
  • the test interface is connected to the test circuit, and the test circuit is connected to a binding interface in the display module for binding with the flexible circuit board through a connecting line.
  • the test equipment provides test signals to the binding interface in the display module through the test interface, the test circuit and the connecting line in turn, thereby realizing the test of the display module performance.
  • the connecting wires are prone to generate carbonized materials due to the high temperature.
  • the carbonized materials gather between adjacent connecting wires, which can easily cause short circuits between the adjacent connecting wires, thereby reducing the yield of the display panel.
  • FIG3 is a top view of a display module according to an embodiment of the present application.
  • the display module (MDL) 100 includes: a substrate 101 , a plurality of pixel units 102 , a touch film layer (not shown in FIG3 ), a plurality of bonding interfaces (pins) 103 , and a plurality of connecting traces 104 .
  • the base substrate 101 has a display area (also referred to as an AA area) 101a and a peripheral area 101b surrounding the display area 101a.
  • the peripheral area 101b includes a binding area 101b1 located on one side of the display area 101a.
  • Figure 4 is a partial schematic diagram of a display module provided in an embodiment of the present application.
  • a plurality of pixel units 102 can be located in the display area 101a, and the plurality of pixel units 102 can be used to display images.
  • the touch film layer is located on the side of the plurality of pixel units 102 away from the base substrate 101, and the touch film layer includes at least touch electrodes.
  • a plurality of binding interfaces 103 are located in the binding area 101b1, and the plurality of binding interfaces 103 are connected to the touch electrodes in the touch film layer.
  • the first target portion z2 is located on a side of the first end z1 of the connecting trace 104 away from the display area 101 a , and the end of the first target portion z2 away from the display area 101 a is obtained by cutting.
  • an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of the base substrate.
  • the plurality of binding interfaces are connected to the touch electrodes in the touch film layer, and the first end of the connecting wire is connected to the binding interface.
  • the width of the first target portion of the connecting wire located at the first end away from the display area is smaller than the width of the binding interface, and the first target portion of the adjacent connecting wires is smaller than the width of the binding interface.
  • the distance between the target portions is smaller than the distance between adjacent bonding interfaces.
  • the test equipment needs to transmit signals to the binding interface 103 through the test interface, test circuit, and connecting trace 104. If the width of the first target portion z2 of the connecting trace 104 is too small, the reliability of the signal transmission will be affected, and the performance test results will be poor. Therefore, the width of the first target portion z2 of the connecting trace 104 can be designed to be greater than or equal to 1.8 ⁇ m (micrometers), which can ensure the reliability of signal transmission.
  • the width of the first end z1 of the connecting trace 104 is greater than the width of the first target portion z2 of the connecting trace 104. This ensures that the first end z1 of the connecting trace 104 and the binding interface 103 have sufficient connection area, ensuring connection reliability.
  • the width of the first end z1 of the connecting trace 104 can be equal to the width of the binding interface 103.
  • the first central axis z21 of the first target portion z2 of the connecting line 104 and the second central axis z11 of the first end z1 of the connecting line 104 both extend along the extension direction of the connecting line 104. That is, the first central axis z21 and the second central axis z11 are parallel.
  • the first central axis z21 and the second central axis z11 are collinear. That is, the first target portion z2 of the connecting trace 104 can be located in the middle of the first end z1 of the connecting trace 104. In this case, both boundaries (z2a and z2b) of the first target portion z2 of the connecting trace 104 along its extension direction are indented relative to the first end z1 of the connecting trace 104, and the indentations are equal.
  • the first target portion z2 of the connecting trace 104 has a first boundary z2a and a second boundary z2b that are opposite to each other.
  • the first end z1 of the connecting trace 104 has a third boundary z1a and a fourth boundary z1b that are opposite to each other.
  • the first boundary z2a, the second boundary z2b, the third boundary z1a, and the fourth boundary z1b all extend along the extension direction of the connecting trace 104.
  • the first boundary z2a is closer to the third boundary z1a than the second boundary z2b, and the second boundary z2b is closer to the fourth boundary z1b than the first boundary z2a.
  • the distance m1 between the first boundary z2a and the third boundary z1a along the target direction M can be equal to the distance m2 between the second boundary z2b and the fourth boundary z1b along the target direction M.
  • the target direction M can be perpendicular to the extension direction of the connecting trace 104.
  • the first boundary z2a and the third boundary z1a are collinear and form a connection
  • the second boundary z2b is closer to the common boundary than the fourth boundary z1b. This allows the distance between the second boundary z2b and the common boundary along the target direction M to be smaller than the distance between the fourth boundary z1b and the common boundary along the target direction M.
  • the width of the first target portion z2 of the connecting trace 104 can be smaller than the width of the first end z1 of the connecting trace 104.
  • the common boundary of the multiple connecting traces 104 may be located on the same side, with the first target portion z2 on the other side being indented relative to the first end.
  • the common boundary of the multiple connecting traces 104 is the right boundary of the connecting trace 104, while the first target portion z2 on the left boundary is indented relative to the first end.
  • the common boundary of the multiple connecting traces 104 is the left boundary of the connecting trace 104, while the first target portion z2 on the right boundary is indented relative to the first end.
  • the third boundary z1a and the fourth boundary z1b of the first end z1 of the connecting line 104 , and the first boundary z2a and the second boundary z2b of the first target portion z2 of the connecting line 104 may all be straight lines.
  • the inward contraction design of the first target portion z2 of the connecting wire 104 relative to the first end z1 of the connecting wire 104 may gradually change at the transition portion z3, thereby avoiding stress concentration and static electricity concentration and improving the reliability of the connecting wire 104.
  • the transition portion z3 has a fifth boundary z3a and a sixth boundary z3b opposite to each other, and at least one of the fifth boundary z3a and the sixth boundary z3b intersects with the extending direction of the connection trace 104 .
  • the fifth boundary z3a and the sixth boundary z3b both intersect the extension direction Y of the connecting trace 104.
  • the fifth boundary z3a may form a common boundary with the first boundary z2a and the third boundary z1a
  • the sixth boundary z3b may intersect the extension direction Y of the connecting trace 104.
  • the fifth boundary z3a and the sixth boundary z3b are both straight lines, and the boundary of the fifth boundary z3a and the sixth boundary z3b that intersects with the extending direction of the connecting line 104 is not aligned with the extending direction of the connecting line 104. That is, the angle ⁇ between the fifth boundary z3a and the sixth boundary z3b that intersects the extending direction of the connection line 104 is greater than 90 degrees.
  • the angles between the fifth boundary z3a and the sixth boundary z3b and the extending direction of the connection line 104 are both obtuse angles.
  • the angle between the sixth boundary z3b and the extending direction of the connection line 104 is also obtuse.
  • the fifth boundary z3a and the sixth boundary z3b may also be curves or broken lines, which is not limited in this embodiment of the present application.
  • the display module 100 also includes a pixel circuit connected to the pixel unit 102 and providing a drive signal to the pixel unit 102.
  • the active layer n2, gate insulating layer n3, gate layer n4, interlayer dielectric layer n5, first source and drain electrode layer n6, first planar layer n7, and second source and drain electrode layer n8 can be used to form the pixel circuit.
  • the anode layer, light-emitting layer, and cathode layer are used to form the pixel unit 102.
  • the pixel circuit may include multiple thin film transistors (TFTs) and at least one storage capacitor.
  • the pixel circuit may include seven thin film transistors and one storage capacitor, that is, the pixel circuit is a 7T1C driving circuit.
  • the pixel circuit may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiments of the present application do not limit the number of thin film transistors included in the pixel circuit and the number of storage capacitors included.
  • Each thin film transistor includes a gate, a source, and a drain.
  • the pixel circuit in each pixel unit includes a plurality of thin film transistors that are interconnected to achieve the function of driving the light-emitting unit in the pixel unit to emit light.
  • the active layer includes multiple active patterns corresponding to multiple thin film transistors, each active pattern including a source region, a drain region, and a channel region.
  • the source and drain of the thin film transistor are located in the first source-drain layer, and the source of the thin film transistor is connected to the source region, and the drain is connected to the drain region.
  • the first gate layer includes a plurality of gate patterns corresponding to a plurality of thin film transistors. The overlapping area of the orthographic projection of the active pattern on the substrate and the orthographic projection of the active pattern on the substrate.
  • the encapsulation layer n14 includes a first film layer n141 , a second film layer n142 , and a third film layer n143 stacked in a direction away from the base substrate 101 .
  • the first film layer n141 and the third film layer n143 may be made of an inorganic material, and the second film layer n142 may be made of an organic material.
  • the first film layer n141 and the third film layer n143 may be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride).
  • the second film layer n142 may be made of a resin material.
  • the resin may be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin may include an acrylic (PMMA) resin, and the thermosetting resin may include an epoxy resin.
  • the second film layer n142 can be produced by inkjet printing (IJP).
  • the first film layer n141 and the third film layer n143 can be produced by chemical vapor deposition (CVD).
  • the touch electrodes S can be located on the first touch layer 1051 and the second touch layer 1052 .
  • the touch electrodes S include multiple first touch electrodes s1 and multiple second touch electrodes s2 .
  • One of the first touch layers 1051 and the second touch layer 1053 includes a main electrode s11 of the first touch electrode s1 and a second touch electrode s2 .
  • the other of the first touch layers 1051 and the second touch layer 1052 includes a bridge electrode s12 of the first touch electrode s1 .
  • the main electrode s11 and the bridge electrode s12 are electrically connected via vias in the touch insulating layer 1052 .
  • a plurality of first touch electrodes s1 are arranged along a second direction Q, and a plurality of second touch electrodes s2 are arranged along a first direction W. Furthermore, the bridging electrode s12 of the first touch electrode s1 is located in a region where it overlaps with the orthographic projection of the second touch electrode s2.
  • the first direction W may be the direction of pixel rows in the display module 100
  • the second direction Q may be the direction of pixel columns in the display module 100.
  • the main electrode s11 of the first touch electrode s1 in the second touch layer 1053 is connected via a via in the touch insulation layer 1052.
  • one of the first touch electrode s1 and the second touch electrode s2 may be a transmitting (TX) electrode, and the other may be a sensing (RX) electrode.
  • TX transmitting
  • RX sensing
  • the display module 100 further includes a touch driving circuit and a touch detection circuit located in the peripheral area 101b.
  • the touch driving circuit can be connected to the emitting electrode to provide the emitting electrode with a touch detection circuit. Touch drive signal.
  • the touch detection circuit can be connected to the sensing electrodes to receive sensing signals between the transmitting electrode and the sensing electrode. If a user's finger approaches the display module 100, the touch detection circuit can detect a change in the sensing signal at the location of the user's finger and determine the location where the sensing signal changed as the touch location.
  • the touch panel (TP) function of the display module can be tested during the testing phase.
  • FIG13 is a cross-sectional view along the AA' direction of FIG4.
  • the connection trace 104 and the bonding interface 103 can be located in different film layers among the multiple film layers of the display module 100.
  • the connection trace 104 is located in the gate layer n4 of the display module 100
  • the bonding interface 103 can be located in the second touch layer 1053 of the display module 100.
  • the display module 100 further includes a first connecting portion 106 located on the first source/drain layer n6 and a second connecting portion 107 located on the second source/drain layer n8 .
  • the first end z1 of the connecting trace 104 is connected to the bonding interface 103 via the first connecting portion 106 and the second connecting portion 107 .
  • the first end of the connecting trace 104 is connected to the first connecting portion 106 through a via in the interlayer dielectric layer n5
  • the first connecting portion 106 and the second connecting portion 107 are connected through a via in the first flat layer n7
  • the second connecting portion 107 is connected through a via in the second flat layer n9, the encapsulation layer n14 and the touch insulation layer 1052.
  • the first target portion z2 of the connection trace 104 may include a first sub-trace 1041 and a second sub-trace 1042 spaced apart along the extending direction of the connection trace 104 .
  • the display module 100 further includes a switch transistor T and a signal transmission line 108 .
  • the switching transistor T includes a gate, a first electrode, and a second electrode.
  • the first electrode is connected to the first sub-trace 1041, and the second electrode is connected to the second sub-trace 1042.
  • the gate is connected to the signal transmission line 108.
  • the switching transistor T is configured to receive a shutdown signal from the signal transmission line 108 during the display phase.
  • the switching transistor T is configured to be in an off state under the action of the shutdown signal.
  • FIG15 is a cross-sectional view of FIG14 along the BB' direction.
  • the switch transistor T includes an active pattern n21 located in the active layer n2.
  • the orthographic projection of the first end of the active pattern n21 on the base substrate 101 overlaps with the orthographic projection of the first sub-line 1041 on the base substrate 101, and the first end of the active pattern n21 overlaps with the first sub-line 1041 on the base substrate 101.
  • the end of the active pattern n21 can serve as the first electrode of the switching transistor T and be connected to the first sub-trace 1041 through the first via k1 in the gate insulating layer n3.
  • the second end of the active pattern n21 can serve as the second electrode of the switching transistor T and be connected to the second sub-trace 1042 through the second via k2 in the gate insulating layer n3.
  • the number of first vias k1 and the number of second vias k2 are both negatively correlated with the width of the first target portion z2 of the connection trace 104. That is, the smaller the width of the first target portion z2, the greater the number of first vias k1 and the number of second vias k2; and the larger the width of the first target portion z2, the fewer the number of first vias k1 and the number of second vias k2.
  • the second via k2 is used to connect the active pattern n21 of the switching transistor T to the second sub-trace 1042. To ensure the reliability of the connection between the active pattern n21 and the second sub-trace 1042, a certain connection area must be maintained between the active pattern n21 and the second sub-trace 1042. If the width of the first target portion z2 is small, a larger number of second vias k2 can be designed to increase the connection area between the active pattern n21 and the second sub-trace 1042.
  • the gate insulating layer n3 of the display module 100 has two first vias k1 and two second vias k2 , the active pattern n21 and the first sub-wiring 1041 are connected through the two first vias k1 , and the active pattern and the second sub-wiring 1042 are connected through the two second vias k2 .
  • the switching transistor T further includes a gate pattern n41 located on the gate layer n4.
  • the orthographic projection of the gate pattern n41 on the base substrate 101 overlaps with the orthographic projection of the active pattern n21 on the base substrate 101.
  • the gate pattern n41 can serve as the gate of the switching transistor T and be connected to the signal transmission line 108.
  • the test equipment needs to provide a detection signal to the bonding interface 103 through the test interface, test circuit, and connection line 104, so the signal needs to be turned on.
  • the signal transmission line 108 can provide an on signal to the gate of the switching transistor T, so that the switching transistor T is in the on state, thereby allowing the detection signal to be transmitted to the bonding interface 103 through the switching transistor T.
  • connecting traces 104 will produce carbonized substances due to the high temperature during cutting, which may cause adjacent connecting traces 104 to short-circuit (for example, the second sub-traces 1042 of adjacent connecting traces 104 to short-circuit).
  • the signal transmission line 108 may provide a turn-off signal to the gate of the switch transistor T, so that the switch transistor T is in the turn-off state.
  • the connecting trace 104 is located on the gate layer n4 of the display module 100.
  • the gate pattern n41 of the switching transistor T is also located on the gate layer n4 of the display module 100.
  • Both the first sub-trace 1041 and the second sub-trace 1042 of the connecting trace 104 have a gap with the gate pattern n41 of the switching transistor T.
  • the bonding interface 103 may be located on the second touch layer 1053.
  • the first end z1 of the connecting trace 104 is connected to the bonding interface 103 via the first connecting portion 106 and the second connecting portion 107.
  • the signal transmission line 108 can be located in the first source/drain layer n6.
  • the orthographic projection of the signal transmission line 108 on the base substrate 101 overlaps with the orthographic projection of the gate pattern n41 on the base substrate 101, and the gate pattern n41 is connected to the signal transmission line 108 via a third via k3 in the second gate insulating layer n2.
  • the width of the gate pattern n41 of the switching transistor T can be equal to the width of the first target portion z2.
  • a certain connection area between the signal transmission line 108 and the gate pattern n41 is required. If the width of the gate pattern n41 is small, the connection area between the gate pattern n41 and the signal transmission line 108 can be increased by designing a larger number of third vias k3.
  • the display module 100 further includes a signal transmission interface 109 and a signal transmission connection line 110.
  • the signal transmission interface 109 can be located on the same layer as the binding interface 103, such as on the second touch layer 1053.
  • the signal transmission connection line 110 can be located on the same layer as the connection line 104, such as on the gate layer n4.
  • the signal transmission interface 109 and the signal transmission connection line 110 can be connected to each other through the first connection portion 106 and the second connection portion. 107.
  • One end of the signal transmission connection trace 110 away from the signal transmission interface 109 is also connected to the signal transmission line 108.
  • the signal transmission connection trace 110 (gate layer n4) and the signal transmission line 108 (first source and drain layer n6) are located in different layers, they can be connected through the fourth via k4 in the interlayer dielectric layer n5.
  • the width and indentation design of the signal transmission connection trace 110 can be the same as those of the connection trace 104.
  • the width of the signal transmission connection trace 110 is also smaller, thereby increasing the connection area between the signal transmission connection trace 110 and the signal transmission line 108 by designing a larger number of fourth vias k4, thereby improving the reliability of the connection.
  • the extension direction of the signal transmission connection trace 110 may be parallel to the extension direction of the connection trace 104, and the extension direction of the signal transmission line 108 may be parallel to the arrangement direction of the plurality of connection traces 104.
  • the plurality of connection traces 104 may be arranged along the pixel row direction of the display module 100, and the extension direction of the signal transmission line 108 may be the pixel row direction.
  • the width of the active pattern n21 may also be equal to the width of the first target portion z2, which is not limited in this embodiment of the present application.
  • the signal transmission line 108 can also be located in the second source-drain layer n8.
  • the signal transmission line 108 can be connected to the gate pattern n41 of the switching transistor T through vias in the interlayer dielectric layer and the second gate insulation layer n2.
  • the signal transmission line 108 can also be located in the gate layer n4.
  • the gate patterns n41 of the multiple switching transistors T arranged along the target direction M can be an integrated structure, and this integrated structure is spaced apart from the first sub-routing 1041 and the second sub-routing 1042.
  • the signal trace 111 may include a first signal sub-trace located in the first touch layer and a second signal sub-trace located in the second touch layer.
  • the first signal sub-trace and the second signal sub-trace are connected through a via in the touch insulating layer.
  • the display function of the display module 100 can also be tested.
  • the display module 100 also includes multiple display binding interfaces, multiple display connection lines, and multiple display signal lines.
  • the binding interface 103 in the figure is replaced with a display binding interface
  • the connection lines in the figure are replaced with display connection lines
  • the signal lines in the figure are replaced with display signal lines.
  • the display connection trace can be connected to the display binding interface, and the design of the display connection trace can be the same as that of the connection trace 104. That is, the width of the portion of the display connection trace near the scribe line is smaller than the width of the display binding interface, and the distance between adjacent portions of the display connection trace near the scribe line is greater than the distance between adjacent display binding interfaces.
  • a switching transistor can be designed in the display connection trace, and the switching transistor is turned on during the test phase and turned off during the display phase.
  • one end of the display signal line is connected to the display binding interface, and the other end is used to connect to the pixel unit, so that the pixel unit can receive the display test signal during the test phase.
  • the display connection trace may be located in the gate layer, and the display bonding interface may be located in the second touch layer.
  • the display signal trace may include a first display signal sub-trace located in the first gate layer, a second display signal sub-trace located in the first source/drain layer, and a third display signal sub-trace located in the second source/drain layer.
  • the first display signal sub-trace and the second display signal sub-trace are connected via a via in the second gate insulation layer, and the second display signal sub-trace and the third display signal sub-trace are connected via a via in the interlayer dielectric layer.
  • the display module can be an organic light emitting diode (OLED) equipped with flexible multi-layer on-cell (FMLOC) touch technology.
  • OLED organic light emitting diode
  • FMLOC flexible multi-layer on-cell
  • an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of the base substrate.
  • the plurality of binding interfaces are connected to the touch film layer, and the first end of the connecting wire is connected to the binding interface.
  • the width of the first target portion of the connecting wire located at the first end away from the display area is smaller than the width of the binding interface, and the distance between adjacent first target portions is smaller than the distance between adjacent binding interfaces.
  • the connecting wire is cut to obtain the connecting wire, even if the connecting wire produces carbonized material due to the high temperature during cutting, the distance between the first target portions of adjacent connecting wires is large, so the carbonized material cannot fill the spacing between the first target portions of adjacent connecting wires, thereby reducing the risk of short circuit of adjacent connecting wires, thereby improving the yield of the display panel.
  • the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a.
  • the peripheral area 101 b includes a binding area 101 b 1 located on one side of the display area 101 a.
  • the test circuit and test interface can be located on the side of the binding area 101b1 away from the display area 101a.
  • a testing device can be connected to the test interface, providing a test signal to the connecting trace 104 via the test interface and test circuit, thereby testing the performance of the display module 100.
  • a cutting device is used to remove the test interface and test circuit along the cutting path to obtain the connecting trace 104.
  • the end of the first target portion z2 of the connecting trace 104 away from the display area 101a is the end obtained by the cutting device along the cutting path.
  • the display module 100 also includes a switching transistor T and a signal transmission line 108.
  • the switching transistor T includes a gate, a first electrode, and a second electrode.
  • the first electrode is connected to the first sub-trace 1041, and the second electrode is connected to the second sub-trace 1042.
  • the gate is connected to the signal transmission line 108.
  • the switching transistor T receives a shutdown signal from the signal transmission line 108 and is turned off by the shutdown signal.
  • the test equipment needs to provide a detection signal to the bonding interface 103 through the test interface, test circuit, and connection line 104, so the signal needs to be turned on.
  • the signal transmission line 108 can provide an on signal to the gate of the switching transistor T, so that the switching transistor T is in the on state, thereby allowing the detection signal to be transmitted to the bonding interface 103 through the switching transistor T.
  • the connecting traces 104 will produce carbonized materials due to the high temperature during cutting, which may cause the adjacent connecting traces 104 to be cut. Part of the cut street is short-circuited (for example, the second sub-traces 1042 of the adjacent connecting traces 104 are short-circuited).
  • the signal transmission line 108 can provide a shutdown signal to the gate of the switching transistor T, thereby turning the switching transistor T off. In this case, since the switching transistor T is in the off state, signal transmission between the first and second electrodes can be prevented. Even if the second sub-line 1042 of the adjacent connecting line 104 is short-circuited, the short-circuit signal will not be transmitted to the first end z1 of the connecting line 104, thus preventing short circuits between different bonding interfaces 103.
  • an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of the base substrate.
  • the plurality of binding interfaces are connected to the touch electrodes in the touch film layer, and the first end of the connecting wire is connected to the binding interface.
  • the width of each position in the connecting trace 104 is equal.
  • the first target portion z2 of the connecting trace 104 does not need to be designed to be inward relative to the first end.
  • the width of the connecting trace 104 can be equal to the width of the binding interface 103.
  • FIG17 is a cross-sectional view taken along the CC' direction of FIG16 .
  • the connection traces 104 and the bonding interface 103 can be located in different layers among the multiple layers of the display module 100.
  • the display module 100 includes a buffer layer (buffer) n1, an active layer (poly) n2, a gate insulator (GI) n3, a gate layer (gate) n4, an inter-level dielectric (ILD) n5, a first source and drain electrode layer n6, a first planarization layer (PLN) n7, a second source and drain electrode layer n8, a second planarization layer n9, an anode layer n10, a pixel definition layer n11, light-emitting layers n1 and n2, a cathode layer n13, and an encapsulation layer n14, which are stacked in sequence.
  • the touch film layer 105 includes a first touch layer 1051, a
  • the display module 100 also includes a pixel circuit for driving the pixel unit 102 to emit light.
  • the active layer n2, gate insulating layer n3, gate layer n4, interlayer dielectric layer n5, first source and drain electrode layer n6, first planarizing layer n7, and second source and drain electrode layer n8 can be used to form the pixel circuit.
  • the anode layer, light-emitting layer, and cathode layer are used to form the pixel unit 102.
  • the pixel circuit may include multiple thin film transistors (TFTs) and at least one storage capacitor.
  • the pixel circuit may include seven thin film transistors and one storage capacitor, that is, the pixel circuit is a 7T1C driving circuit.
  • the pixel circuit may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiments of the present application do not limit the number of thin film transistors included in the pixel circuit and the number of storage capacitors included.
  • Each thin film transistor includes a gate, a source, and a drain.
  • the pixel circuit in each pixel unit includes a plurality of thin film transistors that are interconnected to achieve the function of driving the light-emitting unit in the pixel unit to emit light.
  • the active layer includes multiple active patterns corresponding to multiple thin film transistors, each active pattern including a source region, a drain region, and a channel region.
  • the source and drain of the thin film transistor are located in the first source-drain layer, and the source of the thin film transistor is connected to the source region, and the drain is connected to the drain region.
  • the first gate layer includes a plurality of gate patterns corresponding to the plurality of thin film transistors.
  • the channel region is an overlapping region of an orthographic projection of the gate pattern on the base substrate and an orthographic projection of the active pattern on the base substrate.
  • the main electrode s11 of the first touch electrode s1 in the second touch layer 1053 is connected via a via in the touch insulation layer 1052.
  • one of the first touch electrode s1 and the second touch electrode s2 may be a transmitting (TX) electrode, and the other may be a sensing (RX) electrode.
  • TX transmitting
  • RX sensing
  • the display module 100 further includes a touch driving circuit and a touch control circuit located in the peripheral area 101b.
  • Touch detection circuit can be connected to the transmitting electrode to provide a touch drive signal to the transmitting electrode.
  • the touch detection circuit can be connected to the sensing electrode to receive the sensing signal between the transmitting electrode and the sensing electrode. If a user's finger approaches the display module, the touch detection circuit can detect a change in the sensing signal at the location of the user's finger and determine the location of the change in the sensing signal as the touch location.
  • the touch function of the display module 100 can be tested during the testing phase.
  • the connecting trace 104 is located on the gate layer n4 of the display module 100, and the bonding interface 103 can be located on the second touch layer 1053 of the display module 100.
  • the display module 100 also includes a first connecting portion 106 located on the first source and drain layer n6, and a second connecting portion 107 located on the second source and drain layer n8.
  • the first end z1 of the connecting trace 104 is connected to the bonding interface 103 via the first connecting portion 106 and the second connecting portion 107.
  • the first end of the connecting trace 104 is connected to the first connecting portion 106 through a via in the interlayer dielectric layer n5
  • the first connecting portion 106 and the second connecting portion 107 are connected through a via in the first flat layer n7
  • the second connecting portion 107 is connected through a via in the second flat layer n9, the encapsulation layer n14 and the touch insulation layer 1052.
  • the switching transistor T includes an active pattern n21 located in the active layer n2.
  • the orthographic projection of the first end of the active pattern n21 on the base substrate 101 overlaps with the orthographic projection of the first sub-route 1041 on the base substrate 101.
  • the first end of the active pattern n21 can serve as the first electrode of the switching transistor T and is connected to the first sub-route 1041 via a first via k1 in the gate insulating layer n3.
  • the orthographic projection of the second end of the active pattern n21 on the base substrate 101 overlaps with the orthographic projection of the second sub-route 1042 on the base substrate 101.
  • the second end of the active pattern n21 can serve as the second electrode of the switching transistor T and is connected to the second sub-route 1042 via a second via k2 in the gate insulating layer n3.
  • a first via hole k1 and a second via hole k2 are formed in the gate insulating layer n3 of the display module 100.
  • the active pattern and the first sub-trace 1041 are connected through the first via hole k1, and the active pattern and the second sub-trace 1042 are connected through the second via hole k2.
  • the switching transistor T further includes a gate pattern n41 located on the gate layer n4.
  • the orthographic projection of the gate pattern n41 on the base substrate 101 overlaps with the orthographic projection of the active pattern n21 on the base substrate 101.
  • the gate pattern n41 can serve as the gate of the switching transistor T and be connected to the signal transmission line 108.
  • the signal transmission line 108 provides an on signal to the gate of the switch transistor T
  • the first and second electrodes of the switch transistor T are turned on, and the signal from the second electrode of the switch transistor T can be transmitted to the first electrode of the switch transistor T, and then transmitted to the bonding interface 103.
  • the signal transmission line 108 is a switch transistor
  • the gate of T provides a shutdown signal, and the signal between the first and second electrodes of the switch transistor T is disconnected.
  • the signal from the second electrode of the switch transistor T cannot be transmitted to the first electrode of the switch transistor T, nor can it be transmitted to the binding interface 103.
  • the test equipment needs to provide a detection signal to the bonding interface 103 through the test interface, test circuit, and connection line 104, so the signal needs to be turned on.
  • the signal transmission line 108 can provide an on signal to the gate of the switching transistor T, so that the switching transistor T is in the on state, thereby allowing the detection signal to be transmitted to the bonding interface 103 through the switching transistor T.
  • connecting traces 104 will produce carbonized substances due to the high temperature during cutting, which may cause adjacent connecting traces 104 to short-circuit (for example, the second sub-traces 1042 of adjacent connecting traces 104 to short-circuit).
  • the signal transmission line 108 may provide a turn-off signal to the gate of the switch transistor T, so that the switch transistor T is in the turn-off state.
  • the signal transmission line 108 can be located in the first source/drain layer n6.
  • the orthographic projection of the signal transmission line 108 on the base substrate 101 overlaps with the orthographic projection of the gate pattern n41 on the base substrate 101, and the gate pattern n41 is connected to the signal transmission line 108 via a third via k3 in the second gate insulating layer n2.
  • the width of the gate pattern n41 of the switching transistor T can be equal to the width of the first target portion z2.
  • a certain connection area between the signal transmission line 108 and the gate pattern n41 is required. If the width of the gate pattern n41 is small, the connection area between the gate pattern n41 and the signal transmission line 108 can be increased by designing a larger number of third vias k3.
  • the display module 100 further includes a signal transmission interface 109 and a signal transmission connection line 110 .
  • the signal transmission interface 109 and the binding interface 103 may be located on the same layer, such as the second touch layer 1053 .
  • the signal transmission connection trace 110 can be located on the same layer as the connection trace 104, such as on the gate layer n4.
  • the signal transmission interface 109 and the signal transmission connection trace 110 can be connected via the first connection portion 106 and the second connection portion 107.
  • the end of the signal transmission connection trace 110 away from the signal transmission interface 109 is also connected to the signal transmission line 108.
  • the signal transmission connection trace 110 (gate layer n4) and the signal transmission line 108 (first source and drain layer n6) are located on different layers, they can be connected via the fourth via k4 in the interlayer dielectric layer n5.
  • the width of the signal transmission connection trace 110 can be the same as the width of the connection trace 104.
  • Figure 18 is a cross-sectional view of Figure 16 along the DD' direction. Referring to Figure 18, the width of the active pattern n21 can be equal to the width of the gate pattern n41. In addition, the width of the active pattern n21 can be equal to the width of the first target portion z2. This embodiment of the present application is not limited to this.
  • the extension direction of the signal transmission connection trace 110 may be parallel to the extension direction of the connection trace 104, and the extension direction of the signal transmission line 108 may be parallel to the arrangement direction of the plurality of connection traces 104.
  • the plurality of connection traces 104 may be arranged along the pixel row direction of the display module, and the extension direction of the signal transmission line 108 may be the pixel row direction.
  • the signal transmission line 108 can also be located in the second source-drain layer n8.
  • the signal transmission line 108 can be connected to the gate pattern n41 of the switching transistor T through vias in the interlayer dielectric layer and the second gate insulation layer n2.
  • the signal transmission line 108 can also be located in the gate layer n4.
  • the gate patterns n41 of the multiple switching transistors T arranged along the target direction M can be an integrated structure, and this integrated structure is spaced apart from the first sub-routing 1041 and the second sub-routing 1042.
  • an embodiment of the present application provides a display module, which includes a base substrate, a plurality of pixel units and a touch film layer located in the display area of the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in the binding area of the base substrate.
  • the plurality of binding interfaces are connected to the touch electrodes in the touch film layer, and the first end of the connecting wire is connected to the binding interface.
  • FIG19 is a flow chart of a method for preparing a display module according to an embodiment of the present application. The method can be applied to prepare the display module provided in the above embodiment. Referring to FIG19 , the method includes:
  • Step S101 Acquire an initial display module.
  • the initial base substrate 101c has a display area 101a and a peripheral area 101b surrounding the display area 101a.
  • the peripheral area 101b includes a binding area 101b1 located on one side of the display area 101a and a to-be-cut area 101b2 located on a side of the binding area 101b1 away from the display area 101a.
  • Multiple pixel units 102 are located in the display area 101a, and the multiple pixel units 102 are used to display images.
  • a touch film layer is located on a side of the multiple pixel units 102 away from the base substrate 101, and the touch film layer includes at least touch electrodes.
  • Multiple binding interfaces 103 are located in the binding area 101b1, and the multiple binding interfaces 103 are connected to the touch electrodes in the multiple touch film layers.
  • the first end z1 of the initial connection trace 104a is connected to the binding interface 103, and the first end z1 of the initial connection trace 104a and the first target portion z2 are located in the binding area 101b1.
  • the initial display module 100a may be the display module 100 before being cut along the cutting line.
  • the cutting line may be located between the first end z1 and the second end z3 of the initial connection line 104a.
  • the test equipment can directly provide a detection signal to the touch electrode through the test interface, the test circuit, the initial connection line 104a, and the binding interface 103.
  • the signal transmission line 108 can provide a turn-on signal to the gate of the switching transistor T, and the switching transistor T is in the turn-on state under the action of the turn-on signal.
  • the second electrode and the first electrode of the switching transistor T are turned on.
  • the signal provided by the test equipment can be transmitted from the second electrode of the switching transistor T to the first electrode, thereby providing a detection signal to the touch electrode.
  • Step S103 using a cutting device to cut along a cutting path between the first end of the initial connection line and the second end of the initial connection line.
  • the display module 100 can be obtained by cutting along the cutting lines. After cutting, the to-be-cut area 101b2 of the initial base substrate 101c, the test circuit, the test interface and the portion of the initial connection trace 104a located in the to-be-cut area 101b2 can be removed.
  • the first target portion z2 and the second target portion z4 are directly connected, and the width of the first target portion z2 is equal to the width of the second target portion z4.
  • the initial display module 100a also includes: multiple transition traces.
  • the first end of the transition trace is connected to the second end z3 of the initial connection trace 104a, and the second end of the transition trace is connected to the test circuit.
  • the width of the transition trace can be greater than or equal to the width of the second target portion z4 of the initial connection trace 104a.
  • the width of the transition trace can be equal to the width of the binding interface 103 and greater than the width of the second target portion of the initial connection trace 104a. Since the distance between the cutting path and the transition trace is relatively far, the high temperature during cutting has less impact on the transition trace.
  • the transition trace may be located in the first source/drain layer n6 of the initial display module 100a, and the first end of the transition trace may be connected to the second end of the initial connection trace 104a through a fifth via k5 in the second gate insulating layer n2.
  • FIG26 shows two fifth vias k5.
  • the embodiments of the present application provide a method for manufacturing a display module.
  • the display module manufactured by this method includes a base substrate, a plurality of pixel units and a touch film layer located in a display region of the base substrate, and a plurality of binding interfaces and a plurality of connecting wires located in a binding region of the base substrate.
  • the plurality of binding interfaces are connected to touch electrodes in the touch film layer, and the first ends of the connecting wires are connected to the binding interfaces.
  • the width of the first target portion of the connecting line located at the first end away from the display area is smaller than the width of the binding interface, and the distance between adjacent first target portions is smaller than the distance between adjacent binding interfaces. Therefore, when the connecting lines are cut, even if the connecting lines will produce carbonized materials due to the high temperature during cutting, the total amount of carbonized materials is not enough to fill the spacing between the first target parts of adjacent connecting lines, thereby reducing the risk of short circuit between adjacent connecting lines and improving the yield of the display panel.
  • FIG27 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • the display panel includes a flexible printed circuit (FPC) 200 and a display module 100 as provided in the above-described embodiment.
  • the display module 100 has a display side a and a non-display side b.
  • the flexible printed circuit 200 includes multiple signal interfaces 201 located on the display side a. These multiple signal interfaces 201 are connected to corresponding binding interfaces 103 in the display module 100. At least a portion of the flexible printed circuit 200 is located on the non-display side b of the display module 200.
  • a portion of the flexible circuit board 200 is located on the display side a of the display module 100 for bonding to the display module 100, while the other portion is bent from the side of the display module 100 to the non-display side b of the display module 100. This reduces the size of the display panel's bezel, facilitating the realization of a narrow-bezel product.
  • Words such as “include” or “comprise” and the like mean that the elements or objects appearing before “include” or “comprises” include the elements or objects listed after “include” or “comprises” and their equivalents, and do not exclude other elements or objects.
  • Words such as “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up”, “down”, “left”, “right”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

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Abstract

本申请公开了一种显示模组及其制备方法、显示面板，涉及显示技术领域。显示模组包括衬底基板，位于衬底基板的显示区域的多个像素单元和触控膜层，以及位于衬底基板的绑定区域的多个绑定接口和多条连接走线。多个绑定接口和触控膜层中的触控电极连接，连接走线的第一端和绑定接口连接。连接走线中的第一目标部分的宽度小于绑定接口的宽度，且相邻的第一目标部分之间的距离小于相邻的绑定接口之间的距离。由此，在切割得到连接走线时，即使连接走线会因切割时的高温而产生碳化物质，但碳化物质并不能将相邻的连接走线的第一目标部分之间的间距填满，降低了相邻的连接走线短路的风险，进而提升了显示面板的良率。

Description

显示模组及其制备方法、显示面板 技术领域
本申请涉及显示技术领域，特别涉及一种显示模组及其制备方法、显示面板。
背景技术
显示面板包括显示模组以及与显示模组连接的柔性电路板。显示模组包括衬底基板以及位于衬底基板上的多个像素单元。柔性电路板用于为显示模组中的多个像素单元提供驱动信号，多个像素单元能够在驱动信号的驱动下发光。
发明内容
本申请提供了一种显示模组及其制备方法、显示面板，所述技术方案如下：
一方面，提供了一种显示模组，所述显示模组包括：
衬底基板，所述衬底基板具有显示区域以及围绕所述显示区域的周边区域，所述周边区域包括位于所述显示区域一侧的绑定区域；
多个像素单元，所述多个像素单元位于所述显示区域；
触控膜层，所述触控膜层位于所述多个像素单元远离所述衬底基板的一侧，所述触控膜层至少包括触控电极；
多个绑定接口，所述多个绑定接口位于所述绑定区域，所述多个绑定接口和所述触控电极连接；
以及，多条连接走线，所述连接走线的第一端和所述绑定接口连接，所述连接走线的第一目标部分的宽度小于所述绑定接口的宽度，且相邻的所述连接走线的第一目标部分之间的距离，大于相邻的所述绑定接口之间的距离；
其中，所述第一目标部分位于所述连接走线的第一端远离所述显示区域的一侧，且所述第一目标部分远离所述显示区域的一端通过切割得到。
可选的，所述连接走线的第一目标部分的宽度大于或等于1.8微米。
可选的，所述连接走线的第一端的宽度大于所述连接走线的第一目标部分 的宽度。
可选的，所述连接走线的第一目标部分的第一中轴线，以及所述连接走线的第一端的第二中轴线均沿所述连接走线的延伸方向延伸。
可选的，所述第一中轴线和所述第二中轴线共线。
可选的，所述连接走线的第一目标部分具有相对的第一边界和第二边界，所述连接走线的第一端具有相对的第三边界和第四边界；
所述第一边界和所述第三边界共线，且构成所述连接走线的公共边界，所述第二边界相对于所述第四边界更靠近所述公共边界；
其中，所述第一边界，所述第二边界，所述第三边界以及所述第四边界均沿所述连接走线的延伸方向延伸。
可选的，所述连接走线还包括位于所述第一目标部分和所述连接走线的第一端之间的过渡部分；
所述过渡部分靠近所述连接走线的第一端的宽度和所述连接走线的第一端的宽度相等，所述过渡部分靠近所述第一目标部分的宽度和所述第一目标部分的宽度相等，所述过渡部分的宽度随着和所述第一端之间距离的增大而减小。
可选的，所述过渡部分具有相对的第五边界和第六边界；
所述第五边界和所述第六边界中的至少一个边界和所述连接走线的延伸方向相交。
可选的，所述第五边界和所述第六边界均为直线，所述第五边界和所述第六边界中和所述连接走线的延伸方向相交的边界，与所述连接走线的延伸方向之间的夹角为钝角。
可选的，所述连接走线的第一目标部分包括沿所述连接走线的延伸方向间隔设置第一子走线和第二子走线；
所述显示模组还包括：开关晶体管以及信号传输线，所述开关晶体管的第一极和所述第一子走线连接，所述开关晶体管的第二极和所述第二子走线连接，所述开关晶体管的栅极和所述信号传输线连接，所述开关晶体管用于在显示阶段接收来自所述信号传输线提供的关闭信号，并在所述关闭信号的作用下处于关断状态。
可选的，所述显示模组包括位于所述衬底基板上层叠设置的有源层，栅极绝缘层以及栅极层；所述连接走线位于所述栅极层；
所述开关晶体管包括位于所述有源层的有源图案；所述有源图案的第一端在所述衬底基板上的正投影和所述第一子走线在所述衬底基板上的正投影存在交叠，且所述有源图案的第一端作为所述开关晶体管的第一极并通过所述栅极绝缘层中的第一过孔和所述第一子走线连接，所述有源图案的第二端在所述衬底基板上的正投影和所述第二子走线在所述衬底基板上的正投影存在交叠，所述有源图案的第二端作为所述开关晶体管的第二极并通过所述栅极绝缘层中的第二过孔和所述第二子走线连接；
所述开关晶体管还包括位于所述栅极层的栅极图案，所述栅极图案在所述衬底基板上的正投影和所述有源图案在所述衬底基板上的正投影存在交叠，且所述栅极图案作为所述开关晶体管的栅极并和所述信号传输线连接。
可选的，所述第一过孔的数量和所述第二过孔的数量均与所述连接走线的第一目标部分的宽度负相关。
可选的，所述显示模组还包括位于所述栅极层远离所述衬底基板的一侧的层间介电层和第一源漏极层；所述信号传输线位于所述第一源漏极层；
所述信号传输线在所述衬底基板上的正投影和所述栅极图案在所述衬底基板上的正投影存在交叠，且所述栅极图案通过所述层间介电层中的第三过孔和所述信号传输线连接。
可选的，所述开关晶体管还用于在测试阶段接收来自所述信号传输线提供的开启信号，并在所述开启信号的作用下处于开启状态。
可选的，所述显示模组包括位于所述衬底基板上层叠设置的有源层，栅极绝缘层，栅极层，层间介电层，第一源漏极层，第一平坦层，第二源漏极层，第二平坦层，阳极层，像素界定层，发光层，阴极层以及封装层；所述触控膜层位于所述封装层远离所述衬底基板的一侧，所述触控膜层包括：第一触控层，触控绝缘层以及第二触控层，所述触控电极位于所述第一触控层和所述第二触控层；
其中，所述阳极层，所述发光层，以及所述阴极层用于构成所述多个像素单元；
所述连接走线位于所述栅极层，所述绑定接口位于所述第二触控层，所述连接走线的第一端通过所述栅极层和所述第二触控层之间的绝缘膜层中的过孔与所述绑定接口连接。
可选的，所述显示模组还包括位于所述第一源漏极层的第一连接部，以及位于所述第二源漏极层的第二连接部；
所述连接走线的第一端通过所述层间介电层中的过孔和所述第一连接部连接，所述第一连接部和所述第二连接部通过所述第一平坦层中的过孔连接，所述第二连接部通过所述第二平坦层，所述像素界定层，所述封装层和所述触控绝缘层中的过孔连接。
另一方面，提供了一种显示模组，所述显示模组包括：衬底基板，所述衬底基板具有显示区域以及围绕所述显示区域的周边区域，所述周边区域包括位于所述显示区域一侧的绑定区域；
多个像素单元，所述多个像素单元位于所述显示区域；
触控膜层，所述触控膜层位于所述多个像素单元远离所述衬底基板的一侧，所述触控膜层至少包括触控电极；
多个绑定接口，所述多个绑定接口位于所述绑定区域，所述多个绑定接口和所述触控电极连接；
以及，多条连接走线，所述连接走线的第一端和所述绑定接口连接，所述连接走线的第一目标部分包括沿所述连接走线的延伸方向间隔设置的第一子走线和第二子走线，所述第一目标部分位于所述连接走线的第一端远离所述显示区域的一侧，且所述第一目标部分远离所述显示区域的一端通过切割得到；
所述显示模组还包括：开关晶体管以及信号传输线，所述开关晶体管的第一极和所述第一子走线连接，所述开关晶体管的第二极和所述第二子走线连接，所述开关晶体管的栅极和所述信号传输线连接，所述开关晶体管用于在显示阶段接收来自所述信号传输线提供的关闭信号，并在所述关闭信号的作用下处于关断状态。
又一方面，提供了一种显示模组的制备方法，用于制备上述方面所述的显示模组；所述制备方法包括：
获取初始显示模组，所述初始显示模组包括：初始衬底基板，所述初始衬底基板具有显示区域以及围绕所述显示区域的周边区域，所述周边区域包括位于所述显示区域一侧的绑定区域，以及位于所述绑定区域远离所述显示区域的一侧的待切割区域；多个像素单元，所述多个像素单元位于所述显示区域；触控膜层，所述触控膜层位于所述多个像素单元远离所述衬底基板的一侧，所述 触控膜层至少包括触控电极；多个绑定接口，所述多个绑定接口位于所述绑定区域，所述多个绑定接口和所述触控电极连接；多条初始连接走线，所述初始连接走线的第一端和第一目标部分位于所述绑定区域，所述初始连接走线的第一端和所述绑定接口连接；多个测试电路和多个测试接口，所述多个测试电路，所述多个测试接口以及所述初始连接走线的第二目标部分和第二端均位于所述待切割区域，所述测试电路和所述初始连接走线的第二端连接，且和所述测试接口连接；
采用测试设备依次通过所述测试接口，所述测试电路，所述初始连接走线以及所述绑定接口为所述触控电极提供检测信号，以对所述显示模组的触控性能进行测试；
采用切割设备沿所述初始连接走线的第一端和所述初始连接走线的第二端之间的切割道切割，将所述初始衬底基板的待切割区域，测试电路，测试接口以及所述初始连接走线位于所述待切割区域中的部分切除，所述初始连接走线未被切除的部分为连接走线，所述初始连接走线的第一端为所述连接走线的第一端。
可选的，所述第一目标部分为所述初始连接走线中未被切除的一部分，所述第二目标部分为所述初始连接走线被切除的一部分；
其中，所述第一目标部分和所述第二目标部分直接连接，且所述第一目标部分的宽度和所述第二目标部分的宽度相等。
再一方面，提供了一种显示面板，所述显示面板包括：柔性电路板，以及如上述方面所述的显示模组；
所述显示模组具有相对的显示侧和非显示侧，所述柔性电路板包括位于所述显示侧的多个信号接口，所述多个信号接口和所述显示模组中多个绑定接口对应连接；所述柔性电路板的至少部分位于所述显示模组的非显示侧。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中显示模组的局部示意图；
图2是本申请实施例提供的一种连接走线的短路示意图；
图3是本申请实施例提供的一种显示模组的俯视图；
图4是本申请实施例提供的一种显示模组的局部示意图；
图5是本申请实施例提供的一种切割得到显示模组之前的局部示意图；
图6是本申请实施例提供的另一种显示模组的局部示意图；
图7是本申请实施例提供的又一种显示模组的局部示意图；
图8是本申请实施例提供的一种连接走线的示意图；
图9是本申请实施例提供的另一种连接走线的示意图；
图10是本申请实施例提供的一种显示模组位于显示区域的部分截面示意图；
图11是本申请实施例提供的一种触控电极的示意图；
图12是本申请实施例提供的一种触控膜层的局部示意图；
图13是图4沿AA’方向的截面图；
图14是本申请实施例提供的再一种显示模组的局部示意图；
图15是图14沿BB’方向的截面图；
图16是本申请实施例提供的再一种显示模组的局部示意图；
图17是图16沿CC’方向的截面图；
图18是图16沿DD’方向的截面图；
图19是本申请实施例提供的一种显示模组的制备方法的流程图；
图20是本申请实施例提供的一种初始显示模组的俯视图；
图21是本申请实施例提供的一种初始显示模组的局部示意图；
图22是本申请实施例提供的另一种初始显示模组的局部示意图；
图23是本申请实施例提供的又一种初始显示模组的局部示意图；
图24是本申请实施例提供的再一种初始显示模组的局部示意图；
图25是本申请实施例提供的再一种初始显示模组的局部示意图；
图26是图21沿EE’方向的截面图；
图27是本申请实施例提供的一种显示面板的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，显示面板是在显示模组制备完成后，将柔性电路板绑定在显示模组上得到的。为了保证制备得到的显示面板的良率，需要在绑定柔性电路板之前对显示模组进行性能测试，如触控性能测试或显示性能测试。为了测试显示模组的性能，需要在制备显示模组的过程中，预留测试接口和测试电路。其中，测试接口和测试电路连接，测试电路通过连接走线和显示模组中用于与柔性电路板绑定的一个绑定接口连接。测试设备依次通过测试接口，测试电路以及连接走线为显示模组中的绑定接口提供测试信号，实现对显示模组性能的测试。在测试完成后，需要采用切割设备沿着切割道将测试接口切除，切割道位于连接走线上。
但是，在沿着切割道切割的过程中，连接走线容易因高温而产生碳化物质。碳化物质聚集在相邻的连接走线之间，容易导致相邻的连接走线短路，进而导致显示面板的良率较低。
显示模组在制备的过程中，会进行多次点亮去测试发生的各种性能上的不良。如果存在不良就可以不再进行显示模组的后续工艺，避免后续工艺中资材、人力以及产线的浪费。为了进行性能测试，需要在显示模组的外形外围增加测试接口(包括触控测试接口和显示测试接口)。这些测试接口需要绑定接口(绑定接口为后续和柔性电路板绑定的接口)，测试完成后再把这些测试接口切割掉。
图1是相关技术中显示模组的局部示意图。参考图1，显示模组中绑定接口和连接走线的宽度相等。如此，参考图2，相邻的连接走线之间的距离较小，在模组切割的过程中，连接走线会因高温而产生碳化物质，该碳化物质会将相邻的连接走线连通，导致信号短路(short)而发生不良。
图3是本申请实施例提供的一种显示模组的俯视图。参考图3，该显示模组(module，MDL)100包括：衬底基板101，多个像素单元102，触控膜层(图3未示出)，多个绑定接口(pin)103，以及多条连接走线104。
衬底基板101具有显示区域(可以称为AA区)101a以及围绕显示区域101a的周边区域101b。周边区域101b包括位于显示区域101a一侧的绑定区域101b1。
图4是本申请实施例提供的一种显示模组的局部示意图。结合图3和图4，多个像素单元102可以位于显示区域101a，多个像素单元102可以用于显示图像。触控膜层位于多个像素单元102远离衬底基板101的一侧，触控膜层至少包括触控电极。多个绑定接口103位于绑定区域101b1，且多个绑定接口103和触控膜层中的触控电极连接。连接走线104的第一端z1和绑定接口103连接，且连接走线104的第一目标部分z2的宽度h1小于绑定接口103的宽度h2。另外，相邻的连接走线104的第一目标部分z2之间的距离h3，大于相邻的绑定接口103之间的距离h4。
第一目标部分z2位于连接走线104的第一端z1远离显示区域101a的一侧，且第一目标部分z2远离显示区域101a的一端通过切割得到。
在本申请实施例中，参考图5，在切割得到连接走线104之前，测试电路以及测试接口可以位于绑定区域101b1远离显示区域101a的一侧。测设设备可以和测试接口连接，通过测试接口和测试电路为连接走线104提供测试信号，进而实现对显示模组100性能的测试。在测试完成后，需要采用切割设备沿着切割道将测试接口和测试电路切除，得到连接走线104。连接走线104中第一目标部分z2远离显示区域101a的一端即为切割设备沿着切割道切割得到的端部。
其中，连接走线104的第一目标部分z2的宽度小于绑定接口103的宽度，且相邻的连接走线104的第一目标部分z2之间的距离h3小于相邻的绑定接口103之间的距离h4，可以使得连接走线104的第一目标部分z2的宽度较小，确保相邻的第一目标部分z2之间的距离较大，避免相邻的连接走线104的第一目标部分z2短路。
在沿着切割道切割的过程中，即使连接走线104会因高温而产生碳化物质，但是相邻的连接走线104的第一目标部分z2之间的距离较大，因此切割所产生的碳化物质会聚集在一个较大的间距内。进一步的，碳化物质的总量不足以将该较大的间距填满，可以降低短路的风险。
综上所述，本申请实施例提供了一种显示模组，该显示模组包括衬底基板，位于衬底基板的显示区域的多个像素单元和触控膜层，以及位于衬底基板的绑定区域的多个绑定接口和多条连接走线。多个绑定接口和触控膜层中的触控电极连接，连接走线的第一端和绑定接口连接。连接走线中位于第一端远离显示区域的第一目标部分的宽度小于绑定接口的宽度，且相邻的连接走线的第一目 标部分之间的距离小于相邻的绑定接口之间的距离。由此，在切割得到连接走线时，即使连接走线会因切割时的高温而产生碳化物质，但相邻的连接走线的第一目标部分之间的距离较大，因此碳化物质并不能将相邻的连接走线的第一目标部分之间的间距填满，降低了相邻的连接走线短路的风险，进而提升了显示面板的良率。
在本申请实施例中，在测试阶段，测试设备需要通过测试接口，测试电路以及连接走线104为绑定接口103传输信号。如果连接走线104的第一目标部分z2的宽度太小，则会影响信号传输的可靠性，性能测试的效果也会较差。由此，可以设计连接走线104的第一目标部分z2的宽度大于或等于1.8μm(微米)，如此可以保证信号传输的可靠性。
可选的，连接走线104的第一端z1的宽度大于连接走线104的第一目标部分z2的宽度。由此可以保证连接走线104的第一端z1和绑定接口103具有足够的连接面积，保证连接的可靠性。例如，连接走线104的第一端z1的宽度可以等于绑定接口103的宽度。
参考图4，连接走线104的第一目标部分z2的第一中轴线z21，以及连接走线104的第一端z1的第二中轴线z11均沿连接走线104的延伸方向延伸。也即是，第一中轴线z21和第二中轴线z11平行。
可选的，参考图4，第一中轴线z21和第二中轴线z11共线。也即是，连接走线104的第一目标部分z2可以位于连接走线104的第一端z1的中部。此种情况下，连接走线104的第一目标部分z2中沿其延伸方向的两个边界(z2a和z2b)相对于连接走线104的第一端z1均有内缩，且内缩尺寸相等。
示例的，连接走线104的第一目标部分z2具有相对的第一边界z2a和第二边界z2b。连接走线104的第一端z1具有相对的第三边界z1a和第四边界z1b。第一边界z2a，第二边界z2b，第三边界z1a和第四边界z1b均沿连接走线104的延伸方向延伸。
第一边界z2a相对于第二边界z2b更靠近第三边界z1a，第二边界z2b相对于第一边界z2a更靠近第四边界z1b。第一边界z2a和第三边界z1a沿目标方向M的距离m1，可以等于第二边界z2b和第四边界z1b沿目标方向M的距离m2。其中，目标方向M可以垂直于连接走线104的延伸方向。
可选的，参考图6和图7，第一边界z2a和第三边界z1a共线，且构成连接 走线104的公共边界。第二边界z2b相对于第四边界z1b更靠近公共边界。由此可以使得第二边界z2b和公共边界沿目标方向M的距离，小于第四边界z1b和公共边界沿目标方向M的距离。也即是，可以实现连接走线104的第一目标部分z2的宽度小于连接走线104的第一端z1的宽度。
可选的，多条连接走线104的公共边界可以位于同一侧，而另一侧中第一目标部分z2相对于第一端内缩。示例的，参考图6，多条连接走线104的公共边界均为连接走线104的右侧边界，而左侧边界中第一目标部分z2相对于第一端内缩。或者，参考图7，多条连接走线104的公共边界均为连接走线104的左侧边界，而右侧边界中第一目标部分z2相对于第一端内缩。
可选的，连接走线104的第一端z1的第三边界z1a和第四边界z1b，以及连接走线104的第一目标部分z2的第一边界z2a和第二边界z2b均可以为直线。
在本申请实施例中，参考图4，图6和图7，连接走线104还包括位于第一目标部分z2和连接走线104的第一端z1之间的过渡部分z3。过渡部分z3靠近连接走线104的第一端z1的宽度和连接走线104的第一端z1的宽度相等。过渡部分z3靠近第一目标部分z2的宽度和第一目标部分z2的宽度相等。过渡部分z3的宽度随着和第一端之间的距离的增大而减小。
也即是，连接走线104的第一目标部分z2相对于连接走线104的第一端z1的内缩设计可以是在过渡部分z3处逐渐变化的。由此可以避免应力集中和静电集中，提高连接走线104的可靠性。
可选的，参考图8和图9，过渡部分z3具有相对的第五边界z3a和第六边界z3b。第五边界z3a和第六边界z3b中的至少一个边界和连接走线104的延伸方向相交。
示例的，参考图8，连接走线104的第一目标部分z2相对于连接走线104的第一端z1呈现两侧均内缩的情况下，第五边界z3a以及第六边界z3b均和连接走线104的延伸方向Y相交。或者，参考图9，连接走线104的第一目标部分z2相对于连接走线104的第一端z1呈现单侧内缩的情况下，第五边界z3a可以和第一边界z2a以及第三边界z1a共同构成公共边界，第六边界z3b可以和连接走线104的延伸方向相交。
可选的，第五边界z3a和第六边界z3b均为直线，第五边界z3a以及第六边界z3b中和连接走线104的延伸方向相交的边界，与连接走线104的延伸方向 之间的夹角α为钝角。也即是，第五边界z3a以及第六边界z3b中和连接走线104的延伸方向相交的边界，与连接走线104的延伸方向之间的夹角大于90度。
示例的，在图8中，第五边界z3a以及第六边界z3b和连接走线104的延伸方向之间的夹角均为钝角。或者，在图9中，第六边界z3b和连接走线104的延伸方向之间的夹角为钝角。
可选的，第五边界z3a和第六边界z3b还可以为曲线或折线，本申请实施例对此不做限定。
图10是本申请实施例提供的一种显示模组位于显示区域的部分截面示意图。参考10，显示模组100包括依次层叠的缓冲层(buffer)n1，有源层(poly)n2，栅极绝缘层(gate insulator，GI)n3，栅极层(gate)n4，层间介电层(inter level dielectric，ILD)n5，第一源漏极层n6，第一平坦层(planarization layer，PLN)n7，第二源漏极层n8，第二平坦层n9，阳极层n10，像素界定层n11，发光层n12，阴极层n13以及封装层n14。触控膜层105包括第一触控层1051，触控绝缘层1052以及第二触控层1053。
其中，显示模组100还包括和像素单元102连接，并为像素单元102提供驱动信号的像素电路。有源层n2，栅极绝缘层n3，栅极层n4，层间介电层n5，第一源漏极层n6，第一平坦层n7，以及第二源漏极层n8可以用于构成像素电路。阳极层，发光层，阴极层用于构成像素单元102。
可选的，像素电路可以包括多个薄膜晶体管(thin film transistor，TFT)和至少一个存储电容。可选的，像素电路可以包括七个薄膜晶体管和一个存储电容，即像素电路为7T1C的驱动电路。或者，像素电路可以包括其他数量的薄膜晶体管和其他数量的存储电容。本申请实施例对像素电路所包括的薄膜晶体管的数量，以及包括的存储电容的数量不做限定。
其中，每个薄膜晶体管包括栅极，源极和漏极。每个像素单元中的像素电路包括的多个薄膜晶体管中互相连接，以实现驱动该像素单元中发光单元发光的作用。
有源层包括与多个薄膜晶体管对应的多个有源图案，每个有源图案包括源极区，漏极区以及沟道区。薄膜晶体管的源极和漏极位于第一源漏极层，且薄膜晶体管的源极和源极区连接，漏极和漏极区连接。
第一栅极层包括与多个薄膜晶体管对应的多个栅极图案。沟道区为栅极图 案在衬底基板上的正投影和有源图案在衬底基板上的正投影的重叠区域。
参考图10，封装层n14包括沿远离衬底基板101的方向层叠设置的第一膜层n141，第二膜层n142以及第三膜层n143。
可选的，该第一膜层n141和该第三膜层n143可以由无机材料制成，该第二膜层n142可以由有机材料制成。例如，该第一膜层n141和该第三膜层n143可以由SiNx(氮化硅)、SiOx(氧化硅)和SiOxNy(氮氧化硅)等一种或多种无机氧化物制成。第二膜层n142可以由树脂材料制成。该树脂可以为热塑性树脂或热塑性树脂，热塑性树脂可以包括亚克力(PMMA)树脂，热固性树脂可以包括环氧树脂。
可选的，第二膜层n142可以采用喷墨打印(ink jet printing，IJP)的方法制作。第一膜层n141和第三膜层n143可以采用化学气相沉积(chemical vapor deposition，CVD)的方法制作。
需要说明的是，参考图10，触控电极S可以位于第一触控层1051和第二触控层1052。示例的，参考图11，触控电极S包括多个第一触控电极s1和多个第二触控电极s2。第一触控层1051和第二触控层1053中的其中一个触控层包括第一触控电极s1的主体电极s11，以及第二触控电极s2。第一触控层1051和第二触控层1052中的另一个触控层包括第一触控电极s1的桥接电极s12。主体电极s11和桥接电极s12通过触控绝缘层1052中的过孔电连接。
参考图11，多个第一触控电极s1沿第二方向Q排布，多个第二触控电极s2沿第一方向W排布。并且，第一触控电极s1的桥接电极s12位于和第二触控电极s2的正投影重叠的区域。其中，第一方向W可以为显示模组100的像素行方向，第二方向Q可以为显示模组100的像素列方向。
参考图12，假设第一触控层1051包括第一触控电极s1的桥接电极s12，第二触控层1053包括第一触控电极s1的主体电极s11以及第二触控电极s2。此种情况下，位于第二触控层1053的第一触控电极s1的主体电极s11通过触控绝缘层1052中的过孔连接。
可选的，第一触控电极s1和第二触控电极s2中的其中一个电极可以为发射(TX)电极，另一个电极可以为感应(RX)电极。
在显示模组100中，显示模组100还包括位于周边区域101b的触控驱动电路和触控检测电路。触控驱动电路可以和发射电极连接，用于为发射电极提供 触控驱动信号。触控检测电路可以和感应电极连接，用于从感应电极接收到发射电极和感应电极之间的感应信号。若用户的手指靠近显示模组100，则触控检测电路能够检测到用户的手指所在位置的感应信号发生变化，并可以将该感应信号发生变化的位置确定为触控位置。
在本申请实施例中，在测试阶段可以对显示模组的触控功能进行(touch panel，TP)测试。图13是图4沿AA’方向的截面图。参考图13，连接走线104和绑定接口103可以位于显示模组100的多个膜层中的不同膜层。例如，连接走线104位于显示模组100中的栅极层n4，绑定接口103可以位于显示模组100的第二触控层1053。
显示模组100还包括位于第一源漏极层n6的第一连接部106，以及位于第二源漏极层n8的第二连接部107，连接走线104的第一端z1通过第一连接部106和第二连接部107与绑定接口103连接。
具体的，连接走线104的第一端通过层间介电层n5中的过孔和第一连接部106连接，第一连接部106和第二连接部107通过第一平坦层n7中的过孔连接，第二连接部107通过第二平坦层n9，封装层n14以及触控绝缘层1052中的过孔连接。
在本申请实施例中，参考图14，连接走线104的第一目标部分z2可以包括沿连接走线104的延伸方向间隔设置的第一子走线1041和第二子走线1042。显示模组100还包括：开关晶体管T和信号传输线108。
其中，开关晶体管T包括栅极，第一极和第二极。第一极和第一子走线1041连接，第二极和第二子走线1042连接。栅极和信号传输线108连接。开关晶体管T用于在显示阶段接收来自信号传输线108提供的关闭信号，开关晶体管T用于在关闭信号的作用下处于关断状态。
此种情况下，由于开关晶体管T处于关断状态，因此可以阻止第一极和第二极之间进行信号传输。即使相邻的连接走线104的第一目标部分z2远离第一端的一侧短路(即第二子走线1042短路)，也不会导致短路信号传输至连接走线104的第一端z1，可以避免不同的绑定接口103短路。
图15是图14沿BB’方向的截面图。参考图15，开关晶体管T包括位于有源层n2的有源图案n21。有源图案n21的第一端在衬底基板101上的正投影和第一子走线1041在衬底基板101上的正投影存在交叠，且有源图案n21的第一 端可以作为开关晶体管T的第一极通过栅极绝缘层n3中的第一过孔k1和第一子走线1041连接。有源图案n21的第二端在衬底基板101上的正投影和第二子走线1042在衬底基板101上的正投影存在交叠，有源图案n21的第二端可以作为开关晶体管T的第二极并通过栅极绝缘层n3中的第二过孔k2和第二子走线1042连接。
可选的，第一过孔k1的数量和第二过孔k2的数量均与连接走线104的第一目标部分z2的宽度负相关。也即是，第一目标部分z2的宽度越小，第一过孔k1的数量和第二过孔k2的数量越多；第一目标部分z2的宽度越大，第一过孔k1的数量和第二过孔k2的数量可以越少。
第一过孔k1是用于连接开关晶体管T的有源图案n21和第一子走线1041的过孔，为了保证有源图案n21和第一子走线1041连接的可靠性，需要使得有源图案n21和第一子走线1041之间具有一定的连接面积。如果第一目标部分z2的宽度较小，则可以通过设计较多数量的第一过孔k1来提高有源图案n21和第一子走线1041之间的连接面积。
第二过孔k2是用于连接开关晶体管T的有源图案n21和第二子走线1042的过孔，为了保证有源图案n21和第二子走线1042连接的可靠性，需要使得有源图案n21和第二子走线1042之间具有一定的连接面积。如果第一目标部分z2的宽度较小，则可以通过设计较多数量的第二过孔k2来提高有源图案n21和第二子走线1042之间的连接面积。
参考图15，显示模组100的栅极绝缘层n3中具有两个第一过孔k1和两个第二过孔k2，有源图案n21和第一子走线1041通过两个第一过孔k1连接，有源图案和第二子走线1042通过两个第二过孔k2连接。
开关晶体管T还包括位于栅极层n4的栅极图案n41，栅极图案n41在衬底基板101上的正投影和有源图案n21在衬底基板101上的正投影存在交叠。并且，栅极图案n41可以作为开关晶体管T的栅极并和信号传输线108连接。
假设信号传输线108为开关晶体管T的栅极提供开启信号，则开关晶体管T的第一极和第二极导通，来自开关晶体管T的第二极的信号可以传输至开关晶体管T的第一极，进而传输至绑定接口103。假设信号传输线108为开关晶体管T的栅极提供关断信号，则开关晶体管T的第一极和第二极之间信号断开，来自开关晶体管T的第二极的信号是无法传输至开关晶体管T的第一极的，也无 法传输至绑定接口103。
在测试阶段，测试设备需要通过测试接口，测试电路以及连接走线104为绑定接口103提供检测信号，因此需要使得信号导通。此种情况下，信号传输线108可以为开关晶体管T的栅极提供开启信号，以使得开关晶体管T处于开启状态，进而使得检测信号能够通过开关晶体管T传输至绑定接口103。
在测试阶段之后，需要采用切割设备沿切割道进行切割，而连接走线104会因切割时的高温而产生碳化物质，可能会导致相邻的连接走线104短路(例如相邻的连接走线104的第二子走线1042短路)。
因此在显示阶段，为了避免短路信号传输至绑定接口103，可以使得信号传输线108为开关晶体管T的栅极提供关断信号，以使得开关晶体管T处于关断状态。
参考图15，连接走线104位于显示模组100的栅极层n4，开关晶体管T的栅极图案n41也位于显示模组100的栅极层n4，且连接走线104的第一子走线1041以及第二子走线1042均和开关晶体管T的栅极图案n41具有间隙。并且，绑定接口103可以位于第二触控层1053，连接走线104的第一端z1通过第一连接部106和第二连接部107与绑定接口103连接。
可选的，由于第一源漏极层n6相对于栅极层n4而言，且电阻更小，更利用传输信号。因此可以使得信号传输线108位于第一源漏极层n6。信号传输线108在衬底基板101上的正投影和栅极图案n41在衬底基板101上的正投影存在交叠，且栅极图案n41通过第二栅极绝缘层n2中的第三过孔k3和信号传输线108连接。
进一步的，参考图14，开关晶体管T的栅极图案n41的宽度可以等于第一目标部分z2的宽度。为了保证信号传输线108和栅极图案n41连接的可靠性，需要使得信号传输线108和栅极图案n41之间具有一定的连接面积。如果栅极图案n41的宽度较小，则可以通过设计较多数量的第三过孔k3来提高栅极图案n41和信号传输线108之间的连接面积。
参考图14，显示模组100还包括信号传输接口109和信号传输连接走线110。其中，信号传输接口109可以和绑定接口103位于同层，如位于第二触控层1053。信号传输连接走线110可以和连接走线104位于同层，如位于栅极层n4。信号传输接口109和信号传输连接走线110可以通过第一连接部106和第二连接部 107连接。信号传输连接走线110远离信号传输接口109的一端还和信号传输线108连接。并且，由于信号传输连接走线110(栅极层n4)和信号传输线108(第一源漏极层n6)位于不同层，因此可以通过层间介电层n5中的第四过孔k4连接。
可选的，信号传输连接走线110中除了和信号传输接口109连接的端部之外，其他部分的宽度以及内缩设计可以和连接走线104相同。也即是信号传输连接走线110的宽度也较小，由此可以通过设计较多数量的第四过孔k4来提高信号传输连接走线110和信号传输线108之间的连接面积，提高连接的可靠性。
可选的，信号传输连接走线110的延伸方向可以和连接走线104的延伸方向平行，信号传输线108的延伸方向和多条连接走线104的排布方向平行。例如，多条连接走线104沿显示模组100的像素行方向排布，信号传输线108的延伸方向为像素行方向。
另外，有源图案n21的宽度也可以等于第一目标部分z2的宽度。本申请实施例对此不做限定。
需要说明的是，信号传输线108还可以位于第二源漏极层n8。此种情况下，信号传输线108可以通过层间介电层以及第二栅极绝缘层n2中的过孔和开关晶体管T的栅极图案n41连接。或者，信号传输线108还可以位于栅极层n4。此种情况下，沿目标方向M排布的多个开关晶体管T的栅极图案n41可以为一体结构，且该一体结构和第一子走线1041以及第二子走线1042间隔设置。
在本申请实施例中，参考图5，显示模组100还包括多条信号走线111，信号走线111的一端和绑定接口103连接，另一端和位于显示区域101a的触控电极连接。由此即可使得触控电极在测试阶段接收到触控测试信号。
可选的，信号走线111可以包括位于第一触控层的第一信号子走线，以及位于第二触控层的第二信号子走线。第一信号子走线和第二信号子走线通过触控绝缘层中的过孔连接。
需要说明的是，在测试阶段还可以对显示模组100的显示功能进行测试。此种情况下，显示模组100还包括包括多个显示绑定接口，多个显示连接走线，以及多个显示信号走线。例如参考图5，将图中的绑定接口103替换为显示绑定接口，将图中的连接走线替换为显示连接走线，将图中的信号走线替换为显示信号走线即可。
示例的，显示连接走线可以和显示绑定接口连接，且显示连接走线的设计可以和连接走线104相同。也即是，显示连接走线中靠近切割道的一部分的宽度小于显示绑定接口的宽度，且相邻的显示连接走线中靠近切割道的一部分之间的距离，大于相邻的显示绑定接口的距离。或者，显示连接走线中设计有开关晶体管，并使得开关晶体管在测试阶段处于开启状态，在显示阶段处于关断状态。
并且，显示信号走线的一端和显示绑定接口连接，另一端用于和像素单元连接。由此即可使得像素单元在测试阶段接收到显示测试信号。
可选的，显示连接走线可以位于栅极层，显示绑定接口可以位于第二触控层。显示信号走线可以包括位于第一栅极层的第一显示信号子走线，位于第一源漏极层的第二显示信号子走线，以及位于第二源漏极层的第三显示信号子走线。第一显示信号子走线和第二显示信号子走线通过第二栅极绝缘层中的过孔连接，第二显示信号子走线和第三显示信号子走线通过层间介电层中的过孔连接。
在本申请实施例中，显示模组可以为有机发光二极管(organic light emitting diode，OLED)搭载柔性多层on cell触控技术(flexible multi-layer on cell，FMLOC)得到的显示模组。此种显示模组更轻更薄便于适应折叠及卷曲产品。
参考图3可以看出，显示模组100还可以包括驱动集成电路(integrated circuit，IC)112。该驱动集成电路可以称为驱动芯片，驱动集成电路112可以和多个像素单元102以及绑定接口103连接，主要功能是用于控制来自柔性电路板为像素单元102提供的信号。
综上所述，本申请实施例提供了一种显示模组，该显示模组包括衬底基板，位于衬底基板的显示区域的多个像素单元和触控膜层，以及位于衬底基板的绑定区域的多个绑定接口和多条连接走线。多个绑定接口和触控膜层连接，连接走线的第一端和绑定接口连接。连接走线中位于第一端远离显示区域的第一目标部分的宽度小于绑定接口的宽度，且相邻的第一目标部分之间的距离小于相邻的绑定接口之间的距离。由此，在切割得到连接走线时，即使连接走线会因切割时的高温而产生碳化物质，但相邻的连接走线的第一目标部分之间的距离较大，因此碳化物质并不能将相邻的连接走线的第一目标部分的间距填满，降低了相邻的连接走线短路的风险，进而提升了显示面板的良率。
图16是本申请实施例提供的再一种显示模组的示意图。参考图16，该显示模组100包括：衬底基板101，多个像素单元102，触控膜层(图16未示出)，多个绑定接口103，以及多条连接走线104。
参考图2，衬底基板101具有显示区域101a以及围绕显示区域101a的周边区域101b。周边区域101b包括位于显示区域101a一侧的绑定区域101b1。
结合图5，图11以及图16，多个像素单元102可以位于显示区域101a，多个像素单元102可以用于显示图像。触控膜层位于多个像素单元102远离衬底基板101的一侧，触控膜层至少包括触控电极。多个绑定接口103位于绑定区域101b1，且多个绑定接口103和触控膜层中的触控电极连接。连接走线104的第一端z1和绑定接口103连接。连接走线104的第一目标部分z2包括沿连接走线104的延伸方向间隔设置的第一子走线1041和第二子走线1042。第一目标部分z2位于连接走线104的第一端z1远离显示区域101a的一侧，且第一目标部分z2远离显示区域101a的一端通过切割得到。
在本申请实施例中，参考图5，在切割得到连接走线104之前，测试电路以及测试接口可以位于绑定区域101b1远离显示区域101a的一侧。测设设备可以和测试接口连接，通过测试接口和测试电路为连接走线104提供测试信号，进而实现对显示模组100性能的测试。在测试完成后，需要采用切割设备沿着切割道将测试接口和测试电路切除，得到连接走线104。连接走线104中第一目标部分z2远离显示区域101a的一端即为切割设备沿着切割道切割得到的端部。
显示模组100还包括：开关晶体管T以及信号传输线108。开关晶体管T包括栅极，第一极和第二极。第一极和第一子走线1041连接，第二极和第二子走线1042连接。栅极和信号传输线108连接，开关晶体管T用于在显示阶段接收来自信号传输线108提供的关闭信号，且在关闭信号的作用下处于关断状态。
在测试阶段，测试设备需要通过测试接口，测试电路以及连接走线104为绑定接口103提供检测信号，因此需要使得信号导通。此种情况下，信号传输线108可以为开关晶体管T的栅极提供开启信号，以使得开关晶体管T处于开启状态，进而使得检测信号能够通过开关晶体管T传输至绑定接口103。
在测试阶段之后，需要采用切割设备沿切割道进行切割，而连接走线104会因切割时的高温而产生碳化物质，可能会导致相邻的连接走线104中靠近切 割道的部分短路(例如相邻的连接走线104的第二子走线1042短路)。
因此在显示阶段，为了避免短路信号传输至绑定接口103，可以使得信号传输线108为开关晶体管T的栅极提供关断信号，以使得开关晶体管T处于关断状态。此种情况下，由于开关晶体管T处于关断状态，因此可以阻止第一极和第二极之间进行信号传输。即使相邻的连接走线104的第二子走线1042短路，也不会导致短路信号传输至连接走线104的第一端z1，可以避免不同的绑定接口103短路。
综上所述，本申请实施例提供了一种显示模组，该显示模组包括衬底基板，位于衬底基板的显示区域的多个像素单元和触控膜层，以及位于衬底基板的绑定区域的多个绑定接口和多条连接走线。多个绑定接口和触控膜层中的触控电极连接，连接走线的第一端和绑定接口连接。在切割得到连接走线时，即使连接走线因切割时的高温而产生碳化物质导致靠近切割道的第二子走线短路，但在显示阶段，连接走线的第一目标部分包括的第一子走线和第二子走线之间的开关晶体管处于关断状态。由此，可以避免短路信号传输至绑定接口，避免不同的绑定接口短路，进而提升了显示面板的良率。
参考图16，连接走线104中的各个位置的宽度相等。也即是，连接走线104的第一目标部分z2相对于第一端可以无需进行内缩设计。可选的，连接走线104的宽度可以等于绑定接口103的宽度。
图17是图16沿CC’方向的截面图。参考图17，连接走线104和绑定接口103可以位于显示模组100的多个膜层中的不同膜层。例如，参考图11，显示模组100包括依次层叠的缓冲层(buffer)n1，有源层(poly)n2，栅极绝缘层(gate insulator，GI)n3，栅极层(gate)n4，层间介电层(inter level dielectric，ILD)n5，第一源漏极层n6，第一平坦层(planarization layer，PLN)n7，第二源漏极层n8，第二平坦层n9，阳极层n10，像素界定层n11，发光层n1,2，阴极层n13以及封装层n14。触控膜层105包括第一触控层1051，触控绝缘层1052以及第二触控层1053。
其中，显示模组100还包括用于驱动像素单元102发光的像素电路。有源层n2，栅极绝缘层n3，栅极层n4，层间介电层n5，第一源漏极层n6，第一平坦层n7，以及第二源漏极层n8可以用于构成像素电路。阳极层，发光层，阴极层用于构成像素单元102。
可选的，像素电路可以包括多个薄膜晶体管(thin film transistor，TFT)和至少一个存储电容。可选的，像素电路可以包括七个薄膜晶体管和一个存储电容，即像素电路为7T1C的驱动电路。或者，像素电路可以包括其他数量的薄膜晶体管和其他数量的存储电容。本申请实施例对像素电路所包括的薄膜晶体管的数量，以及包括的存储电容的数量不做限定。
其中，每个薄膜晶体管包括栅极，源极和漏极。每个像素单元中的像素电路包括的多个薄膜晶体管中互相连接，以实现驱动该像素单元中发光单元发光的作用。
有源层包括与多个薄膜晶体管对应的多个有源图案，每个有源图案包括源极区，漏极区以及沟道区。薄膜晶体管的源极和漏极位于第一源漏极层，且薄膜晶体管的源极和源极区连接，漏极和漏极区连接。
第一栅极层包括与多个薄膜晶体管对应的多个栅极图案。沟道区为栅极图案在衬底基板上的正投影和有源图案在衬底基板上的正投影的重叠区域。
需要说明的是，参考图12，触控电极S可以位于第一触控层1051和第二触控层1052。示例的，触控电极S包括多个第一触控电极s1和多个第二触控电极s2。第一触控层1051和第二触控层1053中的其中一个触控层包括第一触控电极s1的主体电极s11，以及第二触控电极s2。第一触控层1051和第二触控层1052中的另一个触控层包括第一触控电极s1的桥接电极s12。主体电极s11和桥接电极s12通过触控绝缘层1052中的过孔电连接。
参考图12，多个第一触控电极s1沿第二方向Q排布，多个第二触控电极s2沿第一方向W排布。并且，第一触控电极s1的桥接电极s12位于和第二触控电极s2的正投影重叠的区域。其中，第一方向W可以为显示模组100的像素行方向，第二方向Q可以为显示模组100的像素列方向。
参考图13，假设第一触控层1051包括第一触控电极s1的桥接电极s12，第二触控层1053包括第一触控电极s1的主体电极s11以及第二触控电极s2。此种情况下，位于第二触控层1053的第一触控电极s1的主体电极s11通过触控绝缘层1052中的过孔连接。
可选的，第一触控电极s1和第二触控电极s2中的其中一个电极可以为发射(TX)电极，另一个电极可以为感应(RX)电极。
在显示模组中，显示模组100还包括位于周边区域101b的触控驱动电路和 触控检测电路。触控驱动电路可以和发射电极连接，用于为发射电极提供触控驱动信号。触控检测电路可以和感应电极连接，用于从感应电极接收到发射电极和感应电极之间的感应信号。若用户的手指靠近显示模组，则触控检测电路能够检测到用户的手指所在位置的感应信号发生变化，并可以将该感应信号发生变化的位置确定为触控位置。
在本申请实施例中，在测试阶段可以对显示模组100的触控功能进行测试。参考图17，连接走线104位于显示模组100中的栅极层n4，绑定接口103可以位于显示模组100的第二触控层1053。显示模组100还包括位于第一源漏极层n6的第一连接部106，以及位于第二源漏极层n8的第二连接部107，连接走线104的第一端z1通过第一连接部106和第二连接部107与绑定接口103连接。
具体的，连接走线104的第一端通过层间介电层n5中的过孔和第一连接部106连接，第一连接部106和第二连接部107通过第一平坦层n7中的过孔连接，第二连接部107通过第二平坦层n9，封装层n14以及触控绝缘层1052中的过孔连接。
参考图17，开关晶体管T包括位于有源层n2的有源图案n21。有源图案n21的第一端在衬底基板101上的正投影和第一子走线1041在衬底基板101上的正投影存在交叠，且有源图案n21的第一端可以作为开关晶体管T的第一极通过栅极绝缘层n3中的第一过孔k1和第一子走线1041连接。有源图案n21的第二端在衬底基板101上的正投影和第二子走线1042在衬底基板101上的正投影存在交叠，有源图案n21的第二端可以作为开关晶体管T的第二极并通过栅极绝缘层n3中的第二过孔k2和第二子走线1042连接。
参考图17，显示模组100的栅极绝缘层n3中具有一个第一过孔k1和一个第二过孔k2。有源图案和第一子走线1041通过一个第一过孔k1连接，有源图案和第二子走线1042通过一个第二过孔k2连接。
开关晶体管T还包括位于栅极层n4的栅极图案n41，栅极图案n41在衬底基板101上的正投影和有源图案n21在衬底基板101上的正投影存在交叠。并且，栅极图案n41可以作为开关晶体管T的栅极并和信号传输线108连接。
假设信号传输线108为开关晶体管T的栅极提供开启信号，则开关晶体管T的第一极和第二极导通，来自开关晶体管T的第二极的信号可以传输至开关晶体管T的第一极，进而传输至绑定接口103。假设信号传输线108为开关晶体管 T的栅极提供关断信号，则开关晶体管T的第一极和第二极之间信号断开，来自开关晶体管T的第二极的信号是无法传输至开关晶体管T的第一极的，也无法传输至绑定接口103。
在测试阶段，测试设备需要通过测试接口，测试电路以及连接走线104为绑定接口103提供检测信号，因此需要使得信号导通。此种情况下，信号传输线108可以为开关晶体管T的栅极提供开启信号，以使得开关晶体管T处于开启状态，进而使得检测信号能够通过开关晶体管T传输至绑定接口103。
在测试阶段之后，需要采用切割设备沿切割道进行切割，而连接走线104会因切割时的高温而产生碳化物质，可能会导致相邻的连接走线104短路(例如相邻的连接走线104的第二子走线1042短路)。
因此在显示阶段，为了避免短路信号传输至绑定接口103，可以使得信号传输线108为开关晶体管T的栅极提供关断信号，以使得开关晶体管T处于关断状态。
参考图17，连接走线104位于显示模组100的栅极层n4，开关晶体管T的栅极图案n41也位于显示模组的栅极层n4，且连接走线104的第一子走线1041以及第二子走线1042均和开关晶体管T的栅极图案n41具有间隙。并且，绑定接口103可以位于第二触控层1053，连接走线104的第一端z1通过第一连接部106和第二连接部107与绑定接口103连接。
可选的，由于第一源漏极层n6相对于栅极层n4而言，且电阻更小，更利用传输信号。因此可以使得信号传输线108位于第一源漏极层n6。信号传输线108在衬底基板101上的正投影和栅极图案n41在衬底基板101上的正投影存在交叠，且栅极图案n41通过第二栅极绝缘层n2中的第三过孔k3和信号传输线108连接。
进一步的，参考图17，开关晶体管T的栅极图案n41的宽度可以等于第一目标部分z2的宽度。为了保证信号传输线108和栅极图案n41连接的可靠性，需要使得信号传输线108和栅极图案n41之间具有一定的连接面积。如果栅极图案n41的宽度较小，则可以通过设计较多数量的第三过孔k3来提高栅极图案n41和信号传输线108之间的连接面积。
参考图17，显示模组100还包括信号传输接口109和信号传输连接走线110。其中，信号传输接口109可以和绑定接口103位于同层，如位于第二触控层1053。 信号传输连接走线110可以和连接走线104位于同层，如位于栅极层n4。信号传输接口109和信号传输连接走线110可以通过第一连接部106和第二连接部107连接。信号传输连接走线110远离信号传输接口109的一端还和信号传输线108连接。并且，由于信号传输连接走线110(栅极层n4)和信号传输线108(第一源漏极层n6)位于不同层，因此可以通过层间介电层n5中的第四过孔k4连接。
可选的，信号传输连接走线110的宽度可以和连接走线104的宽度相同。图18是图16沿DD’方向的截面图。参考图18，有源图案n21的宽度可以和栅极图案n41的宽度相等。另外，有源图案n21的宽度可以等于第一目标部分z2的宽度。本申请实施例对此不做限定。
可选的，信号传输连接走线110的延伸方向可以和连接走线104的延伸方向平行，信号传输线108的延伸方向和多条连接走线104的排布方向平行。例如，多条连接走线104沿显示模组的像素行方向排布，信号传输线108的延伸方向为像素行方向。
需要说明的是，信号传输线108还可以位于第二源漏极层n8。此种情况下，信号传输线108可以通过层间介电层以及第二栅极绝缘层n2中的过孔和开关晶体管T的栅极图案n41连接。或者，信号传输线108还可以位于栅极层n4。此种情况下，沿目标方向M排布的多个开关晶体管T的栅极图案n41可以为一体结构，且该一体结构和第一子走线1041以及第二子走线1042间隔设置。
综上所述，本申请实施例提供了一种显示模组，该显示模组包括衬底基板，位于衬底基板的显示区域的多个像素单元和触控膜层，以及位于衬底基板的绑定区域的多个绑定接口和多条连接走线。多个绑定接口和触控膜层中的触控电极连接，连接走线的第一端和绑定接口连接。在切割得到连接走线时，即使连接走线因切割时的高温而产生碳化物质导致靠近切割道的第二子走线短路，但在显示阶段，连接走线的第一目标部分包括的第一子走线和第二子走线之间的开关晶体管处于关断状态。由此，可以避免短路信号传输至绑定接口，避免不同的绑定接口短路，进而提升了显示面板的良率。
图19是本申请实施例提供了一种显示模组的制备方法的流程图。该方法可以应用于制备上述实施例所提供的显示模组。参考图19，该方法包括：
步骤S101、获取初始显示模组。
在本申请实施例中，参考图20，初始显示模组100a包括：初始衬底基板101c，多个像素单元102，触控膜层(图20未示出)，多个绑定接口103，多条初始连接走线104a，多个测试电路和多个测试接口。
参考图20，初始衬底基板101c具有显示区域101a以及围绕显示区域101a的周边区域101b，周边区域101b包括位于显示区域101a一侧的绑定区域101b1，以及位于绑定区域101b1远离显示区域101a的一侧的待切割区域101b2。
多个像素单元102位于显示区域101a，多个像素单元102用于显示图像。触控膜层位于多个像素单元102远离衬底基板101的一侧，触控膜层至少包括触控电极。多个绑定接口103位于绑定区域101b1，且多个绑定接口103和多触控膜层中的触控电极连接。初始连接走线104a的第一端z1和绑定接口103连接，初始连接走线104a的第一端z1和第一目标部分z2位于绑定区域101b1。多个测试电路，多个测试接口以及初始连接走线104a的第二端z3和第二目标部分z4位于待切割区域101b2。测试电路和初始连接走线104a的第二端z3连接，且和测试接口连接。
在本申请实施例中，初始显示模组100a可以为沿切割道切割之前的显示模组100。切割道可以位于初始连接走线104a的第一端z1和第二端z3之间。
步骤S102、测试设备依次通过测试接口，测试电路，初始连接走线以及绑定接口为触控电极提供检测信号，以对显示模组的触控性能进行测试。
在本申请实施例中，对于图21至图23所示的方案而言，测试设备可以直接通过测试接口，测试电路，初始连接走线104a以及绑定接口103为触控电极提供检测信号。对于图24和图25所示的方案而言，信号传输线108可以为开关晶体管T的栅极提供开启信号，开关晶体管T在开启信号的作用下处于开启状态。此种情况下，开关晶体管T的第二极和第一极导通。测试设备提供的信号可以从开关晶体管T的第二极传输至第一极，进而为触控电极提供检测信号。
步骤S103、采用切割设备沿初始连接走线的第一端和初始连接走线的第二端之间的切割道切割。
在本申请实施例中，沿着切割道切割后即可得到显示模组100。其中，切割之后可以将初始衬底基板101c的待切割区域101b2，测试电路，测试接口以及初始连接走线104a位于待切割区域101b2的部分切除。
其中，初始连接走线104a中未被切除的部分为显示模组100中的连接走线104。例如，切割道位于第一目标部分z2和第二目标部分之间，初始连接走线104a中未被切除的部分包括第一端z1和第一目标部分z2，被切除的部分包括第二端z3和第二目标部分z4。
可选的，在切割之前，第一目标部分z2和第二目标部分z4直接连接，且第一目标部分z2的宽度和第二目标部分z4的宽度相等。
参考图21至图24，第一目标部分z2的宽度和第二目标部分z4的宽度可以均小于绑定接口103的宽度。或者，参考图25，第一目标部分z2的宽度和第二目标部分z4的宽度可以等于绑定接口103的宽度。
可选的，第一目标部分z2的第一中轴线z21和第二目标部分z4的第三中轴线共线。例如，在图21所示的方案中，第一目标部分z2和第二目标部分z4沿其延伸方向的两个边界相对于初始连接走线104a的端部(第一端和第二端)均有内缩。在图22和图23所示的方案中，第一目标部分z2和第二目标部分z4沿其延伸方向的其中一个相对于初始连接走线104a的端部(第一端和第二端)存在内缩。
参考图20以及图21至图25，初始显示模组100a还包括：多条过渡走线。过渡走线的第一端和初始连接走线104a的第二端z3连接，过渡走线的第二端和测试电路连接。其中，过渡走线的宽度可以大于或等于初始连接走线104a的第二目标部分z4的宽度。过渡走线的宽度可以和绑定接口103的宽度相等，且大于初始连接走线104a的第二目标部分的宽度。由于切割道和过渡走线的距离较远，因此切割时的高温对过渡走线的影响较小。
参考图26，过渡走线可以位于初始显示模组100a的第一源漏极层n6，该过渡走线的第一端可以通过第二栅极绝缘层n2中的第五过孔k5和初始连接走线104a的第二端连接。其中图26示出了两个第五过孔k5。
综上所述，本申请实施例提供了一种显示模组的制备方法，该方法制备得到的显示模组包括衬底基板，位于衬底基板的显示区域的多个像素单元和触控膜层，以及位于衬底基板的绑定区域的多个绑定接口和多条连接走线。多个绑定接口和触控膜层中的触控电极连接，连接走线的第一端和绑定接口连接。
连接走线中位于第一端远离显示区域的第一目标部分的宽度小于绑定接口的宽度，且相邻的第一目标部分之间的距离小于相邻的绑定接口之间的距离。 由此，在切割得到连接走线时，即使连接走线会因切割时的高温而产生碳化物质，但碳化物质的总量不足以将相邻的连接走线的第一目标部分之间的间距填满，降低了相邻的连接走线短路的风险，进而提升了显示面板的良率。
或者，在切割得到连接走线时，即使连接走线因切割时的高温而产生碳化物质导致连接走线中靠近切割道的第二子走线短路，但在显示阶段，连接走线的第一目标部分包括的第一子走线和第二子走线之间的开关晶体管处于关断状态。由此，可以避免短路信号传输至绑定接口，避免不同的绑定接口短路，进而提升了显示面板的良率。
图27是本申请实施例提供的一种显示面板的结构示意图。参考图27，显示面板包括：柔性电路板(flexible printed circuit，FPC)200，以及如上述实施例所提供的显示模组100。显示模组100具有相对的显示侧a和非显示侧b。柔性电路板200包括位于显示侧a的多个信号接口201，多个信号接口201和显示模组100中多个绑定接口103对应连接。柔性电路板200的至少部分位于显示模组200的非显示侧b。
从图27可以看出，柔性电路板200的一部分位于显示模组100的显示侧a，用于和显示模组100进行绑定，另一部分从显示模组100的侧边弯折至显示模组100的非显示侧b。由此可以减小显示面板的边框的尺寸，便于实现窄边框的产品。
由于显示面板可以与前面实施例描述的显示模组具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示面板的技术效果。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。
本申请的实施方式部分使用的术语仅用于对本申请的实施例进行解释，而非旨在限定本申请。除非另作定义，本申请的实施方式使用的技术术语或者科学术语应当为本申请所属领域内具有一般技能的人士所理解的通常意义。本申请专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组 成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示模组，其特征在于，所述显示模组包括：
    衬底基板，所述衬底基板具有显示区域以及围绕所述显示区域的周边区域，所述周边区域包括位于所述显示区域一侧的绑定区域；
    多个像素单元，所述多个像素单元位于所述显示区域；
    触控膜层，所述触控膜层位于所述多个像素单元远离所述衬底基板的一侧，所述触控膜层至少包括触控电极；
    多个绑定接口，所述多个绑定接口位于所述绑定区域，所述多个绑定接口和所述触控电极连接；
    以及，多条连接走线，所述连接走线的第一端和所述绑定接口连接，所述连接走线的第一目标部分的宽度小于所述绑定接口的宽度，且相邻的所述连接走线的第一目标部分之间的距离，大于相邻的所述绑定接口之间的距离；
    其中，所述第一目标部分位于所述连接走线的第一端远离所述显示区域的一侧，且所述第一目标部分远离所述显示区域的一端通过切割得到。
  2. 根据权利要求1所述的显示模组，其特征在于，所述连接走线的第一目标部分的宽度大于或等于1.8微米。
  3. 根据权利要求1所述的显示模组，其特征在于，所述连接走线的第一端的宽度大于所述连接走线的第一目标部分的宽度。
  4. 根据权利要求3所述的显示模组，其特征在于，所述连接走线的第一目标部分的第一中轴线，以及所述连接走线的第一端的第二中轴线均沿所述连接走线的延伸方向延伸。
  5. 根据权利要求4所述的显示模组，其特征在于，所述第一中轴线和所述第二中轴线共线。
  6. 根据权利要求4所述的显示模组，其特征在于，所述连接走线的第一目标 部分具有相对的第一边界和第二边界，所述连接走线的第一端具有相对的第三边界和第四边界；
    所述第一边界和所述第三边界共线，且构成所述连接走线的公共边界，所述第二边界相对于所述第四边界更靠近所述公共边界；
    其中，所述第一边界，所述第二边界，所述第三边界以及所述第四边界均沿所述连接走线的延伸方向延伸。
  7. 根据权利要求3所述的显示模组，其特征在于，所述连接走线还包括位于所述第一目标部分和所述连接走线的第一端之间的过渡部分；
    所述过渡部分靠近所述连接走线的第一端的宽度和所述连接走线的第一端的宽度相等，所述过渡部分靠近所述第一目标部分的宽度和所述第一目标部分的宽度相等，所述过渡部分的宽度随着和所述第一端之间距离的增大而减小。
  8. 根据权利要求7所述的显示模组，其特征在于，所述过渡部分具有相对的第五边界和第六边界；
    所述第五边界和所述第六边界中的至少一个边界和所述连接走线的延伸方向相交。
  9. 根据权利要求8所述的显示模组，其特征在于，所述第五边界和所述第六边界均为直线，所述第五边界和所述第六边界中和所述连接走线的延伸方向相交的边界，与所述连接走线的延伸方向之间的夹角为钝角。
  10. 根据权利要求1至9任一所述的显示模组，其特征在于，所述连接走线的第一目标部分包括沿所述连接走线的延伸方向间隔设置第一子走线和第二子走线；
    所述显示模组还包括：开关晶体管以及信号传输线，所述开关晶体管的第一极和所述第一子走线连接，所述开关晶体管的第二极和所述第二子走线连接，所述开关晶体管的栅极和所述信号传输线连接，所述开关晶体管用于在显示阶段接收来自所述信号传输线提供的关闭信号，并在所述关闭信号的作用下处于关断状态。
  11. 根据权利要求10所述的显示模组，其特征在于，所述显示模组包括位于所述衬底基板上层叠设置的有源层，栅极绝缘层以及栅极层；所述连接走线位于所述栅极层；
    所述开关晶体管包括位于所述有源层的有源图案；所述有源图案的第一端在所述衬底基板上的正投影和所述第一子走线在所述衬底基板上的正投影存在交叠，且所述有源图案的第一端作为所述开关晶体管的第一极并通过所述栅极绝缘层中的第一过孔和所述第一子走线连接，所述有源图案的第二端在所述衬底基板上的正投影和所述第二子走线在所述衬底基板上的正投影存在交叠，所述有源图案的第二端作为所述开关晶体管的第二极并通过所述栅极绝缘层中的第二过孔和所述第二子走线连接；
    所述开关晶体管还包括位于所述栅极层的栅极图案，所述栅极图案在所述衬底基板上的正投影和所述有源图案在所述衬底基板上的正投影存在交叠，且所述栅极图案作为所述开关晶体管的栅极并和所述信号传输线连接。
  12. 根据权利要求11所述的显示模组，其特征在于，所述第一过孔的数量和所述第二过孔的数量均与所述连接走线的第一目标部分的宽度负相关。
  13. 根据权利要求11所述的显示模组，其特征在于，所述显示模组还包括位于所述栅极层远离所述衬底基板的一侧的层间介电层和第一源漏极层；所述信号传输线位于所述第一源漏极层；
    所述信号传输线在所述衬底基板上的正投影和所述栅极图案在所述衬底基板上的正投影存在交叠，且所述栅极图案通过所述层间介电层中的第三过孔和所述信号传输线连接。
  14. 根据权利要求10所述的显示模组，其特征在于，所述开关晶体管还用于在测试阶段接收来自所述信号传输线提供的开启信号，并在所述开启信号的作用下处于开启状态。
  15. 根据权利要求1至9任一所述的显示模组，其特征在于，所述显示模组 包括位于所述衬底基板上层叠设置的有源层，栅极绝缘层，栅极层，层间介电层，第一源漏极层，第一平坦层，第二源漏极层，第二平坦层，阳极层，像素界定层，发光层，阴极层以及封装层；所述触控膜层位于所述封装层远离所述衬底基板的一侧，所述触控膜层包括：第一触控层，触控绝缘层以及第二触控层，所述触控电极位于所述第一触控层和所述第二触控层；
    其中，所述阳极层，所述发光层，以及所述阴极层用于构成所述多个像素单元；
    所述连接走线位于所述栅极层，所述绑定接口位于所述第二触控层，所述连接走线的第一端通过所述栅极层和所述第二触控层之间的绝缘膜层中的过孔与所述绑定接口连接。
  16. 根据权利要求15所述的显示模组，其特征在于，所述显示模组还包括位于所述第一源漏极层的第一连接部，以及位于所述第二源漏极层的第二连接部；
    所述连接走线的第一端通过所述层间介电层中的过孔和所述第一连接部连接，所述第一连接部和所述第二连接部通过所述第一平坦层中的过孔连接，所述第二连接部通过所述第二平坦层，所述像素界定层，所述封装层和所述触控绝缘层中的过孔连接。
  17. 一种显示模组，其特征在于，所述显示模组包括：衬底基板，所述衬底基板具有显示区域以及围绕所述显示区域的周边区域，所述周边区域包括位于所述显示区域一侧的绑定区域；
    多个像素单元，所述多个像素单元位于所述显示区域；
    触控膜层，所述触控膜层位于所述多个像素单元远离所述衬底基板的一侧，所述触控膜层至少包括触控电极；
    多个绑定接口，所述多个绑定接口位于所述绑定区域，所述多个绑定接口和所述触控电极连接；
    以及，多条连接走线，所述连接走线的第一端和所述绑定接口连接，所述连接走线的第一目标部分包括沿所述连接走线的延伸方向间隔设置的第一子走线和第二子走线，所述第一目标部分位于所述连接走线的第一端远离所述显示区域的一侧，且所述第一目标部分远离所述显示区域的一端通过切割得到；
    所述显示模组还包括：开关晶体管以及信号传输线，所述开关晶体管的第一极和所述第一子走线连接，所述开关晶体管的第二极和所述第二子走线连接，所述开关晶体管的栅极和所述信号传输线连接，所述开关晶体管用于在显示阶段接收来自所述信号传输线提供的关闭信号，并在所述关闭信号的作用下处于关断状态。
  18. 一种显示模组的制备方法，其特征在于，用于制备上述权利要求1至17任一所述的显示模组；所述制备方法包括：
    获取初始显示模组，所述初始显示模组包括：初始衬底基板，所述初始衬底基板具有显示区域以及围绕所述显示区域的周边区域，所述周边区域包括位于所述显示区域一侧的绑定区域，以及位于所述绑定区域远离所述显示区域的一侧的待切割区域；多个像素单元，所述多个像素单元位于所述显示区域；触控膜层，所述触控膜层位于所述多个像素单元远离所述衬底基板的一侧，所述触控膜层至少包括触控电极；多个绑定接口，所述多个绑定接口位于所述绑定区域，所述多个绑定接口和所述触控电极连接；多条初始连接走线，所述初始连接走线的第一端和第一目标部分位于所述绑定区域，所述初始连接走线的第一端和所述绑定接口连接；多个测试电路和多个测试接口，所述多个测试电路，所述多个测试接口以及所述初始连接走线的第二目标部分和第二端均位于所述待切割区域，所述测试电路和所述初始连接走线的第二端连接，且和所述测试接口连接；
    采用测试设备依次通过所述测试接口，所述测试电路，所述初始连接走线以及所述绑定接口为所述触控电极提供检测信号，以对所述显示模组的触控性能进行测试；
    采用切割设备沿所述初始连接走线的第一端和所述初始连接走线的第二端之间的切割道切割，将所述初始衬底基板的待切割区域，测试电路，测试接口以及所述初始连接走线位于所述待切割区域中的部分切除，所述初始连接走线未被切除的部分为连接走线，所述初始连接走线的第一端为所述连接走线的第一端。
  19. 根据权利要求18所述的方法，其特征在于，所述第一目标部分为所述初 始连接走线中未被切除的一部分，所述第二目标部分为所述初始连接走线被切除的一部分；
    其中，所述第一目标部分和所述第二目标部分直接连接，且所述第一目标部分的宽度和所述第二目标部分的宽度相等。
  20. 一种显示面板，其特征在于，所述显示面板包括：柔性电路板，以及如权利要求1至17任一所述的显示模组；
    所述显示模组具有相对的显示侧和非显示侧，所述柔性电路板包括位于所述显示侧的多个信号接口，所述多个信号接口和所述显示模组中多个绑定接口对应连接；所述柔性电路板的至少部分位于所述显示模组的非显示侧。
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Publication number Priority date Publication date Assignee Title
CN107479283A (zh) * 2017-08-30 2017-12-15 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN114488632A (zh) * 2022-01-27 2022-05-13 武汉天马微电子有限公司 一种显示面板、显示装置及其检测方法
CN115513226A (zh) * 2022-09-23 2022-12-23 京东方科技集团股份有限公司 一种显示基板及显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107479283A (zh) * 2017-08-30 2017-12-15 厦门天马微电子有限公司 一种阵列基板、显示面板及显示装置
CN114488632A (zh) * 2022-01-27 2022-05-13 武汉天马微电子有限公司 一种显示面板、显示装置及其检测方法
CN115513226A (zh) * 2022-09-23 2022-12-23 京东方科技集团股份有限公司 一种显示基板及显示装置

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