Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/30—Stacked capacitors

Definitions

• the present invention relates to a multilayer ceramic capacitor.
• Patent Document 1 discloses a technology for improving the reliability of multilayer ceramic capacitors with external electrodes having the above-mentioned configuration by adjusting the distance between the surface of the laminate and the internal electrodes, etc.
• multilayer ceramic capacitors equipped with external electrodes having the above-described configuration have the problem that moisture may enter the interior of the laminate from the end faces of the laminate.
• the external electrodes have the above-described configuration, one reason for this is thought to be that the external electrodes are only arranged to extend to some of the surfaces of the laminate, and there are surfaces of the laminate to which the external electrodes do not extend.
• the present invention therefore aims to provide a multilayer ceramic capacitor with improved reliability.
• the multilayer ceramic capacitor of the present invention comprises a laminate including stacked dielectric layers and internal electrodes, and having first and second surfaces facing the stacking direction, third and fourth surfaces facing a first direction intersecting the stacking direction, and fifth and sixth surfaces facing a second direction intersecting the stacking direction and the first direction; a first external electrode provided on the fifth surface, a third external electrode provided on the second surface and connected to the first external electrode, a second external electrode provided on the sixth surface, and a fourth external electrode provided on the second surface and connected to the second external electrode; wherein a line connecting the ends of the first internal electrode in the first direction on the fifth surface is aligned with the contour of the end of the first external electrode in the first direction on the fifth surface, or a line connecting the ends of the second internal electrode in the first direction on the sixth surface is aligned with the contour of the end of the second external electrode in the first direction on the sixth surface.
• the present invention makes it possible to provide a multilayer ceramic capacitor with improved reliability.
• FIG. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor according to one embodiment of the present invention.
• FIG. 2 is a cross-sectional view taken along line 101-101 in FIG.
• FIG. 3 is a cross-sectional view taken along line 102-102 in FIG.
• FIG. 4 is a cross-sectional view taken along line 103-103 in FIG.
• FIG. 5 is a view showing the sixth surface side of the multilayer ceramic capacitor according to one embodiment of the present invention.
• FIG. 6 is a view showing the third surface side of the multilayer ceramic capacitor according to one embodiment of the present invention.
• FIG. 7 is a diagram showing a multilayer chip of a multilayer ceramic capacitor according to one embodiment of the present invention.
• FIG. 1 is an external perspective view of a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure.
• the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape.
• the multilayer ceramic capacitor 1 includes a laminate 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes arranged spaced apart from each other at both ends of the laminate 2.
• the arrow T in Figure 1 indicates the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 2.
• the stacking direction T is also called the thickness direction or height direction of the multilayer ceramic capacitor 1 and the laminate 2.
• the arrow L indicates a second direction L that is perpendicular to the stacking direction T of the multilayer ceramic capacitor 1 and the laminate 2.
• the arrow W indicates a first direction W that is perpendicular to the stacking direction T and the second direction L of the multilayer ceramic capacitor 1 and the laminate 2.
• the stacking direction T, the second direction L, and the first direction W are mutually perpendicular.
• the arrows T, L, and L each indicate the same directions as described above.
• One of the pair of external electrodes is primarily provided at one end of the laminate 2 in the second direction L, and the other is provided at the other end.
• Fig. 2 is a diagram showing the internal structure of the laminate 2.
• the laminate 2 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrodes 30.
• the internal electrodes 30 include a first internal electrode 31 and a second internal electrode 32.
• the two surfaces of the laminate 2 that face the stacking direction T are called the first surface 3 and the second surface 4.
• the two surfaces of the laminate 2 that face the first direction W are called the third surface 5 and the fourth surface 6.
• the two surfaces of the laminate 2 that face the second direction L are called the fifth surface 7 and the sixth surface 8.
• the corners and ridges of the laminate 2 are rounded, but are not limited to this. Corners are areas where three surfaces of the laminate 2 intersect, and ridges are areas where two surfaces of the laminate 2 intersect. Concave and concave portions may be formed on some or all of the surfaces of the laminate 2.
• the total number of dielectric layers 20 included in the laminate 2 is preferably 15 or more and 700 or less.
• the ceramic material contained in the dielectric layer 20 may be, for example, a dielectric ceramic whose main component is BaTiO 3 , CaTiO 3 , SrTiO 3 , or CaZrO 3 . Furthermore, the ceramic material may be one in which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, an Ni compound, or an Mg compound is added to the main component.
• a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, an Ni compound, or an Mg compound is added to the main component.
• each dielectric layer 20 is preferably 0.2 ⁇ m or more and 10 ⁇ m or less.
• Fig. 2 is a cross-sectional view taken along line 101-101 in Fig. 1.
• the laminate 2 can be divided, in the lamination direction T connecting the first surface 3 and the second surface 4, into an inner layer portion 10 in which the internal electrodes 30 are provided, a first-surface-side outer layer portion 12 which is the portion between the first surface 3 and the internal electrode 30 closest to the first surface 3, and a second-surface-side outer layer portion 13 which is the portion between the second surface 4 and the internal electrode 30 closest to the second surface 4.
• the first-surface-side outer layer portion 12 and the second-surface-side outer layer portion 13 are collectively referred to as the outer layer portion 11.
• the first surface side outer layer portion 12 is located on the first surface 3 side of the laminate 2 and is a dielectric layer 20 located between the first surface 3 and the internal electrode 30 closest to the first surface 3.
• the first surface side outer layer portion 12 can also be an assembly of multiple dielectric layers 20.
• the second surface side outer layer portion 13 is located on the second surface 4 side of the laminate 2 and is a dielectric layer 20 located between the second surface 4 and the internal electrode 30 closest to the second surface 4.
• the second surface side outer layer portion 13 can also be an assembly of multiple dielectric layers 20.
• the area sandwiched between the first surface side outer layer portion 12 and the second surface side outer layer portion 13 is the internal layer portion 10.
• the dimensions of the laminate 2 are not particularly limited.
• the internal electrode 30 includes a first internal electrode 31 and a second internal electrode 32.
• the first internal electrode 31 is an internal electrode 30 arranged so as to be exposed on the fifth surface 7.
• the second internal electrode 32 is an internal electrode 30 arranged so as to be exposed on the sixth surface 8.
• the first internal electrode 31 has a first opposing portion 33 opposing the second internal electrode 32, and a first lead-out portion 35 extending from the first opposing portion 33 to the fifth surface 7.
• the second internal electrode 32 has a second opposing portion 34 opposing the first internal electrode 31, and a second lead-out portion 36 extending from the second opposing portion 34 to the sixth surface 8.
• the shape of the first opposing portion 33 of the first internal electrode 31 is generally rectangular, but is not particularly limited to this.
• the corners may be rounded or angled (tapered), or the corners may be tapered so that they slope in either direction.
• the shape of the second opposing portion 34 of the second internal electrode 32 is generally rectangular, but is not particularly limited to this.
• the corners may be rounded or angled (tapered), or the corners may be tapered so that they slope in either direction.
• the shape of the first lead portion 35 of the first internal electrode 31 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or angled (tapered). It may also be tapered, with a slope increasing in either direction.
• the shape of the second lead portion 36 of the second internal electrode 32 is not particularly limited, but is preferably rectangular. However, the corners may be rounded or angled (tapered). It may also be tapered, with a slope increasing in either direction.
• the corner portion refers to the portion located at the corner of the external shape of the internal electrode 30 when the internal electrode 30 is viewed in a cross section parallel to the second direction L and the first direction W of the laminate 2.
• the width in the first direction W of the first opposing portion 33 of the first internal electrode 31 and the width in the first direction W of the first lead-out portion 35 of the first internal electrode 31 may be the same width, or one of the widths may be narrower.
• the width in the first direction W of the second opposing portion 34 of the second internal electrode 32 and the width in the first direction W of the second lead-out portion 36 of the second internal electrode 32 may be the same width, or one of the widths may be narrower.
• the first internal electrode 31 and the second internal electrode 32 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.
• an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.
• the portion where the first internal electrode 31 and the second internal electrode 32 overlap is called the opposing electrode portion 14.
• the opposing electrode portion 14 is the portion where the first opposing portion 33 and the second opposing portion 34 overlap.
• capacitance is formed when opposing portions of the internal electrodes 30 face each other with the dielectric layer 20 interposed therebetween, thereby realizing the characteristics of the capacitor.
• capacitance is formed in the opposing electrode portion 14.
• the opposing electrode portion 14 is also called the effective layer portion.
• (W gap) 3 is a cross-sectional view taken along line 102-102 in FIG. 1.
• the portions of the laminate 2 between the first-surface-side outer layer portion 12, the inner layer portion 10, and the second-surface-side outer layer portion 13 and the third surface 5 are referred to as third-surface-side side margin portions 15.
• the portions of the laminate 2 between the first-surface-side outer layer portion 12, the inner layer portion 10, and the second-surface-side outer layer portion 13 and the fourth surface 6 are referred to as fourth-surface-side side margin portions 16.
• No internal electrodes are provided in the third-surface-side side margin portions 15 and the fourth-surface-side side margin portions 16, and only dielectric layers 20 are provided therein.
• the third-surface-side side margin portions 15 and the fourth-surface-side side margin portions 16 are also referred to as W-gaps.
• L gap In the laminate 2, a portion located between the counter electrode portion 14 and the fifth surface 7 or the sixth surface 8 and including the lead portion of either the first internal electrode 31 or the second internal electrode 32 is called an L gap.
• the L gap includes a fifth surface outer layer portion 17 and a sixth surface outer layer portion 18.
• the fifth surface outer layer portion 17 is located between the counter electrode portion 14 and the fifth surface 7 and is a portion including the first lead portion 35.
• the sixth surface outer layer portion 18 is located between the counter electrode portion 14 and the sixth surface 8 and is a portion including the second lead portion 36.
• each of the first internal electrode 31 and the second internal electrode 32 is, for example, approximately 0.2 ⁇ m or more and 2.0 ⁇ m or less.
• first internal electrodes 31 and second internal electrodes 32 be 15 or more and 700 or less.
• external electrodes are formed on the fifth surface 7, the sixth surface 8, and the second surface 4.
• the external electrodes are It includes a first external electrode 411 provided on the fifth surface 7, a second external electrode 421 provided on the sixth surface 8, a third external electrode 412 provided on the second surface 4 and connected to the first external electrode 411, and a fourth external electrode 422 provided on the second surface 4 and connected to the second external electrode 421.
• the external electrodes include plating layers 75.
• the plating layers 75 include a first plating layer 71, a second plating layer 72, and a third plating layer 73. These plating layers are stacked in the order of the first plating layer 71 in contact with the laminate 2, the second plating layer 72, and the third plating layer 73.
• the material of the first plating layer 71 can be Cu.
• the material of the second plating layer 72 can be Ni.
• the material of the third plating layer 73 can be Sn.
• the third plating layer 73 which is the outermost plating layer, is preferably a Sn plating layer.
• Sn is a material that has good solder wettability.
• the second plating layer 72 is preferably a Ni plating layer.
• Ni is a material with high solder barrier properties. By using a Ni plating layer for the second plating layer 72, it is possible to prevent solder from penetrating into the laminate 2 or the internal electrode 30.
• the first plating layer 71 is preferably a Cu plating layer.
• Cu is a material that has good bonding properties with Ni.
• a Cu plating layer for the first plating layer 71 it is possible to prevent the second plating layer 72 from peeling off from the first plating layer 71 when the second plating layer 72 is a Ni plating layer.
• a Cu plating layer for the first plating layer 71 it is possible to improve the bonding properties between the first plating layer 71 and the internal electrode 30 when the internal electrode 30 is made of Ni.
• the third external electrode 412 and the fourth external electrode 422 each include a metal layer 77 in addition to the plating layer 75.
• the metal layer 77 is formed between the laminate 2 and the plating layer 75. In the example shown in FIG. 3 , the metal layer 77 is formed between the laminate 2 and the first plating layer 71.
• the metal layer 77 can be formed by sputtering. The material of the metal layer 77 can be selected as appropriate.
• FIG. 4 is a cross-sectional view taken along line 103-103 in FIG. 1.
• FIG. 4 shows a cross section of the laminate 2 at the center position in the second direction L, on a plane parallel to the first direction W and the lamination direction T.
• the ends of the internal electrodes 30 in the first direction W are called internal electrode width ends 300.
• the positions of the internal electrode width ends 300 in the first direction W are aligned.
• the internal electrode width ends 300 are positioned on approximately the same straight line. A specific description will be given below.
• the internal electrode width end 300 of the internal electrode 30 closest to the first surface 3 is called the third surface side width end 301.
• the internal electrode width end 300 of the internal electrode 30 closest to the second surface 4 is called the fourth surface side width end 302.
• the internal electrode width ends 300 other than the third surface side width end 301 and the fourth surface side width end 302 are called inner layer width ends 303.
• straight line 200 connects third surface side width edge 301 and fourth surface side width edge 302 at the center position in the second direction L of laminate 2.
• Lines 202 and 203 are both parallel to line 200.
• inner layer width edges 301, 302, and 303 are located between line 201 and line 203 in the first direction W.
• the distance in the first direction W between line 200 and line 202 is distance 211.
• the distance in the first direction W between line 200 and line 203 is distance 212.
• Distance 211 is 3 ⁇ m or less.
• Distance 212 is 3 ⁇ m or less.
• a straight line 201 is a straight line that includes the third-surface width edge 301 and the fourth-surface width edge 302 on the fifth surface 7 or the sixth surface 8 of the laminate 2.
• the contours of the ends of the first direction W of the first external electrode 411 and the second external electrode 421 are called ridge lines 44.
• a line 205 is a straight line that indicates the ridge line 44 of the first external electrode 411.
• the lines 201 and 205 are parallel.
• Parallel here does not mean parallel in the strict sense.
• Parallel means that the lines are substantially parallel, which can also be rephrased as a state in which the directions are aligned.
• a substantially parallel state means, for example, that the angle between the lines 201 and 205 is between 0 degrees and 5 degrees.
• the reliability of the multilayer ceramic capacitor 1 can be improved.
• the distance between wires 201 and 205 can be made approximately constant in the stacking direction T.
• the margin in the first direction W when the external electrode covers the internal electrode 30 extended to the fifth surface 7 or sixth surface 8 of the laminate 2 is made approximately constant. This makes it possible to prevent moisture from penetrating into the interior of the laminate 2 from around the internal electrode 30 extended to the fifth surface 7 or sixth surface 8 of the laminate 2. This makes it possible to improve the reliability of the multilayer ceramic capacitor 1.
• line 205 is located between line 201 and third surface 5 in the first direction W.
• the end of second external electrode 421 on the third surface 5 side in the first direction W is located between the surface including the end of internal electrode 30 on the third surface 5 side in the first direction W and the surface including third surface 5.
• the inner layer portion 10 is the portion where the internal electrodes 30 are stacked. Therefore, the above means that the end portion of the second external electrode 421 on the third surface 5 side in the first direction W is located between the surface of the inner layer portion 10 that includes the surface on the third surface 5 side and the surface that includes the third surface 5.
• Second-surface external electrode lines Straight lines indicating a direction parallel to the third external electrode 412 and the fourth external electrode 422 are referred to as second-surface external electrode lines.
• the direction indicated by the second-surface external electrode lines is usually parallel to the second surface 4 and the internal electrodes 30 of the multilayer body 2.
• the multilayer ceramic capacitor 1 is mounted on a substrate or the like with the third external electrode 412 and the fourth external electrode 422 in contact with the substrate or the like.
• the surfaces of the third external electrode 412 and the fourth external electrode 422 can be said to be the mounting surface of the multilayer ceramic capacitor 1.
• the second-surface external electrode lines can be said to be parallel to the mounting surface of the multilayer ceramic capacitor 1.
• the lines 205 are perpendicular to the second-surface external electrode lines. Note that “perpendicular” here does not mean “perpendicular” in the strict sense. “Perpendicular” means being substantially perpendicular. “Substantially perpendicular” means, for example, that the angle between the lines 205 and the second-surface external electrode lines is between 0 degrees and 5 degrees.
• the line 205 is perpendicular to the second-surface external electrode line including the mounting surface.
• the mounting direction of the multilayer ceramic capacitor 1 is perpendicular to the mounting surface. Therefore, the line 205 indicating the ridge line 44 is substantially parallel to the mounting direction.
• the external electrode margin In the first external electrode 411 and the second external electrode 421, the portion between the line 201 and the line 205 described above is called the external electrode margin.
• the external electrode margin is the portion between the internal electrode width end 300 and the ridge line 44 in the first direction W.
• the length of the external electrode margin in the first direction W is defined as the margin width.
• the margin width is 3 ⁇ m or more.
• the length between the end of the first plating layer 71 in the first direction W and the line 201 be 2 ⁇ m or more.
• the margin width of the external electrode margin in the first direction W can also be determined based on the amount of Mg contained in the dielectric layer 20.
• Mg compounds may be added to the ceramic material that forms the dielectric layer 20. Mg tends to suppress grain growth of the dielectric material. When grain growth of the dielectric material is suppressed, the grain size becomes smaller and the number of grain boundaries increases. Increasing the number of grain boundaries can improve the voltage resistance of the dielectric material.
• Mg can reduce the moisture resistance of the multilayer ceramic capacitor 1. Furthermore, Mg tends to accumulate in areas where the internal electrodes 30 are present. Therefore, it is preferable that the margin width of the external electrode margin in the first direction W be long enough to adequately cover the areas with a high Mg content near the internal electrode width ends 300 of the internal electrodes 30. For example, if the Mg concentration at the ends of the fifth surface 7 or sixth surface 8 of the laminate 2 in the first direction W is set to 100%, the margin width of the external electrode margin in the first direction W can be determined so that the external electrode covers the area with an Mg content of 10% or more.
• the area of the first plating layer 71 be 150% or more of the area of the exposed internal electrode 30. This can improve the moisture resistance of the multilayer ceramic capacitor 1.
• the internal electrode 30 is formed of Ni and the first plating layer 71 is a copper plating layer, satisfying the above-mentioned area ratio can further improve the moisture resistance of the multilayer ceramic capacitor 1.
• FIG. 5 is a view of the multilayer ceramic capacitor as viewed in the direction of arrow 105 in FIG. 1 .
• Line 208 in FIG. 5 is a straight line parallel to the surface of the third surface 5 and the stacking direction T.
• Line 209 is a straight line parallel to the fourth surface 6 and the stacking direction T.
• the distance in the first direction W between line 205 indicating the ridge line 44 and line 208 is distance 216.
• the distance in the first direction W between line 205 and line 209 is distance 217.
• the difference between distance 216 and distance 217 is 5 ⁇ m or less. That is, distance 216 and distance 217 are substantially the same.
• the number of dielectric voids is smaller and the overall area of the dielectric voids is smaller than in conventional multilayer ceramic capacitors.
• the number of dielectric voids in the dielectric layers 20 included in the dielectric layers 20 is smaller and the overall area of the dielectric voids is smaller. Therefore, the moisture resistance of the multilayer ceramic capacitor 1 can be improved.
• the number of dielectric voids is small in the above-mentioned portion, and the overall area of the dielectric voids is small. As a result, the moisture resistance of the multilayer ceramic capacitor 1 is prevented from decreasing.
• the multilayer ceramic capacitor 1 of this embodiment there are fewer dielectric voids in the dielectric layers 20 in the outer layer portions. Therefore, the multilayer ceramic capacitor 1 has high moisture resistance.
• the porosity of the dielectric layer 20 in the portion between the contour of the end of the external electrode in the first direction W and the third surface 5 or the fourth surface 6 is 6% or less.
• Internal electrode width end voids 38 and metal segregation 39 such as Ni-Mg-O cause a decrease in the moisture resistance of the multilayer ceramic capacitor 1.
• the formation of internal electrode width end voids 38 and metal segregation 39 such as Ni-Mg-O is suppressed. As a result, the moisture resistance of the multilayer ceramic capacitor 1 is high.
• metal segregation 39 such as Ni-Mg-O may inhibit grain growth of the dielectric material. Therefore, when there is little metal segregation 39 such as Ni-Mg-O, grain growth of the dielectric material progresses, and the dielectric grain size tends to increase. As the dielectric grain size increases, the dielectric constant of the dielectric layer increases, and as a result, the capacitance of the multilayer ceramic capacitor 1 can be increased. In the multilayer ceramic capacitor 1 of this embodiment, the formation of metal segregation 39 such as Ni-Mg-O is inhibited in the area including the opposing electrode portion 14. This prevents excessive grain growth from reducing the number of grain boundaries and reducing reliability.
• the incidence of internal electrode width end voids 38 and metal segregation 39 of Mg or the like near the internal electrode width ends 300 is 15% or less.
• the incidence of internal electrode width end voids 38 and metal segregation 39 of Mg or the like can be calculated as the number of layers with segregation or voids relative to the number of internal electrodes.
• the thickness of the third external electrode 412 in the stacking direction T is preferably, for example, 10 ⁇ m or less. By reducing the thickness to 10 ⁇ m or less, the strength of the external electrode can be increased. Furthermore, the angle between the second surface 4 and the tangent to the end of the third external electrode 412 in the direction of the sixth surface 8 is preferably equal to or greater than 0° and less than 90°. The acute angle can suppress the occurrence of cracks in the laminate 2.
• a length 271 in Fig. 6 indicates the length of the third external electrode 412 in the second direction L on the second surface 4.
• a length 272 in Fig. 6 is the length of the fourth external electrode 422 in the second direction L on the second surface 4.
• a length 273 in Fig. 6 is the distance in the second direction L between the second direction end 413 of the third external electrode 412 and the second direction end 413 of the fourth external electrode 422.
• lengths 271 and 272 By making lengths 271 and 272 longer than length 273, the mechanical strength of multilayer ceramic capacitor 1 can be increased.
• the ratio of the sum of lengths 271 and 272 to the sum of lengths 271, 272, and 273, i.e., (length 271 + length 272) / (length 271 + length 272 + length 273), is preferably 50% or more and 90% or less, and more preferably 60% or more and 80% or less.
• Lengths 271 and 272 are usually equal.
• the areas of the third external electrode 412, the fourth external electrode 422, and the second surface 4 will now be described. That is, when the multilayer ceramic capacitor 1 is viewed from the second surface 4 side, the area of the third external electrode 412 is area 281, and the area of the fourth external electrode 422 is area 282. The area of the second surface 4 is area 284. The higher the ratio of the sum of the areas 281 and 282 to the area 284, the higher the mountability and mechanical strength of the multilayer ceramic capacitor 1.
• the ratio of the sum of the area 281 of the third external electrode 412 and the area 282 of the fourth external electrode 422 to the area 284 of the second surface 4, i.e., (area 281 + area 282) / (area 284), is preferably 50% or more and 90% or less. Note that the areas 281 and 282 are usually equal.
• Fig. 7 is a diagram showing a multilayer chip 90 in which a first side gap sheet 91 and a second side gap sheet 92 are attached to a chip body 80. Note that the method for manufacturing the multilayer ceramic capacitor 1 is not limited to the method described below.
• the laminate 2 is formed using the chip body 80, the first side gap sheet 91, and the second side gap sheet 92.
• the laminate 2 before firing is referred to as the laminated chip 90.
• the portion corresponding to the third-surface side margin portion 15 after firing is referred to as the first side gap sheet 91
• the portion corresponding to the fourth-surface side margin portion 16 after firing is referred to as the second side gap sheet 92.
• the portion other than the first side gap sheet 91 and the second side gap sheet 92 is referred to as the chip body 80.
• the portion corresponding to the first surface outer layer portion 12 after firing is called the first element outer layer portion 81
• the portion corresponding to the second surface outer layer portion 13 after firing is called the second element outer layer portion 82.
• the portion other than the first element outer layer portion 81 and the second element outer layer portion 82 is called the element inner layer portion 83.
• the element inner layer portion 83 becomes the inner layer portion 10 after firing.
• dielectric sheets for the first element body outer layer part 81, the second element body outer layer part 82, and the element body inner layer part 83 are prepared.
• conductive paste for the element body inner layer part 83 is prepared.
• the dielectric sheets become the dielectric layers 20 in the laminate 2.
• the conductive paste becomes the internal electrodes 30 in the laminate 2.
• Both the dielectric sheets and the conductive paste contain a binder and a solvent.
• the binder and solvent may be known.
• the conductive paste contains a metal powder, an organic binder, and an organic solvent.
• Conductive paste for the internal electrode 30 is printed onto the dielectric sheet for the element body layer portion 83 using a printing plate designed to form a pattern in the shape of the internal electrode 30.
• printing methods include screen printing and gravure printing. This prepares a dielectric sheet on which the pattern of the first internal electrode 31 is formed and a dielectric sheet on which the pattern of the second internal electrode 32 is formed.
• the portion that will become the first surface outer layer portion 12 is layered on top of this.
• This portion is formed by layering a predetermined number of dielectric sheets for the first element body outer layer portion 81, which do not have the internal electrode 30 pattern printed on them. In this way, the chip body 80 is obtained.
• the first side gap sheet 91 and the second side gap sheet 92 are attached to the chip body 80 to obtain the laminated chip 90.
• the laminated chip is then fired to obtain the laminate 2.
• the laminated chip may be pressed or polished by barrel polishing or the like to round off corners or ridges, as necessary.
• the firing temperature depends on the materials of the dielectric layer 20 and internal electrode 30, but is preferably between 900°C and 1400°C, for example.
• the external electrodes are formed.
• the external electrodes are formed mainly by electrolytic plating. Formation of the external electrodes is mainly carried out by forming a metal layer 77 on the second surface 4, followed by forming a plating layer 75 on the fifth surface 7, the sixth surface 8, and the second surface 4.
• the formation of the metal layer 77 will now be described.
• the area on the second surface 4 where the metal layer 77 is formed is referred to as the metal layer formation area. Areas other than the metal layer formation area are referred to as the non-formation area.
• the non-forming areas are masked.
• the metal layer 77 is formed in the unmasked areas where the metal layer is to be formed by sputtering, vapor deposition, or the like.
• electrolytic plating is performed using the internal electrode 30 as an electrode.
• the exposed internal electrode 30 serves as an electrode, and a plating layer 75 is formed.
• the plating layer 75 formed on the fifth surface 7 or sixth surface 8 of the laminate extends and connects to the metal layer 77, so that a plating layer is also grown by electrolytic plating in the metal layer formation region.
• a plating layer 75 is formed on the fifth surface 7 or sixth surface 8 of the laminate and in the metal layer formation region.
• the plating layer 75 includes a first plating layer 71, a second plating layer 72, and a third plating layer 73. Therefore, the above-mentioned electrolytic plating is performed a total of three times for each plating layer.
• the external electrode is not formed over the entire surface of the fifth surface 7 or the sixth surface 8.
• the fifth surface 7 or the sixth surface 8 of the laminate 2 there is a portion between the external electrode and the third surface or the fourth surface of the laminate 2 where the external electrode is not formed.
• the external electrodes are formed by electrolytic plating. This is because the external electrodes are unlikely to be formed in areas away from the exposed internal electrodes 30.
• the external electrodes are formed on the fifth surface 7 or sixth surface 8 up to the second surface 4. This is because the metal layer 77 is formed on the second surface 4 as described above.
• the multilayer ceramic capacitor 1 is manufactured through the above manufacturing process.
• the first plating layer 71 may be a base electrode layer formed as a baked layer.
• the base electrode layer is formed by baking a conductive paste applied to the laminate 2 at a temperature of, for example, 700°C or higher and 900°C or lower.
• the conductive paste may be, for example, a material containing a glass component and a metal.

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