WO2025185201A1 - 一种存储器及其访问控制方法、电子设备 - Google Patents

一种存储器及其访问控制方法、电子设备

Info

Publication number
WO2025185201A1
WO2025185201A1 PCT/CN2024/129765 CN2024129765W WO2025185201A1 WO 2025185201 A1 WO2025185201 A1 WO 2025185201A1 CN 2024129765 W CN2024129765 W CN 2024129765W WO 2025185201 A1 WO2025185201 A1 WO 2025185201A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
reference voltage
memory
transistor
common bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/129765
Other languages
English (en)
French (fr)
Other versions
WO2025185201A8 (zh
Inventor
朱正勇
康卜文
赵超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Superstring Academy of Memory Technology
Original Assignee
Beijing Superstring Academy of Memory Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Superstring Academy of Memory Technology filed Critical Beijing Superstring Academy of Memory Technology
Priority to KR1020257043606A priority Critical patent/KR20260015299A/ko
Publication of WO2025185201A1 publication Critical patent/WO2025185201A1/zh
Publication of WO2025185201A8 publication Critical patent/WO2025185201A8/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, device design in the field of semiconductor technology, and in particular to a memory and an access control method thereof, and an electronic device.
  • the present application provides a memory, comprising:
  • At least one memory array comprising at least one memory cell array and a sense amplifier connected to the memory cell array, the memory cell array comprising a plurality of memory cells and a plurality of bit lines; the memory cell comprising a read transistor, the read transistor comprising a first electrode and a second electrode, the first electrode being connected to the bit line, the second electrode being connected to a first reference voltage terminal or a read word line; the sense amplifier being connected to a second reference voltage terminal, and using a second reference voltage at the second reference voltage terminal as a reference voltage;
  • the common bit line corresponds to the memory cell array one-to-one, the common bit line is connected to multiple bit lines in the corresponding memory cell array, each common bit line corresponds to one sense amplifier, each common bit line is connected to a switch sub-circuit, and the switch sub-circuit is also connected to a third reference voltage terminal, wherein,
  • the switch subcircuit is configured to: connect the third reference voltage terminal and the common bit line in a signal sensing phase; and disconnect the third reference voltage terminal and the common bit line in a signal amplification phase;
  • the third reference voltage, the second reference voltage, and the first reference voltage of the third reference voltage terminal satisfy the following conditions: in a signal sensing phase, when the data stored in the memory cell is different, the common bit line outputs different voltages, and the output voltages have different magnitude relationships with the second reference voltage;
  • the first reference voltage is the voltage applied to the read word line during the signal sensing phase, or is the voltage at the first reference voltage terminal.
  • the memory array includes multiple layers of the memory cell arrays stacked in a direction perpendicular to the substrate, and each layer of the memory cell array corresponds to one of the common bit lines.
  • the voltage of the third reference voltage terminal is a fixed voltage; or, the voltage of the third reference voltage terminal is a variable voltage.
  • the voltage of the third reference voltage terminal is a fixed voltage
  • the third reference voltage and the first reference voltage satisfy: when the switching sub-circuit and the read transistor are both turned on, the voltage of the common bit line is greater than the second reference voltage
  • the voltage of the third reference voltage terminal is a fixed voltage
  • the third reference voltage and the first reference voltage satisfy: when the switching sub-circuit and the read transistor are both turned on, the voltage of the common bit line is less than the second reference voltage.
  • the switching subcircuit includes a switching transistor, a gate electrode of the switching transistor is connected to a control line, a first electrode of the switching transistor is connected to the common bit line and an input terminal of the sense amplifier, and a second electrode of the switching transistor is connected to the third reference voltage terminal.
  • gate control terminals of a plurality of the switch sub-circuits connected to a plurality of common bit lines of a same memory array are connected to a same control line, and the control line is configured to simultaneously turn on or off the plurality of the switch sub-circuits.
  • the memory cell further includes a write transistor, and the bit line is a bit line shared by the read transistor and the write transistor.
  • the memory cell further includes a write transistor, and the bit line is a read bit line connected only to the read transistor.
  • the memory includes multiple memory arrays, and multiple sense amplifiers are arranged between two adjacent memory arrays along the extension direction of the common bit line, and every two common bit lines belonging to adjacent memory arrays are connected to the same sense amplifier, wherein one common bit line is connected to one end of the sense amplifier and the first switch sub-circuit, and the other common bit line is connected to the other end of the sense amplifier and the second switch sub-circuit.
  • An embodiment of the present disclosure provides a method for controlling access to a memory, including:
  • the switch sub-circuit connected to the common bit line of the memory cell to be accessed is controlled to be turned on, so as to connect the third reference voltage terminal and the common bit line;
  • the switch sub-circuit connected to the common bit line of the memory cell to be accessed is controlled to be closed, so that the common bit line is disconnected from the third reference voltage terminal.
  • the method further includes: during the data write-back phase, turning off the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal.
  • the method further includes: in a pre-charging stage before the signal sensing stage, closing the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal, and loading the second reference voltage to the common bit line.
  • An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.
  • the electronic device further includes a control circuit, and the control circuit is configured to perform access control on the memory according to the above-mentioned memory access control method.
  • FIG1 is a schematic diagram of a storage array provided by a technical solution
  • FIG2A is a schematic diagram of a memory provided in an embodiment of the present application.
  • FIG2B is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment
  • FIG2C is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment
  • FIG3A is a schematic diagram of a memory provided by other embodiments.
  • FIG3B is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment
  • FIG3C is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment
  • FIG. 3D is a schematic diagram of an equivalent circuit of a sense amplifier provided by an exemplary embodiment.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.
  • orientation or positional relationships such as “middle,” “upper,” “lower,” “front,” “back,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings.
  • This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure.
  • the positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.
  • the terms “mounted,” “connected,” and “connected” should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.
  • a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the gate electrode may be single-gate or double-gate, and the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to the region through which current primarily flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa.
  • the functions of the "source electrode” and “drain electrode” may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms “source electrode” and “drain electrode” may be reversed.
  • connection includes the situation where the components are connected together through an element having some electrical function.
  • element having some kind of electrical function There are no particular restrictions on the term “element having some kind of electrical function” as long as it can transmit and receive electrical signals between connected components. Examples of “element having some kind of electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means approximately parallel or nearly parallel.
  • angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°.
  • perpendicular means approximately perpendicular.
  • the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.
  • Memory can include multiple memory cells in a memory array. Capacitive coupling may exist between adjacent bit lines within multiple memory cells, particularly in 3D stacked memory cell applications. In this case, strong capacitive coupling between bit lines can affect signal sensing and amplification during readout, potentially leading to malfunctions.
  • FIG1 is a schematic diagram of a 3D stacked memory array provided by a technical solution.
  • the memory may include a multi-layer memory cell array (memory cell arrays L1, L2, and L3 shown in FIG1 ), wherein the memory cell array includes a plurality of memory cells, each of which may be a 2T0C memory cell.
  • the memory cell may include a read transistor and a write transistor, wherein the gate electrode of the write transistor is connected to a write word line WWL, the first electrode of the write transistor is connected to a write bit line WBL, the second electrode of the write transistor is connected to the first gate electrode of the read transistor, the second gate electrode of the read transistor is connected to a read word line RWL, the first electrode of the read transistor is connected to a read bit line RBL, and the second electrode of the read transistor is connected to a reference voltage terminal.
  • Each layer of the memory cell array may correspond to a common read bit line, and the read bit line RBL may be connected to the corresponding common read bit line via a switch transistor.
  • one of the multiple switch transistors connected to the common read bit line is turned on, thereby conducting between the corresponding read bit line RBL and the common read bit line, and the other switch transistors are turned off, thereby disconnecting the other read bit lines RBL from the common read bit line.
  • a signal of a memory cell is read, it is electrically connected to a read bit line RBL through the corresponding common read bit line, and the data stored in the memory cell is determined by the signal of the read bit line RBL.
  • the voltage of the read bit line RBL is the precharge voltage
  • the voltage of the read bit line RBL can be greater than the precharge voltage (when the voltage of the reference voltage terminal is greater than the precharge voltage)
  • the voltage of the read bit line RBL can be less than the precharge voltage (when the voltage of the reference voltage terminal is less than the precharge voltage).
  • the memory cell in memory cell array L2 stores data "0"
  • the memory cells in memory cell arrays L1 and L3 store data "1,”
  • the voltage at the reference voltage terminal connected to the second electrode of the read transistor is less than the precharge voltage Vpre of the read bit line RBL, then:
  • the read transistors When reading data, the data stored in the memory cells of memory cell arrays L1 and L3 is "1," the read transistors are turned on, and charge is shared between read bit line RBL1 and the reference voltage terminal.
  • the voltage of read bit line RBL1 drops from the precharge voltage Vpre, for example, by approximately 160 millivolts (mV).
  • the voltage of read bit line RBL3 drops from the precharge voltage Vpre, for example, by approximately 160 millivolts (mV).
  • the voltages of read bit lines RBL1 and RBL3 are lower than the reference voltage of the sense amplifier.
  • the data stored in the memory cell of the memory cell array L2 is "0", and the read transistor is turned off.
  • the voltage of the read bit line RBL2 is maintained at the precharge voltage Vpre, which is greater than the reference voltage of the sense amplifier, so that "0” and "1” can be correctly distinguished; however, when there is a strong coupling capacitance (i.e., the capacitance C BL_BL shown in FIG1 ) between RBL1 and RBL2, and RBL3 and RBL2, then the voltage of RBL2 will follow the voltage of RBL1 and RBL3. The voltage of RBL3 and, therefore, the voltage of RBL2 drops, making data “0” indistinguishable from data “1”.
  • a switch sub-circuit connected to the common bit line is added.
  • the switch sub-circuit is turned on so that the common bit line is connected to a preset reference voltage terminal through the switch sub-circuit, thereby preventing the common bit line from floating.
  • the influence of the preset reference voltage terminal connected to the switch sub-circuit on the voltage of the common bit line is smaller than the influence of the read transistor on the voltage of the common bit line, thereby allowing the data of the storage unit to be correctly read.
  • An embodiment of the present disclosure provides a memory, which may include:
  • At least one memory array and at least one sense amplifier connected to the memory array the memory cell array including a plurality of memory cells and a plurality of bit lines; the memory cell including a read transistor, the read transistor including a first electrode and a second electrode, the first electrode being connected to the bit line, and the second electrode being connected to a first reference voltage terminal; the sense amplifier being connected to a second reference voltage terminal, the sense amplifier using a second reference voltage at the second reference voltage terminal as a reference voltage, i.e., a reference voltage for comparison with a signal detected from the memory cell;
  • the common bit line corresponds to the memory cell array one-to-one, the common bit line is connected to multiple bit lines in the corresponding memory cell array, each common bit line corresponds to one sense amplifier, each common bit line is connected to a switch sub-circuit, and the switch sub-circuit is also connected to a third reference voltage terminal, wherein,
  • the switch subcircuit is configured to: connect the third reference voltage terminal and the common bit line in a signal sensing phase; and disconnect the third reference voltage terminal and the common bit line in a signal amplification phase;
  • the third reference voltage, the second reference voltage, and the first reference voltage of the third reference voltage terminal satisfy the following conditions: in a signal sensing phase, when the data stored in the memory cells are different, the voltage output by the common bit line has a different magnitude relationship with the second reference voltage;
  • the first reference voltage is the voltage applied to the read word line during the signal sensing phase, or is the voltage at the first reference voltage terminal.
  • the solution provided in this embodiment by setting a switch sub-circuit connected to the common bit line, connects the switch sub-circuit during the signal sensing stage, avoids the common bit line from floating, eliminates the influence of coupling between the common bit lines on the voltage of the common bit line, and by setting the relationship between the third reference voltage, the second reference voltage, and the first reference voltage, different voltages can be output on the common bit line when the data stored in the storage unit is different, thereby realizing correct reading of the data.
  • the memory array may include a layer of memory cell array, or may include multiple layers of the memory cell array stacked in a direction perpendicular to the substrate, and each layer of the memory cell array may correspond to one of the common bit lines.
  • the voltage of the third reference voltage terminal may be a fixed voltage; or the voltage of the third reference voltage terminal may be a variable voltage.
  • the voltage of the common bit line after the switch sub-circuit is turned on can be changed by adjusting the voltage of the third reference voltage terminal.
  • the third reference voltage, the second reference voltage, and the first reference voltage at the third reference voltage terminal satisfy the following relationship: the third reference voltage ⁇ the second reference voltage ⁇ the first reference voltage, and the third reference voltage and the first reference voltage satisfy the following relationship: when the switch sub-circuit and the read transistor are both turned on, the voltage of the common bit line is greater than the second reference voltage.
  • the third reference voltage and the first reference voltage are appropriately configured such that, when the switch sub-circuit and the read transistor are both turned on, the charging effect of the first reference voltage terminal on the common bit line is greater than the discharging effect of the third reference voltage terminal on the common bit line, thereby bringing the voltage of the common bit line closer to the first reference voltage.
  • the third reference voltage and the first reference voltage satisfy the following conditions: when the switch sub-circuit and the read transistor are both turned on, the voltage of the common bit line is less than the second reference voltage. That is, the third reference voltage and the first reference voltage are appropriately configured so that when the switch sub-circuit and the read transistor are both turned on, the discharge effect of the first reference voltage terminal on the common bit line is greater than that of the third reference voltage terminal. The charging effect of the voltage terminal on the common bit line is considered, so that the voltage of the common bit line is closer to the first reference voltage.
  • the memory cell further includes a write transistor, and the write bit line and the read bit line of the memory cell can be connected together.
  • the read transistor and the write transistor of the same memory cell share a bit line, that is, the bit line connects the read transistor and the write transistor, and the bit line connected to the common bit line is the bit line shared by the read transistor and the write transistor.
  • the write bit line and read bit line connected to the memory cell can be independently set, that is, the read transistor is connected to the read bit line, the write transistor is connected to the write bit line, and the bit line connected to the common bit line is the read bit line.
  • the memory may include multiple memory arrays, wherein in two adjacent memory arrays, each two common bit lines belonging to the adjacent memory arrays are connected to the same sense amplifier, wherein one common bit line is connected between one end of the sense amplifier and the first switch sub-circuit, and another common bit line is connected between the other end of the sense amplifier and the second switch sub-circuit.
  • the multiple sense amplifiers may be arranged between two adjacent memory arrays along the extension direction of the common bit lines.
  • the storage unit may be a 2T0C storage unit, but is not limited thereto, and may be a 3T0C storage unit, etc.
  • the storage unit may be a storage structure in which the read bit line may float during the signal sensing phase when the switch sub-circuit is not set.
  • the following describes the independent configuration of the read bit line and the write bit line, and the connection of the read bit line and the write bit line.
  • FIG2A is a schematic diagram of a memory circuit provided by some embodiments.
  • a memory device comprising at least one memory array, the memory array comprising a plurality of memory cell arrays (m memory cell arrays are shown in FIG2A ) stacked vertically on a substrate (i.e., stacked in a direction perpendicular to substrate 1).
  • Each layer of the memory cell array comprises multiple rows and columns of memory cells 11 and multiple read bit lines RBL. Each column or every two columns of memory cells 11 is connected to a read bit line RBL.
  • Each layer of the memory cell array corresponds to a common read bit line CRBL (e.g., m common read bit lines CRBL1 to CRBLm corresponding to the m memory cell arrays, respectively, as shown in FIG2A ).
  • the common read bit line CRBL may be parallel to substrate 1.
  • the memory cell 11 may include a read transistor T1 and a write transistor T2.
  • the read transistor T1 may include a first gate electrode, a second gate electrode, a first electrode, and a second electrode.
  • the first gate electrode of the read transistor T1 is connected to a read word line RWL, and the second gate electrode is connected to the first electrode of the write transistor T2.
  • the first electrode of the read transistor T1 is connected to a read bit line RBL, and the read bit line RBL is connected to a common read bit line CRBL.
  • the read bit line RBL may be connected to the common read bit line CRBL via a switching transistor, and the conduction and disconnection between the read bit line RBL and the common read bit line CRBL are controlled by the switching transistor (the switching transistor is omitted in FIG. 2A ).
  • the second electrode of the read transistor T1 is connected to a first reference voltage terminal Vref1 (the voltage value of the first reference voltage terminal Vref1 is also represented by Vref1).
  • the second electrode of the write transistor T2 is connected to the write bit line WBL, and the gate electrode of the write transistor T2 is connected to the write word line WWL.
  • the memory cell 11 also includes a storage node SN, and the storage node SN includes the second gate electrode of the read transistor T1.
  • the memory may further include: multiple sense amplifiers SA and multiple switch sub-circuits 12.
  • the sense amplifier SA can determine whether the data stored in the memory cell 11 is a logical value of "1" or "0" by sensing signal changes on the common read bit line CRBL.
  • Each common read bit line CRBL is connected to the first terminal of a switch sub-circuit 12, and the second terminal of the switch sub-circuit 12 is connected to the third reference voltage terminal Vref3.
  • the switch sub-circuit 12 can control the connection (electrical connection) and disconnection between the common read bit line CRBL and the third reference voltage terminal Vref3.
  • the sense amplifier SA may include two input ports: a first input terminal S1 and a second input terminal S2.
  • One of the first input terminal S1 and the second input terminal S2 can serve as a signal detection terminal, and the other can serve as a signal reference terminal.
  • the second input terminal S2 can serve as a signal reference terminal and be connected to the second reference voltage terminal Vref2;
  • the first input terminal S1 serves as a signal detection terminal and is connected to the common read bit line RBL. It can detect signal changes on the common read bit line RBL and amplify and read the stored data of the memory cell connected to the first input terminal S1.
  • a first terminal of the switch sub-circuit 12 may also be connected to a first input terminal S1 of the sense amplifier SA.
  • the switch sub-circuit 12 may be a switch transistor, namely a third transistor T3.
  • the gate electrode of the third transistor T3 is connected to a control line CTRL, which is connected to a gate control terminal of a peripheral circuit via the control line CTRL.
  • a first electrode of the third transistor T3 is connected to the common read bit line CRBL and the first input terminal of the sense amplifier SA.
  • a second electrode of the third transistor T3 is connected to the third reference voltage terminal Vref3.
  • the switch sub-circuit 12 may be another circuit capable of implementing a switch function.
  • the voltages of the first reference voltage terminal Vref1, the second reference voltage terminal Vref2, and the third reference voltage terminal Vref3 may satisfy the following: Vref3>Vref2>Vref1.
  • the embodiments of the present disclosure are not limited thereto, and the voltages of the first reference voltage terminal Vref1, the second reference voltage terminal Vref2, and the third reference voltage terminal Vref3 may satisfy the following: Vref3 ⁇ Vref2 ⁇ Vref1.
  • Vref3>Vref2>Vref1 an example is provided for describing a memory cell in the first layer storing data "1" and a memory cell in the second layer storing data "0.”
  • the memory cell in the first layer stores data "1.”
  • read transistor T1 is turned on, and the first reference voltage terminal Vref1 discharges the first common read bit line CRBL1 (before the signal sensing phase, the voltage of CRBL1 is Vref2).
  • Switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 charges the first common read bit line CRBL1.
  • the effect of the first reference voltage terminal Vref1 discharging the first common read bit line CRBL1 can be greater than the effect of the third reference voltage terminal Vref3 charging the first common read bit line CRBL1, thereby causing the voltage of the first common read bit line CRBL1 to drop from Vref2 to less than Vref2.
  • the data stored in the storage cell of the second layer is "0".
  • the read transistor T1 is turned off, the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 charges the second common read bit line CRBL2, so that the voltage of the second common read bit line CRBL2 rises from Vref2 to greater than Vref2.
  • the voltage of the second common read bit line CRBL2 can still rise to greater than Vref2.
  • Vref3 When Vref3 ⁇ Vref2 ⁇ Vref1, description will be made by taking a memory cell 11 in the first layer storing data "1" and a memory cell 11 in the second layer storing data "0" as an example.
  • the data stored in the storage cell 11 of the first layer is "1".
  • the read transistor T1 In the signal sensing stage, the read transistor T1 is turned on, the first reference voltage terminal Vref1 charges the first common read bit line CRBL1 (before the signal sensing stage, the CRBL1 voltage is Vref2), the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 discharges the first common read bit line CRBL1.
  • the effect of the first reference voltage terminal Vref1 charging the first common read bit line CRBL1 can exceed the effect of the third reference voltage terminal Vref3 discharging the first common read bit line CRBL1, thereby causing the voltage of the first common read bit line CRBL1 to rise from Vref2 to greater than Vref2.
  • the data stored in the memory cell 11 of the second layer is "0".
  • the read transistor T1 is turned off, the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 discharges the second common read bit line CRBL2, so that the voltage of the second common read bit line CRBL2 drops from Vref2 to less than Vref2.
  • the voltage of the second common read bit line CRBL2 can still drop to less than Vref2.
  • the equivalent resistance of the read transistor T1 when it is turned on may be smaller than the equivalent resistance of the switch sub-circuit 12 when it is turned on.
  • the voltage of the common read bit line CRBL is closer to the voltage of the first reference voltage terminal Vref1.
  • Vref3>Vref2>Vref1 the common read bit line CRBL is closer to the voltage of the first reference voltage terminal Vref1.
  • the voltage of the common read bit line CRBL may drop to be lower than Vref2 ; when Vref3 ⁇ Vref2 ⁇ Vref1 , the voltage of the common read bit line CRBL may rise to be higher than Vref2 .
  • the switch sub-circuit 12 may include a third transistor T3.
  • a gate electrode of the third transistor T3 is connected to a gate control terminal of a peripheral circuit via a control line CTRL.
  • a first electrode of the third transistor T3 is connected to the common read bit line CRBL and the first input terminal S1 of the sense amplifier.
  • a second electrode of the third transistor T3 is connected to the third reference voltage terminal Vref3.
  • the third transistor T3 may be an N-type transistor, but the present disclosure is not limited thereto.
  • the third transistor T3 may be a P-type transistor.
  • the on-resistance of the third transistor T3 can be changed by changing the voltage of the control line CTRL.
  • changing the third reference voltage Vref3 can also change the voltage of the common read bit line CRBL. Therefore, the voltage of the common read bit line CRBL can be changed by changing at least one of the voltages of CTRL and the third reference voltage Vref3.
  • the multiple switch sub-circuits 12 connected to multiple common read bit lines CRBL of the same memory array are connected to the same control line CTRL, and the control line CTRL is configured to simultaneously turn on or off the multiple switch sub-circuits 12 connected to the control line CTRL.
  • the memory cell 11 shown in FIG2A is merely an example, and the present disclosure is not limited thereto.
  • the memory cell 11 may include a read transistor T1 and a write transistor T2.
  • the read transistor T1 has a first electrode connected to a read bit line RBL, a second electrode connected to a first reference voltage terminal Vref1, a first gate electrode connected to a read word line RWL, and a second gate electrode connected to a first electrode of a write transistor T2.
  • the write transistor T2 has a second electrode connected to a write bit line WBL, a first gate electrode connected to a first write word line WWL1, and a second gate electrode connected to a second write word line WWL2.
  • the memory cell 11 also includes a storage node SN, which includes the second gate electrode of the read transistor T1.
  • the operating state of the read transistor T1 in the memory cell 11 is similar to that of the read transistor T1 in the memory cell 11 in FIG2A and will not be further described.
  • the memory cell 11 may include a read transistor T1 and a write transistor T2.
  • the read transistor T1 has a first electrode connected to a read bit line RBL, a second electrode connected to a read word line RWL, and a gate electrode connected to a first electrode of the write transistor T2.
  • the write transistor T2 has a second electrode connected to a write bit line WBL, and a gate electrode connected to a write word line WWL.
  • the memory cell 11 also includes a storage node SN, which includes the gate electrode of the read transistor T1.
  • the read word line RWL is loaded with the first reference voltage Vref1 , and the first reference voltage Vref1 , the third reference voltage Vref3 , and the second reference voltage Vref2 satisfy: Vref3>Vref2>Vref1 ; or, Vref3 ⁇ Vref2 ⁇ Vref1 .
  • a memory cell 11 storing data "1" in the first layer and a memory cell 11 storing data "0" in the second layer are used as examples for explanation.
  • the data stored in the memory cell 11 in the first layer is "1".
  • the read transistor T1 is turned on, the read word line RWL (the voltage loaded at this time is Vref1) discharges the first common read bit line CRBL1 (before the signal sensing phase, the voltage of CRBL1 is Vref2), the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 charges the first common read bit line CRBL1, through at least one of the following: the on-resistance of the switch sub-circuit 12 and the on-resistance of the read transistor T1 (the on-resistance is the same as the on-resistance of the third transistor T3 or the read transistor T1) is connected.
  • the on-resistance can be changed by changing the size of the transistor and the voltage loaded on the gate electrode of the third transistor T3 or the read transistor T1), and the size relationship between Vref3 and Vref1 can be set so that the effect of the read word line RWL discharging the first common read bit line CRBL1 exceeds the effect of the third reference voltage terminal Vref3 charging the first common read bit line CRBL1, thereby causing the voltage of the first common read bit line CRBL1 to drop from Vref2 to less than Vref2.
  • the data stored in the memory cell 11 of the second layer is "0".
  • the read transistor T1 is turned off.
  • the third reference voltage terminal Vref3 charges the second common read bit line CRBL2, causing the voltage of the second common read bit line CRBL2 to rise from Vref2 to a voltage greater than Vref2.
  • the voltage of the second common read bit line CRBL2 can still rise to a voltage greater than Vref2.
  • the memory cell 11 can output more than two states, that is, the read transistor T1 can have multiple states with different degrees of conduction. Accordingly, the common read bit line exhibits different voltages in different conduction states of the read transistor T1. By sensing the voltage of the common read bit line CRBL, different logical data can be read.
  • the voltage value of the third reference voltage terminal Vref3 can be changed according to the different conduction states of the read transistor. Therefore, the third reference voltage terminal Vref3 and the first reference voltage terminal Vvef1 can charge or discharge the common read bit line CRBL in different conduction states of the read transistor T1.
  • the read transistor T1 may include four states: disconnected, a first conductive state, a second conductive state, and a third conductive state (the degree of conduction of the subsequent three conductive states increases in sequence), corresponding to four different logical data.
  • the third reference voltage terminal Vref3 (using Vref3>Vref2>Vref1 as an example) charges the common read bit line CRBL, causing the voltage of the common read bit line CRBL to rise from Vref2 to a voltage greater than Vref2.
  • the third reference voltage terminal Vref3 charges the common read bit line CRBL, and the first reference voltage terminal Vref1 discharges the common read bit line CRBL, causing the voltage of the common read bit line CRBL to drop from Vref2 to a voltage V1 less than Vref2.
  • the third reference voltage terminal Vref3 charges the common read bit line CRBL, and the first reference voltage terminal Vref1 discharges the common read bit line CRBL, causing the voltage of the common read bit line CRBL to drop from Vref2 to a voltage V1 less than Vref2.
  • the third reference voltage terminal Vref3 charges the common read bit line CRBL, and the first reference voltage terminal Vref1 discharges the common read bit line CRBL, causing the voltage of the common read bit line CRBL to drop from Vref2 to a voltage V3 less than Vref2.
  • the voltage value of the third reference voltage terminal Vref3 can be adjusted in different conduction states of the read transistor so that V3 ⁇ V2 ⁇ V1, thereby causing the common read bit line CRBL to present different voltages in different conduction states, thereby correctly reading the data stored in the memory cell.
  • the above four states are only examples, and the memory cell 11 can be other multi-bit memory cells.
  • FIG3A is a schematic diagram of a memory circuit provided in some other embodiments.
  • the memory provided in this embodiment may include: multiple memory arrays 1, with two adjacent memory arrays 1 shown in FIG3A .
  • the memory arrays 1 include multiple layers of memory cell arrays 10 stacked vertically on a substrate.
  • Each layer of the memory cell array 10 includes multiple rows and columns of memory cells 11 and multiple bit lines (not shown in FIG3A ), with each column or every two columns of memory cells 11 connected to a bit line.
  • Each layer of the memory cell array 10 corresponds to a common bit line CBL (such as CBL1 to CBLk and CBLk to CBLn shown in FIG3A ).
  • the memory may also include: multiple sense amplifiers SA and multiple switching sub-circuits 12.
  • the two input terminals of the sense amplifier SA are respectively connected to the common bit lines of adjacent memory arrays 1. If the common bit lines of two adjacent memory arrays share SA, the two input terminals of SA are respectively connected to the common bit lines of the two memory arrays.
  • the other common bit line serves as the signal reference terminal.
  • the second input terminal S2 can serve as a signal reference terminal
  • the first input terminal S1 is connected to the common bit line CBL and serves as a signal detection terminal. Signal changes of the common bit line CBL can be detected through the first input terminal S1 to amplify and read the storage data of the memory cell 11 connected to the first input terminal S1.
  • the first input terminal S1 can be used as a signal reference terminal
  • the second input terminal S2 can be used as a signal detection terminal to detect signal changes of the common bit line CBL, thereby reading the storage data of the memory cell 11 connected to the second input terminal S2.
  • Each common bit line CBL is connected to the first end of a switch sub-circuit 12, and the second end of the switch sub-circuit 12 is connected to the third reference voltage terminal Vref3.
  • the switch sub-circuit 12 can control the connection (electrical connection) and disconnection between the common bit line CBL and the third reference voltage terminal Vref3.
  • the first end of the switch sub-circuit 12 can also be connected to the input terminal of the sense amplifier SA connected to the common bit line CBL. For example, for the memory array 1 on the left, the first end of the switch sub-circuit 12 is connected to the first input terminal S1 of the sense amplifier SA, and for the memory array 1 on the right, the first end of the switch sub-circuit 12 is connected to the second input terminal S2 of the sense amplifier SA.
  • the memory cell 11 may include a read transistor T1 and a write transistor T2.
  • the first gate electrode of the read transistor T1 is connected to a read word line RWL, and the second gate electrode is connected to the first electrode of the write transistor T2.
  • the first electrode of the read transistor T1 is connected to a bit line BL, which is connected to a common bit line CBL.
  • the bit line BL may be connected to the common bit line CBL via a switching transistor, and the switching transistor controls the conduction and disconnection between the bit line BL and the common bit line CBL (the switching transistor is omitted in FIG3A ).
  • the second electrode of the read transistor T1 is connected to a first reference voltage terminal Vref1
  • the second electrode of the write transistor T2 is connected to the bit line BL
  • the gate electrode of the write transistor T2 is connected to the write word line WWL. That is, in this embodiment, the read bit line and the write bit line are connected to form a single bit line.
  • the memory cell 11 also includes a storage node SN, which includes the second gate electrode of the read transistor T1.
  • the memory cell 11 may include a read transistor T1 and a write transistor T2.
  • the first gate electrode of the read transistor T1 is connected to a read word line RWL, and the second gate electrode is connected to the first electrode of the write transistor T2.
  • the first electrode of the read transistor T1 is connected to a bit line BL, which is connected to a common bit line CBL.
  • the bit line BL may be connected to the common bit line CBL via a switching transistor, and the switching transistor controls the conduction and disconnection between the bit line BL and the common bit line CBL (the switching transistor is omitted in FIG3A ).
  • the second electrode of the read transistor T1 is connected to a first reference voltage terminal Vref1, and the second electrode of the write transistor T2 is connected to the bit line BL.
  • the first gate electrode of the write transistor T2 is connected to a first write word line WWL1, and the second gate electrode is connected to a second write word line WWL2.
  • the memory cell 11 also includes a storage node SN, which includes the second gate electrode of the read transistor T1.
  • the memory may include a first memory array and a second memory array.
  • the multiple switch sub-circuits 12 respectively connected to the multiple common bit lines of the first memory array may be connected to the same control line, for example, the first control line CTRL1; the multiple switch sub-circuits 12 respectively connected to the multiple common bit lines of the second memory array may be connected to the same control line, for example, the second control line CTRL2.
  • the switch sub-circuit 12 includes a third transistor T3
  • the gate electrodes of the multiple third transistors T3 respectively connected to the multiple common bit lines of the first memory array may be connected to the first control line CTRL1, and the gate electrodes of the multiple third transistors T3 respectively connected to the multiple common bit lines of the second memory array may be connected to the second control line CTRL2.
  • the sense amplifier SA may include a pre-charge sub-circuit 31 and a differential amplification sub-circuit 32 , wherein:
  • the pre-charging sub-circuit 31 is connected to the first input terminal S1, the second input terminal S2, the first control terminal EQ_ctrl, and the second reference voltage terminal Vref2, and is configured to, under the control of the first control terminal EQ_ctrl, load the voltage of the second reference voltage terminal Vref2 to the first input terminal S1 and the second input terminal S2;
  • the differential amplifier sub-circuit 32 is connected to the first input terminal S1, the second input terminal S2, the first enable terminal SAP_EN, the first voltage control terminal SAP, the second enable terminal SAN_EN, and the second voltage control terminal SAN, and is configured to amplify the differential input between the first input terminal S1 and the second input terminal S2 and output it through the first input terminal S1 and the second input terminal S2 under the control of the first enable terminal SAP_EN, the second enable terminal SAN_EN, the first voltage control terminal SAP, and the second voltage control terminal SAN.
  • the pre-charge sub-circuit 31 may include a fourth transistor T4 and a fifth transistor T5 , wherein:
  • the first electrode of the fourth transistor T4 is connected to the first input terminal S1, and the second electrode is connected to the The first electrode is connected to the second reference voltage terminal Vref2, the second electrode of the fifth transistor T5 is connected to the second input terminal S2, and the gate electrode of the fourth transistor T4 and the gate electrode of the fifth transistor T5 are connected to the first control terminal EQ_ctrl;
  • the differential amplifier sub-circuit 32 may include a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 , a ninth transistor T9 , a tenth transistor T10 , and an eleventh transistor T11 , wherein:
  • the gate electrode of the sixth transistor T6 and the gate electrode of the eighth transistor T8 are connected to the second input terminal S2, the first electrode of the sixth transistor T6 is connected to the first electrode of the tenth transistor T10, and the second electrode of the sixth transistor T6 is connected to the first input terminal S1;
  • the gate electrode of the seventh transistor T7 and the gate electrode of the ninth transistor T9 are connected to the first input terminal S1, the first electrode of the seventh transistor T7 is connected to the first electrode of the tenth transistor T10, and the second electrode of the seventh transistor T7 is connected to the second input terminal S2;
  • a first electrode of the eighth transistor T8 is connected to the first input terminal S1, and a second electrode of the eighth transistor T8 is connected to the first electrode of the eleventh transistor T11;
  • a first electrode of the ninth transistor T9 is connected to the second input terminal S2, and a second electrode of the ninth transistor T9 is connected to the first electrode of the eleventh transistor T11;
  • a second electrode of the tenth transistor T10 is connected to the first voltage control terminal SAP, and a gate electrode of the tenth transistor T10 is connected to the first enable terminal SAP_EN;
  • a second electrode of the eleventh transistor T11 is connected to the second voltage control terminal SAN, and a gate electrode of the eleventh transistor T11 is connected to the second enable terminal SAN_EN.
  • the sixth transistor T6 , the seventh transistor T7 , and the tenth transistor T10 may be P-type transistors
  • the fourth transistor T4 , the fifth transistor T5 , the eighth transistor T8 , the ninth transistor T9 , and the eleventh transistor T11 may be N-type transistors.
  • the first voltage control terminal SAP may be, for example, a high-level signal
  • the second voltage control terminal SAN may be, for example, a low-level signal
  • the sense amplifier circuit shown in FIG3D is only an example, and the embodiments of the present disclosure are not limited thereto. Any circuit that can implement sense amplification can be applied in the embodiments of the present application.
  • the memory cell 11 is shown in FIG3B
  • the sense amplifier is shown in FIG3D
  • the access process to a memory cell 11 may include a precharge phase t1, a signal sensing phase t2, a signal amplification phase t3, and a data write-back phase t4, where:
  • Precharge phase t1 The first control terminal EQ_ctrl is loaded with a conduction signal, the fourth transistor T4 and the fifth transistor T5 are turned on, and the voltage of the second reference voltage terminal Vref2 is loaded to the first input terminal S1 and the second input terminal S2.
  • the voltage of the first input terminal S1 is loaded to the common bit line CBL, that is, the voltage of the common bit line CBL is Vref2;
  • the first control line CTRL1 is loaded with a shutdown signal, so that the third transistor T3 is turned off;
  • the read word line RWL and the write word line WWL are loaded with a shutdown signal, and the read transistor T1 and the write transistor T2 are turned off;
  • Signal sensing phase t2 The first control terminal EQ_ctrl is loaded with a shutdown signal, turning off the fourth transistor T4 and the fifth transistor T5; the first control line CTRL1 is loaded with a conduction signal, turning on the third transistor T3; the read word line RWL is loaded with a conduction signal.
  • the read transistor T1 When the data stored in the memory cell is "0", the read transistor T1 is turned off, and the third reference voltage terminal Vref3 discharges the common bit line CBL (for example, the voltage discharged to the common bit line CBL is Vref3), making the voltage of the common bit line CBL less than Vref2.
  • the read transistor T1 When the data stored in the memory cell is "1", the read transistor T1 is turned on, the first reference voltage terminal Vref1 charges the common bit line CBL, and the third reference voltage terminal Vref3 charges the common bit line CBL.
  • the common bit line CBL is discharged, and the charging effect of the first reference voltage terminal Vref1 on the common bit line CBL is greater than the discharging effect of the third reference voltage terminal Vref3 on the common bit line CBL, thereby boosting the voltage of the common bit line CBL to a voltage greater than Vref2.
  • Signal amplification stage t3 the first control line CTRL1 is loaded with a shutdown signal, so that the third transistor T3 is turned off; the read word line RWL is loaded with a shutdown signal, so that the read transistor T1 is turned off; the first enable terminal SAP_EN and the second enable terminal SAN_EN are loaded with an enable signal (in the remaining stages, the first enable terminal SAP_EN and the second enable terminal SAN_EN can be loaded with a non-enable signal), so that the tenth transistor T10 is turned on and the eleventh transistor T11 is turned on, so that the differential sub-circuit 32 can amplify the signal.
  • the first input terminal S1 and the second input terminal S2 output corresponding voltages.
  • the data stored in the storage cell is "1"
  • the voltage of the first input terminal S1 is pulled up to the voltage corresponding to the data "1”
  • the common bit line CBL is the voltage corresponding to the data "1”
  • the second input terminal S2 is pulled down to the voltage corresponding to the data "0”.
  • the data "1” can be read by reading the level of the first input terminal S1. If the data stored in the memory cell 11 is “0”, the voltage of the first input terminal S1 is pulled down to the voltage corresponding to the data "0”, the common bit line CBL is the voltage corresponding to the data "0”, and the second input terminal S2 is pulled up to the voltage corresponding to the data "1".
  • the data "0” can be read by reading the level of the first input terminal S1.
  • Data write-back phase t4 The read word line RWL is loaded with a shutdown signal, turning off the read transistor T1.
  • the first control line CTRL1 is loaded with a shutdown signal, keeping the third transistor T3 off.
  • the write word line WWL is loaded with a conduction signal, turning on the write transistor T2.
  • the common bit line CBL and the storage node SN share charge, writing the voltage corresponding to the data "1" or "0" to the storage node SN.
  • the precharge phase then re-enters, waiting for the read and write operations to be performed.
  • the above-mentioned on- and off-signals depend on the transistor type.
  • the on-signal is a high-level signal
  • the off-signal is a low-level signal
  • the on-signal is a low-level signal
  • the off-signal is a high-level signal.
  • the enable and disable signals depend on the transistor type. The enable signal turns the transistor on, and the disable signal turns it off.
  • the present disclosure provides an access control method for the above-mentioned memory, which may include:
  • a switch subcircuit connected to a common bit line of the memory cell to be accessed to be turned on, so as to connect the third reference voltage terminal and the common bit line;
  • the switch sub-circuit connected to the common bit line of the memory cell to be accessed is controlled to be closed, so that the common bit line is disconnected from the third reference voltage terminal.
  • the solution provided in this embodiment prevents the common bit line from floating by connecting the third reference voltage terminal and the common bit line during the signal sensing phase, eliminates the influence of common bit line coupling on data reading, and realizes correct data reading.
  • the method may further include: during the data write-back phase, turning off the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal.
  • the method may further include: in a pre-charging stage before the signal sensing stage, closing the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal, and loading the second reference voltage to the common bit line.
  • the present disclosure also provides an electronic device comprising the memory device described in any of the preceding embodiments.
  • the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
  • the storage device may include, but is not limited to, computer memory.
  • the electronic device may further include a control circuit configured to control access to the memory according to any of the access control methods described above.
  • the control circuit may include circuits and control lines capable of generating control signals to control the switch subcircuit, thereby implementing access control to the memory.
  • the control circuit together with the SA and the like, implements access to the memory.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

存储器及其访问方法、电子设备，存储器包括：至少一个存储阵列和与存储阵列连接的多个感测放大器，存储阵列包括至少一个存储单元阵列，存储单元阵列包括多个存储单元和多条位线；存储单元的读晶体管分别连接位线和第一参考电压端或者读字线；位线连接一条公共位线，公共位线连接开关子电路(12)，开关子电路(12)被配置为：在信号感应阶段，连通第三参考电压端和公共位线；在信号放大阶段，断开第三参考电压端和公共位线，且根据存储单元存储的数据不同，在信号感测阶段在公共位线输出不同的电压。

Description

一种存储器及其访问控制方法、电子设备
本申请要求于2024年3月6日提交的、申请号为202410255545.0、发明名称为“一种存储器及其访问控制方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体技术领域的器件设计，尤指一种存储器及其访问控制方法、电子设备。
背景技术
随着集成电路技术的发展，器件的关键尺寸日益缩小，单个芯片所包含的器件种类及数量随之增加，使得工艺生产中的任何微小差异都可能对器件性能造成影响。为了尽可能降低产品的成本，人们希望在有限的衬底上做出尽可能多的器件单元。自从摩尔定律问世以来，业界提出了各种半导体结构设计和工艺优化，以满足人们对当前产品的需求。比如，对存储单元进行3D堆叠，但3D堆叠的器件的存储单元之间存在耦合，对数据读出可能产生影响。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供了一种存储器，包括：
至少一个存储阵列，所述存储阵列包括至少一个存储单元阵列和与所述存储单元阵列连接的感测放大器，所述存储单元阵列包括多个存储单元和多条位线；所述存储单元包括读晶体管，所述读晶体管包括第一电极和第二电极，所述第一电极连接所述位线，所述第二电极连接第一参考电压端或者读字线；所述感测放大器连接第二参考电压端，以所述第二参考电压端的第二参考电压作为基准电压；
至少一条公共位线，所述公共位线与所述存储单元阵列一一对应，所述公共位线与对应的所述存储单元阵列中的多条位线连接，每条所述公共位线对应一个所述感测放大器，每条所述公共位线连接一个开关子电路，所述开关子电路还连接第三参考电压端，其中，
所述开关子电路被配置为：在信号感应阶段，连通所述第三参考电压端和所述公共位线；在信号放大阶段，断开所述第三参考电压端和所述公共位线；
且所述第三参考电压端的第三参考电压、所述第二参考电压、第一参考电压满足：在信号感应阶段，所述存储单元存储的数据不同时，所述公共位线输出不同的电压，且输出的电压与所述第二参考电压的大小关系不同；
所述第一参考电压为信号感应阶段所述读字线上加载的电压，或者为所述第一参考电压端的电压。
在一些实施例中，所述存储阵列包括沿垂直于衬底方向堆叠的多层所述存储单元阵列，每层所述存储单元阵列对应一条所述公共位线。
在一些实施例中，所述第三参考电压端的电压为固定电压；或者，所述第三参考电压端的电压为可变电压。
在一些实施例中，所述第三参考电压端的电压为固定电压，且所述第三参考电压<所述第二参考电压<第一参考电压，且所述第三参考电压、第一参考电压满足：所述开关子电路和所述读晶体管均导通时，所述公共位线的电压大于所述第二参考电压。
在一些实施例中，所述第三参考电压端的电压为固定电压，所述第三参考电压>所述第二参考电压>所述第一参考电压，且所述第三参考电压、第一参考电压满足：所述开关子电路和所述读晶体管均导通时，所述公共位线的电压小于所述第二参考电压。
在一些实施例中，所述开关子电路包括一个开关晶体管，所述开关晶体管的栅电极连接控制线，所述开关晶体管的第一电极连接所述公共位线和所述感测放大器的一个输入端，所述开关晶体管的第二电极连接所述第三参考电压端。
在一些实施例中，同一存储阵列的多条公共位线连接的多个所述开关子电路的栅控制端连接同一条控制线，所述控制线被配置为：同时开启或关断多个所述开关子电路。
在一些实施例中，所述存储单元还包括写晶体管，所述位线为所述读晶体管和所述写晶体管共用的位线。
在一些实施例中，所述存储单元还包括写晶体管，所述位线为仅与所述读晶体管连接的读位线。
在一些实施例中，所述存储器包括多个存储阵列，多个所述感测放大器设置于沿所述公共位线的延伸方向相邻的两个存储阵列中间，且每两条分别属于相邻存储阵列的公共位线连接到同一个所述感测放大器，其中一条公共位线连接所述感测放大器的一端和第一开关子电路，另一条公共位线连接所述感测放大器的另一端和第二开关子电路。
本公开实施例提供一种存储器的访问控制方法，包括：
在信号感应阶段，控制与待访问的存储单元的公共位线连接的开关子电路开启，连通所述第三参考电压端和所述公共位线；
在信号放大阶段，控制与所述待访问的存储单元的公共位线连接的所述开关子电路关闭，使得所述公共位线与所述第三参考电压端断开。
在一些实施例中，所述方法还包括：在数据回写阶段，关闭与待访问的所述存储单元的公共位线连接的所述开关子电路，使得所述公共位线与所述第三参考电压端断开。
在一些实施例中，所述方法还包括：在所述信号感应阶段之前的预充电阶段，关闭与待访问的所述存储单元的公共位线连接的所述开关子电路，使得所述公共位线与所述第三参考电压端断开，将所述第二参考电压加载到所述公共位线。
本公开实施例提供一种电子设备，包括上述任一实施例所述的存储器。
在一些实施例中，所述电子设备还包括控制电路，所述控制电路配置为按照上述存储器的访问控制方法对所述存储器进行访问控制。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施 例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为一技术方案提供的存储阵列示意图；
图2A为本申请实施例提供的存储器示意图；
图2B为一示例性实施例提供的存储单元等效电路示意图；
图2C为一示例性实施例提供的存储单元等效电路示意图；
图3A为另一些实施例提供的存储器示意图；
图3B为一示例性实施例提供的存储单元等效电路示意图；
图3C为一示例性实施例提供的存储单元等效电路示意图；
图3D为一示例性实施例提供的感测放大器等效电路示意图。
详述
下文中将结合附图对本公开实施例进行详细说明。在不冲突的情况下，本公开实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。
本公开的实施方式并不一定限定附图所示尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是物理连接或信号连接，可以是接触连接或一体地连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。栅电极可以是单栅或者双栅，晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，可以是第一电极为漏电极、第二电极为源电极，或者可以是第一电极为源电极、第二电极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具 有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指大约垂直，比如，两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
存储器可以包括一个存储阵列中的多个存储单元。多个存储单元中相邻的位线之间可能存在耦合电容，尤其是3D堆叠的存储单元应用场景中。在这种情况下，位线之间的强电容耦合会影响信号读出阶段的信号感测和信号放大过程，并可能导致误操作。
图1为一技术方案提供的3D堆叠的存储阵列示意图。如图1所示，存储器可以包括多层存储单元阵列(图1中示出的存储单元阵列L1、L2和L3)，所述存储单元阵列包括多个存储单元，所述存储单元可以是2T0C存储单元，所述存储单元可以包括读晶体管和写晶体管，写晶体管的栅电极连接写字线WWL，写晶体管的第一电极连接写位线WBL，写晶体管的第二电极连接读晶体管的第一栅电极，读晶体管的第二栅电极连接读字线RWL，读晶体管的第一电极连接读位线RBL，读晶体管的第二电极连接一参考电压端。每层存储单元阵列可以对应一条公共读位线，所述读位线RBL可以通过开关晶体管连接到对应的公共读位线。在一条公共读位线被选中时，与公共读位线连接的多个开关晶体管中，其中一个所述开关晶体管开启，则对应的读位线RBL和公共读位线之间导通，其他开关晶体管关闭，使得其他读位线RBL与所述公共读位线之间断开。每次读取一个存储单元的信号时，通过对应的公共读位线电连接到一条读位线RBL，通过读位线RBL的信号确定存储单元存储的数据，比如，进行数据读取时，存储单元存储的数据为“0”时，读位线RBL的电压为预充电的电压；存储单元存储的数据为“1”时，根据读晶体管的另一电极(不与读位线RBL连接的电极，本实施例中，为读晶体管的第二电极)连接的参考电压端与读位线RBL预充电的电压之间的关系不同，通过电荷共享，读位线RBL的电压可以是大于预充电的电压(当参考电压端的电压大于预充电的电压时)，或者，读位线RBL的电压小于预充电的电压(当参考电压端的电压小于预充电的电压时)，即，存储单元存储的数据为逻辑数值“0”或“1”时，读位线RBL的电压不同，从而可以区分“0”和“1”。但是，存储单元存储的数据为“0”时，进行数据读取时，读晶体管关断，读位线RBL浮空，此时，如果读位线RBL与其他读位线RBL之间的耦合较大，读位线RBL的电压可能可变，导致数据读取错误。以图1中三个存储单元为例，存储单元阵列L2的存储单元存储的数据为“0”，存储单元阵列L1和存储单元阵列L3的存储单元存储的数据为“1”，且读晶体管的第二电极连接的参考电压端的电压小于读位线RBL预充电电压Vpre，则：
进行数据读取时，存储单元阵列L1和存储单元阵列L3的存储单元中存储的数据为“1”，读晶体管导通，读位线RBL1和参考电压端进行电荷共享，读位线RBL1的电压从预充电电压Vpre下降，比如，下降160毫伏(mV)左右。读位线RBL3类似，读位线RBL3的电压从预充电电压Vpre下降，比如，下降160毫伏(mV)左右。读位线RBL1和读位线RBL3的电压小于感测放大器的基准电压；
存储单元阵列L2的存储单元中存储的数据为“0”，读晶体管关断，正常情况下，读位线RBL2的电压保持在预充电电压Vpre，预充电电压Vpre大于感测放大器的基准电压，从而可以正确区分“0”和“1”；但是，当RBL1和RBL2，RBL3和RBL2之间存在较强的耦合电容(即图1中示出的电容CBL_BL)时，则，RBL2的电压会跟随RBL1和 RBL3电压，因此，RBL2的电压下降，从而使得数据“0”无法与数据“1”区分。
本公开实施例中，增加与公共位线连接的开关子电路，在信号感测阶段时，导通所述开关子电路，使得公共位线通过所述开关子电路连接到预设的参考电压端，避免公共位线浮空，且，所述开关子电路连接的预设的参考电压端对公共位线的电压的影响小于读晶体管对公共位线的电压的影响，从而使得存储单元的数据可以正确读出。
本公开实施例提供一种存储器，可以包括：
至少一个存储阵列和与所述存储阵列连接的至少一个感测放大器，所述存储单元阵列包括多个存储单元和多条位线；所述存储单元包括读晶体管，所述读晶体管包括第一电极和第二电极，所述第一电极连接所述位线，所述第二电极连接第一参考电压端；所述感测放大器连接第二参考电压端，所述感测放大器以所述第二参考电压端的第二参考电压作为基准电压，即，与从存储单元检测到的信号进行比较时的基准电压；
至少一条公共位线，所述公共位线与所述存储单元阵列一一对应，所述公共位线与对应的所述存储单元阵列中的多条位线连接，每条所述公共位线对应一个所述感测放大器，每条所述公共位线连接一个开关子电路，所述开关子电路还连接第三参考电压端，其中，
所述开关子电路被配置为：在信号感应阶段，连通所述第三参考电压端和所述公共位线；在信号放大阶段，断开所述第三参考电压端和所述公共位线；
所述第三参考电压端的第三参考电压、所述第二参考电压、第一参考电压满足：在信号感应阶段，所述存储单元的存储的数据不同时，所述公共位线输出的电压与所述第二参考电压的大小关系不同；
所述第一参考电压为信号感应阶段所述读字线加载的电压，或者为所述第一参考电压端的电压。
本实施例提供的方案，通过设置与公共位线连接的开关子电路，在信号感应阶段连通开关子电路，避免公共位线浮空，消除公共位线之间的耦合对公共位线的电压的影响，且通过设置第三参考电压、第二参考电压、第一参考电压之间的关系，可以在存储单元存储的数据不同时，在公共位线输出不同的电压，实现数据的正确读取。
在一些实施例中，所述存储阵列可以包括一层存储单元阵列，或者，可以包括沿垂直于衬底方向堆叠的多层所述存储单元阵列，每层所述存储单元阵列可以对应一条所述公共位线。
在一些实施例中，所述第三参考电压端的电压可以为固定电压；或者，所述第三参考电压端的电压可以为可变电压。可以通过调节第三参考电压端的电压来改变开关子电路导通后公共位线的电压。
在一些实施例中，所述第三参考电压端的第三参考电压、所述第二参考电压、第一参考电压满足：所述第三参考电压<所述第二参考电压<第一参考电压，且所述第三参考电压、第一参考电压满足：所述开关子电路和所述读晶体管均导通时，所述公共位线的电压大于所述第二参考电压。即，配置合适的第三参考电压，第一参考电压，使得在开关子电路和读晶体管均导通时，第一参考电压端对公共位线的充电效应大于第三参考电压端对公共位线的放电效应，从而公共位线的电压更接近第一参考电压。
在一些实施例中，所述第三参考电压>所述第二参考电压>所述第一参考电压，且所述第三参考电压、第一参考电压满足：所述开关子电路和所述读晶体管均导通时，所述公共位线的电压小于所述第二参考电压。即，配置合适的第三参考电压，第一参考电压，使得在开关子电路和读晶体管均导通时，第一参考电压端对公共位线的放电效应大于第三参 考电压端对公共位线的充电效应，从而公共位线的电压更接近第一参考电压。
在一些实施例中，所述存储单元还包括写晶体管，存储单元的写位线和读位线可以连接在一起，同一存储单元的读晶体管和写晶体管共用一条位线，即所述位线连接所述读晶体管和所述写晶体管，上述与公共位线连接的位线为所述读晶体管和写晶体管共用的位线。
在一些实施例中，所述存储单元连接的写位线和读位线可以独立设置，即，读晶体管连接读位线，写晶体管连接写位线，上述与公共位线连接的位线则为读位线。
在一些实施例中，所述存储器可以包括多个存储阵列，相邻两个存储阵列中，每两条分别属于相邻存储阵列的公共位线连接到同一个所述感测放大器，其中一条公共位线连接所述感测放大器的一端和第一开关子电路，另一条公共位线连接所述感测放大器的另一端和第二开关子电路。多个所述感测放大器可以设置于沿所述公共位线的延伸方向相邻的两个存储阵列中间。
在一些实施例中，所述存储单元可以为2T0C存储单元，但不限于此，可以为3T0C存储单元等，所述存储单元可以是在未设置开关子电路时，在信号感测阶段读位线可能浮空的存储结构。
下面以读位线和写位线独立设置，以及，读位线和写位线连接的示例分别进行说明。
图2A为一些实施例提供的存储器电路示意图。如图2A所示，本公开实施例提供一种存储器，所述存储器包括至少一个存储阵列，所述存储阵列包括在衬底上垂直堆叠(即沿垂直于衬底1方向堆叠)的多个存储单元阵列(图2A中示出了m个存储单元阵列)，每层存储单元阵列包括多行多列存储单元11和多条读位线RBL，每列或者每两列存储单元11连接到一条读位线RBL，每层存储单元阵列对应一条公共读位线CRBL(如图2A中示出的与m个存储单元阵列分别对应的m个公共读位线CRBL1至CRBLm)，公共读位线CRBL可以平行于衬底1。存储单元11可以包括读晶体管T1和写晶体管T2，读晶体管T1可以包括第一栅电极、第二栅电极、第一电极和第二电极，读晶体管T1的第一栅电极连接读字线RWL，第二栅电极连接写晶体管T2的第一电极，读晶体管T1的第一电极连接读位线RBL，读位线RBL连接公共读位线CRBL，读位线RBL可以通过开关晶体管连接到公共读位线CRBL，通过开关晶体管控制读位线RBL和公共读位线CRBL之间的导通和断开(图2A中省略了开关晶体管)，读晶体管T1的第二电极连接第一参考电压端Vref1(第一参考电压端Vref1的电压值也用Vref1表示)，写晶体管T2的第二电极连接写位线WBL，写晶体管T2的栅电极连接写字线WWL，存储单元11还包括存储节点SN，所述存储节点SN包含所述读晶体管T1的第二栅电极。
所述存储器还可以包括：多个感测放大器SA和多个开关子电路12。本实施例中，感测放大器SA可以通过感应公共读位线CRBL的信号变化来确定存储单元11存储的数据为逻辑数值“1”或“0”。每条公共读位线CRBL连接一个开关子电路12的第一端，开关子电路12的第二端连接第三参考电压端Vref3，可以通过开关子电路12控制公共读位线CRBL与第三参考电压端Vref3之间的连通(电连接)与断开。感测放大器SA可以包括两个输入端口：第一输入端S1和第二输入端S2。第一输入端S1第二输入端S2其中之一可以作为信号检测端，另一可以作为信号基准端。比如，对于图2A中的感测放大器SA，第二输入端S2可以作为信号基准端，连接到第二参考电压端Vref2；第一输入端S1作为信号检测端，与公共读位线RBL连接，可以检测公共供位线RBL的信号变化，实现对与第一输入端S1连接的存储单元的存储数据的放大和读取。开关子电路12的第一端还可以连接到感测放大器SA的第一输入端S1。
在一些实施例中，所述开关子电路12可以为一个开关晶体管，即第三晶体管T3，所 述第三晶体管T3的栅电极连接控制线CTRL，通过控制线CTRL连接至外围电路的栅控制端，所述第三晶体管T3的第一电极连接所述公共读位线CRBL和所述感测放大器SA的第一输入端，所述第三晶体管T3的第二电极连接所述第三参考电压端Vref3。但本公开实施例不限于此，所述开关子电路12可以是其他可以实现开关功能的电路。
在一些实施例中，第一参考电压端Vref1、第二参考电压端Vref2、第三参考电压端Vref3的电压可以满足：Vref3>Vref2>Vref1。但本公开实施例不限于此，第一参考电压端Vref1、第二参考电压端Vref2、第三参考电压端Vref3的电压可以满足：Vref3<Vref2<Vref1。
Vref3>Vref2>Vref1时，以第一层的一个存储的数据为“1”的存储单元和第二层的一个存储的数据为“0”的存储单元为例进行说明。第一层的该存储单元存储的数据为“1”，在信号感测阶段，读晶体管T1导通，第一参考电压端Vref1对第一公共读位线CRBL1进行放电(信号感测阶段之前，CRBL1电压为Vref2)，开关子电路12导通，第三参考电压端Vref3对第一公共读位线CRBL1进行充电，通过如下至少之一：对开关子电路12和读晶体管T1的导通电阻(即对第三晶体管T3和读晶体管T1)进行设置，对Vref3和Vref1的之间的大小进行设置，可以使得第一参考电压端Vref1对第一公共读位线CRBL1进行放电的效果超过第三参考电压端Vref3对第一公共读位线CRBL1进行充电的效果，从而使得第一公共读位线CRBL1的电压从Vref2下降至小于Vref2。
第二层的该存储单元存储的数据为“0”，在信号感测阶段，读晶体管T1关断，开关子电路12导通，第三参考电压端Vref3对第二公共读位线CRBL2进行充电，使得第二公共读位线CRBL2的电压从Vref2上升至大于Vref2。即使存在周边的公共读位线与第二公共读位线CRBL2进行耦合，由于第二公共读位线CRBL2处于非浮空状态，因此，第二公共读位线CRBL2的电压仍可上升至大于Vref2。可以看到，存储单元存储的数据不同，分别为“1”和“0”时，公共读位线CRBL的电压不同，从而可以正确的读出存储单元的数据。
Vref3<Vref2<Vref1时，以第一层的一个存储的数据为“1”的存储单元11和第二层的一个存储的数据为“0”的存储单元11为例进行说明。第一层的该存储单元11存储的数据为“1”，在信号感测阶段，读晶体管T1导通，第一参考电压端Vref1对第一公共读位线CRBL1进行充电(信号感测阶段之前，CRBL1电压为Vref2)，开关子电路12导通，第三参考电压端Vref3对第一公共读位线CRBL1进行放电，通过如下至少之一：对开关子电路12和读晶体管T1的导通电阻(即对第三晶体管T3和读晶体管T1)进行设置，对Vref3和Vref1的之间的大小进行设置，可以使得第一参考电压端Vref1对第一公共读位线CRBL1进行充电的效果超过第三参考电压端Vref3对第一公共读位线CRBL1进行放电的效果，从而使得第一公共读位线CRBL1的电压从Vref2上升至大于Vref2。
第二层的该存储单元11存储的数据为“0”，在信号感测阶段，读晶体管T1关断，开关子电路12导通，第三参考电压端Vref3对第二公共读位线CRBL2进行放电，使得第二公共读位线CRBL2的电压从Vref2下降至小于Vref2。即使存在周边的公共读位线与第二公共读位线CRBL2进行耦合，由于第二公共读位线CRBL2处于非浮空状态，因此，第二公共读位线CRBL2的电压仍可下降至小于Vref2。可以看到，存储单元11存储的数据不同，分别为“1”和“0”时，公共读位线CRBL的电压不同(其中之一大于Vref2，另一小于Vref2)，从而可以正确的读出存储单元11的数据。
在一些实施例中，所述读晶体管T1导通时的等效电阻可以小于所述开关子电路12导通时的等效电阻。本实施例中，在读晶体管T1和开关子电路12均导通时，公共读位线CRBL的电压更接近第一参考电压端Vref1的电压，在Vref3>Vref2>Vref1时，公共 读位线CRBL的电压可以下降至小于Vref2；在Vref3<Vref2<Vref1时，公共读位线CRBL的电压可以上升至大于Vref2。
在一些实施例中，如图2A所示，所述开关子电路12可以包括第三晶体管T3，所述第三晶体管T3的栅电极通过控制线CTRL连接到外围电路的栅控制端，第一电极连接所述公共读位线CRBL和所述感测放大器的第一输入端S1，第二电极连接所述第三参考电压端Vref3。所述第三晶体管T3可以是N型晶体管，但本公开实施例不限于此，第三晶体管T3可以是P型晶体管。
在一些实施例中，可以通过改变控制线CTRL的电压改变第三晶体管T3的导通电阻。另外，改变第三参考电压Vref3也可以改变公共读位线CRBL的电压，因此，可以通过改变CTRL的电压、第三参考电压Vref3至少之一来改变公共读位线CRBL的电压。
在一些实施例中，同一存储阵列的多条公共读位线CRBL连接的多个所述开关子电路12连接同一控制线CTRL，所述控制线CTRL被配置为：同时开启或关断连接到所述控制线CTRL的所述多个开关子电路12。
图2A中所示的存储单元11仅为示例，本公开实施例不限于此，在一些实施例中，如图2B所示，所述存储单元11可以包括读晶体管T1和写晶体管T2，所述读晶体管T1的第一电极连接读位线RBL，第二电极连接第一参考电压端Vref1，第一栅电极连接读字线RWL，第二栅电极连接写晶体管T2的第一电极；写晶体管T2的第二电极连接写位线WBL，第一栅电极连接第一写字线WWL1，第二栅电极连接第二写字线WWL2。所述存储单元11还包括存储节点SN，所述存储节点SN包含所述读晶体管T1的第二栅电极。该存储单元11的读晶体管T1的工作状态类似图2A中存储单元11的读晶体管T1的工作状态，不再赘述。
在一些实施例中，如图2C所示，所述存储单元11可以包括读晶体管T1和写晶体管T2，所述读晶体管T1的第一电极连接读位线RBL，第二电极连接读字线RWL，栅电极连接所述写晶体管T2的第一电极，写晶体管T2的第二电极连接写位线WBL，栅电极连接写字线WWL。所述存储单元11还包括存储节点SN，所述存储节点SN包含所述读晶体管T1的栅电极。
当存储单元11如图2C所示时，在信号感测阶段，读字线RWL加载第一参考电压Vref1，第一参考电压Vref1与第三参考电压Vref3、第二参考电压Vref2满足：Vref3>Vref2>Vref1；或者，Vref3<Vref2<Vref1。
当存储单元11如图2C所示，且Vref3>Vref2>Vref1时，以第一层的一个存储数据“1”的存储单元11和第二层的一个存储数据“0”的存储单元11为例进行说明。第一层的该存储单元11存储的数据为“1”，在信号感测阶段，读晶体管T1导通，读字线RWL(此时加载的电压为Vref1)对第一公共读位线CRBL1进行放电(信号感测阶段之前，CRBL1电压为Vref2)，开关子电路12导通，第三参考电压端Vref3对第一公共读位线CRBL1进行充电，通过如下至少之一：对开关子电路12的导通电阻和读晶体管T1的导通电阻(导通电阻与第三晶体管T3或者读晶体管T1的尺寸，以及，加载在栅电极的电压有关，可以通过改变晶体管的尺寸、改变加载在第三晶体管T3或者读晶体管T1的栅电极的电压至少之一来改变导通电阻)进行设置，对Vref3和Vref1的大小关系进行设置，可以使得读字线RWL对第一公共读位线CRBL1进行放电的效果超过第三参考电压端Vref3对第一公共读位线CRBL1进行充电的效果，从而使得第一公共读位线CRBL1的电压从Vref2下降至小于Vref2。
第二层的该存储单元11存储的数据为“0”，在信号感测阶段，读晶体管T1关断， 开关子电路12导通，第三参考电压端Vref3对第二公共读位线CRBL2进行充电，使得第二公共读位线CRBL2的电压从Vref2上升至大于Vref2。即使存在周边的公共读位线与第二公共读位线CRBL2进行耦合，由于第二公共读位线CRBL2处于非浮空状态，因此，第二公共读位线CRBL2的电压仍可上升至大于Vref2。可以看到，存储单元11存储的数据不同，分别为“1”和“0”时，公共读位线CRBL的电压不同，从而可以正确的读出存储单元11的数据。
上述方案可以应用在多比特的存储单元中。比如，存储单元11可以输出超过两种状态，即，读晶体管T1可以存在导通程度不同的多种状态，相应的，公共读位线在读晶体管T1的不同导通状态下，呈现不同的电压，通过感测公共读位线CRBL的电压，读出不同的逻辑数据。在一些实施例中，第三参考电压端Vref3的电压值可以根据读晶体管的不同导通状态改变，从而能在读晶体管T1的不同导通状态下，第三参考电压端Vref3和第一参考电压端Vvef1对公共读位线CRBL进行充电或放电，使得在不同的导通状态下公共读位线CRBL呈现不同的电压，实现存储单元存储的数据的正确读取。比如，读晶体管T1可以包括四种状态，断开，第一导通状态、第二导通状态、第三导通状态(后续三种导通状态的导通程度依次增大)，分别对应不同的四种逻辑数据，则读晶体管T1为断开状态下，第三参考电压端Vref3(以Vref3>Vref2>Vref1为例进行说明)对公共读位线CRBL进行充电，使得公共读位线CRBL的电压从Vref2上升至大于Vref2。读晶体管T1为第一导通状态下，第三参考电压端Vref3对公共读位线CRBL进行充电，第一参考电压端Vref1对公共读位线CRBL进行放电，使得公共读位线CRBL的电压从Vref2下降至小于Vref2的电压V1；读晶体管T1为第二导通状态下，第三参考电压端Vref3对公共读位线CRBL进行充电，第一参考电压端Vref1对公共读位线CRBL进行放电，使得公共读位线CRBL的电压从Vref2下降至小于Vref2的电压V2；读晶体管T1为第三导通状态下，第三参考电压端Vref3对公共读位线CRBL进行充电，第一参考电压端Vref1对公共读位线CRBL进行放电，使得公共读位线CRBL的电压从Vref2下降至小于Vref2的电压V3，可以调节读晶体管不同导通状态下，第三参考电压端Vref3的电压值，使得V3<V2<V1，从而使得在不同的导通状态下公共读位线CRBL呈现不同的电压，实现存储单元存储的数据的正确读取。上述四种状态仅为示例，存储单元11可以是其他多比特的存储单元。
图3A为另一些实施例提供的存储器电路示意图。如图3A所示，本实施例提供的存储器可以包括：多个存储阵列1，图3A中示出2个相邻的存储阵列1。存储阵列1包括在衬底上垂直堆叠的多层存储单元阵列10。每层存储单元阵列10包括多行多列存储单元11和多条位线(图3A中未示出)，每列或每两列存储单元11连接到一条位线。每层存储单元阵列10对应一条公共位线CBL(如图3A中示出的CBL1至CBLk，以及，CBLk至CBLn)。所述存储器还可以包括：多个感测放大器SA和多个开关子电路12。感测放大器SA的两个输入端分别连接相邻的存储阵列1的公共位线。若两个相邻的存储阵列的公共位线共用SA时，SA的两个输入端分别与两个存储阵列的公共位线连接。检测其中一条公共位线的信号变化时，另一条公共位线作为所述信号基准端。比如对于图3A中左侧的存储阵列1，第二输入端S2可以作为信号基准端，第一输入端S1与公共位线CBL连接，作为信号检测端，可以通过第一输入端S1检测公共位线CBL的信号变化，实现对与第一输入端S1连接的存储单元11的存储数据的放大和读取。
或者，对于图3A中右侧的存储阵列1，第一输入端S1可以作为信号基准端，第二输入端S2作为信号检测端检测公共位线CBL的信号变化，实现对与第二输入端S2连接的存储单元11的存储数据的读取。
每条公共位线CBL连接一个开关子电路12的第一端，开关子电路12的第二端连接第三参考电压端Vref3，可以通过开关子电路12控制公共位线CBL与第三参考电压端Vref3之间的连通(电连接)与断开。开关子电路12的第一端还可以连接到公共位线CBL所连接的感测放大器SA的输入端，比如，对左侧的存储阵列1，开关子电路12的第一端连接到感测放大器SA的第一输入端S1，对右侧的存储阵列1，开关子电路12的第一端连接到感测放大器SA的第二输入端S2。
如图3B所示，所述存储单元11可以包括读晶体管T1和写晶体管T2，读晶体管T1的第一栅电极连接读字线RWL，第二栅电极连接写晶体管T2的第一电极，读晶体管T1的第一电极连接位线BL，位线BL连接公共位线CBL，位线BL可以通过开关晶体管连接到公共位线CBL，通过开关晶体管控制位线BL和公共位线CBL之间的导通和断开(图3A中省略了开关晶体管)，读晶体管T1的第二电极连接第一参考电压端Vref1，写晶体管T2的第二电极连接位线BL，写晶体管T2的栅电极连接写字线WWL。即，本实施例中，读位线和写位线连接为一条位线。所述存储单元11还包括存储节点SN，所述存储节点SN包含所述读晶体管T1的第二栅电极。
或者，如图3C所示，所述存储单元11可以包括读晶体管T1和写晶体管T2，读晶体管T1的第一栅电极连接读字线RWL，第二栅电极连接写晶体管T2的第一电极，读晶体管T1的第一电极连接位线BL，位线BL连接公共位线CBL，位线BL可以通过开关晶体管连接到公共位线CBL，通过开关晶体管控制位线BL和公共位线CBL之间的导通和断开(图3A中省略了开关晶体管)，读晶体管T1的第二电极连接第一参考电压端Vref1，写晶体管T2的第二电极连接位线BL，写晶体管T2的第一栅电极连接第一写字线WWL1，第二栅电极连接第二写字线WWL2。所述存储单元11还包括存储节点SN，所述存储节点SN包含所述读晶体管T1的第二栅电极。
在一些实施例中，所述存储器可以包括第一存储阵列和第二存储阵列，分别连接到第一存储阵列的多条公共位线的多个开关子电路12可以连接到同一控制线，比如，连接到第一控制线CTRL1；分别连接到第二存储阵列的多条公共位线的多个开关子电路12可以连接到同一控制线，比如，连接到第二控制线CTRL2。开关子电路12包括第三晶体管T3时，分别连接到第一存储阵列的多条公共位线的多个第三晶体管T3的栅电极可以连接到第一控制线CTRL1，分别连接到第二存储阵列的多条公共位线的多个第三晶体管T3的栅电极可以连接到第二控制线CTRL2。
在一些实施例中，如图3D所示，所述感测放大器SA可以包括预充电子电路31和差分放大子电路32，其中：
所述预充电子电路31与第一输入端S1、第二输入端S2、第一控制端EQ_ctrl、第二参考电压端Vref2连接，被配置为，在所述第一控制端EQ_ctrl的控制下，将所述第二参考电压端Vref2的电压加载到所述第一输入端S1和所述第二输入端S2；
所述差分放大子电路32与所述第一输入端S1、第二输入端S2、第一使能端SAP_EN、第一电压控制端SAP、第二使能端SAN_EN、第二电压控制端SAN连接，被配置为，在所述第一使能端SAP_EN、第二使能端SAN_EN、第一电压控制端SAP、第二电压控制端SAN的控制下，将所述第一输入端S1和所述第二输入端S2之间的差分输入进行放大后通过所述第一输入端S1和所述第二入端S2输出。
在一些实施例中，如图3D所示，所述预充电子电路31可以包括第四晶体管T4和第五晶体管T5，其中：
所述第四晶体管T4的第一电极连接第一输入端S1，第二电极连接第五晶体管T5的 第一电极且连接第二参考电压端Vref2，第五晶体管T5的第二电极连接第二输入端S2，第四晶体管T4的栅电极和第五晶体管T5的栅电极连接第一控制端EQ_ctrl；
在一些实施例中，如图3D所示，所述差分放大子电路32可以包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10和第十一晶体管T11，其中：
第六晶体管T6的栅电极、第八晶体管T8的栅电极连接第二输入端S2，第六晶体管T6的第一电极连接第十晶体管T10的第一电极，第六晶体管T6的第二电极连接第一输入端S1；
第七晶体管T7的栅电极、第九晶体管T9的栅电极连接第一输入端S1，第七晶体管T7的第一电极连接第十晶体管T10的第一电极，第七晶体管T7的第二电极连接第二输入端S2；
第八晶体管T8的第一电极连接第一输入端S1，第八晶体管T8的第二电极连接第十一晶体管T11的第一电极；
第九晶体管T9的第一电极连接第二输入端S2，第九晶体管T9的第二电极连接第十一晶体管T11的第一电极；
第十晶体管T10的第二电极连接第一电压控制端SAP，第十晶体管T10的栅电极连接第一使能端SAP_EN；
第十一晶体管T11的第二电极连接第二电压控制端SAN，第十一晶体管T11的栅电极连接第二使能端SAN_EN。
在一些实施例中，所述第六晶体管T6、第七晶体管T7、第十晶体管T10可以是P型晶体管，所述第四晶体管T4、第五晶体管T5、第八晶体管T8、第九晶体管T9、第十一晶体管T11可以是N型晶体管。
在一些实施例中，所述第一电压控制端SAP比如可以是高电平信号，第二电压控制端SAN比如可以是低电平信号。
图3D所示的感测放大器电路仅为示例，本公开实施例不限于此，可以实现感测放大的电路均可应用在本申请实施例中。
下面通过一示例对图3A所示的存储器的工作过程进行说明。本实施例中，存储单元11如图3B所示，感测放大器如图3D所示，Vref1>Vref2>Vref3。本实施例中，对存储器某一个存储单元11(以第一存储阵列的一个存储单元11为例)的访问过程，可以包括预充电阶段t1、信号感测阶段t2、信号放大阶段t3和数据回写阶段t4，其中：
预充电阶段t1：第一控制端EQ_ctrl加载导通信号，第四晶体管T4、第五晶体管T5导通，加载第二参考电压端Vref2的电压至第一输入端S1和第二输入端S2，第一输入端S1的电压加载到公共位线CBL，即公共位线CBL的电压为Vref2；第一控制线CTRL1加载关断信号，使得第三晶体管T3关断；读字线RWL和写字线WWL加载关断信号，读晶体管T1和写晶体管T2关断；
信号感测阶段t2：第一控制端EQ_ctrl加载关断信号，使得第四晶体管T4、第五晶体管T5关断；第一控制线CTRL1加载导通信号，使得第三晶体管T3导通；读字线RWL加载导通信号，当存储单元存储的数据为“0”时，读晶体管T1关断，第三参考电压端Vref3对公共位线CBL进行放电(比如放电至公共位线CBL的电压为Vref3)，使得公共位线CBL电压小于Vref2。当存储单元存储的数据为“1”时，读晶体管T1导通，第一参考电压端Vref1对公共位线CBL进行充电，第三参考电压端Vref3对公共位线CBL 进行放电，且第一参考电压端Vref1对公共位线CBL的充电效果大于第三参考电压端Vref3对公共位线CBL的放电效果，从而使得公共位线CBL电压升压至大于Vref2的电压。
信号放大阶段t3：第一控制线CTRL1加载关断信号，使得第三晶体管T3关断；读字线RWL加载关断信号，使得读晶体管T1关断；第一使能端SAP_EN和第二使能端SAN_EN加载使能信号(其余阶段第一使能端SAP_EN和第二使能端SAN_EN可以加载非使能信号)，使得第十晶体管T10导通，第十一晶体管T11导通，从而差分子电路32可以对信号进行放大，根据存储单元11存储的数据不同，第一输入端S1和第二输入端S2输出相应的电压，比如，存储单元存储的数据为“1”，则第一输入端S1的电压拉升至数据“1”对应的电压，公共位线CBL为数据“1”对应的电压，第二输入端S2拉低至数据“0”对应的电压，读第一输入端S1的电平即可读出数据“1”。存储单元11存储的数据为“0”，则第一输入端S1的电压拉低至数据“0”对应的电压，公共位线CBL为数据“0”对应的电压，第二输入端S2拉升至数据“1”对应的电压，读第一输入端S1的电平即可读出数据“0”。
数据回写阶段t4：读字线RWL加载关断信号，读晶体管T1关断；第一控制线CTRL1加载关断信号，第三晶体管T3保持关断；写字线WWL加载导通信号，写晶体管T2导通，公共位线CBL与存储节点SN进行电荷共享，将数据“1”或“0”对应的电压写入存储节点SN。后续重新进入预充电阶段，继续等待执行读写操作。
上述导通信号和关断信号与晶体管类型有关。晶体管为N型晶体管时，导通信号为高电平信号，关断信号为低电平信号，晶体管为P型晶体管时，导通信号为低电平信号，关断信号为高电平信号。使能信号和非使能信号与晶体管类型有关。使能信号即为使得晶体管导通的信号，非使能信号即为使得晶体管关断的信号。
本公开实施例提供一种上述存储器的访问控制方法，可以包括：
在信号感应阶段，控制与待访问的所述存储单元的公共位线连接的开关子电路开启，连通所述第三参考电压端和所述公共位线；
在信号放大阶段，控制与待访问的所述存储单元的公共位线连接的所述开关子电路关闭，使得所述公共位线与所述第三参考电压端断开。
本实施例提供的方案，通过在信号感应阶段连通第三参考电压端和所述公共位线，避免公共位线浮空，消除公共位线耦合对数据读出的影响，实现数据的正确读出。
在一些实施例中，所述方法还可以包括：在数据回写阶段，关闭与待访问的所述存储单元的公共位线连接的所述开关子电路，使得所述公共位线与所述第三参考电压端断开。
在一些实施例中，所述方法还可以包括：在所述信号感应阶段之前的预充电阶段，关闭与待访问的所述存储单元的公共位线连接的所述开关子电路，使得所述公共位线与所述第三参考电压端断开，将所述第二参考电压加载到所述公共位线。
本公开实施例还提供了一种电子设备，包括前述任一实施例所述存储器。所述电子设备可以为：存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
在一些实施例中，所述电子设备还可以包括控制电路，所述控制电路配置为按照上述任一所述的访问控制方法对所述存储器进行访问控制。所述控制电路可以包括可以产生控制信号的电路和控制线，对所述开关子电路进行控制，从而实现对存储器的访问控制。控制电路与SA等一起实现对存储器的访问。
虽然本发明所揭露的实施方式如上，但所述的内容仅为便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种存储器，包括：
    至少一个存储阵列和与所述存储阵列连接的至少一个感测放大器，所述存储阵列包括至少一个存储单元阵列，所述存储单元阵列包括多个存储单元和多条位线；所述存储单元包括读晶体管，所述读晶体管包括第一电极和第二电极，所述第一电极连接所述位线，所述第二电极连接第一参考电压端或者读字线；所述感测放大器连接第二参考电压端，以所述第二参考电压端的第二参考电压作为基准电压；
    至少一条公共位线，所述公共位线与所述存储单元阵列一一对应，所述公共位线与对应的所述存储单元阵列中的多条位线连接，每条所述公共位线对应一个所述感测放大器，每条所述公共位线连接一个开关子电路，所述开关子电路还连接第三参考电压端，其中，
    所述开关子电路被配置为：在信号感应阶段，连通所述第三参考电压端和所述公共位线；在信号放大阶段，断开所述第三参考电压端和所述公共位线；
    所述第三参考电压端的第三参考电压、所述第二参考电压、第一参考电压满足：在信号感应阶段，所述存储单元存储的数据不同时，所述公共位线输出不同的电压，且输出的电压与所述第二参考电压的大小关系不同；
    所述第一参考电压为信号感应阶段所述读字线上加载的电压，或者为所述第一参考电压端的电压。
  2. 根据权利要求1所述的存储器，其中，所述存储阵列包括沿垂直于衬底方向堆叠的多层所述存储单元阵列，每层所述存储单元阵列对应一条所述公共位线。
  3. 根据权利要求1所述的存储器，其中，所述第三参考电压端的电压为固定电压；或者，所述第三参考电压端的电压为可变电压。
  4. 根据权利要求1所述的存储器，其中，所述第三参考电压端的电压为固定电压，且所述第三参考电压<所述第二参考电压<第一参考电压，且所述第三参考电压、第一参考电压满足：所述开关子电路和所述读晶体管均导通时，所述公共位线的电压大于所述第二参考电压。
  5. 根据权利要求1所述的存储器，其中，所述第三参考电压端的电压为固定电压，所述第三参考电压>所述第二参考电压>所述第一参考电压，且所述第三参考电压、第一参考电压满足：所述开关子电路和所述读晶体管均导通时，所述公共位线的电压小于所述第二参考电压。
  6. 根据权利要求1所述的存储器，其中，所述开关子电路包括一个开关晶体管，所述开关晶体管的栅电极连接控制线，所述开关晶体管的第一电极连接所述公共位线和所述感测放大器的一个输入端，所述开关晶体管的第二电极连接所述第三参考电压端。
  7. 根据权利要求6所述的存储器，其中，同一存储阵列的多条公共位线连接的多个所述开关子电路的栅控制端连接同一条控制线，所述控制线被配置为：同时开启或关断多个所述开关子电路。
  8. 根据权利要求1所述的存储器，其中，所述存储单元还包括写晶体管，所述位线为同一存储单元的所述读晶体管和所述写晶体管共用的位线。
  9. 根据权利要求1所述的存储器，其中，所述存储单元还包括写晶体管，所述位线为仅与所述读晶体管连接的读位线。
  10. 根据权利要求1所述的存储器，其中，所述存储器包括多个存储阵列，多个所述 感测放大器设置于沿所述公共位线的延伸方向相邻的两个存储阵列中间，且每两条分别属于相邻存储阵列的公共位线连接到同一个所述感测放大器，其中一条公共位线连接所述感测放大器的一端和第一开关子电路，另一条公共位线连接所述感测放大器的另一端和第二开关子电路。
  11. 一种如权利要求1至10任一所述的存储器的访问控制方法，包括：
    在信号感应阶段，控制与待访问的所述存储单元的公共位线连接的开关子电路开启，连通所述第三参考电压端和所述公共位线；
    在信号放大阶段，控制与待访问的所述存储单元的公共位线连接的所述开关子电路关闭，使得所述公共位线与所述第三参考电压端断开。
  12. 根据权利要求11所述的存储器的访问控制方法，所述方法还包括：在数据回写阶段，关闭与待访问的所述存储单元的公共位线连接的所述开关子电路，使得所述公共位线与所述第三参考电压端断开。
  13. 根据权利要求11所述的存储器的访问控制方法，所述方法还包括：在所述信号感应阶段之前的预充电阶段，关闭与待访问的所述存储单元的公共位线连接的所述开关子电路，使得所述公共位线与所述第三参考电压端断开，将所述第二参考电压加载到所述公共位线。
  14. 一种电子设备，包括如权利要求1至10任一所述的存储器。
  15. 根据权利要求14所述的电子设备，其中，所述电子设备还包括控制电路，所述控制电路配置为按照权利要求11至13任一所述的存储器的访问控制方法对所述存储器进行访问控制。
PCT/CN2024/129765 2024-03-06 2024-11-04 一种存储器及其访问控制方法、电子设备 Pending WO2025185201A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020257043606A KR20260015299A (ko) 2024-03-06 2024-11-04 메모리 및 그 액세스 제어 방법, 전자 장비

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202410255545.0 2024-03-06
CN202410255545.0A CN120612987A (zh) 2024-03-06 2024-03-06 一种存储器及其访问控制方法、电子设备

Publications (2)

Publication Number Publication Date
WO2025185201A1 true WO2025185201A1 (zh) 2025-09-12
WO2025185201A8 WO2025185201A8 (zh) 2025-10-02

Family

ID=96929618

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/129765 Pending WO2025185201A1 (zh) 2024-03-06 2024-11-04 一种存储器及其访问控制方法、电子设备

Country Status (3)

Country Link
KR (1) KR20260015299A (zh)
CN (1) CN120612987A (zh)
WO (1) WO2025185201A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030086312A1 (en) * 2001-11-05 2003-05-08 Hynix Semiconductor Inc. Nonovolatile ferroelectric memory device and driving method thereof
CN102737697A (zh) * 2011-03-30 2012-10-17 台湾积体电路制造股份有限公司 差分读写回读出放大器电路和方法
CN115602207A (zh) * 2021-07-07 2023-01-13 长鑫存储技术有限公司（Cn） 数据存储电路及其控制方法、存储装置
CN117316228A (zh) * 2023-09-27 2023-12-29 北京超弦存储器研究院 一种存储电路、存储器及其访问方法、电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030086312A1 (en) * 2001-11-05 2003-05-08 Hynix Semiconductor Inc. Nonovolatile ferroelectric memory device and driving method thereof
CN102737697A (zh) * 2011-03-30 2012-10-17 台湾积体电路制造股份有限公司 差分读写回读出放大器电路和方法
CN115602207A (zh) * 2021-07-07 2023-01-13 长鑫存储技术有限公司（Cn） 数据存储电路及其控制方法、存储装置
CN117316228A (zh) * 2023-09-27 2023-12-29 北京超弦存储器研究院 一种存储电路、存储器及其访问方法、电子设备

Also Published As

Publication number Publication date
CN120612987A (zh) 2025-09-09
WO2025185201A8 (zh) 2025-10-02
KR20260015299A (ko) 2026-02-02

Similar Documents

Publication Publication Date Title
US10902893B2 (en) Negative bitline write assist circuit and method for operating the same
CN104756192B (zh) 具有节能读取架构的存储器阵列
US9728239B2 (en) Semiconductor memory device
CN115810374B (zh) 存储电路、具有bcam寻址和逻辑运算功能的存内计算电路
US8259510B2 (en) Disturb-free static random access memory cell
US9355709B2 (en) Digit line equilibration using access devices at the edge of sub-arrays
US7760540B2 (en) Combination SRAM and NVSRAM semiconductor memory array
JPWO2011013298A1 (ja) Ｓｒａｍセル
WO2016204823A1 (en) Non-volatile static ram and method of operation thereof
CN101999147A (zh) 半导体存储装置
CN116645984B (zh) 存储器装置中的信号产生电路系统布局
US20240371433A1 (en) Memory circuits, memory structures, and methods for fabricating a memory device
WO2025208845A1 (zh) 一种存储器及其访问控制方法、电子设备
US9401207B2 (en) Pseudo SRAM using resistive elements for non-volatile storage
CN117316228A (zh) 一种存储电路、存储器及其访问方法、电子设备
WO2025185201A1 (zh) 一种存储器及其访问控制方法、电子设备
US9281042B1 (en) Non-volatile memory using bi-directional resistive elements and capacitive elements
WO2025227600A1 (zh) 灵敏感应器、数据处理方法以及存储器
EP0551756A1 (en) Memory cell with ferro-electric capacitors
US11722048B2 (en) Voltage generating circuits including assist circuits and operating methods thereof
CN112927738B (zh) 基于非易失器件的电路和电荷域存内计算方法
US7269077B2 (en) Memory architecture of display device and memory writing method for the same
CN119673249A (zh) 一种存储器及其访问控制方法、电子设备
WO2026025640A1 (zh) 一种感测电路、存储器及其访问控制方法、电子设备
CN120913615B (zh) 一种4t2fc铁电存储单元及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24928131

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 1020257043606

Country of ref document: KR

Free format text: ST27 STATUS EVENT CODE: A-0-1-A10-A15-NAP-PA0105 (AS PROVIDED BY THE NATIONAL OFFICE)

WWE Wipo information: entry into national phase

Ref document number: 1020257043606

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020257043606

Country of ref document: KR