WO2025129506A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2025129506A1
WO2025129506A1 PCT/CN2023/140335 CN2023140335W WO2025129506A1 WO 2025129506 A1 WO2025129506 A1 WO 2025129506A1 CN 2023140335 W CN2023140335 W CN 2023140335W WO 2025129506 A1 WO2025129506 A1 WO 2025129506A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
anode
electrode
line
orthographic projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2023/140335
Other languages
English (en)
French (fr)
Other versions
WO2025129506A9 (zh
Inventor
刘畅畅
闫政龙
石领
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380012435.5A priority Critical patent/CN120530740A/zh
Priority to PCT/CN2023/140335 priority patent/WO2025129506A1/zh
Publication of WO2025129506A1 publication Critical patent/WO2025129506A1/zh
Publication of WO2025129506A9 publication Critical patent/WO2025129506A9/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, including a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate;
  • the driving circuit layer includes a plurality of circuit units, at least one circuit unit includes at least a pixel driving circuit and a first power line, and the first power line is configured to provide a first power line number to the pixel driving circuit;
  • the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode includes an anode main body and an anode connecting part, one end of the anode connecting part is connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit;
  • at least one circuit unit also includes a shielding electrode, the shielding electrode is connected to the first power line, the orthographic projection of at least one shielding electrode on the substrate at least partially overlaps with the orthographic projection
  • the present disclosure further provides a display device, comprising the aforementioned display substrate.
  • the present disclosure further provides a method for preparing a display substrate, comprising:
  • a driving circuit layer is formed on the substrate, wherein the driving circuit layer includes a plurality of circuit units, at least one of which includes at least a pixel driving circuit and a first power line, wherein the first power line is configured to provide a first power line signal to the pixel driving circuit; at least one of the circuit units also includes a shielding electrode, wherein the shielding electrode is connected to the first power line;
  • a light-emitting structure layer is formed on the driving circuit layer, the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode includes an anode main body and an anode connecting part, one end of the anode connecting part is connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit; the orthographic projection of at least one shielding electrode on the substrate at least partially overlaps with the orthographic projection of a second anode center line of at least one anode on the substrate, the second anode center line is a straight line that bisects the anode main body in a first direction and extends along a second direction, and the first direction intersects the second direction.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic diagram of a planar structure of a display substrate
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate
  • FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure
  • FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4 ;
  • FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.
  • FIG8 is a schematic diagram of an embodiment of the present disclosure after forming a first semiconductor layer pattern
  • FIGS. 9A and 9B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern
  • FIGS. 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern
  • FIG. 11A and 11B are schematic diagrams of a second semiconductor layer pattern formed according to an embodiment of the present disclosure.
  • 12A and 12B are schematic diagrams of an embodiment of the present disclosure after a third conductive layer pattern is formed;
  • FIG13 is a schematic diagram of an embodiment of the present disclosure after forming a sixth insulating layer pattern
  • FIGS. 14A and 14B are schematic diagrams of an embodiment of the present disclosure after a fourth conductive layer pattern is formed;
  • 14C and 14D are schematic diagrams of initial signal lines of the mesh structure in FIG. 14A ;
  • FIG15 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern
  • 16A and 16B are schematic diagrams of an embodiment of the present disclosure after a fifth conductive layer pattern is formed;
  • FIG17 is a schematic diagram of an embodiment of the present disclosure after forming a second planar layer pattern
  • 18A and 18B are schematic diagrams of an embodiment of the present disclosure after a sixth conductive layer pattern is formed;
  • FIG19 is a schematic diagram of an embodiment of the present disclosure after forming a third planar layer pattern
  • 20A and 20B are schematic diagrams of an embodiment of the present disclosure after forming an anode conductive layer pattern.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the “source electrode” and the “drain electrode” may be interchanged, and the “source terminal” and the “drain terminal” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, chamfers, curved edges and deformations, etc.
  • "About" in this disclosure means that the limits are not strictly defined, and the values within the range of process and measurement errors are allowed.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, wherein the timing controller is connected to the data driver, the scan driver and the light emitting driver respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo) respectively.
  • the timing controller is connected to the data driver, the scan driver and the light emitting driver respectively
  • the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively
  • the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively
  • the light emitting driver is connected to a plurality of light emitting signal lines (E1 to Eo) respectively.
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, and at least one sub-pixel Pxij may be a plurality of sub-pixels Pxij.
  • a circuit unit and a light emitting unit may be included, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is connected to the scan signal line, the light emitting signal line and the data signal line respectively, and the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit.
  • the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, a clock signal suitable for the specification of the scan driver, a scan start signal, etc. may be provided to the scan driver, and a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. may be provided to the light emitting driver.
  • the data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller.
  • the data driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, and n may be a natural number.
  • the scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan driver may sequentially provide a scan signal having a conduction level pulse to the scan signal lines S1 to Sm.
  • the scan driver may be configured in the form of a shift register, and may sequentially transmit a scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of a clock signal to generate a scan signal, and m may be a natural number.
  • the light-emitting driver may generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller.
  • the light-emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light-emitting signal lines E1 to Eo.
  • the light-emitting driver may be configured in the form of a shift register, and may sequentially transmit an emission stop signal provided in the form of a cut-off level pulse to the next level circuit under the control of a clock signal to generate an emission signal, and o may be a natural number.
  • a pixel array may be provided on a display substrate.
  • FIG2 is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4.
  • Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit.
  • the light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.
  • the first sub-pixel P1 may be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light
  • the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light
  • the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the four sub-pixels may be arranged in a horizontal parallel, vertical parallel or square manner, etc., which is not limited in the present disclosure.
  • the pixel unit may include three sub-pixels, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a green sub-pixel (G) that emits green light, and the third sub-pixel P3 may be a blue sub-pixel (B) that emits blue light.
  • the three sub-pixels may be arranged in horizontal parallel, vertical parallel, or in a triangular pattern, which is not limited in the present disclosure.
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of four sub-pixels in the display area.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate or a rigid substrate.
  • the driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor.
  • the light emitting structure layer 103 may include a plurality of light emitting units, each of which may include a light emitting element.
  • the light emitting device may include at least an anode, an organic light emitting layer and a cathode, wherein the anode is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, and the cathode is connected to the organic light emitting layer.
  • the organic light emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light emitting structure layer 103.
  • the display substrate includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate;
  • the driving circuit layer includes a plurality of circuit units, at least one circuit unit includes at least a pixel driving circuit and a first power line, and the first power line is configured to provide a first power line number to the pixel driving circuit;
  • the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes at least an anode, the anode includes an anode main body and an anode connecting part, one end of the anode connecting part is connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit;
  • at least one circuit unit also includes a shielding electrode, the shielding electrode is connected to the first power line, and the positive projection of at least one shielding electrode on the substrate overlaps at
  • the pixel driving circuit includes at least a second transistor as a compensation transistor and a third transistor as a driving transistor, the gate electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the second electrode of the third transistor through the second node electrode, and the second electrode of the second transistor is connected to the gate electrode of the third transistor through the first node electrode; the positive projection of the anode connection portion on the substrate does not overlap with the positive projection of the second node electrode on the substrate.
  • an orthographic projection of the first power line on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate.
  • the shielding electrode is disposed between the second node electrodes of two adjacent circuit units in the first direction.
  • an orthographic projection of the shield electrode on the substrate does not overlap with an orthographic projection of the second node electrode on the substrate.
  • an orthographic projection of the first node electrode on the substrate at least partially overlaps an orthographic projection of the first scan signal line on the substrate.
  • At least one circuit unit also includes a first initial signal line extending along the first direction and a first initial connection line extending along the second direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit, the first initial signal connection line being connected to the first initial signal line to form a mesh connection structure for transmitting the first initial signal, and/or, at least one circuit unit also includes a second initial signal line extending along the first direction and a second initial connection line extending along the second direction, the second initial signal line being configured to provide a second initial signal to the pixel driving circuit, the second initial signal connection line being connected to the second initial signal line to form a mesh connection structure for transmitting the second initial signal, and/or, at least one circuit unit also includes a third initial signal line extending along the first direction and a third initial connection line extending along the second direction, the third initial signal line being configured to provide a third initial signal to the pixel driving circuit, the third initial signal connection line being connected to the third initial signal line to form a mesh connection structure
  • At least one of the first initial connection line, the second initial connection line and the third initial connection line includes a first initial connection electrode and a second initial connection electrode connected to each other; in a direction perpendicular to the substrate, the driving circuit layer includes a plurality of conductive layers, and the first initial connection electrode and the second initial connection electrode are arranged in different conductive layers.
  • the display substrate of the exemplary embodiments of the present disclosure is described below by way of some examples.
  • FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit of an exemplary embodiment of the present disclosure.
  • the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 10 signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, fourth scanning signal line S4, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT1, third initial signal line INIT3, data signal line DATA and first power line VDD).
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4.
  • the first node N1 is respectively connected to the second electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C
  • the second node N2 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the second electrode of the eighth transistor T8,
  • the third node N3 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.
  • the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the second node N2 .
  • the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the second node N2 , and a second electrode of the second transistor T2 is connected to the first node N1 .
  • the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the third node N3, and a second electrode of the third transistor T3 is connected to the second node N2.
  • the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the third node N3.
  • the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the third node N3.
  • the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the second node N2, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.
  • the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.
  • the eighth transistor T8 may be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.
  • a first electrode of the light emitting device EL is connected to the fourth node N4, and a second electrode of the light emitting device EL is connected to the second power supply line VSS.
  • the light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode, a quantum dot light emitting layer, and a second electrode.
  • the signal of the first power line VDD is a high level signal provided continuously
  • the second power line VDD is a high level signal provided continuously
  • the signal of the line VSS is a low level signal which is continuously provided.
  • the first transistor T1 to the eighth transistor T8 in the pixel driving circuit may be a P-type transistor, or may be an N-type transistor. In some other possible exemplary embodiments, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit may include a P-type transistor and an N-type transistor.
  • the first transistor T1 to the eighth transistor T8 in the pixel driving circuit may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and an oxide transistor.
  • the active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide oxide semiconductor
  • Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • the first transistor T1 and the second transistor T2 in the pixel driving circuit may be oxide transistors (N-type transistors), and the third transistor T3 to the eighth transistor T8 may be low-temperature polysilicon transistors (P-type transistors).
  • FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5, in an exemplary embodiment, the operation process of the pixel driving circuit may include:
  • the first stage A1 can be called the reset stage of the second node N2 and the fourth node N4.
  • the signals of the first scanning signal line S1, the second scanning signal line S2 and the third scanning signal line S3 are low level signals, and the signals of the fourth scanning signal line S4 and the light emitting signal line EM are high level signals, so that the seventh transistor T7 and the eighth transistor T8 are turned on, and the other switch transistors are turned off.
  • the seventh transistor T7 is turned on so that the signal of the second initial signal line INIT2 is provided to the fourth node N4, the first electrode of the light emitting device EL is initialized (reset), the original charge in the first electrode of the light emitting device EL is cleared, and the potential of the fourth node N4 is Vinit2.
  • the eighth transistor T8 is turned on so that the signal of the third initial signal line INIT3 is provided to the second node N2, the second node N2 is initialized (reset), and the potential of the second node N2 is Vinit3.
  • the second stage A2 can be called the first node N1 and the second transistor T2 reset stage.
  • the signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, the fourth scanning signal line S4 and the light emitting signal line EM are high level signals, so that the first transistor T1 and the second transistor T2 are turned on, and the other switch transistors are turned off.
  • the first transistor T1 and the second transistor T2 are turned on so that the signal of the first initial signal line INIT1 is provided to the first node N1 and the second node N2 respectively, the first node N1 and the second node N2 are initialized (reset), and the original charge in the first node N1 is cleared.
  • the potential of the first node N1 and the second node N2 is Vinit1.
  • the third stage A3 can be called a data writing stage.
  • the signal of the third scanning signal line S3 is a low level signal
  • the signal of the fourth scanning signal line S4 is a low level signal for a short period of time
  • the signals of the first scanning signal line S1, the second scanning signal line S2 and the light emitting signal line EM are high level signals, so that the second transistor T2 and the fourth transistor T4 are turned on, and the other switch transistors are turned off.
  • the second transistor T2 is turned on so that the first node N1 and the second node N2 are turned on. Since the third transistor T3 is continuously turned on at this stage, the fourth transistor T4 is turned on so that the data signal output by the data signal line DATA is provided to the first node N1 through the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C.
  • the voltage of the first node N1 is Vd-
  • the fourth stage A4 may be referred to as a stage in which the second node N2 , the third node N3 , and the fourth node N4 are reset.
  • the signals of the first scanning signal line S1 and the third scanning signal line S3 are low level signals
  • the signal of the second scanning signal line S2 is low level signal for a short period of time
  • the signals of the fourth scanning signal line S4 and the light emitting signal line EM are high level signals.
  • the flat signal turns on the seventh transistor T7 and the eighth transistor T8, and turns off the other switch transistors.
  • the seventh transistor T7 is turned on so that the signal of the second initial signal line INIT2 is provided to the fourth node N4. Since the third transistor T3 is continuously turned on at this stage, the eighth transistor T8 is turned on so that the signal of the third initial signal line INIT3 is provided to the second node N2 and the third node N3, and the second node N2, the third node N3 and the fourth node N4 are reset respectively.
  • the potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2.
  • the second node N2, the third node N3 and the fourth node N4 are reset, which can eliminate and improve the hysteresis deviation caused by the grayscale difference between adjacent pixels, reduce the hysteresis deviation, and can also reset the OLED anode periodically to improve low-frequency flicker.
  • the fifth stage A5 can be called the light-emitting stage.
  • the signals of the first scanning signal line S1, the third scanning signal line S3 and the light-emitting signal line EM are low-level signals, and the signals of the second scanning signal line S2 and the fourth scanning signal line S4 are high-level signals, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the other switch transistors are turned off.
  • the fifth transistor T5 and the sixth transistor T6 are turned on, so that the power supply voltage output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, the third node N3, the turned-on third transistor T3, the second node N2, and the turned-on sixth transistor T6, thereby driving the light-emitting device EL to emit light.
  • the driving current of the third transistor T3 of each pixel driving circuit is not affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, thereby ensuring uniform display brightness of the display product and improving the display effect of the entire display product.
  • FIG6 is a schematic diagram of the planar structure of a display substrate of an exemplary embodiment of the present disclosure, illustrating the planar structure of a plurality of circuit units (two unit rows and four unit columns).
  • the display substrate of the exemplary embodiment of the present disclosure may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate.
  • the driving circuit layer may include a plurality of circuit units, at least one of which may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device.
  • the light-emitting structure layer may include a plurality of light-emitting units, at least one of which may include a light-emitting device, which is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.
  • the circuit unit mentioned in the present disclosure is an area divided according to the pixel driving circuit.
  • the light-emitting unit mentioned in the present disclosure is an area divided according to the light-emitting device.
  • the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.
  • the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, the plurality of circuit units in each unit row are sequentially arranged along a first direction X, and the plurality of unit rows are sequentially arranged along a second direction Y to form an array of circuit units arranged in an array, and the first direction X intersects with the second direction Y.
  • At least one circuit unit may include a pixel driving circuit, and a first scanning signal line 21, a second scanning signal line 22, a third scanning signal line 23, a fourth scanning signal line 24, a light emitting signal line 25, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first power supply line 71, and a data signal line 72 connected to the pixel driving circuit.
  • the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23, the fourth scanning signal line 24, the light emitting signal line 25, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 may be in a straight line shape or a folded line shape with a main portion extending along the first direction X
  • the first power supply line 71 and the data signal line 72 may be in a straight line shape or a folded line shape with a main portion extending along the second direction Y.
  • the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the fourth scan signal line 24 are configured to provide a scan signal to the pixel driving circuit
  • the light emitting signal line 25 is configured to provide a light emitting control signal to the pixel driving circuit
  • the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide an initial signal to the pixel driving circuit
  • the first power line 71 is configured to provide a first power signal to the pixel driving circuit
  • the data signal line 72 is configured to provide a data signal to the pixel driving circuit. Signal.
  • a extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions.
  • a extends along direction B means “the main part of A extends along direction B".
  • the pixel driving circuit in at least one circuit unit may include a storage capacitor and a plurality of transistors
  • the storage capacitor may include a first electrode plate and a second electrode plate stacked
  • the plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor.
  • the first transistor T1 and the second transistor T2 are oxide transistors
  • the third transistor T3 to the eighth transistor T8 are low temperature polysilicon transistors.
  • the gate electrode of the first transistor T1 is connected to the third scan signal line 23
  • the first electrode of the first transistor T1 is connected to the first initial signal line 41
  • the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2.
  • the gate electrode of the second transistor T2 is connected to the first scan signal line 21
  • the first electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 through the second connection electrode 52 as the second node electrode
  • the second electrode of the second transistor T2 is connected to the gate electrode (first electrode plate) of the third transistor T3 through the first connection electrode 51 as the first node electrode.
  • the gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 24, the first electrode of the fourth transistor T4 is connected to the data signal line 72, and the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3.
  • the gate electrode of the fifth transistor T5 is connected to the light emitting signal line 25, the first electrode of the fifth transistor T5 is connected to the first power supply line 71, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.
  • the gate electrode of the sixth transistor T6 is connected to the light emitting signal line 25, the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the gate electrode of the seventh transistor T7 is connected to the second scanning signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42.
  • the gate electrode of the eighth transistor T8 is connected to the second scanning signal line 22, the first electrode of the eighth transistor T8 is connected to the third initial signal line 43, and the second electrode of the eighth transistor T8 is connected to the second electrode of the third transistor T3 through the second connecting electrode 52.
  • the first power lines 71 in two circuit units adjacent to each other in the first direction X may be an integrated structure connected to each other.
  • an orthographic projection of the first power line 71 on the substrate at least partially overlaps an orthographic projection of the first connection electrode 51 on the substrate.
  • an orthographic projection of the first power line 71 on the substrate at least partially overlaps an orthographic projection of the active layer of the second transistor T2 on the substrate.
  • an orthographic projection of the first connection electrode 51 on the substrate at least partially overlaps an orthographic projection of the first scan signal line 21 on the substrate.
  • an orthographic projection of the first power line 71 on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate.
  • At least one circuit unit further includes a shielding electrode 74 , which is connected to the first power line 71 and disposed between the second connection electrodes 52 of two adjacent circuit units in the first direction X.
  • the orthographic projection of the shielding electrode 74 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate.
  • an orthographic projection of the second connection electrode 52 on the substrate does not overlap with an orthographic projection of the fourth scan signal line 24 on the substrate.
  • FIG7 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure, illustrating the planar structure of the anode in multiple light-emitting units.
  • the light-emitting structure layer may include multiple light-emitting units, at least one
  • the light emitting unit may include a light emitting device, at least one of the light emitting devices may include an anode 90, and the anode 90 is connected to a pixel driving circuit of a corresponding circuit unit.
  • At least one anode 90 may include an anode main body and an anode connecting part.
  • the shape of the anode main body may be circular or elliptical, and the shape of the anode connecting part may be a strip.
  • One end of the anode connecting part is directly connected to the anode main body, and the other end of the anode connecting part is connected to the pixel driving circuit through a via.
  • the anode body of at least one anode may have a first anode center line OX and a second anode center line OY
  • the first anode center line OX may be a straight line that bisects the anode body of the anode in the second direction Y and extends along the first direction X
  • the second anode center line OY may be a straight line that bisects the anode body of the anode in the first direction X and extends along the second direction Y.
  • an orthographic projection of the at least one shield electrode 74 on the substrate at least partially overlaps an orthographic projection of the second anode centerline OY of the at least one anode 90 on the substrate.
  • the orthographic projection of the anode body of at least one anode 90 on the substrate at least partially overlaps with the orthographic projections of two first power lines 71 in two adjacent circuit units in the first direction X on the substrate, and the two first power lines 71 can be mirror-symmetric relative to the second anode center line OY.
  • an orthographic projection of the anode connection portion of the at least one anode 90 on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate.
  • a first power block 71-1 and a second power block 71-2 may be provided on at least one first power line 71, the orthographic projection of the anode body of at least one anode 90 on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 on the substrate, and the first power block 71-1 and the second power block 71-2 may be mirror-symmetrical relative to the first anode center line OX.
  • the orthographic projection of the anode body of at least one anode 90 on the substrate at least partially overlaps with the orthographic projection of two first power blocks 71-1 in two adjacent circuit units in the first direction X on the substrate, and the two first power blocks 71-1 can be mirror-symmetrical relative to the second anode center line OY.
  • the orthographic projection of the anode body of at least one anode 90 on the substrate at least partially overlaps with the orthographic projection of two second power blocks 71-2 in two adjacent circuit units in the first direction X on the substrate, and the two second power blocks 71-2 can be mirror-symmetrical relative to the second anode center line OY.
  • the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer, and a third flat layer sequentially disposed on the substrate.
  • the first semiconductor layer may include at least the active layer of the third transistor T3 to the eighth transistor T8, the first conductive layer may include at least the second scan signal line 22, the fourth scan signal line 24, and the first plate of the storage capacitor, the second conductive layer may include at least the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the first transistor T1 and the second transistor T2, the third conductive layer may include at least the first scan signal line 21, the third scan signal line 23, and the first initial connection electrode 33, the fourth conductive layer may include at least the second initial connection electrode 46, the fifth conductive layer may include at least a plurality of connection electrodes, and the sixth conductive layer may include at least the first power line 71, the data signal line 72, and the shielding electrode 74.
  • the "patterning process” mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials.
  • Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition
  • coating can be carried out by any one or more of spraying, spin coating and inkjet printing
  • etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process, and the patterning chemical is called a “thin film”. The "layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • Forming a first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 8 .
  • the first semiconductor layer pattern in each circuit unit may include the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 in the circuit unit are interconnected as an integral structure.
  • the fourth active layer 14 and the fifth active layer 15 may be located on the same side of the third active layer 13 in the present circuit unit
  • the sixth active layer 16 and the seventh active layer 17 may be located on the same side of the third active layer 13 in the present circuit unit
  • the fifth active layer 15 and the sixth active layer 16 may be located on different sides of the third active layer 13 of the present circuit unit.
  • the fourth active layer 14 of the circuit unit in the Mth circuit row may be located on a side of the third active layer 13 away from the M+1th circuit row, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 of the circuit unit in the Mth circuit row may be located on a side of the third active layer 13 close to the circuit unit in the M+1th unit row.
  • the third active layer 13 may have an ⁇ shape
  • the fourth, fifth, sixth, seventh, and eighth active layers 14, 15, 16, 17, and 18 may have an I shape.
  • the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer 14, and the second region 15-2 of the fifth active layer 15 may be connected to each other, and the first region 13-1 of the third active layer 13 may simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15.
  • the second region 13-2 of the third active layer 13 is connected to the first region 16-1 of the sixth active layer 16, and the second region 13-2 of the third active layer 13 may serve as the first region 16-1 of the sixth active layer 16.
  • the second region 16-2 of the sixth active layer 16 is connected to the second region 17-2 of the seventh active layer 17, and the second region 16-2 of the sixth active layer 16 may serve as the second region 17-2 of the seventh active layer 17.
  • the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, the first region 17-1 of the seventh active layer 17, the first region 18-1 of the eighth active layer 18, and the second region 18-2 of the eighth active layer 18 may be separately provided.
  • the first semiconductor layers in two adjacent circuit units may be symmetrically arranged with respect to a column center line
  • the column center line may be a straight line located between two adjacent circuit units in the first direction X and extending along the second direction Y.
  • the first semiconductor layers (the third active layer 13 to the eighth active layer 18) of the Nth unit column and the N+1th unit column may be symmetrically arranged with respect to the column center line.
  • the first semiconductor layers of the N+1th unit column and the N+2th unit column may be symmetrically arranged with respect to the column center line.
  • the first semiconductor layers in adjacent cell rows may be substantially the same.
  • the first semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor to the eighth transistor are LTPS thin film transistors.
  • patterning the first semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a first semiconductor layer pattern.
  • forming the first conductive layer pattern may include: On the substrate formed with the aforementioned pattern, a second insulating film and a first conductive film are sequentially deposited, and the first conductive film is patterned by a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 9A and 9B , wherein FIG. 9B is a plan view of the first conductive layer in FIG. 9A .
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern in each circuit unit includes at least: a second scan signal line 22 , a fourth scan signal line 24 , a light emitting control line 25 , and a first electrode plate 81 of a storage capacitor.
  • the shape of the first electrode plate 81 may be rectangular, the corners of the rectangle may be chamfered, and the orthographic projection of the first electrode plate 81 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the first electrode plate 81 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.
  • the shape of the second scan signal line 22 can be a straight line or a broken line with the main part extending along the first direction X.
  • the second scan signal line 22 in the Mth unit row circuit unit can be located on the side of the first electrode 81 of the circuit unit close to the M+1th unit row circuit unit.
  • the area where the second scan signal line 22 overlaps with the seventh active layer of the circuit unit serves as the gate electrode of the seventh transistor T7, and the area where the second scan signal line 22 overlaps with the eighth active layer of the circuit unit serves as the gate electrode of the eighth transistor T8.
  • the shape of the fourth scan signal line 24 can be a straight line or a broken line with the main part extending along the first direction X.
  • the fourth scan signal line 24 in the Mth unit row circuit unit can be located on the side of the first electrode 81 of the circuit unit away from the M+1th unit row circuit unit, and the area where the fourth scan signal line 24 overlaps with the fourth active layer of the circuit unit serves as the gate electrode of the fourth transistor T4.
  • the shape of the light-emitting control line 25 can be a straight line or a broken line with the main part extending along the first direction X.
  • the light-emitting control line 25 can be located between the first electrode 81 and the second scanning signal line 22.
  • the area where the light-emitting control line 25 overlaps with the fifth active layer of the circuit unit serves as the gate electrode of the fifth transistor T5
  • the area where the light-emitting control line 25 overlaps with the sixth active layer of the circuit unit serves as the gate electrode of the sixth transistor T6.
  • the first conductive layers in two adjacent circuit units may be symmetrically arranged relative to the center line of the column.
  • the first conductive layers of the Nth unit column and the N+1th unit column may be symmetrically arranged relative to the center line of the column.
  • the first conductive layers of the N+1th unit column and the N+2th unit column may be symmetrically arranged relative to the center line of the column.
  • the first conductive layers in adjacent cell rows may be substantially the same.
  • the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer.
  • the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the third active layer to the eighth active layer are both conductorized.
  • forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 10A and 10B , where FIG. 10B is a plan view schematic diagram of the second conductive layer in FIG. 10A .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern in each circuit unit includes at least a first shielding line 31 , a second shielding line 32 , and a second electrode plate 82 of the storage capacitor.
  • the outline of the second electrode plate 82 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the second electrode plate 82 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 81 on the substrate.
  • the second electrode plate 82 can serve as another electrode plate of the storage capacitor, and the first electrode plate 81 and the second electrode plate 82 constitute the storage capacitor of the pixel driving circuit.
  • the second electrode plate 82 is provided with an opening 83, and the shape of the opening 83 may be a block shape (eg The opening 83 is shaped like a rectangle and can be located in the middle of the second electrode plate 82, so that the second electrode plate 82 forms a ring structure.
  • the opening 83 exposes the third insulating layer covering the first electrode plate 81, and the orthographic projection of the first electrode plate 81 on the substrate includes the orthographic projection of the opening 83 on the substrate.
  • the opening 83 is configured to accommodate the eleventh via hole formed subsequently, and the eleventh via hole is located in the opening 83 and exposes the first electrode plate 81, so that the first connecting electrode formed subsequently is connected to the first electrode plate 81.
  • the second electrode plate 82 may be provided with a first electrode plate connection line 84 and a second electrode plate connection line 85.
  • the first electrode plate connection line 84 and the second electrode plate connection line 85 may be respectively provided on both sides of the second electrode plate 82 in the first direction X, and respectively connected to the second electrode plates 82 in the adjacent circuit units in the first direction X, so that the second electrode plates 82 in the adjacent circuit units in a unit row are connected to each other.
  • the second electrode plate 82 in the Nth column and the second electrode plate 82 in the N+1th column may be connected to each other through the first electrode plate connection line 84.
  • the second electrode plate 82 in the N+1th column and the second electrode plate 82 in the N+2th column may be connected to each other through the second electrode plate connection line 85. Since the second electrode plate 82 in each circuit unit is connected to the first power line formed subsequently, by forming the second electrode plates 82 of the adjacent circuit units into an integrated structure connected to each other, the second electrode plates 82 of the integrated structure can be reused as a power signal line, so that the plurality of second electrode plates 82 in a unit row can be ensured to have the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the widths of the first electrode plate connection line 84 and the second electrode plate connection line 85 may be different, and the width is a dimension in the second direction Y.
  • the shape of the first shielding line 31 can be a straight line or a folded line with the main part extending along the first direction X, and the first shielding line 31 can be located between the second electrode plate 82 and the fourth scanning signal line 24.
  • the first shielding line 31 can be a folded line of unequal width, and the width of the first shielding line 31 at the position where it overlaps with the second active layer formed subsequently can be greater than the width at other positions.
  • the first shielding line 31 at a wider position can serve as a shielding layer of the second transistor T2 to shield the channel region of the second transistor T2 and ensure the electrical performance of the oxide second transistor T2.
  • the first shielding line 31 can also serve as the bottom gate electrode of the second transistor T2.
  • the first shielding line 31 may be a straight line or a broken line of unequal width, and the width is the dimension in the second direction Y.
  • the first shielding line 31 may include at least a first sub-shielding line segment 31-1 and a second sub-shielding line segment 31-2 connected to each other, and the width of the first sub-shielding line segment 31-1 is greater than the width of the second sub-shielding line segment 31-2.
  • the first sub-shielding line segment 31-1 may be arranged in an area where a second active layer to be formed subsequently is located, and the orthographic projection of the first sub-shielding line segment 31-1 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the second sub-shielding line segment 31-2 may be arranged in an area outside the second active layer to be formed subsequently, and the orthographic projection of the second sub-shielding line segment 31-2 on the substrate does not overlap with the orthographic projection of the second active layer on the substrate.
  • the shape of the second shielding line 32 may be a straight line or a folded line with the main part extending along the first direction X, and the second shielding line 32 may be located on the side of the fourth scanning signal line 24 away from the second electrode plate 82.
  • the second shielding line 32 may be a folded line of unequal width, and the width of the second shielding line 32 at the position where it overlaps with the first active layer formed subsequently may be greater than the width at other positions, and the second shielding line 32 at the wider position may serve as a shielding layer of the first transistor T1 to shield the channel region of the first transistor T1 and ensure the electrical performance of the oxide first transistor T1.
  • the second shielding line 32 may also serve as the bottom gate electrode of the first transistor T1.
  • the second conductive layers in two adjacent circuit units may be symmetrically arranged with respect to the center line of the column.
  • the second conductive layers of the Nth unit column and the N+1th unit column may be symmetrically arranged with respect to the center line of the column.
  • the second conductive layers of the N+1th unit column and the N+2th unit column may be symmetrically arranged with respect to the center line of the column.
  • the second conductive layers in adjacent cell rows may be substantially the same.
  • forming the second semiconductor layer pattern may include: In summary: On the substrate forming the aforementioned pattern, a fourth insulating film and a second semiconductor film are sequentially deposited, and the second semiconductor film is patterned through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern arranged on the fourth insulating layer, as shown in Figures 11A and 11B, Figure 11B is a plan schematic diagram of the second semiconductor layer in Figure 11A.
  • the second semiconductor layer pattern in each circuit unit includes at least a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2 .
  • the shape of the first active layer 11 and the second active layer 12 can be "I"-shaped, and the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the second shading line 32 on the substrate, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the first shading line 31 on the substrate.
  • the first region 11-1 of the first active layer 11 can be located on a side of the second shielding line 32 away from the second electrode plate 82
  • the second region 12-2 of the second active layer 12 can be located on a side of the first shielding line 31 close to the second electrode plate 82
  • the second region 11-2 of the first active layer 11 and the first region 12-1 of the second active layer 12 can be connected to each other
  • the second region 11-2 of the first active layer 11 can serve as the first region 12-1 of the second active layer 12.
  • the second semiconductor layers in two adjacent circuit units may be symmetrically arranged with respect to the center line of the column.
  • the second semiconductor layers of the Nth unit column and the N+1th unit column may be symmetrically arranged with respect to the center line of the column.
  • the second semiconductor layers of the N+1th unit column and the N+2th unit column may be symmetrically arranged with respect to the center line of the column.
  • the second semiconductor layers in adjacent cell rows may be substantially the same.
  • the second semiconductor layer may be made of oxide, that is, the first transistor T1 and the second transistor T2 are oxide transistors.
  • the second semiconductor film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.
  • forming the third conductive layer pattern may include: depositing a fifth insulating film and a third conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIGS. 12A and 12B, wherein FIG. 12B is a plan view schematic diagram of the third conductive layer in FIG. 12A.
  • the third conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer pattern in each circuit unit includes at least a first scan signal line 21 , a third scan signal line 23 , and a first preliminary connection electrode 33 .
  • the shape of the first scan signal line 21 can be a straight line or a broken line with the main part extending along the first direction X.
  • the first scan signal line 21 can be located between the second electrode plate 82 and the fourth scan signal line 24, and the area where the first scan signal line 21 overlaps with the second active layer serves as the gate electrode of the second transistor T2.
  • the orthographic projection of the first scanning signal line 21 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 31 on the substrate, and the first scanning signal line 21 and the first shielding line 31 can be connected to the same signal source, so that the first shielding line 31 can serve as the bottom gate electrode of the second transistor T2, and the first scanning signal line 21 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.
  • the first scan signal line 21 may be a straight line or a folded line of unequal width, and the width is the dimension in the second direction Y.
  • the first scan signal line 21 may include at least a first sub-scan line segment 21-1 and a second sub-scan line segment 21-2 connected to each other, and the width of the first sub-scan line segment 21-1 is greater than the width of the second sub-scan line segment 21-2.
  • the first sub-scan line segment 21-1 may be arranged in the area where the second active layer is located, and the orthographic projection of the first sub-scan line segment 21-1 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the second sub-scan line segment 21-2 may be arranged in an area outside the second active layer, and the orthographic projection of the second sub-scan line segment 21-2 on the substrate does not overlap with the orthographic projection of the second active layer on the substrate.
  • the orthographic projection of the first sub-scanning line segment 21-1 on the substrate at least partially overlaps with the orthographic projection of the first sub-blocking line segment 31-1 on the substrate, and the orthographic projection of the second sub-scanning line segment 21-2 on the substrate overlaps with the orthographic projection of the second sub-blocking line segment 31-1 on the substrate.
  • the orthographic projections of the occluding line segments 31 - 2 on the substrate at least partially overlap.
  • the shape of the third scan signal line 23 can be a straight line or a broken line with the main part extending along the first direction X.
  • the third scan signal line 23 can be located on the side of the fourth scan signal line 24 away from the second electrode plate 82, and the area where the third scan signal line 23 overlaps with the first active layer serves as the gate electrode of the first transistor T1.
  • the orthographic projection of the third scan signal line 23 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 32 on the substrate, and the third scan signal line 23 and the second shielding line 32 can be connected to the same signal source, so that the second shielding line 32 can serve as the bottom gate electrode of the first transistor T1, and the third scan signal line 23 can serve as the top gate electrode of the first transistor T1, forming the first transistor T1 with a top-gate and bottom-gate structure.
  • the first initial connection electrode 33 is shaped like a zigzag line with a main portion extending along the second direction.
  • the first initial connection electrode 33 is configured to be connected to a second initial connection electrode formed subsequently, and the first initial connection electrode and the second initial connection electrode together constitute an initial connection line.
  • the first initial connection electrode 33 may include a first end 33A, a second end 33B, a first connection block 33-1, a second connection block 33-2, and a third connection block 33-3.
  • the first end 33A of the first initial connection electrode 33 is an end of the first initial connection electrode 33 close to the first scan signal line 21, and the second end 33B of the first initial connection electrode 33 is an end of the first initial connection electrode 33 close to the third scan signal line 23.
  • the first connection block 33-1 may be disposed at a side of the first end 33A close to the second end 33B, and the first connection block 33-1 is configured to be connected to the first initial signal line formed subsequently.
  • the second connection block 33-2 may be disposed at a side of the first connection block 33-1 close to the second end 33B, and the second connection block 33-2 is configured to be connected to the second initial signal line formed subsequently.
  • the third connection block 33-3 may be disposed at a side of the second connection block 33-2 close to the second end 33B, and the third connection block 33-3 is configured to be connected to the third initial signal line formed subsequently.
  • the third conductive layers in two adjacent circuit units may be symmetrically arranged with respect to the center line of the column.
  • the third conductive layers of the Nth unit column and the N+1th unit column may be symmetrically arranged with respect to the center line of the column.
  • the third conductive layers of the N+1th unit column and the N+2th unit column may be symmetrically arranged with respect to the center line of the column.
  • the third conductive layers in adjacent cell rows may be substantially the same.
  • Forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein a plurality of vias are disposed on the sixth insulating layer, as shown in FIG. 13 .
  • the plurality of vias in each circuit unit includes at least a first via V1 to a fourteenth via V14 .
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed first initial signal line to the first region of the first active layer through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of the first active layer (also the first area of the second active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second area of the first active layer (also the first area of the second active layer), and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second area of the first active layer (also the first area of the second active layer) through the via hole.
  • a curved portion is provided on the fourth scanning signal line 24 in the region where the second via hole V2 is located, and the curved portion protrudes away from the second electrode plate 82 so that the orthographic projection of the second via hole V2 on the substrate does not overlap with the orthographic projection of the fourth scanning signal line 24 on the substrate.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, and the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the On the surface of the second region of the second active layer, the third via hole V3 is configured to connect a first connection electrode formed subsequently to the second region of the second active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of the third active layer (also the first area of the sixth active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of the third active layer (also the first area of the sixth active layer), and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second area of the third active layer (also the first area of the sixth active layer) through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the fourth active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the first area of the fourth active layer through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of the fifth active layer, and the sixth via hole V6 is configured to connect a subsequently formed fourth connecting electrode to the first area of the fifth active layer through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second area of the sixth active layer (also the second area of the seventh active layer), and the seventh via hole V7 is configured to connect the subsequently formed fifth connecting electrode 55 to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first region of the seventh active layer, and the eighth via V8 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the first region of the eighth active layer, and the ninth via hole V9 is configured to connect a subsequently formed third initial signal line to the first region of the eighth active layer through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the tenth via hole V10 are etched away to expose the surface of the second region of the eighth active layer, and the tenth via hole V10 is configured to connect a subsequently formed second connecting electrode to the second region of the eighth active layer through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the opening 83 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first electrode 31, and the eleventh via hole V11 is configured to connect a subsequently formed first connecting electrode to the first electrode 31 through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second electrode plate connecting line 85 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second electrode plate connecting line 85, and the twelfth via hole V12 is configured to connect the subsequently formed fourth connecting electrode to the second electrode plate connecting line 85 through the via hole.
  • two circuit units adjacent to each other in a portion of the first direction X may share the same twelfth via hole V12.
  • two circuit units in the N-1th unit column and the Nth unit column may share the same twelfth via hole V12.
  • two circuit units in the N+1th unit column and the N+2th unit column may share the same twelfth via hole V12.
  • two circuit units in the N+3th unit column and the N+4th unit column may share the same twelfth via hole V12.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first end 33A of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the first end 33A, and the thirteenth via hole V13 is configured to connect the subsequently formed second initial connection electrode to the first end 33A through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second end 33B of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the fourteenth via hole V14 is etched away to expose the surface of the second end 33B, and the fourteenth via hole V14 is configured to connect the subsequently formed second initial connection electrode to the second end 33B through the via hole.
  • the plurality of via holes in the at least one circuit unit may further include a fifteenth via hole V15, a sixteenth via hole V16, and a seventeenth via hole V17.
  • the fifteenth via V15 can be arranged in the circuit units of the Nth unit column and the N+3th unit column, the orth projection of the fifteenth via V15 on the substrate is located within the range of the orth projection of the first connection block 33-1 of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the fifteenth via V15 is etched away to expose the surface of the first connection block 33-1, and the fifteenth via V15 is configured to connect the subsequently formed first initial signal line to the first connection block 33-1 through the via.
  • the sixteenth via V16 can be arranged in the circuit unit of the N+1th unit column, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second connection block 33-2 of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the sixteenth via V16 is etched away to expose the surface of the second connection block 33-2, and the sixteenth via V16 is configured to connect the subsequently formed second initial signal line to the second connection block 33-2 through the via.
  • the seventeenth via V17 can be arranged in the circuit unit of the N+2th unit column, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the third connection block 33-3 of the first initial connection electrode 33 on the substrate, the sixth insulating layer in the seventeenth via V17 is etched away to expose the surface of the third connection block 33-3, and the sixteenth via V16 is configured to connect the subsequently formed third initial signal line to the third connection block 33-3 through the via.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the sixth insulating layer, as shown in FIGS. 14A and 14B , where FIG. 14B is a plan view of the fourth conductive layer in FIG. 14A .
  • the fourth conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the fourth conductive layer in each circuit unit includes at least: a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55 and a second initial connection electrode 56.
  • the shape of the first connection electrode 51 may be a strip extending along the second direction Y, the first end of the first connection electrode 51 is connected to the second region of the second active layer through the third via hole V3, and the second end of the first connection electrode 51 is connected to the first electrode plate 31 through the eleventh via hole V11.
  • the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 enables the second electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 to have the same potential, forming a first node N1 of the pixel driving circuit.
  • the first connection electrode 51 may be referred to as a first node electrode.
  • the orthographic projection of the first connection electrode 51 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 21 on the substrate. Since the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first connection electrode 51 can increase the parasitic capacitance between the first scan signal line 21 and the first node N1. In an exemplary embodiment, after the fourth scan signal line 24 outputs the on signal, the first scan signal line 21 is used to generate a falling edge. The parasitic capacitor can lower the potential of the first node N1, thereby increasing the current and effectively improving the display brightness.
  • a first compensation block 51-1 may be provided on the first connecting electrode 51, a first end of the first compensation block 51-1 is connected to the first end of the first connecting electrode 51, a second end of the first compensation block 51-1 extends toward the direction of the first scanning signal line 21, and an orthographic projection of the first compensation block 51-1 on the substrate at least partially overlaps with an orthographic projection of the first scanning signal line 21 on the substrate.
  • the first connection electrode 51 and the first compensation block 51 - 1 may be an integral structure connected to each other.
  • the shape of the second connection electrode 52 may be a strip shape in which the main part extends along the second direction Y, the first end of the second connection electrode 52 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via hole V2, the third via hole V3 is connected to the second region of the second active layer, the second end of the second connection electrode 52 is connected to the second region of the eighth active layer through the tenth via hole V10, and the area between the first end and the second end of the second connection electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) through the fourth via hole V4.
  • the second connection electrode 52 makes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the second electrode of the eighth transistor T8 have the same potential, forming a second node N2 of the pixel driving circuit.
  • the second connection electrode 52 may be referred to as a second node electrode.
  • a curved portion is provided on the fourth scan signal line 24 in the region where the second via hole V2 is located, and the curved portion protrudes in a direction away from the second electrode plate 82, so that the fourth scan signal line 24 can avoid the second connection electrode 52, and the orthographic projection of the second connection electrode 52 on the substrate does not overlap with the orthographic projection of the fourth scan signal line 24 on the substrate. Since the second connection electrode 52 serves as the second node N2 of the pixel driving circuit, the parasitic capacitance between the second node N2 and the fourth scan signal line 24 can be effectively reduced, which can reduce the parasitic capacitance of the second node N2 on the one hand, and reduce the influence on the data signal writing process on the other hand.
  • a bent portion that avoids the second connection electrode 52 is provided on the fourth scan signal line 24, and a bent portion that avoids the first initial connection electrode 33 is provided on the third scan signal line 23, so that the orthographic projection of the fourth scan signal line 24 on the substrate at least partially overlaps with the orthographic projection of the third scan signal line 23 on the substrate, resulting in an increase in parasitic capacitance between the third scan signal line 23 and the fourth scan signal line 24. Since the third scan signal line 23 outputs a conduction signal in the second period, the conduction signal will not affect the fourth scan signal line 24 outputting a conduction signal in the third period, nor will it affect the data signal writing process.
  • the orthographic projection of the second connecting electrode 52 on the substrate does not overlap with the orthographic projection of the first sub-scanning line segment 21-1 in the first scanning signal line 21 on the substrate
  • the orthographic projection of the second connecting electrode 52 on the substrate does not overlap with the orthographic projection of the first sub-blocking line segment 31-1 in the first shielding line 31 on the substrate
  • the orthographic projection of the second connecting electrode 52 on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning line segment 21-2 in the first scanning signal line 21 on the substrate
  • the orthographic projection of the second connecting electrode 52 on the substrate at least partially overlaps with the orthographic projection of the second sub-scanning line segment 21-2 in the first shielding line 31 on the substrate.
  • the width of the second sub-shielding line segment 31-2 is smaller than the width of the first sub-shielding line segment 31-1
  • the width of the second sub-scanning line segment 21-2 is smaller than the width of the first sub-scanning line segment 21-1
  • the parasitic capacitance between the second connecting electrode 52 and the first scanning signal line 21 (first shielding line 31) can be effectively reduced.
  • the parasitic capacitance of the second node N2 can be reduced, and on the other hand, the impact on the first scanning signal line can be reduced.
  • the third connection electrode 53 may be in a block shape (eg, rectangular), connected to the first region of the fourth active layer through a fifth via hole V5, and configured to be connected to a twelfth connection electrode formed subsequently.
  • the fourth connection electrode 54 may be in the shape of a strip extending along the second direction Y, the first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the sixth via hole V6, the second end of the fourth connection electrode 54 is connected to the second electrode plate connection line 85 through the twelfth via hole V12, and the fourth connection electrode 54 is configured to be connected to the eleventh connection electrode formed subsequently.
  • the second electrode 82 is connected, so the fourth connection electrode 54 enables the first electrode of the fifth transistor T5 in the circuit unit and the second electrode 82 of the storage capacitor to have the same potential.
  • the fourth connection electrodes 54 of two circuit units adjacent to each other in the partial first direction X may be an integrated structure connected to each other.
  • the fourth connection electrodes 54 of two circuit units of the N-1th unit column and the Nth unit column may be an integrated structure connected to each other.
  • the fourth connection electrodes 54 of two circuit units of the N+1th unit column and the N+2th unit column may be an integrated structure connected to each other.
  • the fourth connection electrodes 54 of two circuit units of the N+3th unit column and the N+4th unit column may be an integrated structure connected to each other.
  • the shape of the fifth connection electrode 55 can be a block shape (such as a rectangle), and the fifth connection electrode 55 is connected to the second area of the sixth active layer (also the second area of the seventh active layer) through the seventh via hole V7.
  • the fifth connection electrode 55 is configured to be connected to the thirteenth connection electrode formed subsequently to form a fourth node N4 of the pixel driving circuit.
  • the shape of the second initial connection electrode 56 can be a zigzag shape with the main body extending along the second direction Y, the first end of the second initial connection electrode 56 is connected to the first end 33A of the first initial connection electrode 33 through the thirteenth via hole V13, and the second end of the second initial connection electrode 56 is connected to the second end 33B of the first initial connection electrode 33 through the fourteenth via hole V14.
  • the first initial signal line 41 is also connected to the first connection block 33-1 through the fifteenth via hole V15. Since the first connection block 33-1 is connected to the first initial connection electrode 33, the first initial connection electrodes 33 of adjacent unit rows are connected to each other through the second initial connection electrode 56, and the first initial connection electrodes 33 and the second initial connection electrodes 56 connected to each other in the Nth unit column and the N+3th unit column form the first initial connection line, realizing the connection between the first initial signal line 41 extending along the first direction X and the first initial connection line extending along the second direction Y, so that the first initial signal line 41 and the first initial connection line form a mesh structure for transmitting the first initial signal in the display area, which can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the second initial signal line 42 is also connected to the second connection block 33-2 through the sixteenth via hole V16. Since the second connection block 33-2 is connected to the first initial connection electrode 33, the first initial connection electrodes 33 of adjacent unit rows are connected to each other through the second initial connection electrode 56, and the first initial connection electrode 33 and the second initial connection electrode 56 connected to each other in the N+1th unit column form a second initial connection line, which realizes the connection between the second initial signal line 42 extending along the first direction X and the second initial connection line extending along the second direction Y, so that the second initial signal line 42 and the second initial connection line form a meshed mesh structure for transmitting the second initial signal in the display area, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • the shape of the third initial signal line 43 may be a straight line extending along the first direction X.
  • the third initial signal line 43 is in the shape of a zigzag line or a folded line, and can be arranged between the second scanning signal line 22 and the second initial signal line 42.
  • the third initial signal line 43 is connected to the first area of the eighth active layer through the ninth via hole V9, so that the third initial signal line 43 is connected to the first electrode of the eighth transistor T8, and the third initial signal line 43 can write the transmitted third initial signal into the first electrode of the eighth transistor T8.
  • the third initial signal line 43 is also connected to the third connection block 33-3 through the seventeenth via hole V17. Since the third connection block 33-3 is connected to the first initial connection electrode 33, the first initial connection electrodes 33 of adjacent unit rows are connected to each other through the second initial connection electrode 56, and the first initial connection electrode 33 and the second initial connection electrode 56 connected to each other in the N+2th unit column form a third initial connection line, which realizes the connection between the third initial signal line 43 extending along the first direction X and the third initial connection line extending along the second direction Y, so that the third initial signal line 43 and the third initial connection line form a mesh structure for transmitting the third initial signal in the display area, which can not only effectively reduce the resistance of the third initial signal line and reduce the voltage drop of the third initial signal, but also effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.
  • 14C and 14D are schematic diagrams of the initial signal lines of the mesh structure in FIG14A.
  • the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can be arranged in each unit row
  • the first initial connection line 44 can be arranged in the Nth unit column and the N+3th unit column
  • the second initial connection line 45 can be arranged in the N+1th unit column
  • the third initial connection line 46 can be arranged in the N+2th unit column.
  • the initial connection lines in each unit column are composed of the first initial connection electrode 33 and the second initial connection electrode 56 connected to each other.
  • the first initial connection electrode 33 and the second initial connection electrode 56 are arranged in different conductive layers and are connected to each other through vias.
  • the first initial connection line 44 located in the Nth unit column and the N+3th unit column is connected to the first initial signal line 41 in multiple circuit units through the fifteenth via V15 in multiple circuit units, forming a mesh structure for transmitting the first initial signal in the display area.
  • the second initial connection line 45 in the N+1th unit column is connected to the second initial signal line 42 in multiple circuit units through the sixteenth via hole V16 in multiple circuit units, forming a mesh structure for transmitting the second initial signal in the display area.
  • the third initial connection line 46 located in the N+2th unit column is connected to the third initial signal line 43 in multiple circuit units through the seventeenth via hole V17 in multiple circuit units, forming a mesh structure for transmitting the third initial signal in the display area.
  • Forming a first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are disposed on the first planar layer, as shown in FIG. 15 .
  • the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the fourth connecting electrode 54, and the twenty-first via hole V21 is configured to connect the subsequently formed eleventh connecting electrode to the fourth connecting electrode 54 through the via hole.
  • two circuit units adjacent to each other in a portion of the first direction X may share the same 21st via hole V21.
  • two circuit units in the N-1th unit column and the Nth unit column may share the same 21st via hole V21.
  • two circuit units in the N+1th unit column and the N+2th unit column may share the same 21st via hole V21.
  • two circuit units in the N+3th unit column and the N+4th unit column may share the same 21st via hole V21.
  • the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect the subsequently formed twelfth connecting electrode to the third connecting electrode 53 through the via hole.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer in the twenty-third via hole V23 is etched away to expose the surface of the fifth connecting electrode 55, and the twenty-third via hole V23 is configured to connect the subsequently formed thirteenth connecting electrode to the fifth connecting electrode 55 through the via hole.
  • forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the first flat layer, as shown in FIGS. 16A and 16B, where FIG. 16B is a plan view of the fifth conductive layer in FIG. 16A.
  • the fifth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • the fifth conductive layer of each circuit unit includes at least an eleventh connection electrode 61 , a twelfth connection electrode 62 , and a thirteenth connection electrode 63 .
  • the eleventh connection electrodes 61 of two circuit units adjacent to each other in the first direction X may be an integrated structure connected to each other.
  • the eleventh connection electrodes 61 of two circuit units in the N-1th unit column and the Nth unit column may be an integrated structure connected to each other.
  • the eleventh connection electrodes 61 of two circuit units in the N+1th unit column and the N+2th unit column may be an integrated structure connected to each other.
  • the eleventh connection electrodes 61 of two circuit units in the N+3th unit column and the N+4th unit column may be an integrated structure connected to each other.
  • the twelfth connection electrode 62 may be in a block shape (eg, rectangular), is connected to the third connection electrode 53 through a 22nd via hole V22, and is configured to be connected to a subsequently formed data signal line.
  • the thirteenth connection electrode 63 may be in a block shape (eg, rectangular), connected to the fifth connection electrode 55 through the twenty-third via hole V23, and configured to be connected to a subsequently formed anode connection electrode.
  • Forming a second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fifth conductive layer pattern, wherein a plurality of vias are disposed on the second planar layer, as shown in FIG. 17 .
  • the plurality of vias in each circuit unit includes at least a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-third via V34, a thirty-third via V35, a thirty-third via V36, a thirty-third via V37, a thirty-third via V38, a thirty-third via V39, a thirty-third via V40, a thirty-third via V41, a thirty-third via V42, a thirty The thirty-second via hole V32 and the thirty-third via hole V33.
  • the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the twelfth connecting electrode 62 on the substrate, the second flat layer in the thirty-second via hole V32 is etched away to expose the surface of the twelfth connecting electrode 62, and the thirty-second via hole V32 is configured to connect a subsequently formed data signal line to the twelfth connecting electrode 62 through the via hole.
  • the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the thirteenth connecting electrode 63 on the substrate, the second flat layer in the thirty-third via hole V33 is etched away to expose the surface of the thirteenth connecting electrode 63, and the thirty-third via hole V33 is configured to connect a subsequently formed anode connecting electrode to the thirteenth connecting electrode 63 through the via hole.
  • Forming a sixth conductive layer pattern may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a sixth conductive layer disposed on the second flat layer, as shown in FIGS. 18A and 18B , where FIG. 18B is a plan view of the sixth conductive layer in FIG. 18A .
  • the sixth conductive layer may be referred to as a third source-drain metal (SD3) layer.
  • the fifth conductive layer of each circuit unit includes at least a first power line 71 , a data signal line 72 , and an anode connection electrode 73 .
  • the shape of the first power line 71 may be a straight line or a folded line with the main part extending along the second direction Y, and the first power line 71 is connected to the eleventh connection electrode 61 through the thirty-first via hole V31. Since the eleventh connection electrode 61 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is respectively connected to the first electrode of the fifth transistor T5 and the second electrode plate 82 of the storage capacitor, the first power line 71 writes the first power signal into the fifth transistor T5 and the second electrode plate 82 of the storage capacitor.
  • the first power line 71 may be a zigzag line of unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.
  • the first power lines 71 of two circuit units adjacent to each other in the first direction X may be interconnected as an integrated structure.
  • the first power lines 71 of two circuit units in the N-1th unit column and the Nth unit column may be interconnected as an integrated structure.
  • the first power lines 71 of two circuit units in the N+1th unit column and the N+2th unit column may be interconnected as an integrated structure.
  • the first power lines 71 of two circuit units in the N+3th unit column and the N+4th unit column may be interconnected as an integrated structure.
  • the positive projection of the first power line 71 on the substrate at least partially overlaps with the positive projection of the first connecting electrode 51 on the substrate.
  • the first power line 71 with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby avoiding the influence of data voltage jumps and other signals on the potential of the first node N1, and improving the driving performance of the pixel driving circuit.
  • the orthographic projection of the first power line 71 on the substrate includes the orthographic projection of the first connection electrode 51 on the substrate, that is, the first power line 71 completely covers the first connection electrode 51 .
  • the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate.
  • the first power line 71 can block the light emitted by the light-emitting device and the reflected light of the film layer from irradiating the oxide second transistor, which can prevent the characteristics of the oxide second transistor from drifting due to light, thereby improving the electrical characteristics of the oxide second transistor.
  • the orthographic projection of the first power line 71 on the substrate does not overlap with the orthographic projection of the second connection electrode 52 on the substrate, which can effectively reduce the parasitic capacitance of the second node N2.
  • a shielding electrode 74 is provided on the first power line 71.
  • the shape of the shielding electrode 74 can be a strip shape extending along the second direction Y.
  • the first end of the shielding electrode 74 is connected to the first power line 71, and the second end of the shielding electrode 74 extends toward the direction of the anode connection electrode 73 in the circuit unit.
  • the shielding electrode 74 may be disposed in the middle of the first power line 71 of the integral structure, and the first power line 71 of the integral structure may be substantially mirror-symmetrical with respect to the shielding electrode 74 .
  • an orthographic projection of the shielding electrode 74 on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate, so as to effectively reduce the parasitic capacitance of the second node N2 .
  • a portion of the shielding electrode 74 may be disposed between portions of adjacent second connection electrodes 52, and the shielding electrode 74 having a constant potential may effectively prevent the mutual influence of the second nodes N2 in adjacent circuit units, thereby improving the driving performance of the pixel driving circuit.
  • the shielding electrode 74 may be disposed between the second connection electrode 52 of the circuit unit in the Nth unit column and the second connection electrode 52 of the circuit unit in the N+1th unit column.
  • the shielding electrode 74 may be disposed between the second connection electrode 52 of the circuit unit in the N+2th unit column and the second connection electrode 52 of the circuit unit in the N+3th unit column.
  • the shield electrode 74 is also configured to improve the planarity of the anode.
  • a first power block 71-1 and a second power block 71-2 may also be provided on the first power line 71.
  • the first power block 71-1 and the second power block 71-2 may be block-shaped (e.g., trapezoidal) and may be provided on one side of the first power line 71 close to the shielding electrode 74 and respectively correspond to the two ends of the shielding electrode 74.
  • the first power block 71-1 and the second power block 71-2 are configured to improve the flatness of the anode.
  • the first power line 71 , the first power block 71 - 1 , the second power block 71 - 2 , and the shielding electrode 74 may be an integrated structure connected to each other.
  • the shape of the data signal line 72 may be a straight line or a folded line with a main portion extending along the second direction Y, and the data signal line 72 is connected to the twelfth connection electrode 62 through the thirty-second via hole V32. Since the twelfth connection electrode 62 is connected to the third connection electrode 53, and the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 72 is connected to the first electrode of the fourth transistor T4, and the data signal line 72 can write the data signal to the first electrode of the fourth transistor T4.
  • the shape of the anode connection electrode 73 may be a block shape (such as a rectangle), and the anode connection electrode 73 is connected to the thirteenth connection electrode 63 through the thirty-third via hole V33, and the anode connection electrode 73 is configured to be connected to the subsequently formed anode. Since the anode connection electrode 73 is connected to the fifth connection electrode 55, and the fifth connection electrode 55 is connected to the second region of the sixth active layer and the second region of the seventh active layer through the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.
  • forming the third planar layer pattern may include: coating a third planar film on the substrate on which the aforementioned pattern is formed, patterning the third planar film using a patterning process to form a third planar layer covering the sixth conductive layer pattern, wherein a plurality of vias are disposed on the third planar layer, as shown in FIG. 19 .
  • the vias in each circuit unit include at least a forty-first via V41.
  • the orthographic projection of the forty-first via hole V41 on the substrate is within the range of the orthographic projection of the anode connecting electrode 73 on the substrate, the third flat layer in the forty-first via hole V41 is removed to expose the surface of the anode connecting electrode 73, and the forty-first via hole V41 is configured to connect a subsequently formed anode to the anode connecting electrode 73 through the via hole.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emitting control line, a first initial signal line, a second initial signal line, a third initial signal line, a data signal line, and a first power supply line connected to the pixel drive circuit.
  • the driving circuit layer may include a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first flat layer, a fifth conductive layer, a second flat layer, a sixth conductive layer and a third flat layer sequentially arranged on the substrate.
  • the first semiconductor layer may include at least the active layer of the third transistor to the eighth transistor, the first conductive layer may include at least the second scanning signal line, the fourth scanning signal line and the first plate of the storage capacitor, the second conductive layer may include at least the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the first transistor and the second transistor, the third conductive layer may include at least the first scanning signal line and the third scanning signal line, the fourth conductive layer may include at least a plurality of connection electrodes, the fifth conductive layer may include at least a plurality of connection electrodes, and the sixth conductive layer may include at least a data signal line, a first power line and an anode connection electrode.
  • the substrate may be a flexible substrate, or may be a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).
  • the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.
  • the first insulating layer may be called a buffer layer
  • the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be called a gate insulating (GI) layer
  • the sixth insulating layer may be called an interlayer insulating (ILD) layer
  • the seventh insulating layer may be called a passivation (PVX) layer.
  • the first planar layer, the second planar layer and the third planar layer may be made of organic materials, such as resin, etc.
  • the pixel driving circuits in two adjacent circuit units in a unit row may be substantially mirror-symmetrical with respect to the column center line.
  • the pixel driving circuit in the Nth column and the pixel driving circuit in the N+1th column may be mirror-symmetrical with respect to the column center line.
  • the pixel driving circuit in the N+1th column and the pixel driving circuit in the N+2th column may be mirror-symmetrical with respect to the column center line.
  • a light emitting structure layer may be prepared on the driving circuit layer, and the preparation process of the light emitting structure layer may include the following operations.
  • Forming an anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the third flat layer, wherein the anode conductive layer may include at least a plurality of anode patterns, as shown in FIGS. 20A and 20B , wherein FIG. 20B is a plan view schematic diagram of the anode conductive layer in FIG. 20A .
  • the plurality of anode patterns may include a first anode 90A for a red light emitting device, a second anode 90B for a blue light emitting device, a third anode 90C for a first green light emitting device, and a fourth anode 90D for a second green light emitting device.
  • the first anode 90A may be located at a red sub-pixel emitting red light
  • the second anode 90B may be located at a blue sub-pixel emitting blue light
  • the third anode 90C may be located at a first green sub-pixel emitting green light
  • the fourth anode 90D may be located at a second green sub-pixel emitting green light.
  • first anode 90A and the second anode 90B may be sequentially disposed along the first direction X
  • the third anode 90C and the fourth anode 90D may be sequentially disposed along the first direction X
  • the third anode 90C and the fourth anode 90D may be sequentially disposed along the first direction X
  • 90D may be respectively disposed on one side of the first anode 90A and the second anode 90B in the second direction Y.
  • first anode 90A and the second anode 90B may be disposed sequentially along the second direction Y
  • the third anode 90C and the fourth anode 90D may be disposed sequentially along the second direction Y
  • third anode 90C and the fourth anode 90D may be disposed on one side of the first anode 90A and the second anode 90B in the first direction X.
  • the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D can be respectively connected to the anode connecting electrode 73 of the corresponding circuit unit through the forty-first via hole V41, and the anode shape and area of the four sub-pixels in a pixel unit can be the same, or can be different.
  • At least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include an anode main body and an anode connecting portion that are connected to each other.
  • the shape of the anode main body may be circular or elliptical, and the shape of the anode connecting portion may be a bar.
  • the anode connecting portion is connected to the anode connecting electrode 73 through the forty-first via V41, thereby enabling connection between the anode and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the anode body portion and the anode connecting portion of at least one anode may be an integral structure connected to each other.
  • the anode body portion of at least one anode may have a first anode centerline OX and a second anode centerline OY
  • the first anode centerline OX may be a straight line bisecting the anode body portion of the anode in the second direction Y and extending along the first direction X
  • the second anode centerline OY may be a straight line bisecting the anode body portion of the anode in the first direction X and extending along the second direction Y.
  • the third anode 90C and the fourth anode 90D may each have a first anode centerline OX and a second anode centerline OY.
  • the orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projection of two first power lines 71 in two adjacent circuit units in the first direction X on the substrate, and the two first power lines 71 can be mirror-symmetrical relative to the second anode center line OY of the anode.
  • the orthographic projection of the anode body of at least one anode on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 of at least one first power line 71 on the substrate, for example, the orthographic projection of the anode body of the third anode 90C on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 of one first power line 71 on the substrate.
  • the orthographic projection of the anode body of the fourth anode 90D on the substrate at least partially overlaps with the orthographic projection of the first power block 71-1 and the second power block 71-2 of another first power line 71 on the substrate.
  • the position and shape of the first power block 71-1 and the second power block 71-2 of at least one first power line 71 may be substantially mirror-symmetrical with respect to the first anode center line OX of at least one anode.
  • the position and shape of the first power block 71-1 and the second power block 71-2 of one first power line 71 are substantially mirror-symmetrical with respect to the first anode center line OX of the third anode 90C.
  • the position and shape of the first power block 71-1 and the second power block 71-2 of another first power line 71 are substantially mirror-symmetrical with respect to the first anode center line OX of the fourth anode 90D.
  • the orthographic projection of the first power block 71-1 on the substrate and the orthographic projection of the anode main body on the substrate have a first overlapping area
  • the orthographic projection of the second power block 71-2 on the substrate and the orthographic projection of the anode main body on the substrate have a second overlapping area
  • the position and shape of the first overlapping area and the position and shape of the second overlapping area can be substantially mirror-symmetrical with respect to the first anode center line OX of the anode.
  • the position and shape of the first overlapping area and the position and shape of the second overlapping area can be substantially mirror-symmetrical with respect to the first anode center line OX of the third anode 90C.
  • the position and shape of the first overlapping area and the position and shape of the second overlapping area can be substantially mirror-symmetrical with respect to the first anode center line OX of the fourth anode 90D.
  • the orthographic projection of the first power block 71-1 in one first power line 71 on the substrate and the orthographic projection of the anode main body on the substrate have a first overlapping area
  • the orthographic projection of the first power block 71-1 in the other first power line 71 on the substrate and the anode main body on the substrate have a first overlapping area
  • the orthographic projection of the pole body portion on the substrate has a third overlapping region, and the position and shape of the first overlapping region and the position and shape of the third overlapping region may be substantially mirror-symmetrical with respect to the second anode center line OY of the anode.
  • the orthographic projection of the second power block 71-2 in one first power line 71 on the substrate and the orthographic projection of the anode main body on the substrate have a second overlapping area
  • the orthographic projection of the second power block 71-2 in the other first power line 71 on the substrate and the orthographic projection of the anode main body on the substrate have a fourth overlapping area
  • the position and shape of the second overlapping area and the position and shape of the fourth overlapping area can be basically mirror-symmetrical relative to the second anode center line OY of the anode.
  • the orthographic projection of at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the anode body of at least one anode on the substrate.
  • the orthographic projection of at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the anode body of the third anode 90C on the substrate.
  • the orthographic projection of at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the anode body of the fourth anode 90D on the substrate.
  • the orthographic projection of at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the second anode center line OY of at least one anode on the substrate.
  • the orthographic projection of at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the second anode center line OY of the third anode 90C on the substrate.
  • the orthographic projection of at least one shield electrode 74 on the substrate at least partially overlaps with the orthographic projection of the second anode center line OY of the fourth anode 90D on the substrate.
  • an orthographic projection of the anode connection portion of the at least one anode on the substrate does not overlap with an orthographic projection of the second connection electrode 52 on the substrate.
  • the anode connection portion of at least one anode may include a first connection sub-portion 90 - 1 and a second connection sub-portion 90 - 2 configured to avoid overlapping with the second connection electrode 52 .
  • the anode connecting portion of the first anode 90A and the second anode 90B may include at least a first connecting sub-portion 90-1 and a second connecting sub-portion 90-2, wherein the first end of the first connecting sub-portion 90-1 is connected to the anode main body, the second end of the first connecting sub-portion 90-1 extends along the first direction X in a direction away from the anode main body, and then is connected to the first end of the second connecting sub-portion 90-2, and the second end of the second connecting sub-portion 90-2 extends along the second direction Y in a direction away from the first connecting sub-portion 90-1, so that the anode connecting portions of the first anode 90A and the second anode 90B avoid the area where the second connecting electrode 52 is located.
  • the orthographic projection of the first connecting sub-portion 90-1 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, and the orthographic projection of the second connecting sub-portion 90-2 on the substrate does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate, so as to effectively reduce the parasitic capacitance of the second node N2.
  • the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the subsequent preparation process may include: first forming a pixel definition layer pattern, then forming an organic light-emitting layer by evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer
  • the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.
  • a display substrate has a problem of instantaneous high current when the light-emitting signal line provides a turn-on signal, which affects the display effect.
  • the instantaneous high current is caused by the large parasitic capacitance of the second node N2. Since the third initial signal line in the pixel driving circuit is connected to the second node N2 through the eighth transistor T8, when the parasitic capacitance of the second node N2 is large, it is equivalent to the second node N2 having a large capacitor storing the bias voltage (on bias) of the third initial signal line.
  • the sixth transistor T6 is turned on
  • the charge in the parasitic capacitance of the second node N2 is released first, and then an instantaneous high current occurs.
  • An exemplary embodiment of the present disclosure provides a display substrate, which effectively reduces the parasitic capacitance of the second node N2 through layout adjustment and structural optimization, so that the parasitic capacitance of the second node N2 is reduced by 9.35f, effectively avoiding the problem of instantaneous large current, and greatly reducing the transient current of the sixth transistor T6 being turned on, thereby improving the display quality and display effect.
  • the present disclosure can reduce the parasitic capacitance of the second node N2 and the influence on the data signal writing process by setting the second connection electrode and the fourth scan signal line not to overlap.
  • the present disclosure sets the first scan signal line and the first shielding line to have unequal widths, and the second connecting electrode overlaps with the first scan signal line and the first shielding line of smaller width, thereby effectively reducing the parasitic capacitance between the second node N2 and the first scan signal line and the first shielding line.
  • the present disclosure can minimize the parasitic capacitance of the second node N2 by arranging that the first power line does not overlap with the second connection electrode, the shielding electrode does not overlap with the second connection electrode, and the anode connection portion does not overlap with the second connection electrode.
  • the present disclosure arranges a shielding electrode between adjacent second connection electrodes.
  • the shielding electrode with a constant potential can effectively prevent the mutual influence of the second nodes N2 in adjacent circuit units, thereby improving the driving performance of the pixel driving circuit.
  • the present disclosure increases the parasitic capacitance between the first scanning signal line and the first node N1 by setting the first connecting electrode to overlap with the first scanning signal line, and uses the falling edge of the first scanning signal line to lower the potential of the first node N1, thereby increasing the current and effectively improving the display brightness.
  • the present disclosure sets the first power line to overlap with the first connection electrode, which can effectively prevent data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit.
  • the present disclosure sets the first power line to overlap with the active layer of the second transistor, which can prevent the characteristics of the oxide second transistor from drifting due to light, thereby improving the electrical characteristics of the oxide second transistor.
  • the present invention arranges the shielding electrode to overlap with the second anode center line of the anode, and arranges the first power line, the first power block and the second power block to be mirror-symmetrical relative to the second anode center line, and the first power block and the second power block 71 to be mirror-symmetrical relative to the first anode center line.
  • the present invention discloses a first initial signal line extending in a first direction of a main body and a first initial connection line extending in a second direction of the main body, a second initial signal line extending in a first direction of the main body and a second initial connection line extending in a second direction of the main body, and a third initial signal line extending in a first direction of the main body and a second initial connection line extending in a third direction, so that the first initial signal line, the second initial signal line and the third initial signal line respectively form a mesh connection structure, which not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively improves the uniformity of the initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.
  • the preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.
  • the structure and preparation process shown above in the present disclosure are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.
  • the display substrate of the present disclosure may be applied to other display devices having a pixel driving circuit, such as a quantum dot display, etc., which is not limited in the present disclosure.
  • the present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment.
  • the preparation method may include:
  • a driving circuit layer is formed on the substrate, wherein the driving circuit layer includes a plurality of circuit units, at least one of which includes at least a pixel driving circuit and a first power line, wherein the first power line is configured to provide a first power line signal to the pixel driving circuit; at least one of the circuit units also includes a shielding electrode, wherein the shielding electrode is connected to the first power line;
  • the present disclosure also provides a display device, which includes the aforementioned display substrate.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板及其制备方法、显示装置。显示基板包括设置在基底（101）上的驱动电路层（102）和发光结构层（103）；驱动电路层（101）包括多个电路单元，电路单元至少包括像素驱动电路；发光结构层（103）包括多个发光单元，发光单元至少包括阳极（90），阳极（90）包括阳极主体部和阳极连接部，阳极连接部的一端与阳极主体部连接，阳极连接部的另一端与像素驱动电路连接；至少一个电路单元还包括屏蔽电极（94），屏蔽电极（94）在基底上的正投影与至少一个阳极（90）的第二阳极中心线（OY）在基底上的正投影至少部分交叠，第二阳极中心线（OY）是在第一方向上平分阳极主体部且沿着第二方向延伸的直线。

Description

显示基板及其制备方法、显示装置 技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层；所述驱动电路层包括多个电路单元，至少一个电路单元至少包括像素驱动电路和第一电源线，所述第一电源线被配置为向所述像素驱动电路提供第一电源线号；所述发光结构层包括多个发光单元，至少一个发光单元至少包括阳极，所述阳极包括阳极主体部和阳极连接部，所述阳极连接部的一端与所述阳极主体部连接，所述阳极连接部的另一端与所述像素驱动电路连接；至少一个电路单元还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接，至少一个屏蔽电极在所述基底上的正投影与至少一个阳极的第二阳极中心线在所述基底上的正投影至少部分交叠，所述第二阳极中心线是在第一方向上平分所述阳极主体部且沿着第二方向延伸的直线，所述第一方向和所述第二方向交叉。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，包括：
在基底上形成驱动电路层，所述驱动电路层包括多个电路单元，至少一个电路单元至少包括像素驱动电路和第一电源线，所述第一电源线被配置为向所述像素驱动电路提供第一电源线号；至少一个电路单元还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接；
在所述驱动电路层上形成发光结构层，所述发光结构层包括多个发光单元，至少一个发光单元至少包括阳极，所述阳极包括阳极主体部和阳极连接部，所述阳极连接部的一端与所述阳极主体部连接，所述阳极连接部的另一端与所述像素驱动电路连接；至少一个屏蔽电极在所述基底上的正投影与至少一个阳极的第二阳极中心线在所述基底上的正投影至少部分交叠，所述第二阳极中心线是在第一方向上平分所述阳极主体部且沿着第二方向延伸的直线，所述第一方向和所述第二方向交叉。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种显示基板的剖面结构示意图；
图4为本公开示例性实施例一种像素驱动电路的等效电路示意图；
图5为图4所示像素驱动电路的一种驱动时序图；
图6为本公开示例性实施例一种显示基板的平面结构示意图；
图7为本公开示例性实施例另一种显示基板的平面结构示意图；
图8为本公开实施例形成第一半导体层图案后的示意图；
图9A和图9B为本公开实施例形成第一导电层图案后的示意图；
图10A和图10B为本公开实施例形成第二导电层图案后的示意图；
图11A和图11B为本公开实施例形成第二半导体层图案后的示意图；
图12A和图12B为本公开实施例形成第三导电层图案后的示意图；
图13为本公开实施例形成第六绝缘层图案后的示意图；
图14A和图14B为本公开实施例形成第四导电层图案后的示意图；
图14C和图14D为图14A中网状结构的初始信号线的示意图；
图15为本公开实施例形成第一平坦层图案后的示意图；
图16A和图16B为本公开实施例形成第五导电层图案后的示意图；
图17为本公开实施例形成第二平坦层图案后的示意图；
图18A和图18B为本公开实施例形成第六导电层图案后的示意图；
图19为本公开实施例形成第三平坦层图案后的示意图；
图20A和图20B为本公开实施例形成阳极导电层图案后的示意图。
附图标记说明:
11—第一有源层；           12—第二有源层；           13—第三有源层；
14—第四有源层；           15—第五有源层；           16—第六有源层；
17—第七有源层；           18—第八有源层；           21—第一扫描信号线；
22—第二扫描信号线；       23—第三扫描信号线；       24—第四扫描信号线；
25—发光控制线；           31—第一遮挡线；           32—第二遮挡线；
33—第一初始连接电极；     41—第一初始信号线；       42—第二初始信号线；
43—第三初始信号线；       44—第一初始连接线；       45—第二初始连接线；
46—第三初始连接线；       51—第一连接电极；         52—第二连接电极；
53—第三连接电极；         54—第四连接电极；         55—第五连接电极；
56—第二初始连接电极；     61—第十一连接电极         62—第十二连接电极；
63—第十三连接电极         71—第一电源线；           72—数据连接线；
73—阳极连接电极；         74—遮挡电极；             81—第一极板；
82—第二极板；             83—开口；                 84—第一极板连接线；
85—第二极板连接线；       90—阳极；                 101—基底；
102—驱动电路层；          103—发光结构层；          104—封装结构层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征 可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij 可以包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，发光单元可以包括发光器件，发光器件与电路单元的像素驱动电路连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。在示例性实施方式中，像素阵列可以设置在显示基板上。
图2为一种显示基板的平面结构示意图。如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光单元输出相应的电流。发光单元可以包括发光器件，发光器件与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2和第四子像素P4可以是出射绿色光线的绿色子像素(G)，第三子像素P3可以是出射蓝色光线的蓝色子像素(B)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
在一些可能的实施方式中，像素单元可以包括三个子像素，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射绿色光线的绿色子像素(G)，第三子像素P3可以是出射蓝色光线的蓝色子像素(B)，三个子像素可以采用水平并列、竖直并列或品字等方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了显示区域中四个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，每个电路单元可以至少包括由多个晶体管和存储电容构成的像素驱动电路。发光结构层103可以包括多个发光单元，每个发光单元可以包括发 光器件，发光器件可以至少包括阳极、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
本公开示例性实施例提供了一种显示基板。在示例性实施方式中，显示基板包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层；所述驱动电路层包括多个电路单元，至少一个电路单元至少包括像素驱动电路和第一电源线，所述第一电源线被配置为向所述像素驱动电路提供第一电源线号；所述发光结构层包括多个发光单元，至少一个发光单元至少包括阳极，所述阳极包括阳极主体部和阳极连接部，所述阳极连接部的一端与所述阳极主体部连接，所述阳极连接部的另一端与所述像素驱动电路连接；至少一个电路单元还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接，至少一个屏蔽电极在所述基底上的正投影与至少一个阳极的第二阳极中心线在所述基底上的正投影至少部分交叠，所述第二阳极中心线是在第一方向上平分所述阳极主体部且沿着第二方向延伸的直线，所述第一方向和所述第二方向交叉。
在示例性实施方式中，所述像素驱动电路至少包括作为补偿晶体管的第二晶体管和作为驱动晶体管的第三晶体管，所述第二晶体管的栅电极与第一扫描信号线连接，所述第二晶体管的第一极通过第二节点电极与所述第三晶体管的第二极连接，所述第二晶体管的第二极通过第一节点电极与所述第三晶体管的栅电极连接；所述阳极连接部在所述基底上的正投影与所述第二节点电极在所述基底上的正投影没有交叠。
在示例性实施方式中，所述第一电源线在所述基底上的正投影与所述第二节点电极在所述基底上的正投影没有交叠。
在示例性实施方式中，所述屏蔽电极设置在所述第一方向相邻两个电路单元的所述第二节点电极之间。
在示例性实施方式中，所述屏蔽电极在所述基底上的正投影与所述第二节点电极在所述基底上的正投影没有交叠。
在示例性实施方式中，所述第一节点电极在所述基底上的正投影与所述第一扫描信号线在所述基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个电路单元还包括沿着所述第一方向延伸的第一初始信号线和沿着所述第二方向延伸的第一初始连接线，所述第一初始信号线被配置为向所述像素驱动电路提供第一初始信号，所述第一初始信号连接线与所述第一初始信号线连接，形成传输所述第一初始信号的网状连通结构，和/或，至少一个电路单元还包括沿着所述第一方向延伸的第二初始信号线和沿着所述第二方向延伸的第二初始连接线，所述第二初始信号线被配置为向所述像素驱动电路提供第二初始信号，所述第二初始信号连接线与所述第二初始信号线连接，形成传输所述第二初始信号的网状连通结构，和/或，至少一个电路单元还包括沿着所述第一方向延伸的第三初始信号线和沿着所述第二方向延伸的第三初始连接线，所述第三初始信号线被配置为向所述像素驱动电路提供第三初始信号，所述第三初始信号连接线与所述第三初始信号线连接，形成传输所述第三初始信号的网状连通结构。
在示例性实施方式中，所述第一初始连接线、所述第二初始连接线和所述第三初始连接线中的至少一个包括相互连接的第一初始连接电极和第二初始连接电极；在垂直于所述基底的方向上，所述驱动电路层包括多个导电层，所述第一初始连接电极和所述第二初始连接电极设置在不同的导电层中。
下面通过一些示例对本公开示例性实施例的显示基板进行举例说明。
图4为本公开示例性实施例一种像素驱动电路的等效电路示意图。如图4所示，像素驱动电路可以包括8个晶体管(第一晶体管T1至第八晶体管T8)和1个存储电容C，像素驱动电路分别与10个信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT1、第三初始信号线INIT3、数据信号线DATA和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2、第三节点N3和第四节点N4。其中，第一节点N1分别与第二晶体管T2的第二极、第三晶体管T3的栅电极和存储电容C的第一端连接，第二节点N2分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的第二极、第六晶体管T6的第一极和第八晶体管T8的第二极连接，第三节点N3分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第四节点N4分别与第六晶体管T6的第二极和第七晶体管T7的第二极连接。
在示例性实施方式中，存储电容C的第一端与第一节点N1连接，存储电容C的第二端与第一电源线VDD连接。
在示例性实施方式中，第一晶体管T1可以称为第一初始化晶体管，第一晶体管T1的栅电极与第三扫描信号线S3连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管T1的第二极与第二节点N2连接。
在示例性实施方式中，第二晶体管T2可以称为补偿晶体管，第二晶体管T2的栅电极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第一节点N1连接。
在示例性实施方式中，第三晶体管T3可以称为驱动晶体管，第三晶体管T3的栅电极与第一节点N1连接，第三晶体管T3的第一极与第三节点N3连接，第三晶体管T3的第二极与第二节点N2连接。
在示例性实施方式中，第四晶体管T4可以称为数据写入晶体管，第四晶体管T4的栅电极与第四扫描信号线S4连接，第四晶体管T4的第一极与数据信号线DATA连接，第四晶体管T4的第二极与第三节点N3连接。
在示例性实施方式中，第五晶体管T5可以称为第一发光控制晶体管，第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第三节点N3连接。
在示例性实施方式中，第六晶体管T6可以称为第二发光控制晶体管，第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第二节点N2连接，第六晶体管T6的第二极与第四节点N4连接。
在示例性实施方式中，第七晶体管T7可以称为第二初始化晶体管，第七晶体管T7的栅电极与第二扫描信号线S2连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与第四节点N4连接。
在示例性实施方式中，第八晶体管T8可以称为第三初始化晶体管，第八晶体管T8的栅电极与第二扫描信号线S2连接，第八晶体管T8的第一极与第三初始信号线INIT3连接，第八晶体管T8的第二极与第二节点N2连接。
在示例性实施方式中，发光器件EL的第一极与第四节点N4连接，发光器件EL的第二极与第二电源线VSS连接。发光器件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极、量子点发光层和第二极。
在示例性实施方式中，第一电源线VDD的信号为持续提供的高电平信号，第二电源 线VSS的信号为持续提供的低电平信号。
在一些可能示例性的实施方式中，像素驱动电路中的第一晶体管T1至第八晶体管T8可以是P型晶体管，或者可以是N型晶体管。在另一些可能示例性的实施方式中，像素驱动电路中的第一晶体管T1至第八晶体管T8可以包括P型晶体管和N型晶体管。
在示例性实施方式中，像素驱动电路中的第一晶体管T1至第八晶体管T8可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和氧化物晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
如图4所示，本示例性实施例中，像素驱动电路中的第一晶体管T1和第二晶体管T2可以采用氧化物晶体管(N型晶体管)，第三晶体管T3至第八晶体管T8可以采用低温多晶硅晶体管(P型晶体管)。
图5为图4所示像素驱动电路的一种驱动时序图。如图5所示，在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，可以称为第二节点N2和第四节点N4复位阶段。第一扫描信号线S1、第二扫描信号线S2和第三扫描信号线S3的信号为低电平信号，第四扫描信号线S4和发光信号线EM的信号为高电平信号，使第七晶体管T7和第八晶体管T8导通，其它开关晶体管断开。
第七晶体管T7导通使得第二初始信号线INIT2的信号提供至第四节点N4，对发光器件EL的第一极进行初始化(复位)，清除发光器件EL的第一极中原有电荷，使第四节点N4的电位为Vinit2。第八晶体管T8导通使得第三初始信号线INIT3的信号提供至第二节点N2，对第二节点N2进行初始化(复位)，使第二节点N2的电位为Vinit3。
第二阶段A2，可以称为第一节点N1和第二晶体管T2复位阶段。第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4和发光信号线EM的信号为高电平信号，使第一晶体管T1导通和第二晶体管T2导通，其它开关晶体管断开。
第一晶体管T1和第二晶体管T2导通使得第一初始信号线INIT1的信号分别提供至第一节点N1和第二节点N2，对第一节点N1和第二节点N2进行初始化(复位)，清除第一节点N1中原有电荷，第一节点N1和第二节点N2的电位为Vinit1。
第三阶段A3，可以称为数据写入阶段。第三扫描信号线S3的信号为低电平信号，第四扫描信号线S4的信号在一小段时间为低电平信号，第一扫描信号线S1、第二扫描信号线S2和发光信号线EM的信号为高电平信号，使第二晶体管T2和第四晶体管T4导通，其它开关晶体管断开。
第二晶体管T2导通使得第一节点N1和第二节点N2导通，由于此阶段第三晶体管T3持续导通，因此第四晶体管T4导通使得数据信号线DATA输出的数据信号经过第三节点N3、导通的第三晶体管T3、第二节点N2、导通的第二晶体管T2提供至第一节点N1，并将数据信号线DATA输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，第一节点N1的电压为Vd-|Vth|，Vd为数据信号线DATA输出的数据电压，Vth为第三晶体管T3的阈值电压。
第四阶段A4，可以称为第二节点N2、第三节点N3和第四节点N4复位阶段。
第一扫描信号线S1和第三扫描信号线S3的信号为低电平信号，第二扫描信号线S2的信号在一小段时间为低电平信号，第四扫描信号线S4和发光信号线EM的信号为高电 平信号，使第七晶体管T7和第八晶体管T8导通，其它开关晶体管断开。
第七晶体管T7导通使得第二初始信号线INIT2的信号提供至第四节点N4，由于此阶段第三晶体管T3持续导通，第八晶体管T8导通使得第三初始信号线INIT3的信号提供至第二节点N2和第三节点N3，分别对第二节点N2、第三节点N3和第四节点N4进行复位，第二节点N2和第三节点N3的电位为Vinit3，第四节点N4的电位为Vinit2。本阶段对第二节点N2、第三节点N3第四节点N4进行复位，可以消改善除相邻像素之间灰度差异引起的迟滞偏差，减小迟滞偏差，还可以对OLED阳极进行周期性的复位，改善低频的闪烁。
第五阶段A5，可以称为发光阶段。第一扫描信号线S1、第三扫描信号线S3和发光信号线EM的信号为低电平信号，第二扫描信号线S2和第四扫描信号线S4的信号为高电平信号，使第五晶体管T5和第六晶体管T6导通，其它开关晶体管断开。
第五晶体管T5和第六晶体管T6导通使第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三节点N3、导通的第三晶体管T3、第二节点N2、导通的第六晶体管T6向发光器件EL的第一极提供驱动电压，驱动发光器件EL发光。
在发光阶段，每个像素驱动电路的第三晶体管T3的驱动电流不受第三晶体管T3的阈值电压的影响，消除了第三晶体管T3的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
图6为本公开示例性实施例一种显示基板的平面结构示意图，示意了多个电路单元(2个单元行4个单元列)的平面结构。在示例性实施方式中，在垂直于显示基板的方向上，本公开示例性实施例显示基板可以包括设置在基底上的驱动电路层以及设置在驱动电路层远离基底一侧的发光结构层。在平行于显示基板的平面上，驱动电路层可以包括多个电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路被配置为向所连接的发光器件输出相应的电流。发光结构层可以包括多个发光单元，至少一个发光单元可以包括发光器件，发光器件与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施例中，本公开中所说的电路单元，是按照像素驱动电路划分的区域。本公开中所说的发光单元，是按照发光器件划分的区域。在示例性实施例中，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
在示例性实施方式中，多个电路单元可以形成多个多个单元行和多个单元列，每个单元行中的多个电路单元沿着第一方向X依次设置，多个单元行沿着第二方向Y依次设置，构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。
如图6所示，至少一个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第四扫描信号线24、发光信号线25、第一初始信号线41、第二初始信号线42、第三初始信号线43、第一电源线71和数据信号线72。在示例性实施方式中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第四扫描信号线24、发光信号线25、第一初始信号线41、第二初始信号线42和第三初始信号线43的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第一电源线71和数据信号线72的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状。在示例性实施方式中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23和第四扫描信号线24被配置为向像素驱动电路提供扫描信号，发光信号线25被配置为向像素驱动电路提供发光控制信号，第一初始信号线41、第二初始信号线42和第三初始信号线43被配置为向像素驱动电路提供初始信号，第一电源线71被配置为向像素驱动电路提供第一电源信号，数据信号线72被配置为向像素驱动电路提供数据 信号。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
在示例性实施方式中，至少一个电路单元中的像素驱动电路可以包括存储电容和多个晶体管，存储电容可以包括叠设的第一极板和第二极板，多个晶体管可以包括作为第一初始化晶体管的第一晶体管T1、作为补偿晶体管的第二晶体管T2、作为驱动晶体管的第三晶体管T3、作为数据写入晶体管的第四晶体管T4、作为第一发光控制晶体管的第五晶体管T5、作为第二发光控制晶体管的第六晶体管T6、作为第二初始化晶体管的第七晶体管T7和作为第三初始化晶体管的第八晶体管T8。其中，第一晶体管T1和第二晶体管T2为氧化物晶体管，第三晶体管T3至第八晶体管T8为低温多晶硅晶体管。
在示例性实施方式中，第一晶体管T1的栅电极与第三扫描信号线23连接，第一晶体管T1的第一极与第一初始信号线41连接，第一晶体管T1的第二极与第二晶体管T2的第一极连接。第二晶体管T2的栅电极与第一扫描信号线21连接，第二晶体管T2的第一极通过作为第二节点电极的第二连接电极52与第三晶体管T3的第二极连接，第二晶体管T2的第二极通过作为第一节点电极的第一连接电极51与第三晶体管T3的栅电极(第一极板)连接。第四晶体管T4的栅电极与第四扫描信号线24连接，第四晶体管T4的第一极与数据信号线72连接，第四晶体管T4的第二极与第三晶体管T3的第一极连接。第五晶体管T5的栅电极与发光信号线25连接，第五晶体管T5的第一极与第一电源线71连接，第五晶体管T5的第二极与第三晶体管T3的第一极连接。第六晶体管T6的栅电极与发光信号线25连接，第六晶体管T6的第一极与第三晶体管T3的第二极连接，第六晶体管T6的第二极与第七晶体管T7的第二极连接。第七晶体管T7的栅电极与第二扫描信号线22连接，第七晶体管T7的第一极与第二初始信号线42连接。第八晶体管T8的栅电极与第二扫描信号线22连接，第八晶体管T8的第一极与第三初始信号线43连接，第八晶体管T8的第二极通过第二连接电极52与第三晶体管T3的第二极连接。
在示例性实施方式中，部分第一方向X相邻的两个电路单元中的第一电源线71可以为相互连接的一体结构。
在示例性实施方式中，第一电源线71在基底上的正投影与第一连接电极51在基底上的正投影至少部分交叠。
在示例性实施方式中，第一电源线71在基底上的正投影与第二晶体管T2的有源层在基底上的正投影至少部分交叠。
在示例性实施方式中，第一连接电极51在基底上的正投影与第一扫描信号线21在基底上的正投影至少部分交叠。
在示例性实施方式中，第一电源线71在基底上的正投影与第二连接电极52在基底上的正投影没有交叠。
在示例性实施方式中，至少一个电路单元还包括屏蔽电极74，屏蔽电极74与第一电源线71连接，且设置在第一方向X相邻两个电路单元的第二连接电极52之间。
在示例性实施方式中，屏蔽电极74在基底上的正投影与第二连接电极52基底上的正投影没有交叠。
在示例性实施方式中，第二连接电极52在基底上的正投影与第四扫描信号线24基底上的正投影没有交叠。
图7为本公开示例性实施例另一种显示基板的平面结构示意图，示意了多个发光单元中阳极的平面结构。在示例性实施方式中，发光结构层可以包括多个发光单元，至少一个 发光单元可以包括发光器件，至少一个发光器件可以包括阳极90，阳极90与对应电路单元的像素驱动电路连接。
如图7所示，至少一个阳极90可以包括阳极主体部和阳极连接部，阳极主体部的形状可以为圆形状或者椭圆形状，阳极连接部的形状可以为条形状，阳极连接部的一端与阳极主体部直接连接，阳极连接部的另一端通过过孔与与像素驱动电路连接。
在示例性实施方式中，至少一个阳极的阳极主体部可以具有第一阳极中心线OX和第二阳极中心线OY，第一阳极中心线OX可以是在第二方向Y上平分该阳极的阳极主体部且沿着第一方向X延伸的直线，第二阳极中心线OY可以是在第一方向X上平分该阳极的阳极主体部且沿着第二方向Y延伸的直线。
在示例性实施方式中，至少一个屏蔽电极74在基底上的正投影与至少一个阳极90的第二阳极中心线OY在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个阳极90的阳极主体部在基底上的正投影与第一方向X上相邻的两个电路单元中的两条第一电源线71在基底上的正投影至少部分交叠，且两条第一电源线71可以相对于第二阳极中心线OY镜像对称。
在示例性实施方式中，至少一个阳极90的阳极连接部在基底上的正投影与第二连接电极52在基底上的正投影没有交叠。
在示例性实施方式中，至少一条第一电源线71上可以设置有第一电源块71-1和第二电源块71-2，至少一个阳极90的阳极主体部在基底上的正投影与第一电源块71-1和第二电源块71-2在基底上的正投影至少部分交叠，第一电源块71-1和第二电源块71-2可以相对于第一阳极中心线OX镜像对称。
在示例性实施方式中，至少一个阳极90的阳极主体部在基底上的正投影与第一方向X上相邻的两个电路单元中的两个第一电源块71-1在基底上的正投影至少部分交叠，两个第一电源块71-1可以相对于第二阳极中心线OY镜像对称。
在示例性实施方式中，至少一个阳极90的阳极主体部在基底上的正投影与第一方向X上相邻的两个电路单元中的两个第二电源块71-2在基底上的正投影至少部分交叠，两个第二电源块71-2可以相对于第二阳极中心线OY镜像对称。
在示例性实施方式中，驱动电路层可以包括在基底上依次设置的第一绝缘层、第一半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第二半导体层、第五绝缘层、第三导电层、第六绝缘层、第四导电层、第一平坦层、第五导电层、第二平坦层、第六导电层和第三平坦层。第一半导体层可以至少包括第三晶体管T3至第八晶体管T8的有源层，第一导电层可以至少包括第二扫描信号线22、第四扫描信号线24和存储电容的第一极板，第二导电层可以至少包括存储电容的第二极板，第二半导体层可以至少包括第一晶体管T1和第二晶体管T2的有源层，第三导电层可以至少包括第一扫描信号线21、第三扫描信号线23和第一初始连接电极33，第四导电层可以至少包括第二初始连接电极46，第五导电层可以至少包括多个连接电极，第六导电层可以至少包括第一电源线71、数据信号线72和屏蔽电极74。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括沉积膜层、在膜层上涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多8种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工 艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以8个电路单元(2个单元行、4个单元列)为例，显示基板的制备过程可以包括如下操作。
(1)形成第一半导体层图案。在示例性实施方式中，形成第一半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成覆盖基底的第一绝缘层，以及设置在第一绝缘层上的第一半导体层图案，如图8所示。
在示例性实施方式中，每个电路单元中的第一半导体层图案可以包括第三晶体管T3的第三有源层13至第八晶体管T8的第八有源层18，且电路单元中的第三有源层13至第七有源层17为相互连接的一体结构。
在示例性实施方式中，在第一方向X上，第四有源层14和第五有源层15可以位于本电路单元中第三有源层13的同一侧，第六有源层16和第七有源层17可以位于本电路单元中第三有源层13的同一侧，第五有源层15和第六有源层16可以位于本电路单元的第三有源层13的不同侧。在第二方向Y上，第M电路行中电路单元的第四有源层14可以位于第三有源层13远离第M+1电路行的一侧，第M电路行中电路单元的第五有源层15、第六有源层16、第七有源层17和第八有源层18可以位于第三有源层13靠近第M+1单元行电路单元的一侧。
在示例性实施方式中，第三有源层13的形状可以呈“Ω”字形，第四有源层14、第五有源层15、第六有源层16、第七有源层17和第八有源层18的形状可以呈“I”字形。
在示例性实施方式中，每个晶体管的有源层可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第三有源层13的第一区13-1、第四有源层14的第二区14-2和第五有源层15的第二区15-2可以相互连接，第三有源层13的第一区13-1可以同时作为第四有源层14的第二区14-2和第五有源层15的第二区15-2。第三有源层13的第二区13-2与第六有源层16的第一区16-1连接，第三有源层13的第二区13-2可以作为第六有源层16的第一区16-1。第六有源层16的第二区16-2与第七有源层17的第二区17-2连接，第六有源层16的第二区16-2可以作为第七有源层17的第二区17-2。第四有源层14的第一区14-1、第五有源层15的第一区15-1、第七有源层17的第一区17-1、第八有源层18的第一区18-1和第八有源层18的第二区18-2可以单独设置。
在示例性实施方式中，一个单元行中，相邻两个电路单元中的第一半导体层可以相对于列中心线对称设置，列中心线可以是位于第一方向X相邻的两个电路单元之间且沿着第二方向Y延伸的直线。例如，第N单元列和第N+1单元列的第一半导体层(第三有源层13至第八有源层18)可以相对于列中心线对称设置。又如，第N+1单元列和第N+2单元列的第一半导体层可以相对于列中心线对称设置。
在示例性实施方式中，相邻单元行中的第一半导体层可以基本上相同。
在示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第三晶体管至第八晶体管为LTPS薄膜晶体管。在示例性实施方式中，通过图案化工艺对第一半导体薄膜进行图案化，可以包括：先在第一绝缘薄膜上形成非晶硅(a-si)薄膜，对非晶硅薄膜进行脱氢处理，对脱氢处理后的非晶硅薄膜进行结晶处理，形成多晶硅薄膜。随后，对多晶硅薄膜进行图案化，形成第一半导体层图案。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括： 在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖第一半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图9A和图9B所示，图9B为图9A中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个电路单元中的第一导电层图案至少包括：第二扫描信号线22、第四扫描信号线24、发光控制线25和存储电容的第一极板81。
在示例性实施方式中，第一极板81的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板81在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板81可以同时作为存储电容的一个极板和第三晶体管T3的栅电极。
在示例性实施方式中，第二扫描信号线22的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第M单元行电路单元中的第二扫描信号线22可以位于本电路单元的第一极板81靠近第M+1单元行电路单元的一侧，第二扫描信号线22与本电路单元的第七有源层相重叠的区域作为第七晶体管T7的栅电极，第二扫描信号线22与本电路单元的第八有源层相重叠的区域作为第八晶体管T8的栅电极。
在示例性实施方式中，第四扫描信号线24的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第M单元行电路单元中的第四扫描信号线24可以位于本电路单元的第一极板81远离第M+1单元行电路单元的一侧，第四扫描信号线24与本电路单元的第四有源层相重叠的区域作为第四晶体管T4的栅电极。
在示例性实施方式中，发光控制线25的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，发光控制线25可以位于第一极板81与第二扫描信号线22之间，发光控制线25与本电路单元的第五有源层相重叠的区域作为第五晶体管T5的栅电极，发光控制线25与本电路单元的第六有源层相重叠的区域作为第六晶体管T6的栅电极。
在示例性实施方式中，一个单元行中，相邻两个电路单元中的第一导电层可以相对于列中心线对称设置。例如，第N单元列和第N+1单元列的第一导电层可以相对于列中心线对称设置。又如，第N+1单元列和第N+2单元列的第一导电层可以相对于列中心线对称设置。
在示例性实施方式中，相邻单元行中的第一导电层可以基本上相同。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成第三晶体管T3至第八晶体管T8的沟道区域，未被第一导电层遮挡区域的第一半导体层被导体化，即第三有源层至第八有源层的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图10A和图10B所示，图10B为图10A中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，每个电路单元中的第二导电层图案至少包括：第一遮挡线31、第二遮挡线32和存储电容的第二极板82。
在示例性实施方式中，第二极板82的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板82在基底上的正投影与第一极板81在基底上的正投影至少部分交叠，第二极板82可以作为存储电容的另一个极板，第一极板81和第二极板82构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板82上设置有开口83，开口83的形状可以为块形(如 矩形)状，可以位于第二极板82的中部，使第二极板82形成环形结构。开口83暴露出覆盖第一极板81的第三绝缘层，且第一极板81在基底上的正投影包含开口83在基底上的正投影。在示例性实施方式中，开口83被配置为容置后续形成的第十一过孔，第十一过孔位于开口83内并暴露出第一极板81，使后续形成的第一连接电极与第一极板81连接。
在示例性实施方式中，第二极板82上可以设置有第一极板连接线84和第二极板连接线85，第一极板连接线84和第二极板连接线85可以分别设置在第二极板82第一方向X的两侧，且分别与第一方向X相邻电路单元中的第二极板82连接，使得一个单元行中相邻电路单元中的第二极板82相互连接。例如，第N列的第二极板82和第N+1列的第二极板82可以通过第一极板连接线84相互连接。又如，第N+1列的第二极板82和第N+2列的第二极板82可以通过第二极板连接线85相互连接。由于每个电路单元中的第二极板82与后续形成的第一电源线连接，通过将相邻电路单元的第二极板82形成相互连接的一体结构，一体结构的第二极板82可以复用为电源信号线，可以保证一单元行中的多个第二极板82具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第一极板连接线84和第二极板连接线85的宽度可以不同，宽度是第二方向Y的尺寸。
在示例性实施方式中，第一遮挡线31的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第一遮挡线31可以位于第二极板82和第四扫描信号线24之间。在示例性实施方式中，第一遮挡线31可以为非等宽度的折线，第一遮挡线31与后续形成的第二有源层相重叠位置的宽度可以大于其它位置的宽度，较宽位置的第一遮挡线31可以作为第二晶体管T2的遮挡层，以遮挡第二晶体管T2的沟道区域，保证氧化物第二晶体管T2的电学性能。在示例性实施方式中，第一遮挡线31可以同时作为第二晶体管T2的底栅电极。
在示例性实施方式中，第一遮挡线31可以为非等宽度的直线或者折线，宽度是第二方向Y的尺寸。第一遮挡线31可以至少包括相互连接的第一子遮挡线段31-1和第二子遮挡线段31-2，第一子遮挡线段31-1的宽度大于第二子遮挡线段31-2的宽度。在示例性实施方式中，第一子遮挡线段31-1可以设置在后续形成的第二有源层所在区域，第一子遮挡线段31-1在基底上的正投影与第二有源层在基底上的正投影至少部分交叠，第二子遮挡线段31-2可以设置在后续形成的第二有源层以外区域，第二子遮挡线段31-2在基底上的正投影与第二有源层在基底上的正投影没有交叠。
在示例性实施方式中，第二遮挡线32的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第二遮挡线32可以位于第四扫描信号线24远离第二极板82的一侧。在示例性实施方式中，第二遮挡线32可以为非等宽度的折线，第二遮挡线32与后续形成的第一有源层相重叠位置的宽度可以大于其它位置的宽度，较宽位置的第二遮挡线32可以作为第一晶体管T1的遮挡层，以遮挡第一晶体管T1的沟道区域，保证氧化物第一晶体管T1的电学性能。在示例性实施方式中，第二遮挡线32可以同时作为第一晶体管T1的底栅电极。
在示例性实施方式中，一个单元行中，相邻两个电路单元中的第二导电层可以相对于列中心线对称设置。例如，第N单元列和第N+1单元列的第二导电层可以相对于列中心线对称设置。又如，第N+1单元列和第N+2单元列的第二导电层可以相对于列中心线对称设置。
在示例性实施方式中，相邻单元行中的第二导电层可以基本上相同。
(4)形成第二半导体层图案。在示例性实施方式中，形成第二半导体层图案可以包 括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成覆盖基底的第四绝缘层，以及设置在第四绝缘层上的第二半导体层图案，如图11A和图11B所示，图11B为图11A中第二半导体层的平面示意图。
在示例性实施方式中，每个电路单元中的第二半导体层图案至少包括：第一晶体管T1的第一有源层11和第二晶体管T2的第二有源层12。
在示例性实施方式中，第一有源层11和第二有源层12的形状可以呈“I”字形，第一有源层11在基底上的正投影与第二遮挡线32在基底上的正投影至少部分交叠，第二有源层12在基底上的正投影与第一遮挡线31在基底上的正投影至少部分交叠。
在示例性实施方式中，第一有源层11的第一区11-1可以位于第二遮挡线32远离第二极板82的一侧，第二有源层12的第二区12-2可以位于第一遮挡线31靠近第二极板82的一侧，第一有源层11的第二区11-2和第二有源层12的第一区12-1可以相互连接，第一有源层11的第二区11-2可以作为第二有源层12的第一区12-1。
在示例性实施方式中，一个单元行中，相邻两个电路单元中的第二半导体层可以相对于列中心线对称设置。例如，第N单元列和第N+1单元列的第二半导体层可以相对于列中心线对称设置。又如，第N+1单元列和第N+2单元列的第二半导体层可以相对于列中心线对称设置。
在示例性实施方式中，相邻单元行中的第二半导体层可以基本上相同。
在示例性实施方式中，第二半导体层可以采用氧化物，即第一晶体管T1和第二晶体管T2为氧化物晶体管。在示例性实施方式中，第二半导体薄膜可以采用氧化铟镓锌(IGZO)，氧化铟镓锌(IGZO)的电子迁移率高于非晶硅。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成覆盖第二半导体层的第五绝缘层，以及设置在第五绝缘层上的第三导电层图案，如图12A和图12B所示，图12B为图12A中第三导电层的平面示意图。在示例性实施方式中，第三导电层可以称为第三栅金属(GATE3)层。
在示例性实施方式中，每个电路单元中的第三导电层图案至少包括：第一扫描信号线21、第三扫描信号线23和第一初始连接电极33。
在示例性实施方式中，第一扫描信号线21的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第一扫描信号线21可以位于第二极板82和第四扫描信号线24之间，第一扫描信号线21与第二有源层相重叠的区域作为第二晶体管T2的栅电极。
在示例性实施方式中，第一扫描信号线21在基底上的正投影与第一遮挡线31在基底上的正投影至少部分交叠，第一扫描信号线21和第一遮挡线31可以连接相同的信号源，使得第一遮挡线31可以作为第二晶体管T2的底栅电极，第一扫描信号线21可以作为第二晶体管T2的顶栅电极，形成顶栅底栅结构的第二晶体管T2。
在示例性实施方式中，第一扫描信号线21可以为非等宽度的直线或者折线，宽度是第二方向Y的尺寸。第一扫描信号线21可以至少包括相互连接的第一子扫描线段21-1和第二子扫描线段21-2，第一子扫描线段21-1的宽度大于第二子扫描线段21-2的宽度。在示例性实施方式中，第一子扫描线段21-1可以设置在第二有源层所在区域，第一子扫描线段21-1在基底上的正投影与第二有源层在基底上的正投影至少部分交叠，第二子扫描线段21-2可以设置在第二有源层以外区域，第二子扫描线段21-2在基底上的正投影与第二有源层在基底上的正投影没有交叠。
在示例性实施方式中，第一子扫描线段21-1在基底上的正投影与第一子遮挡线段31-1在基底上的正投影至少部分交叠，第二子扫描线段21-2在基底上的正投影与第二子 遮挡线段31-2在基底上的正投影至少部分交叠。
在示例性实施方式中，第三扫描信号线23的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第三扫描信号线23可以位于第四扫描信号线24远离第二极板82的一侧，第三扫描信号线23与第一有源层相重叠的区域作为第一晶体管T1的栅电极。
在示例性实施方式中，第三扫描信号线23在基底上的正投影与第二遮挡线32在基底上的正投影至少部分交叠，第三扫描信号线23和第二遮挡线32可以连接相同的信号源，使得第二遮挡线32可以作为第一晶体管T1的底栅电极，第三扫描信号线23可以作为第一晶体管T1的顶栅电极，形成顶栅底栅结构的第一晶体管T1。
在示例性实施方式中，第一初始连接电极33的形状为主体部分沿着所述第二方向延伸的折线状，第一初始连接电极33被配置为与后续形成的第二初始连接电极连接，且第一初始连接电极和第二初始连接电极一起组成初始连接线。
在示例性实施方式中，第一初始连接电极33可以包括第一端33A、第二端33B、第一连接块33-1、第二连接块33-2和第三连接块33-3。第一初始连接电极33的第一端33A为第一初始连接电极33靠近第一扫描信号线21的端部，第一初始连接电极33的第二端33B为第一初始连接电极33靠近第三扫描信号线23的端部。第一连接块33-1可以设置在第一端33A靠近第二端33B的一侧，第一连接块33-1被配置为与后续形成的第一初始信号线连接。第二连接块33-2可以设置在第一连接块33-1靠近第二端33B的一侧，第二连接块33-2被配置为与后续形成的第二初始信号线连接。第三连接块33-3可以设置在第二连接块33-2靠近第二端33B的一侧，第三连接块33-3被配置为与后续形成的第三初始信号线连接。
在示例性实施方式中，一个单元行中，相邻两个电路单元中的第三导电层可以相对于列中心线对称设置。例如，第N单元列和第N+1单元列的第三导电层可以相对于列中心线对称设置。又如，第N+1单元列和第N+2单元列的第三导电层可以相对于列中心线对称设置。
在示例性实施方式中，相邻单元行中的第三导电层可以基本上相同。
(6)形成第六绝缘层图案。在示例性实施方式中，形成第六绝缘层图案可以包括：在形成前述图案的基底上，沉积第六绝缘薄膜，采用图案化工艺对第六绝缘薄膜进行图案化，形成覆盖第三导电层的第六绝缘层，第六绝缘层上设置有多个过孔，如图13所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第一过孔V1至第十四过孔V14。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第一过孔V1被配置为使后续形成的第一初始信号线通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一有源层的第二区(也是第二有源层的第一区)在基底上的正投影的范围之内，第二过孔V2内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第一有源层的第二区(也是第二有源层的第一区)的表面，第二过孔V2被配置为使后续形成的第二连接电极通过该过孔与第一有源层的第二区(也是第二有源层的第一区)连接。
在示例性实施方式中，在第二过孔V2所在区域，第四扫描信号线24上设置有弯曲部，弯曲部向着远离第二极板82方向的凸出，使得第二过孔V2在基底上的正投影与第四扫描信号线24在基底上的正投影没有交叠。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第二有源层的第二区在基底上的正投影的范围之内，第三过孔V3内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出 第二有源层的第二区的表面，第三过孔V3被配置为使后续形成的第一连接电极通过该过孔与第二有源层的第二区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第三有源层的第二区(也是第六有源层的第一区)在基底上的正投影的范围之内，第四过孔V4内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第二区(也是第六有源层的第一区)的表面，第四过孔V4被配置为使后续形成的第二连接电极通过该过孔与第三有源层的第二区(也是第六有源层的第一区)连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第五过孔V5内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第五过孔V5被配置为使后续形成的第三连接电极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第六过孔V6内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第六过孔V6被配置为使后续形成的第四连接电极通过该过孔与第五有源层的第一区连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第七过孔V7内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面，第七过孔V7被配置为使后续形成的第五连接电极55通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第八过孔V8被配置为使后续形成的第二初始信号线通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第八有源层的第一区在基底上的正投影的范围之内，第九过孔V9内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第一区的表面，第九过孔V9被配置为使后续形成的第三初始信号线通过该过孔与第八有源层的第一区连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第八有源层的第二区在基底上的正投影的范围之内，第十过孔V10内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第二区的表面，第十过孔V10被配置为使后续形成的第二连接电极通过该过孔与第八有源层的第二区连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于开口83在基底上的正投影的范围之内，第十一过孔V11内的第六绝缘层、第五绝缘层、第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板31的表面，第十一过孔V11配置为使后续形成的第一连接电极通过该过孔与第一极板31连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第二极板连接线85在基底上的正投影的范围之内，第十二过孔V12内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出第二极板连接线85的表面，第十二过孔V12被配置为使后续形成的第四连接电极通过该过孔与第二极板连接线85连接。
在示例性实施方式中，部分第一方向X相邻的两个电路单元可以共用同一个第十二过孔V12。例如，第N-1单元列和第N单元列的两个电路单元可以共用同一个第十二过孔V12。又如，第N+1单元列和第N+2单元列的两个电路单元可以共用同一个第十二过孔V12。再如，第N+3单元列和第N+4单元列的两个电路单元可以共用同一个第十二过 孔V12。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于第一初始连接电极33的第一端33A在基底上的正投影的范围之内，第十三过孔V13内的第六绝缘层被刻蚀掉，暴露出第一端33A的表面，第十三过孔V13被配置为使后续形成的第二初始连接电极通过该过孔与第一端33A连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影位于第一初始连接电极33的第二端33B在基底上的正投影的范围之内，第十四过孔V14内的第六绝缘层被刻蚀掉，暴露出第二端33B的表面，第十四过孔V14被配置为使后续形成的第二初始连接电极通过该过孔与第二端33B连接。
在示例性实施方式中，至少一个电路单元中的多个过孔还可以包括第十五过孔V15、第十六过孔V16和第十七过孔V17。
在示例性实施方式中，第十五过孔V15可以设置在第N单元列和第N+3单元列的电路单元中，第十五过孔V15在基底上的正投影位于第一初始连接电极33的第一连接块33-1在基底上的正投影的范围之内，第十五过孔V15内的第六绝缘层被刻蚀掉，暴露出第一连接块33-1的表面，第十五过孔V15被配置为使后续形成的第一初始信号线通过该过孔与第一连接块33-1连接。
在示例性实施方式中，第十六过孔V16可以设置在第N+1单元列的电路单元中，第十六过孔V16在基底上的正投影位于第一初始连接电极33的第二连接块33-2在基底上的正投影的范围之内，第十六过孔V16内的第六绝缘层被刻蚀掉，暴露出第二连接块33-2的表面，第十六过孔V16被配置为使后续形成的第二初始信号线通过该过孔与第二连接块33-2连接。
在示例性实施方式中，第十七过孔V17可以设置在第N+2单元列的电路单元中，第十七过孔V17在基底上的正投影位于第一初始连接电极33的第三连接块33-3在基底上的正投影的范围之内，第十七过孔V17内的第六绝缘层被刻蚀掉，暴露出第三连接块33-3的表面，第十六过孔V16被配置为使后续形成的第三初始信号线通过该过孔与第三连接块33-3连接。
(7)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第六绝缘层上的第四导电层，如图14A和图14B所示，图14B为图14A中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，每个电路单元中的第四导电层至少包括：第一初始信号线41、第二初始信号线42、第三初始信号线43、第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55和第二初始连接电极56。
在示例性实施方式中，第一连接电极51的形状可以为沿着第二方向Y延伸的条形状，第一连接电极51的第一端通过第三过孔V3与第二有源层的第二区连接，第一连接电极51的第二端通过第十一过孔V11与第一极板31连接。在示例性实施方式中，由于第一极板31同时作为第三晶体管T3的栅电极，因而第一连接电极51使第二晶体管T2的第二极、第三晶体管T3的栅电极和第一极板31具有相同的电位，形成像素驱动电路的第一节点N1。在示例性实施方式中，第一连接电极51可以称为第一节点电极。
在示例性实施方式中，第一连接电极51在基底上的正投影与第一扫描信号线21在基底上的正投影至少部分交叠。由于第一连接电极51作为像素驱动电路的第一节点N1，因而第一连接电极51可以增加第一扫描信号线21和第一节点N1之间的寄生电容。在示例性实施方式中，在第四扫描信号线24输出导通信号后，利用第一扫描信号线21的下降沿， 该寄生电容可以将第一节点N1的电位拉低，从而增大电流，可以有效提升显示亮度。
在示例性实施方式中，第一连接电极51上可以设置有第一补偿块51-1，第一补偿块51-1的第一端与第一连接电极51的第一端连接，第一补偿块51-1的第二端向着第一扫描信号线21的方向延伸，第一补偿块51-1在基底上的正投影与第一扫描信号线21在基底上的正投影至少部分交叠。
在示例性实施方式中，第一连接电极51和第一补偿块51-1可以为相互连接的一体结构。
在示例性实施方式中，第二连接电极52的形状可以为主体部分沿着第二方向Y延伸的条形状，第二连接电极52的第一端通过第二过孔V2与第一有源层的第二区(也是第二有源层的第一区)连接第三过孔V3与第二有源层的第二区连接，第二连接电极52的第二端通过第十过孔V10与第八有源层的第二区连接，第二连接电极52的第一端与第二端之间的区域通过第四过孔V4与第三有源层的第二区(也是第六有源层的第一区)连接。在示例性实施方式中，第二连接电极52使第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的第二极、第六晶体管T6的第一极和第八晶体管T8的第二极具有相同的电位，形成像素驱动电路的第二节点N2。在示例性实施方式中，第二连接电极52可以称为第二节点电极。
在示例性实施方式中，在第二过孔V2所在区域，第四扫描信号线24上设置有弯曲部，弯曲部向着远离第二极板82方向的凸出，使得第四扫描信号线24可以避让第二连接电极52，第二连接电极52在基底上的正投影与第四扫描信号线24在基底上的正投影没有交叠。由于第二连接电极52作为像素驱动电路的第二节点N2，因而可以有效减少第二节点N2与第四扫描信号线24之间的寄生电容，一方面可以减少第二节点N2的寄生电容，另一方面可以减小对数据信号写入过程的影响。
在示例性实施方式中，第四扫描信号线24上设置避让第二连接电极52的弯曲部，第三扫描信号线23上设置避让第一初始连接电极33的弯曲部，使得第四扫描信号线24在基底上的正投影与第三扫描信号线23在基底上的正投影至少部分交叠，造成第三扫描信号线23和第四扫描信号线24之间的寄生电容增大。由于第三扫描信号线23在第二时段输出导通信号，该导通信号不会影响第四扫描信号线24在第三时段输出导通信号，也不会影响数据信号写入过程。
在示例性实施方式中，第二连接电极52在基底上的正投影与第一扫描信号线21中第一子扫描线段21-1在基底上的正投影没有交叠，第二连接电极52在基底上的正投影与第一遮挡线31中的第一子遮挡线段31-1在基底上的正投影没有交叠，第二连接电极52在基底上的正投影与第一扫描信号线21中第二子扫描线段21-2在基底上的正投影至少部分交叠，第二连接电极52在基底上的正投影与第一遮挡线31中的第二子扫描线段21-2在基底上的正投影至少部分交叠。由于第二子遮挡线段31-2的宽度小于第一子遮挡线段31-1的宽度，第二子扫描线段21-2的宽度小于第一子扫描线段21-1的宽度，因而可以有效减少第二连接电极52与第一扫描信号线21(第一遮挡线31)之间的寄生电容，一方面可以减少第二节点N2的寄生电容，另一方面可以较少对第一扫描信号线的影响。
在示例性实施方式中，第三连接电极53的形状可以为块形状(如矩形)，第三连接电极53通过第五过孔V5与第四有源层的第一区连接，第三连接电极53被配置为与后续形成的第十二连接电极连接。
在示例性实施方式中，第四连接电极54的形状可以为沿着第二方向Y延伸的条形状，第四连接电极54的第一端通过第六过孔V6与第五有源层的第一区连接，第四连接电极54的第二端通过第十二过孔V12与第二极板连接线85连接，第四连接电极54被配置为与后续形成的第十一连接电极连接。在示例性实施方式中，由于第二极板连接线85与第 二极板82连接，因而第四连接电极54实现了电路单元中第五晶体管T5的第一极和存储电容的第二极板82具有相同的电位。
在示例性实施方式中，部分第一方向X相邻的两个电路单元的第四连接电极54可以为相互连接的一体结构。例如，第N-1单元列和第N单元列的两个电路单元的第四连接电极54可以为相互连接的一体结构。又如，第N+1单元列和第N+2单元列的两个电路单元的第四连接电极54可以为相互连接的一体结构。再如，第N+3单元列和第N+4单元列的两个电路单元的第四连接电极54可以为相互连接的一体结构。
在示例性实施方式中，第五连接电极55的形状可以为块形状(如矩形)，第五连接电极55通过第七过孔V7与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第五连接电极55被配置为与后续形成的第十三连接电极连接，形成像素驱动电路的第四节点N4。
在示例性实施方式中，第二初始连接电极56的形状可以为主体部分沿着第二方向Y延伸的折线状，第二初始连接电极56的第一端通过第十三过孔V13与第一初始连接电极33的第一端33A连接，第二初始连接电极56的第二端通过第十四过孔V14与第一初始连接电极33的第二端33B连接。
在示例性实施方式中，第一初始信号线41的形状可以为沿着第一方向X延伸的直线状或者折线状，可以设置在第三扫描信号线23远离第二极板82的一侧。在每个电路单元，第一初始信号线41通过第一过孔V1与第一有源层的第一区连接，实现了第一初始信号线41与第一晶体管T1的第一极的连接，第一初始信号线41可以将传输的第一初始信号写入第一晶体管T1的第一极。
在示例性实施方式中，在第N单元列和第N+3单元列的电路单元中，第一初始信号线41还通过第十五过孔V15与第一连接块33-1连接。由于第一连接块33-1与第一初始连接电极33连接，相邻单元行的第一初始连接电极33通过第二初始连接电极56相互连接，第N单元列和第N+3单元列中相互连接的第一初始连接电极33和第二初始连接电极56组成第一初始连接线，实现了沿着第一方向X延伸的第一初始信号线41与沿着第二方向Y延伸的第一初始连接线的连接，使得第一初始信号线41和第一初始连接线在显示区域形成网状的传输第一初始信号的网状结构，不仅可以有效降低第一初始信号线的电阻，减小第一初始信号的压降，而且可以有效提升显示基板中第一初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第二初始信号线42的形状可以为沿着第一方向X延伸的直线状或者折线状，可以设置在第二扫描信号线22远离第二极板82的一侧。在每个电路单元，第二初始信号线42通过第八过孔V8与第七有源层的第一区连接，实现了第二初始信号线42与第七晶体管T7的第一极的连接，第二初始信号线42可以将传输的第二初始信号写入第七晶体管T7的第一极。
在示例性实施方式中，在第N+1单元列的电路单元中，第二初始信号线42还通过第十六过孔V16与第二连接块33-2连接。由于第二连接块33-2与第一初始连接电极33连接，相邻单元行的第一初始连接电极33通过第二初始连接电极56相互连接，第N+1单元列中相互连接的第一初始连接电极33和第二初始连接电极56组成第二初始连接线，实现了沿着第一方向X延伸的第二初始信号线42与沿着第二方向Y延伸的第二初始连接线的连接，使得第二初始信号线42和第二初始连接线在显示区域形成网状的传输第二初始信号的网状结构，不仅可以有效降低第二初始信号线的电阻，减小第二初始信号的压降，而且可以有效提升显示基板中第二初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第三初始信号线43的形状可以为沿着第一方向X延伸的直线 状或者折线状，可以设置在第二扫描信号线22和第二初始信号线42之间。在每个电路单元，第三初始信号线43通过第九过孔V9与第八有源层的第一区连接，实现了第三初始信号线43与第八晶体管T8的第一极的连接，第三初始信号线43可以将传输的第三初始信号写入第八晶体管T8的第一极。
在示例性实施方式中，在第N+2单元列的电路单元中，第三初始信号线43还通过第十七过孔V17与第三连接块33-3连接。由于第三连接块33-3与第一初始连接电极33连接，相邻单元行的第一初始连接电极33通过第二初始连接电极56相互连接，第N+2单元列中相互连接的第一初始连接电极33和第二初始连接电极56组成第三初始连接线，实现了沿着第一方向X延伸的第三初始信号线43与沿着第二方向Y延伸的第三初始连接线的连接，使得第三初始信号线43和第三初始连接线在显示区域形成网状的传输第三初始信号的网状结构，不仅可以有效降低第三初始信号线的电阻，减小第三初始信号的压降，而且可以有效提升显示基板中第三初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
图14C和图14D为图14A中网状结构的初始信号线的示意图。如图14C和图14D所示，第一初始信号线41、第二初始信号线42和第三初始信号线43可以设置在每个单元行中，第一初始连接线44可以设置在第N单元列和第N+3单元列中，第二初始连接线45可以设置在第N+1单元列中，第三初始连接线46可以设置在第N+2单元列中，每个单元列中的初始连接线均由相互连接的第一初始连接电极33和第二初始连接电极56组成，第一初始连接电极33和第二初始连接电极56设置在不同的导电层中，两者通过过孔相互连接。
在示例性实施方式中，位于第N单元列和第N+3单元列中的第一初始连接线44通过多个电路单元中的第十五过孔V15与多个电路单元中的第一初始信号线41连接，在显示区域形成网状的传输第一初始信号的网状结构。
在示例性实施方式中，位于第N+1单元列中的第二初始连接线45通过多个电路单元中的第十六过孔V16与多个电路单元中的第二初始信号线42连接，在显示区域形成网状的传输第二初始信号的网状结构。
在示例性实施方式中，位于第N+2单元列中的第三初始连接线46通过通过多个电路单元中的第十七过孔V17与多个电路单元中的第三初始信号线43连接，在显示区域形成网状的传输第三初始信号的网状结构。
在示例性实施方式中，第一初始连接线44、第二初始连接线45和第三初始连接线46可以周期性设置在多个单元列中，相邻的两条第一初始连接线44之间设置有第二初始连接线45和第三初始连接线46，相邻的两条第二初始连接线45之间设置有第一初始连接线44和第三初始连接线46，相邻的两条第三初始连接线46之间设置有第一初始连接线44和第二初始连接线45。
在示例性实施方式中，第一初始连接线44、第二初始连接线45和第三初始连接线46在多个单元列中的设置方式可以有多种方式。例如，两条第一初始连接线44可以设置在一个相邻的两个单元列中，两条第二初始连接线45可以设置在另一个相邻的两个单元列中，两条第三初始连接线46可以设置在又一个相邻的两个单元列中，本公开在此不做限定。
(8)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第四导电层图案的第一平坦层，第一平坦层上设置有多个过孔，如图15所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第二十一过孔V21、第 二十二过孔V22和第二十三过孔V23。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第四连接电极54在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层被刻蚀掉，暴露出第四连接电极54的表面，第二十一过孔V21被配置为使后续形成的第十一连接电极通过该过孔与第四连接电极54连接。
在示例性实施方式中，部分第一方向X相邻的两个电路单元可以共用同一个第二十一过孔V21。例如，第N-1单元列和第N单元列的两个电路单元可以共用同一个第二十一过孔V21。又如，第N+1单元列和第N+2单元列的两个电路单元可以共用同一个第二十一过孔V21。再如，第N+3单元列和第N+4单元列的两个电路单元可以共用同一个第二十一过孔V21。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第三连接电极53在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层被刻蚀掉，暴露出第三连接电极53的表面，第二十二过孔V22被配置为使后续形成的第十二连接电极通过该过孔与第三连接电极53连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第五连接电极55在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层被刻蚀掉，暴露出第五连接电极55的表面，第二十三过孔V23被配置为使后续形成的第十三连接电极通过该过孔与第五连接电极55连接。
(9)形成第五导电层图案。在示例性实施方式中，形成第五导电层可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第一平坦层上的第五导电层，如图16A和图16B所示，图16B为图16A中第五导电层的平面示意图。在示例性实施方式中，第五导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，每个电路单元的第五导电层至少包括：第十一连接电极61、第十二连接电极62和第十三连接电极63。
在示例性实施方式中，第十一连接电极61的形状可以为沿着第一方向X延伸的条形状，第十一连接电极61通过第二十一过孔V21与第四连接电极54连接，第十一连接电极61被配置为与后续形成的第一电源线连接。
在示例性实施方式中，部分第一方向X相邻的两个电路单元的第十一连接电极61可以为相互连接的一体结构。例如，第N-1单元列和第N单元列的两个电路单元的第十一连接电极61可以为相互连接的一体结构。又如，第N+1单元列和第N+2单元列的两个电路单元的第十一连接电极61可以为相互连接的一体结构。再如，第N+3单元列和第N+4单元列的两个电路单元的第十一连接电极61可以为相互连接的一体结构。
在示例性实施方式中，第十二连接电极62的形状可以为块形状(如矩形)，第十二连接电极62通过第二十二过孔V22与第三连接电极53连接，第十二连接电极62被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第十三连接电极63的形状可以为块形状(如矩形)，第十三连接电极63通过第二十三过孔V23与第五连接电极55连接，第十三连接电极63被配置为与后续形成的阳极连接电极连接。
(10)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第五导电层图案的第二平坦层，第二平坦层上设置有多个过孔，如图17所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第三十一过孔V31、第 三十二过孔V32和第三十三过孔V33。
在示例性实施方式中，第三十一过孔V31在基底上的正投影位于第十一连接电极61在基底上的正投影的范围之内，第三十一过孔V31内的第二平坦层被刻蚀掉，暴露出第十一连接电极61的表面，第三十一过孔V31被配置为使后续形成的第一电源线通过该过孔与第十一连接电极61连接。
在示例性实施方式中，第三十二过孔V32在基底上的正投影位于第十二连接电极62在基底上的正投影的范围之内，第三十二过孔V32内的第二平坦层被刻蚀掉，暴露出第十二连接电极62的表面，第三十二过孔V32被配置为使后续形成的数据信号线通过该过孔与第十二连接电极62连接。
在示例性实施方式中，第三十三过孔V33在基底上的正投影位于第十三连接电极63在基底上的正投影的范围之内，第三十三过孔V33内的第二平坦层被刻蚀掉，暴露出第十三连接电极63的表面，第三十三过孔V33被配置为使后续形成的阳极连接电极通过该过孔与第十三连接电极63连接。
(11)形成第六导电层图案。在示例性实施方式中，形成第六导电层可以包括：在形成前述图案的基底上，沉积第六导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第二平坦层上的第六导电层，如图18A和图18B所示，图18B为图18A中第六导电层的平面示意图。在示例性实施方式中，第六导电层可以称为第三源漏金属(SD3)层。
在示例性实施方式中，每个电路单元的第五导电层至少包括：第一电源线71、数据信号线72和阳极连接电极73。
在示例性实施方式中，第一电源线71的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一电源线71通过第三十一过孔V31与第十一连接电极61。由于第十一连接电极61与第四连接电极54连接，第四连接电极54分别与第五晶体管T5的第一极和存储电容的第二极板82连接，因而实现了第一电源线71将第一电源信号写入第五晶体管T5和存储电容的第二极板82。
在示例性实施方式中，第一电源线71可以为非等宽度的折线，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施方式中，部分第一方向X相邻的两个电路单元的第一电源线71可以为相互连接的一体结构。例如，第N-1单元列和第N单元列的两个电路单元的第一电源线71可以为相互连接的一体结构。又如，第N+1单元列和第N+2单元列的两个电路单元的第一电源线71可以为相互连接的一体结构。再如，第N+3单元列和第N+4单元列的两个电路单元的第一电源线71可以为相互连接的一体结构。
在示例性实施方式中，第一电源线71在基底上的正投影与第一连接电极51在基底上的正投影至少部分交叠，具有恒定电位的第一电源线71可以有效屏蔽数据电压跳变和其它信号对像素驱动电路中第一节点N1的影响，避免了数据电压跳变和其它信号影响第一节点N1的电位，提高了像素驱动电路的驱动性能。
在示例性实施方式中，第一电源线71在基底上的正投影包含第一连接电极51在基底上的正投影，即第一电源线71完全覆盖第一连接电极51。
在示例性实施方式中，第一电源线71在基底上的正投影与第二有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一电源线71可以阻挡发光器件的发光和膜层反射光照射到氧化物第二晶体管，可以防止氧化物第二晶体管因光照发生特性漂移，提高了氧化物第二晶体管的电学特性。
在示例性实施方式中，第一电源线71在基底上的正投影与第二连接电极52在基底上的正投影没有交叠，可以有效减少第二节点N2的寄生电容。
在示例性实施方式中，第一电源线71上设置有屏蔽电极74，屏蔽电极74的形状可以为沿着第二方向Y延伸的条形状，屏蔽电极74的第一端与第一电源线71连接，屏蔽电极74的第二端向着本电路单元中阳极连接电极73的方向延伸。
在示例性实施方式中，屏蔽电极74可以设置在一体结构的第一电源线71的中部，一体结构的第一电源线71可以相对于屏蔽电极74基本上镜像对称。
在示例性实施方式中，屏蔽电极74在基底上的正投影与第二连接电极52在基底上的正投影没有交叠，以有效减少第二节点N2的寄生电容。
在示例性实施方式中，在第一方向X上，屏蔽电极74的部分可以设置在部分相邻的第二连接电极52之间，具有恒定电位的屏蔽电极74可以有效相邻电路单元中第二节点N2的相互影响，提高了像素驱动电路的驱动性能。例如，屏蔽电极74可以设置在第N单元列中电路单元的第二连接电极52与第N+1单元列中电路单元的第二连接电极52之间。又如，屏蔽电极74可以设置在第N+2单元列中电路单元的第二连接电极52与第N+3单元列中电路单元的第二连接电极52之间。
在示例性实施方式中，屏蔽电极74还被配置为提高阳极的平坦性。
在示例性实施方式中，第一电源线71上还可以设置有第一电源块71-1和第二电源块71-2。第一电源块71-1和第二电源块71-2的形状可以为块形(如梯形)状，可以设置在第一电源线71靠近屏蔽电极74的一侧，且分别与屏蔽电极74的两个端部相对应。在示例性实施方式中，第一电源块71-1和第二电源块71-2被配置为提高阳极的平坦性。
第一电源线71、第一电源块71-1、第二电源块71-2和屏蔽电极74可以为相互连接的一体结构。
在示例性实施方式中，数据信号线72的形状可以为主体部分沿着第二方向Y延伸的直线状或折线状，数据信号线72通过第三十二过孔V32与第十二连接电极62连接。由于第十二连接电极62与第三连接电极53连接，第三连接电极53通过过孔与第四有源层的第一区连接，因而实现了数据信号线72与第四晶体管T4的第一极的连接，数据信号线72可以将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，阳极连接电极73的形状可以为块形状(如矩形)，阳极连接电极73通过第三十三过孔V33与第十三连接电极63连接，阳极连接电极73被配置为与后续形成的阳极连接。由于阳极连接电极73与第五连接电极55连接，第五连接电极55通过过孔与第六有源层的第二区和第七有源层的第二区连接，因而可以实现后续形成的阳极与第六晶体管T6的第二极和第七晶体管T7的第二极的连接，像素驱动电路可以驱动发光器件发光。
(12)形成第三平坦层图案。在示例性实施方式中，形成第三平坦层图案可以包括：在形成前述图案的基底上，涂覆第三平坦薄膜，采用图案化工艺对第三平坦薄膜进行图案化，形成覆盖第六导电层图案的第三平坦层，第三平坦层上设置有多个过孔，如图19所示。
在示例性实施方式中，每个电路单元中的过孔至少包括第四十一过孔V41。
在示例性实施方式中，第四十一过孔V41在基底上的正投影位于阳极连接电极73在基底上的正投影的范围之内，第四十一过孔V41内的第三平坦层被去掉，暴露出阳极连接电极73的表面，第四十一过孔V41被配置为使后续形成的阳极通过该过孔与阳极连接电极73连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光控制线、第一初始信号线、第二初始信号线、第三初始信号线、数据信号线和第一电源线。在垂直于显 示基板的方向上，驱动电路层可以包括在基底上依次设置的第一绝缘层、第一半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第二半导体层、第五绝缘层、第三导电层、第六绝缘层、第四导电层、第一平坦层、第五导电层、第二平坦层、第六导电层和第三平坦层。第一半导体层可以至少包括第三晶体管至第八晶体管的有源层，第一导电层可以至少包括第二扫描信号线、第四扫描信号线和存储电容的第一极板，第二导电层可以至少包括存储电容的第二极板，第二半导体层可以至少包括第一晶体管和第二晶体管的有源层，第三导电层可以至少包括第一扫描信号线和第三扫描信号线，第四导电层可以至少包括多个连接电极，第五导电层可以至少包括多个连接电极，第六导电层可以至少包括数据信号线、第一电源线和阳极连接电极。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括在玻璃载板上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层、第五导电层和第六导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可以称为缓冲(Buffer)层，第二绝缘层、第三绝缘层、第四绝缘层和第五绝缘层可以称为栅绝缘(GI)层，第六绝缘层可以称为层间绝缘(ILD)层，第七绝缘层可以称为钝化(PVX)层。第一平坦层、第二平坦层和第三平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，一个单元行中相邻两个电路单元中的像素驱动电路可以相对于列中心线基本上镜像对称。例如，第N列的像素驱动电路和第N+1列的像素驱动电路可以相对于列中心线镜像对称。又如，第N+1列的像素驱动电路和第N+2列的像素驱动电路可以相对于列中心线镜像对称。
在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(13)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第三平坦层上的阳极导电层，阳极导电层可以至少包括多个阳极图案，如图20A和图20B所示，图20B为图20A中阳极导电层的平面示意图。
在示例性实施方式中，多个阳极图案可以包括红色发光器件的第一阳极90A、蓝色发光器件的第二阳极90B、第一绿色发光器件的第三阳极90C和第二绿色发光器件的第四阳极90D，第一阳极90A可以位于出射红色光线的红色子像素，第二阳极90B可以位于出射蓝色光线的蓝色子像素，第三阳极90C可以位于出射绿色光线的第一绿色子像素，第四阳极90D可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一阳极90A和第二阳极90B可以沿着第一方向X依次设置，第三阳极90C和第四阳极90D可以沿着第一方向X依次设置，第三阳极90C和第四阳极 90D可以分别设置在第一阳极90A和第二阳极90B第二方向Y的一侧。或者，第一阳极90A和第二阳极90B可以沿着第二方向Y依次设置，第三阳极90C和第四阳极90D可以沿着第二方向Y依次设置，第三阳极90C和第四阳极90D可以设置在第一阳极90A和第二阳极90B第一方向X的一侧。
在示例性实施方式中，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D可以分别通过第四十一过孔V41与对应电路单元的阳极连接电极73连接，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同。
在示例性实施方式中，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D中的至少一个可以包括相互连接的阳极主体部和阳极连接部，阳极主体部的形状可以为圆形状或者椭圆形状，阳极连接部的形状可以为条形状，阳极连接部通过第四十一过孔V41与阳极连接电极73连接，因而可以实现阳极与第六晶体管T6的第二极和第七晶体管T7的第二极的连接。
在示例性实施方式中，至少一个阳极的阳极主体部和阳极连接部可以为相互连接的一体结构。
在示例性实施方式中，至少一个阳极的阳极主体部可以具有第一阳极中心线OX和第二阳极中心线OY，第一阳极中心线OX可以是在第二方向Y上平分该阳极的阳极主体部且沿着第一方向X延伸的直线，第二阳极中心线OY可以是在第一方向X上平分该阳极的阳极主体部且沿着第二方向Y延伸的直线。例如，第三阳极90C和第四阳极90D可以均具有第一阳极中心线OX和第二阳极中心线OY。
在示例性实施方式中，至少一个阳极的阳极主体部在基底上的正投影与第一方向X上相邻的两个电路单元中的两条第一电源线71在基底上的正投影至少部分交叠，且该两条第一电源线71可以相对于该阳极的第二阳极中心线OY镜像对称。
在示例性实施方式中，至少一个阳极的阳极主体部在基底上的正投影与至少一个第一电源线71的第一电源块71-1和第二电源块71-2在基底上的正投影至少部分交叠，例如，第三阳极90C的阳极主体部在基底上的正投影与一条第一电源线71的第一电源块71-1和第二电源块71-2在基底上的正投影至少部分交叠。又如，第四阳极90D的阳极主体部在基底上的正投影与另一条第一电源线71的第一电源块71-1和第二电源块71-2在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个第一电源线71的第一电源块71-1和第二电源块71-2的位置和形状可以相对于至少一个阳极的第一阳极中心线OX基本上镜像对称。例如，一条第一电源线71的第一电源块71-1和第二电源块71-2的位置和形状相对于第三阳极90C的第一阳极中心线OX基本上镜像对称。又如，另一条第一电源线71的第一电源块71-1和第二电源块71-2的位置和形状相对于第四阳极90D的第一阳极中心线OX基本上镜像对称。
在示例性实施方式中，至少一个第一电源线71中，第一电源块71-1在基底上的正投影与阳极主体部在基底上的正投影具有第一交叠区域，第二电源块71-2在基底上的正投影与阳极主体部在基底上的正投影具有第二交叠区域，第一交叠区域的位置和形状与第二交叠区域的位置和形状可以相对于该阳极的第一阳极中心线OX基本上镜像对称。例如，第一交叠区域的位置和形状与第二交叠区域的位置和形状可以相对于第三阳极90C的第一阳极中心线OX基本上镜像对称。又如，第一交叠区域的位置和形状与第二交叠区域的位置和形状可以相对于第四阳极90D的第一阳极中心线OX基本上镜像对称。
在示例性实施方式中，第一方向X上相邻的两个电路单元中的两条第一电源线71中，一条第一电源线71中的第一电源块71-1在基底上的正投影与阳极主体部在基底上的正投影具有第一交叠区域，另一条第一电源线71中的第一电源块71-1在基底上的正投影与阳 极主体部在基底上的正投影具有第三交叠区域，第一交叠区域的位置和形状与第三交叠区域的位置和形状可以相对于该阳极的第二阳极中心线OY基本上镜像对称。
在示例性实施方式中，第一方向X上相邻的两个电路单元中的两条第一电源线71中，一条第一电源线71中的第二电源块71-2在基底上的正投影与阳极主体部在基底上的正投影具有第二交叠区域，另一条第一电源线71中的第二电源块71-2在基底上的正投影与阳极主体部在基底上的正投影具有第四交叠区域，第二交叠区域的位置和形状与第四交叠区域的位置和形状可以相对于该阳极的第二阳极中心线OY基本上镜像对称。
在示例性实施方式中，至少一个屏蔽电极74在基底上的正投影与至少一个阳极的阳极主体部在基底上的正投影至少部分交叠。例如，至少一个屏蔽电极74在基底上的正投影与第三阳极90C的阳极主体部在基底上的正投影至少部分交叠。又如，至少一个屏蔽电极74在基底上的正投影与第四阳极90D的阳极主体部在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个屏蔽电极74在基底上的正投影与至少一个阳极的第二阳极中心线OY在基底上的正投影至少部分交叠。例如，至少一个屏蔽电极74在基底上的正投影与第三阳极90C的第二阳极中心线OY在基底上的正投影至少部分交叠。又如，至少一个屏蔽电极74在基底上的正投影与第四阳极90D的第二阳极中心线OY在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个阳极的阳极连接部在基底上的正投影与第二连接电极52在基底上的正投影没有交叠。
在示例性实施方式中，至少一个阳极的阳极连接部可以包括第一连接子部90-1和第二连接子部90-2，第一连接子部90-1和第二连接子部90-2被配置为避免与第二连接电极52交叠。
在示例性实施方式中，第一阳极90A和第二阳极90B的阳极连接部可以至少包括第一连接子部90-1和第二连接子部90-2，第一连接子部90-1的第一端与阳极主体部连接，第一连接子部90-1的第二端沿着第一方向X向着远离阳极主体部的方向延伸后，与第二连接子部90-2的第一端连接，第二连接子部90-2的第二端沿着第二方向Y向着远离第一连接子部90-1的方向延伸，使得第一阳极90A和第二阳极90B的阳极连接部避开第二连接电极52的所在区域。
在示例性实施方式中，第一连接子部90-1在基底上的正投影与第二连接电极52在基底上的正投影没有交叠，第二连接子部90-2基底上的正投影与第二连接电极52在基底上的正投影没有交叠，以有效减少第二节点N2的寄生电容。
在示例性实施方式中，阳极导电层可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层图案，然后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，然后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
一种显示基板存在发光信号线提供导通信号时出现瞬间大电流的问题，影响了显示效果。研究发现，出现瞬间大电流是由于第二节点N2的寄生电容较大导致的。由于像素驱动电路中的第三初始信号线通过第八晶体管T8与第二节点N2连接，因而当第二节点N2的寄生电容较大时，相当于第二节点N2存在一个存储第三初始信号线的偏置电压(on bias)的大电容，在发光信号线提供导通信号(第六晶体管T6导通)时，第二节点N2的寄生电容中的电荷量优先释放，进而出现瞬间大电流。
本公开示例性实施例提供了一种显示基板，通过布局调整和结构优化，有效减小了第二节点N2的寄生电容，使得第二节点N2的寄生电容减小9.35f，有效避免了出现瞬间大电流的问题，且大大减小了第六晶体管T6导通的瞬态电流，提高了显示品质和显示效果。
本公开通过设置第二连接电极与第四扫描信号线没有交叠，不仅可以减少第二节点N2的寄生电容，而且可以减小对数据信号写入过程的影响。
本公开通过设置第一扫描信号线和第一遮挡线为非等宽度，第二连接电极与宽度较小的第一扫描信号线和第一遮挡线交叠，有效减少了第二节点N2与第一扫描信号线和第一遮挡线之间的寄生电容。
本公开通过设置第一电源线与第二连接电极没有交叠，屏蔽电极与第二连接电极没有交叠，阳极连接部与第二连接电极没有交叠，可以最大限度地减少第二节点N2的寄生电容。
本公开通过设置屏蔽电极设置在相邻的第二连接电极之间，具有恒定电位的屏蔽电极可以有效相邻电路单元中第二节点N2的相互影响，提高了像素驱动电路的驱动性能。
本公开通过设置第一连接电极与第一扫描信号线交叠，增加了第一扫描信号线和第一节点N1之间的寄生电容，利用第一扫描信号线的下降沿将第一节点N1的电位拉低，从而增大电流，可以有效提升显示亮度。
本公开通过设置第一电源线与第一连接电极交叠，可以有效避免数据电压跳变和其它信号影响第一节点N1的电位，提高了像素驱动电路的驱动性能。本公开通过设置第一电源线与第二晶体管的有源层交叠，可以防止氧化物第二晶体管因光照发生特性漂移，提高了氧化物第二晶体管的电学特性。
本公开通过设置屏蔽电极与阳极的第二阳极中心线交叠，通过设置第一电源线、第一电源块和第二电源块相对于第二阳极中心线镜像对称，第一电源块和第二电源块71相对于第一阳极中心线镜像对称，可以有效提高阳极的平坦性，可以避免阳极高度差，可以保证各个区域中发光器件的发光性能基本上相同，不仅避免了大视角色偏，而且避免了熄屏水印等不良，提高了显示基板的品质。
本公开通过设置主体部分沿第一方向延伸的第一初始信号线和主体部分沿第二方向延伸的第一初始连接线，通过设置主体部分沿第一方向延伸的第二初始信号线和主体部分沿第二方向延伸的第二初始连接线，通过设置主体部分沿第一方向延伸的第三初始信号线和主体部分沿第三方向延伸的第二初始连接线，使得第一初始信号线、第二初始信号线和第三初始信号线分别形成网状连通结构，不仅有效降低了初始信号线的电阻，减小了初始电压的压降，而且有效提升了显示基板中初始电压的均一性，有效提升了显示均一性，提高了显示品质和显示质量。
本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的其它显示装置中，如量子点显示等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述制备方法可以包括：
在基底上形成驱动电路层，所述驱动电路层包括多个电路单元，至少一个电路单元至少包括像素驱动电路和第一电源线，所述第一电源线被配置为向所述像素驱动电路提供第一电源线号；至少一个电路单元还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接；
在所述驱动电路层上形成发光结构层，所述发光结构层包括多个发光单元，至少一个 发光单元至少包括阳极，所述阳极包括阳极主体部和阳极连接部，所述阳极连接部的一端与所述阳极主体部连接，所述阳极连接部的另一端与所述像素驱动电路连接；至少一个屏蔽电极在所述基底上的正投影与至少一个阳极的第二阳极中心线在所述基底上的正投影至少部分交叠，所述第二阳极中心线是在第一方向上平分所述阳极主体部且沿着第二方向延伸的直线，所述第一方向和所述第二方向交叉。
本公开还提供一种显示装置，显示装置包括前述的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
虽然本公开所揭露的实施方式如上，但应该注意，上述实施方式仅仅是示例性的，而不是限制性的。因此，本公开不限于在此具体示出和描述的内容。可以对实施的形式及细节进行多种修改、替换或省略，而不脱离本公开的范围。

Claims (19)

  1. 一种显示基板，包括设置在基底上的驱动电路层以及设置在所述驱动电路层远离所述基底一侧的发光结构层；所述驱动电路层包括多个电路单元，至少一个电路单元至少包括像素驱动电路和第一电源线，所述第一电源线被配置为向所述像素驱动电路提供第一电源线号；所述发光结构层包括多个发光单元，至少一个发光单元至少包括阳极，所述阳极包括阳极主体部和阳极连接部，所述阳极连接部的一端与所述阳极主体部连接，所述阳极连接部的另一端与所述像素驱动电路连接；至少一个电路单元还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接，至少一个屏蔽电极在所述基底上的正投影与至少一个阳极的第二阳极中心线在所述基底上的正投影至少部分交叠，所述第二阳极中心线是在第一方向上平分所述阳极主体部且沿着第二方向延伸的直线，所述第一方向和所述第二方向交叉。
  2. 根据权利要求1所述的显示基板，其中，至少一个阳极的阳极主体部在所述基底上的正投影与所述第一方向上相邻的两个电路单元中的两条第一电源线在所述基底上的正投影至少部分交叠，所述两条第一电源线相对于所述第二阳极中心线镜像对称。
  3. 根据权利要求1所述的显示基板，其中，至少一条第一电源线上设置有第一电源块和第二电源块，至少一个阳极的阳极主体部在所述基底上的正投影与所述第一电源块和所述第二电源块在所述基底上的正投影至少部分交叠，所述第一电源块和所述第二电源块相对于第一阳极中心线镜像对称，所述第一阳极中心线是在所述第二方向Y上平分所述阳极主体部且沿着所述第一方向延伸的直线。
  4. 根据权利要求3所述的显示基板，其中，至少一个阳极的阳极主体部在所述基底上的正投影与所述第一方向上相邻的两个电路单元中的两个第一电源块在所述基底上的正投影至少部分交叠，所述两个第一电源块相对于所述第二阳极中心线镜像对称；至少一个阳极的阳极主体部在所述基底上的正投影与所述第一方向上相邻的两个电路单元中的两个第二电源块在所述基底上的正投影至少部分交叠，所述两个第二电源块相对于所述第二阳极中心线镜像对称。
  5. 根据权利要求1所述的显示基板，其中，所述像素驱动电路至少包括作为补偿晶体管的第二晶体管和作为驱动晶体管的第三晶体管，所述第二晶体管的栅电极与第一扫描信号线连接，所述第二晶体管的第一极通过第二节点电极与所述第三晶体管的第二极连接，所述第二晶体管的第二极通过第一节点电极与所述第三晶体管的栅电极连接；所述阳极连接部在所述基底上的正投影与所述第二节点电极在所述基底上的正投影没有交叠。
  6. 根据权利要求5所述的显示基板，其中，所述第一电源线在所述基底上的正投影与所述第二节点电极在所述基底上的正投影没有交叠。
  7. 根据权利要求5所述的显示基板，其中，所述屏蔽电极设置在所述第一方向相邻两个电路单元的所述第二节点电极之间。
  8. 根据权利要求5所述的显示基板，其中，所述屏蔽电极在所述基底上的正投影与所述第二节点电极在所述基底上的正投影没有交叠。
  9. 根据权利要求5所述的显示基板，其中，所述像素驱动电路还包括作为数据写入晶体管的第四晶体管，所述第四晶体管的栅电极与第四扫描信号线连接，所述第四晶体管的第一极与数据信号线连接，所述第四晶体管的第二极与所述第三晶体管的第一极连接，所述第二节点电极在所述基底上的正投影与所述第四扫描信号线在所述基底上的正投影没有交叠。
  10. 根据权利要求5所述的显示基板，其中，所述第一扫描信号线至少包括相互连接的第一子扫描线段和第二子扫描线段，所述第一子扫描线段的宽度大于所述第二子扫 描线段的宽度，所述宽度为所述第二方向的尺寸；所述第二节点电极在所述基底上的正投影与所述第一子扫描线段在所述基底上的正投影没有交叠，所述第二节点电极在所述基底上的正投影与所述第二子扫描线段在所述基底上的正投影至少部分交叠。
  11. 根据权利要求5所述的显示基板，其中，至少一个电路单元还包括第一遮挡线，所述第一遮挡线至少包括相互连接的第一子遮挡线段和第二子遮挡线段，所述第一子遮挡线段的宽度大于所述第二子遮挡线段的宽度，所述宽度为所述第二方向的尺寸；所述第二节点电极在所述基底上的正投影与所述第一子遮挡线段在所述基底上的正投影没有交叠，所述第二节点电极在所述基底上的正投影与所述第二子扫描线段在所述基底上的正投影至少部分交叠。
  12. 根据权利要求5所述的显示基板，其中，所述第一节点电极在所述基底上的正投影与所述第一扫描信号线在所述基底上的正投影至少部分交叠。
  13. 根据权利要求12所述的显示基板，其中，所述第一节点电极的第一端与所述第二晶体管的第二极连接，所述第一节点电极的第二端与所述第三晶体管的栅电极连接；所述第一节点电极的第一端连接有第一补偿块，所述第一补偿块在所述基底上的正投影与所述第一扫描信号线在所述基底上的正投影至少部分交叠。
  14. 根据权利要求5所述的显示基板，其中，所述第一电源线在所述基底上的正投影与所述第一节点电极在所述基底上的正投影至少部分交叠。
  15. 根据权利要求5所述的显示基板，其中，所述第一电源线在所述基底上的正投影与所述第二晶体管的有源层在所述基底上的正投影至少部分交叠。
  16. 根据权利要求1至15任一项所述的显示基板，其中，至少一个电路单元还包括沿着所述第一方向延伸的第一初始信号线和沿着所述第二方向延伸的第一初始连接线，所述第一初始信号线被配置为向所述像素驱动电路提供第一初始信号，所述第一初始信号连接线与所述第一初始信号线连接，形成传输所述第一初始信号的网状连通结构，和/或，至少一个电路单元还包括沿着所述第一方向延伸的第二初始信号线和沿着所述第二方向延伸的第二初始连接线，所述第二初始信号线被配置为向所述像素驱动电路提供第二初始信号，所述第二初始信号连接线与所述第二初始信号线连接，形成传输所述第二初始信号的网状连通结构，和/或，至少一个电路单元还包括沿着所述第一方向延伸的第三初始信号线和沿着所述第二方向延伸的第三初始连接线，所述第三初始信号线被配置为向所述像素驱动电路提供第三初始信号，所述第三初始信号连接线与所述第三初始信号线连接，形成传输所述第三初始信号的网状连通结构。
  17. 根据权利要求16所述的显示基板，其中，所述第一初始连接线、所述第二初始连接线和所述第三初始连接线中的至少一个包括相互连接的第一初始连接电极和第二初始连接电极；在垂直于所述基底的方向上，所述驱动电路层包括多个导电层，所述第一初始连接电极和所述第二初始连接电极设置在不同的导电层中。
  18. 一种显示装置，包括如权利要求1至17任一项所述的显示基板。
  19. 一种显示基板的制备方法，包括：
    在基底上形成驱动电路层，所述驱动电路层包括多个电路单元，至少一个电路单元至少包括像素驱动电路和第一电源线，所述第一电源线被配置为向所述像素驱动电路提供第一电源线号；至少一个电路单元还包括屏蔽电极，所述屏蔽电极与所述第一电源线连接；
    在所述驱动电路层上形成发光结构层，所述发光结构层包括多个发光单元，至少一个发光单元至少包括阳极，所述阳极包括阳极主体部和阳极连接部，所述阳极连接部的一端与所述阳极主体部连接，所述阳极连接部的另一端与所述像素驱动电路连接；至少一个屏蔽电极在所述基底上的正投影与至少一个阳极的第二阳极中心线在所述基底上的正投影至少部分交叠，所述第二阳极中心线是在第一方向上平分所述阳极主体部且沿着第二方向 延伸的直线，所述第一方向和所述第二方向交叉。
PCT/CN2023/140335 2023-12-20 2023-12-20 显示基板及其制备方法、显示装置 Pending WO2025129506A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202380012435.5A CN120530740A (zh) 2023-12-20 2023-12-20 显示基板及其制备方法、显示装置
PCT/CN2023/140335 WO2025129506A1 (zh) 2023-12-20 2023-12-20 显示基板及其制备方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2023/140335 WO2025129506A1 (zh) 2023-12-20 2023-12-20 显示基板及其制备方法、显示装置

Publications (2)

Publication Number Publication Date
WO2025129506A1 true WO2025129506A1 (zh) 2025-06-26
WO2025129506A9 WO2025129506A9 (zh) 2025-08-21

Family

ID=96136178

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/140335 Pending WO2025129506A1 (zh) 2023-12-20 2023-12-20 显示基板及其制备方法、显示装置

Country Status (2)

Country Link
CN (1) CN120530740A (zh)
WO (1) WO2025129506A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115705821A (zh) * 2021-08-11 2023-02-17 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
WO2023039886A1 (zh) * 2021-09-18 2023-03-23 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN116613175A (zh) * 2023-06-21 2023-08-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115705821A (zh) * 2021-08-11 2023-02-17 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
WO2023039886A1 (zh) * 2021-09-18 2023-03-23 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN116613175A (zh) * 2023-06-21 2023-08-18 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
WO2025129506A9 (zh) 2025-08-21
CN120530740A (zh) 2025-08-22

Similar Documents

Publication Publication Date Title
WO2024260148A9 (zh) 显示基板及其制备方法、显示装置
WO2023241490A9 (zh) 显示基板和显示装置
WO2023016341A1 (zh) 显示基板及其制备方法、显示装置
WO2025065838A1 (zh) 显示基板及其驱动方法、显示装置
WO2024036629A1 (zh) 显示基板及其驱动方法、显示装置
WO2024065629A1 (zh) 显示基板及其制备方法、显示装置
WO2025055653A1 (zh) 显示基板及其制备方法、显示装置
WO2024092434A1 (zh) 显示基板及其制备方法、显示装置
WO2024234922A1 (zh) 显示基板及其制备方法、显示装置
WO2023206462A1 (zh) 显示基板及其制备方法、显示装置
WO2024031315A1 (zh) 显示基板及其制备方法、显示装置
WO2024036574A1 (zh) 显示基板及其制备方法、显示装置
WO2023221040A1 (zh) 显示基板及其制备方法、显示装置
WO2025086910A9 (zh) 显示基板及其制备方法、显示装置
WO2024234932A1 (zh) 显示基板及其制备方法、显示装置
WO2024244827A1 (zh) 显示基板、显示装置
WO2024221364A1 (zh) 显示基板及其制备方法、显示装置
WO2024086976A9 (zh) 显示基板及其制备方法、显示装置
WO2025129506A9 (zh) 显示基板及其制备方法、显示装置
WO2024216551A1 (zh) 显示基板及其制备方法、显示装置
WO2025081415A1 (zh) 显示基板及其制备方法、显示装置
WO2025039226A1 (zh) 显示基板及其驱动方法和制备方法、显示装置
WO2024221194A1 (zh) 显示基板及其制备方法、显示装置
WO2025065277A9 (zh) 显示基板及其制备方法、显示装置
WO2025015497A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202380012435.5

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 18856891

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23961846

Country of ref document: EP

Kind code of ref document: A1

WWP Wipo information: published in national office

Ref document number: 202380012435.5

Country of ref document: CN