WO2025129495A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2025129495A1
WO2025129495A1 PCT/CN2023/140232 CN2023140232W WO2025129495A1 WO 2025129495 A1 WO2025129495 A1 WO 2025129495A1 CN 2023140232 W CN2023140232 W CN 2023140232W WO 2025129495 A1 WO2025129495 A1 WO 2025129495A1
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WO
WIPO (PCT)
Prior art keywords
time period
signal line
time
driving circuit
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
PCT/CN2023/140232
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English (en)
French (fr)
Inventor
李孟
谢涛峰
徐元杰
肖星亮
柴铭志
李卓安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2023/140232 priority Critical patent/WO2025129495A1/zh
Priority to CN202380012437.4A priority patent/CN120530450A/zh
Publication of WO2025129495A1 publication Critical patent/WO2025129495A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a display substrate, wherein the content displayed by the display substrate includes a plurality of display frames, the display substrate includes: a data unit, a pixel driving circuit arranged in an array, a plurality of second reset signal lines, and a plurality of second scanning signal lines, at least one pixel driving circuit includes: a driving transistor, a compensation transistor, and a third reset transistor, wherein the driving transistor is respectively connected to a first node, a second node, and a third node, the compensation transistor is respectively connected to the second scanning signal line, the first node, and the third node, and the third reset transistor is respectively connected to the second reset signal line and the second node;
  • the data unit is configured to provide a valid level signal to a second reset signal line connected to at least one pixel driving circuit within a time period, and to provide a valid level signal to a second scanning signal line connected to at least one pixel driving circuit within a time period, or to provide a valid level signal to the second reset signal line connected to at least one pixel driving circuit within at least two time periods, and to provide a valid level signal to the second scanning signal line connected to at least one pixel driving circuit within at least two time periods.
  • it further includes: a plurality of first scan signal lines, a plurality of first reset signal lines, and a plurality of light emitting signal lines
  • at least one pixel driving circuit further includes: a write transistor, a first reset transistor, and a first light emitting transistor, wherein the write transistor is respectively connected to the first scan signal line and the second node, the first reset transistor is respectively connected to the first reset signal line and the third node, and the first light emitting transistor is respectively connected to the light emitting signal line and the second node;
  • the data unit is configured to provide a valid level signal to a first scan signal line connected to at least one pixel driving circuit in a first time period, provide a valid level signal to a first reset signal line connected to at least one pixel driving circuit in a second time period, provide a valid level signal to a light emitting signal line connected to at least one pixel driving circuit in a third time period, and provide an invalid level signal to a first scan signal line, a second scan signal line, a first reset signal line, a second reset signal line, and a light emitting signal line connected to at least one pixel driving circuit in a fourth time period;
  • the second time period occurs before the first time period, and the end time of the second time period occurs before the start time of the first time period; the first time period occurs before the fourth time period, and the end time of the first time period occurs before the start time of the fourth time period; the fourth time period occurs before the third time period, and the end time of the fourth time period is the start time of the third time period.
  • At least one time period during which a signal of a second scanning signal line to which at least one pixel driving circuit is connected is a valid level signal at least partially overlaps with at least one time period of the first time period and the second time period, and does not overlap with at least one time period of the third time period and the fourth time period;
  • At least one time period of the effective level signal of the signal of the second reset signal line connected to at least one pixel driving circuit does not overlap with at least one time period of the first time period, the second time period, the third time period and the fourth time period.
  • the sixth time period overlaps at least partially with the first time period and the second time period, respectively, and the fifth time period occurs after the sixth time period;
  • the fifth time period is the time period in which the data unit provides a valid level signal to the second reset signal line connected to at least one pixel driving circuit
  • the sixth time period is the time period in which the data unit provides a valid level signal to the second scan signal line connected to at least one pixel driving circuit.
  • the duration of the sixth time period is greater than the duration of the first time period, and greater than the duration of the second time period;
  • the first time period and the second time period are within the sixth time period.
  • the start time of the sixth time period occurs before the start time of the second time period
  • the end time of the sixth time period occurs after the end time of the first time period and before the start time of the fifth time period
  • the end time of the fifth time period is the start time of the fourth time period
  • the data unit is also configured to provide an invalid level signal to a first reset signal line, a second reset signal line, and a light-emitting signal line connected to at least one pixel driving circuit in a first time period, to provide an invalid level signal to a second reset signal line, a first scan signal line, and a light-emitting signal line connected to at least one pixel driving circuit in a second time period, to provide an invalid level signal to the first reset signal line, the second reset signal line, the first scan signal line, and the second scan signal line connected to at least one pixel driving circuit in a third time period, and to provide an invalid level signal to the first reset signal line, the first scan signal line, the second scan signal line, and the light-emitting signal line connected to at least one pixel driving circuit in a fifth time period.
  • the seventh time period at least partially overlaps with the fifth time period
  • the eighth time period at least partially overlaps with the first time period and the second time period, respectively
  • the sixth time period occurs after the eighth time period
  • the fifth time period and the sixth time period are time periods in which the data unit provides a valid level signal to a second reset signal line connected to at least one pixel driving circuit, and the fifth time period occurs before the sixth time period
  • the seventh time period and the eighth time period are time periods in which the data unit provides a valid level signal to a second scanning signal line connected to at least one pixel driving circuit, and the seventh time period occurs before the eighth time period.
  • the duration of the seventh time period is greater than the duration of the fifth time period, and the duration of the eighth time period is greater than the sum of the duration of the first time period and the duration of the second time period;
  • the fifth time period is within the seventh time period, and the first time period and the second time period are within the eighth time period.
  • the start time of the seventh time period occurs at the start time of the fifth time period.
  • the end time of the seventh time period occurs after the start time of the fifth time period
  • the start time of the eighth time period occurs before the start time of the second time period
  • the end time of the eighth time period occurs after the end time of the first time period and before the start time of the sixth time period
  • the end time of the sixth time period is the start time of the fourth time period.
  • the duration of the eighth time period is greater than the duration of the seventh time period, the duration of the seventh time period is greater than twice the duration of the ninth time period, the start time of the ninth time period is the end time of the seventh time period, and the end time of the ninth time period is the start time of the eighth time period;
  • the data unit provides an invalid level signal to a first scanning signal line, a second scanning signal line, a first reset signal line, a second reset signal line and a light emitting signal line connected to at least one pixel driving circuit in the ninth time period.
  • the seventh time period at least partially overlaps with the fifth time period and the second time period, respectively, the eighth time period at least partially overlaps with the first time period, and the sixth time period occurs after the eighth time period;
  • the fifth time period and the sixth time period are time periods in which the data unit provides a valid level signal to a second reset signal line connected to at least one pixel driving circuit, and the fifth time period occurs before the sixth time period
  • the seventh time period and the eighth time period are time periods in which the data unit provides a valid level signal to a second scanning signal line connected to at least one pixel driving circuit, and the seventh time period occurs before the eighth time period.
  • the duration of the seventh time period is greater than the sum of the duration of the fifth time period and the duration of the second time period, and the duration of the eighth time period is greater than the duration of the first time period;
  • the second time period and the fifth time period are within the seventh time period, and the first time period is within the eighth time period.
  • the start time of the seventh time period occurs before the start time of the fifth time period
  • the end time of the seventh time period occurs after the end time of the second time period
  • the start time of the eighth time period occurs before the start time of the first time period
  • the end time of the eighth time period occurs after the end time of the first time period and before the start time of the sixth time period
  • the end time of the sixth time period is the start time of the fourth time period.
  • the duration of the seventh time period is greater than four times the duration of the eighth time period and greater than four times the duration of the ninth time period
  • the start time of the ninth time period is the end time of the seventh time period
  • the end time of the ninth time period is the start time of the eighth time period.
  • the seventh time period at least partially overlaps with the fifth time period
  • the eighth time period at least partially overlaps with the second time period
  • the ninth time period at least partially overlaps with the first time period
  • the sixth time period occurs between the ninth time period and the fourth time period
  • the fifth time period and the sixth time period are time periods in which the data unit provides a valid level signal to a second reset signal line connected to at least one pixel driving circuit, and the fifth time period occurs before the sixth time period
  • the seventh time period, the eighth time period and the ninth time period are time periods in which the data unit provides a valid level signal to a second scanning signal line connected to at least one pixel driving circuit
  • the seventh time period occurs before the eighth time period
  • the eighth time period occurs before the ninth time period.
  • the duration of the seventh time period is greater than the duration of the fifth time period
  • the duration of the eighth time period is greater than the duration of the second time period
  • the duration of the ninth time period is greater than the duration of the first time period
  • the fifth time period is within the seventh time period, the second time period is within the eighth time period, and the first time period is within the ninth time period.
  • the start time of the seventh time period occurs before the start time of the fifth time period
  • the end time of the seventh time period occurs after the end time of the fifth time period
  • the start time of the eighth time period occurs before the start time of the second time period
  • the end time of the eighth time period occurs after the end time of the second time period
  • the start time of the ninth time period occurs before the start time of the first time period
  • the end time of the ninth time period occurs after the end time of the first time period
  • the end time of the sixth time period is the start time of the fourth time period.
  • the duration of at least one of the seventh time period and the eighth time period is greater than the duration of the ninth time period, and greater than the duration of at least one of the tenth time period and the eleventh time period, the start time of the tenth time period is the end time of the seventh time period, the end time of the tenth time period is the start time of the eighth time period, the start time of the eleventh time period is the end time of the eighth time period, and the end time of the eleventh time period is the start time of the ninth time period;
  • the data unit provides an inactive level signal to a first scanning signal line, a second scanning signal line, a first reset signal line, a second reset signal line, and a light emitting signal line connected to at least one pixel driving circuit in the tenth time period and the eleventh time period.
  • the data unit is also configured to provide an invalid level signal to a first reset signal line, a second reset signal line, and a light-emitting signal line connected to at least one pixel driving circuit in a first time period, provide an invalid level signal to a second reset signal line, a first scan signal line, and a light-emitting signal line connected to at least one pixel driving circuit in a second time period, provide an invalid level signal to the first reset signal line, the second reset signal line, the first scan signal line, and the second scan signal line connected to at least one pixel driving circuit in a third time period, provide an invalid level signal to the first reset signal line, the first scan signal line, and the light-emitting signal line connected to at least one pixel driving circuit in a fifth time period, and provide an invalid level signal to the first reset signal line, the first scan signal line, the second scan signal line, and the light-emitting signal line connected to at least one pixel driving circuit in a sixth time period.
  • it further includes: a plurality of light emitting signal lines, a plurality of first reset signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, a plurality of first scanning signal lines, and a plurality of first power supply lines
  • at least one pixel driving circuit further includes: a first reset transistor, a second reset transistor, a write transistor, a first light emitting transistor, a second light emitting transistor, and a capacitor;
  • the control electrode of the compensation transistor is connected to the second scanning signal line, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the third node;
  • the control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node;
  • the control electrode of the write transistor is connected to the first scan signal line, the first electrode of the write transistor is connected to the data signal line, and the second electrode of the write transistor is connected to the second node;
  • the control electrode of the first reset transistor is connected to the first reset signal line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the third node;
  • the control electrode of the second reset transistor is connected to the second reset signal line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the fourth node;
  • the control electrode of the third reset transistor is connected to the second reset signal line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the second node;
  • the control electrode of the first light emitting transistor is connected to the light emitting signal line, the first electrode of the first light emitting transistor is connected to the first power line, and the second electrode of the first light emitting transistor is connected to the second node;
  • the control electrode of the second light emitting transistor is connected to the light emitting signal line, the first electrode of the second light emitting transistor is connected to the third node, and the second electrode of the second light emitting transistor is connected to the fourth node;
  • One end of the capacitor is connected to the first power line, and the other end of the capacitor is connected to the first node.
  • At least one transistor in at least one pixel driving circuit is a P-type transistor or an N-type transistor
  • the first light emitting transistor and the second light emitting transistor are of the same transistor type
  • the second reset transistor and the third reset transistor are of the same transistor type.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • the present disclosure further provides a method for driving a display substrate, which is configured to drive the above-mentioned display substrate, and the method includes:
  • a valid level signal is provided to a second reset signal line connected to at least one pixel driving circuit in a time period, and a valid level signal is provided to a second scanning signal line connected to at least one pixel driving circuit in a time period, or a valid level signal is provided to a second reset signal line connected to at least one pixel driving circuit in at least two time periods, and a valid level signal is provided to a second scanning signal line connected to at least one pixel driving circuit in at least two time periods.
  • FIG1 is a schematic structural diagram of a display substrate
  • FIG2A is a schematic diagram of a planar structure of a display substrate
  • FIG2B is a second schematic diagram of a planar structure of a display substrate
  • FIG2C is a third schematic diagram of a planar structure of a display substrate
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate provided in an embodiment of the present disclosure
  • FIG5 is a working timing diagram 1 of the pixel driving circuit provided in FIG4 ;
  • FIG6 is a second working timing diagram of the pixel driving circuit provided in FIG4 ;
  • FIG. 7 is a third working timing diagram of the pixel driving circuit provided in FIG. 4 ;
  • FIG. 8 is a fourth working timing diagram of the pixel driving circuit provided in FIG. 4 .
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • FIG. 1 is a schematic diagram of the structure of a display substrate.
  • the display substrate may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, wherein the timing controller is respectively connected to the data driver, the scan driver, and the light emitting driver, wherein the data driver is respectively connected to a plurality of data signal lines, the scan driver is respectively connected to a plurality of scan signal lines, and the light emitting driver is respectively connected to a plurality of light emitting signal lines.
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light emitting signal line, and the data signal line.
  • the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc.
  • the data driver may generate a data voltage to be provided to the data signal line using the grayscale value and the control signal received from the timing controller. For example, the data driver can sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.
  • the scan driver can generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver can sequentially provide a scan signal with a conduction level pulse to the scan signal line.
  • the scan driver can be constructed in the form of a shift register, and can sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit to generate the scan signal under the control of the clock signal.
  • the light-emitting driver can generate an emission signal to be provided to the light-emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller.
  • the light-emitting driver can sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal line.
  • the light-emitting driver can be constructed in the form of a shift register, and can sequentially transmit the emission stop signal provided in the form of a cut-off level pulse to the next level circuit to generate the emission signal under the control of the clock signal.
  • FIG2A is a schematic diagram of a planar structure of a display substrate
  • FIG2B is a schematic diagram of a planar structure of a display substrate
  • FIG2C is a schematic diagram of a planar structure of a display substrate.
  • the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light
  • the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line, and output the corresponding current to the light emitting device.
  • the light emitting devices in the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels, and the light emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of the sub-pixels.
  • the first subpixel P1 may be a red subpixel (R) emitting red light
  • the second subpixel P2 may be a blue subpixel (B) emitting blue light
  • the third subpixel P3 may be a green subpixel (G) emitting green light.
  • the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon, which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a herringbone manner, which is not limited in the present disclosure.
  • FIG2A is an example in which a pixel unit includes three sub-pixels, and the three sub-pixels are arranged in a horizontal parallel manner
  • FIG2B is an example in which a pixel unit includes three sub-pixels, and the three sub-pixels are arranged in a herringbone manner.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, square or diamond shape, etc., which is not limited in the present disclosure.
  • FIG. 2C is an example in which a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square shape.
  • the shape of the sub-pixel may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged horizontally, vertically or in a herringbone pattern, which is not limited in the present disclosure.
  • FIG3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of the display substrate.
  • the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101.
  • the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.
  • the substrate 101 may be a flexible substrate, or may be a rigid substrate.
  • the driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit, and FIG3 only takes one transistor 101 and one capacitor 101A as an example.
  • the light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303 and a cathode 304, the anode 301 being connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 being connected to the anode 301, and the cathode 304 being connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304.
  • the encapsulation structure layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403.
  • the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials.
  • the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the organic light emitting layer 303 may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.
  • the touch structure layer of each sub-pixel may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer;
  • the first touch metal layer may include a plurality of bridging electrodes;
  • the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes; and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.
  • the pixel driving circuit in the display substrate may include: a driving transistor and a compensation transistor, wherein the compensation transistor is respectively connected to the gate electrode and the drain electrode of the driving transistor to charge and compensate the gate electrode of the driving transistor.
  • the compensation transistor is a metal oxide transistor.
  • FIG4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate provided in an embodiment of the present disclosure
  • FIG5 is a first operation timing diagram of the pixel driving circuit provided in FIG4
  • FIG6 is a second operation timing diagram of the pixel driving circuit provided in FIG4
  • FIG7 is a third operation timing diagram of the pixel driving circuit provided in FIG4
  • FIG8 is a fourth operation timing diagram of the pixel driving circuit provided in FIG4 .
  • an embodiment of the present disclosure provides a display substrate, and the content displayed by the display substrate includes a plurality of display frames, and the display substrate includes: a data unit, an array-arranged pixel driving circuit, a plurality of second reset signal lines Reset2, and a plurality of second scan signal lines Gate2.
  • At least one pixel driving circuit includes: a driving transistor T3, a compensation transistor T4, and a second reset signal line Reset2.
  • the data unit comprises a transistor T2 and a third reset transistor T8, wherein the driving transistor T3 is connected to the first node N1, the second node N2 and the third node N3, respectively, the compensation transistor T2 is connected to the second scanning signal line Gate2, the first node N1 and the third node N3, respectively, and the third reset transistor T8 is connected to the second reset signal line Reset2 and the second node N2, respectively.
  • the data unit is configured to provide an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit in one time period, and to provide an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit in one time period, or to provide an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit in at least two time periods, and to provide an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit in at least two time periods.
  • FIG. 5 to 7 are described by taking the case where the data unit is configured to provide an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit in at least two time periods, and to provide an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit in at least two time periods.
  • FIG. 8 is described by taking the case where the data unit is configured to provide an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit in one time period, and to provide an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit in one time period.
  • an effective level signal of a signal line refers to a signal that can turn on a transistor connected to the signal line
  • an ineffective level signal of a signal line refers to a signal that can turn off a transistor connected to the signal line.
  • the display substrate provided by the embodiment of the present disclosure includes: a first driving mode and a second driving mode, the refresh rate of the first driving mode is less than the refresh rate of the second driving mode, for example: the refresh rate of the first driving mode can be 1HZ-60HZ, and the refresh rate of the second driving mode can be 60HZ-480HZ.
  • the content displayed by the display substrate includes multiple display frames.
  • the display frame includes: a refresh frame and at least one hold frame.
  • the display frame only includes: a refresh frame.
  • the first driving mode may be referred to as a low-frequency driving mode
  • the second driving mode may be referred to as a high-frequency driving mode
  • the refresh rate refers to the number of times the display substrate refreshes data within one second.
  • the refresh rate of the first drive mode set for the same display substrate is fixed, and the refresh rates of the first drive modes set for different display substrates may be different.
  • the refresh rate of the display substrate in the first drive mode may range from 1 Hz to 60 Hz, and exemplarily, the refresh rate in the first drive mode may be about 10 Hz.
  • the display substrate in order to reduce the power consumption of the product, will adopt the first drive mode and the second drive mode to alternately display the function.
  • the display substrate refreshes the display data in the refresh frame and maintains the display data refreshed in the refresh frame in the hold frame.
  • a display frame may include a refresh frame but not a hold frame.
  • the display substrate refreshes the display data in the refresh frame.
  • the refresh rate of the display substrate in the second drive mode can range from 60Hz to 480Hz.
  • the refresh rate in the first drive mode can be about 120Hz.
  • the data unit is configured to provide a signal in a refresh frame.
  • a time period in which the data unit provides an effective level signal to the second scan signal line Gate2 connected to at least one pixel driving circuit does not overlap with at least one time period in which the data unit provides an effective level signal to the second scan signal line Gate2 connected to at least one pixel driving circuit.
  • the data unit is configured to provide an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit within a time period, and to provide an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit within a time period, and the time for the data unit to provide the effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit can be reduced by reducing the time for the data unit to provide the effective level signal to the second reset signal line Reset2 connected to the at least one pixel driving circuit.
  • the time for providing the effective level signal to the second scan signal line Gate2 connected to the at least one pixel driving circuit is reduced, that is, the conduction time of the compensation transistor is reduced, or the data unit is configured to provide the effective level signal to the second reset signal line Reset2 connected to the at least one pixel driving circuit in at least two time periods, and provide the effective level signal to the second scan signal line Gate2 connected to the at least one pixel driving circuit in at least two time periods, and the effective level signal can be provided to the second scan signal line Gate2 connected to the at least one pixel driving circuit in at least two time periods, thereby reducing the time for providing the effective level signal to the second scan signal line Gate2 connected to the at least one pixel driving circuit.
  • the time of the level signal that is, the conduction time of the compensation transistor is reduced, thereby reducing the positive bias temperature stress of the compensation transistor caused by the high-temperature operation of the display substrate, ensuring the consistency of the signal of the first node of at least one pixel driving circuit, avoiding the display substrate from generating reliability horizontal stripes, ensuring the display uniformity of the display substrate, and improving the display effect of the display substrate.
  • FIG4 is an equivalent circuit diagram of the pixel driving circuit of the display substrate provided in an embodiment of the present disclosure
  • FIG5 is a working timing diagram 1 of the pixel driving circuit provided in FIG4
  • FIG6 is a working timing diagram 2 of the pixel driving circuit provided in FIG4
  • FIG7 is a working timing diagram 3 of the pixel driving circuit provided in FIG4
  • FIG8 is a working timing diagram 4 of the pixel driving circuit provided in FIG4.
  • the pixel driving circuit may include eight transistors (a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a writing transistor T4 , a first light emitting transistor T5 , a second light emitting transistor T6 , a second reset transistor T7 and a third reset transistor T4 ) and a capacitor C.
  • the display substrate may further include: a plurality of second scan signal lines Gate2, a plurality of first reset signal lines Reset1, a plurality of second reset signal lines Reset2, a plurality of emission signal lines EM, a plurality of first initial signal lines Vinit1, a plurality of second initial signal lines Vinit2, a plurality of third initial signal lines Vinit3 and a plurality of first power lines VDD.
  • the scan signal lines may include a first scan signal line Gate1 , a second scan signal line Gate2 , a first reset signal line Reset1 , and a second reset signal line Reset2 .
  • one end of the capacitor C is electrically connected to the first node N1, and the other end of the capacitor C is electrically connected to the first power supply line VDD.
  • the control electrode of the first reset transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line Vinit1, and the second electrode of the first reset transistor T1 is electrically connected to the third node N3.
  • the control electrode of the compensation transistor T2 is electrically connected to the second scan signal line Gate2, the first electrode of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode of the compensation transistor T2 is electrically connected to the second node N2.
  • the control electrode of the drive transistor T3 is electrically connected to the first node N1, the first electrode of the drive transistor T3 is electrically connected to the second node N2, and the second electrode of the drive transistor T3 is electrically connected to the third node N3.
  • the control electrode of the write transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the write transistor T4 is electrically connected to the data signal line Data, and the second electrode of the write transistor T4 is electrically connected to the second node N2.
  • the control electrode of the first light emitting transistor T5 is electrically connected to the light emitting signal line EM, the first electrode of the first light emitting transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the first light emitting transistor T5 is electrically connected to the second node N2.
  • the control electrode of the second light emitting transistor T6 is electrically connected to the light emitting signal line EM, the first electrode of the second light emitting transistor T6 is electrically connected to the third node N3, and the second electrode of the second light emitting transistor T6 is electrically connected to the fourth node N4.
  • the control electrode of the second reset transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4.
  • the control electrode of the third reset transistor T8 is electrically connected to the second reset signal line Reset2, the first electrode of the third reset transistor T8 is electrically connected to the third initial signal line Vinit3, and the second electrode of the third reset transistor T8 is electrically connected to the second node N2.
  • the second reset signal line Reset2 connected to the second reset transistor T7 and the second reset signal line Reset2 connected to the third reset transistor T8 may be the same signal line, or may be different signal lines with the same signal, which is not limited in the present disclosure.
  • the display substrate may further include: a second power line VSS.
  • the light emitting device L may be electrically connected to the fourth node N4 and the second power line VSS.
  • the light emitting element L may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
  • the OLED may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), the first electrode of the OLED being connected to the fourth node N4, and the second electrode of the OLED being electrically connected to the second power line VSS.
  • the signal of the first power line VDD is a continuously provided high level signal
  • the signal of the second power line VSS is a low level signal
  • the first reset transistor T1 transmits the first initial signal of the first initial signal line Vinit1 to the third node N3 to initialize the charge amount of the third node N3.
  • the compensation transistor T2 transmits a signal of the third node N3 to the first node N1 and may threshold compensate the driving transistor T3 or initialize the charge amount of the first node N1.
  • the driving transistor T3 determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between the control electrode and the first electrode.
  • the write transistor T4 when the first scan signal line Gate1 inputs an active level signal, the write transistor T4 allows the data voltage of the data signal line Data to be input to the second node N2.
  • the first light emitting transistor T5 and the second light emitting transistor T6 enable the light emitting element to emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the second reset transistor T7 can be referred to as an anode reset transistor.
  • the second reset transistor T7 transmits the second initial signal of the second initial signal line Vinit2 to the anode of the light-emitting element L to initialize the charge amount of the anode of the light-emitting element.
  • the third reset transistor T8 can be called a second node reset transistor.
  • the third reset transistor T8 transmits the third initial signal of the third initial signal line Vinit3 to the second node N2, and can initialize the charge amount of the second node N2.
  • the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • At least one transistor in at least one pixel driving circuit is a P-type transistor or an N-type transistor
  • the first light emitting transistor T5 and the second light emitting transistor T6 are of the same transistor type
  • the second reset transistor T71 and the third reset transistor T8 are of the same transistor type.
  • FIG. 4 is illustrated by taking the compensation transistor T2 as an N-type transistor and the other transistors as P-type transistors as an example.
  • the first reset transistor T1 may be a P-type transistor or an N-type transistor.
  • the P-type transistor may be a low temperature polysilicon transistor
  • the N-type transistor may be a metal oxide transistor.
  • the compensation transistor T2 may be an N-type transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.
  • the display substrate when all transistors in the pixel driving circuit are P-type transistors and N-type transistors, the display substrate uses a low temperature polycrystalline oxide combination (Low Temperature + Poly-Silicon, referred to as LTPS) technology.
  • LTPS Low Temperature + Poly-Silicon
  • the LTPO technology has a smaller leakage current and a faster pixel response.
  • the display substrate has an additional A layer of oxide reduces the energy required to excite the pixels, thereby reducing power consumption when the screen is displayed.
  • the first initial signal line Vinit1 connected to at least one pixel driving circuit provides a first initial signal in a refresh frame and a hold frame, the first initial signal is a DC signal, and a voltage value of the first initial signal is constant.
  • the second initial signal line Vinit2 connected to at least one pixel driving circuit provides a second initial signal in a refresh frame and a hold frame, the second initial signal is a DC signal, and a voltage value of the second initial signal is constant.
  • the third initial signal line Vinit3 connected to at least one pixel driving circuit provides a third initial signal in a refresh frame and a hold frame, the third initial signal is a DC signal, and the voltage value of the third initial signal is constant.
  • the voltage value of the third initial signal provided by the third initial signal line Vinit3 may be approximately the voltage value of the signal of the first power line VDD.
  • the voltage value of the third initial signal may be approximately 5 volts to 8 volts.
  • the data unit in at least one display frame, is configured to provide an effective level signal to the first scan signal line Gate1 connected to at least one pixel driving circuit in the first time period t1, provide an effective level signal to the first reset signal line Reset1 connected to at least one pixel driving circuit in the second time period t2, provide an effective level signal to the light emitting signal line EM connected to at least one pixel driving circuit in the third time period t3, and provide an ineffective level signal to the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the light emitting signal line EM connected to at least one pixel driving circuit in the fourth time period t4.
  • the second time period t2 occurs before the first time period t1, and the end time of the second time period t2 occurs before the start time of the first time period t1, the first time period t1 occurs before the fourth time period t4, and the end time of the first time period t1 occurs before the start time of the fourth time period t4, the fourth time period t4 occurs before the third time period t3, and the end time of the fourth time period t4 is the start time of the third time period t3.
  • At least one time period during which the signal of the second scan signal line Gate2 connected to at least one pixel driving circuit is an effective level signal at least partially overlaps with at least one time period of the first time period t1 and the second time period t2, and does not overlap with at least one time period of the third time period t3 and the fourth time period t4;
  • At least one time period of the effective level signal of the signal of the second reset signal line Reset2 to which at least one pixel driving circuit is connected does not overlap with at least one time period of the first time period t1, the second time period t2, the third time period t3, and the fourth time period t4.
  • the sixth time period t6 overlaps at least partially with the first time period t1 and the second time period t2, respectively, and the fifth time period t5 occurs after the sixth time period t6.
  • the fifth time period t5 is a time period in which the data unit provides an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit
  • the sixth time period t6 is a time period in which the data unit provides an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit.
  • the duration of the sixth time period t6 is greater than the sum of the duration of the first time period t1 and the duration of the second time period t2 ; the first time period t1 and the second time period t2 are within the sixth time period t6 .
  • the start time of the sixth time period t6 occurs before the start time of the second time period t2
  • the end time of the sixth time period t6 occurs after the end time of the first time period t1
  • the start time of the fifth time period t5 is the start time of the fourth time period t4.
  • the duration of the sixth time period may be greater than 18 hours.
  • the data unit is further configured to provide an invalid level signal to the first reset signal line Reset1, the second reset signal line Reset2 and the light emitting signal line EM connected to the at least one pixel driving circuit in the first time period t1, provide an invalid level signal to the second reset signal line Reset2, the first scan signal line Gate1 and the light emitting signal line EM connected to the at least one pixel driving circuit in the second time period t2, provide an invalid level signal to the first reset signal line Reset1, the second reset signal line Reset2, the first scan signal line Gate1 and the second scan signal line Gate2 connected to the at least one pixel driving circuit in the third time period t3, and provide an invalid level signal to the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2 and the light emitting signal line EM connected to the at least one pixel driving circuit in the fifth time period t5.
  • the present disclosure reduces the time period for providing a valid level signal to a second scanning signal line connected to at least one pixel driving circuit by reducing the time period for providing a valid level signal to a second reset signal line connected to at least one pixel driving circuit by a data unit, thereby reducing the positive bias temperature stress of the compensation transistor, improving the display uniformity of the display substrate, and improving the display effect of the display substrate displaying a low grayscale display image without affecting the display effect of the display substrate.
  • the signal of the first reset signal line Reset1 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the second reset signal line Reset2 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the first scanning signal line Gate1 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the second scanning signal line Gate2 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the luminous signal line EM connected to at least one pixel driving circuit is a single pulse signal.
  • the seventh time period t7 at least partially overlaps with the fifth time period t5
  • the eighth time period t8 at least partially overlaps with the first time period t1 and the second time period t2, respectively
  • the sixth time period t6 occurs after the eighth time period t8.
  • the fifth time period t5 and the sixth time period t6 are time periods in which the data unit provides an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit, and the fifth time period t5 occurs before the sixth time period t6, the seventh time period t7 and the eighth time period t8 are time periods in which the data unit provides an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit, and the seventh time period t7 occurs before the eighth time period t8.
  • the duration of the seventh time period t7 is greater than the duration of the fifth time period t5
  • the duration of the eighth time period t8 is greater than the sum of the duration of the first time period t1 and the duration of the second time period t2
  • the fifth time period t5 is within the seventh time period t7
  • the first time period t1 and the second time period t2 are within the eighth time period t8.
  • the duration of the eighth time period t8 is greater than the duration of the seventh time period t7
  • the duration of the seventh time period t7 is greater than twice the duration of the ninth time period t9
  • the start time of the ninth time period t9 is the end time of the seventh time period t7
  • the end time of the ninth time period t9 is the start time of the eighth time period t8.
  • the data unit provides an invalid level signal to the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the light emitting signal line EM connected to at least one pixel driving circuit in the ninth time period t9.
  • the duration between the start time of the seventh time period t7 and the end time of the eighth time period t8 is 38H
  • the duration of the seventh time period t7 can be 14H
  • the duration of the eighth time period t8 can be 18H
  • the duration of the ninth time period can be 6H.
  • the durations of the seventh time period, the eighth time period and the ninth time period can be limited according to the display state of the display substrate, and the present disclosure does not make any limitation on this.
  • the working process of the pixel driving circuit provided in FIG5 provides a valid level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit in two discontinuous time periods through a data unit, which can reduce the positive bias temperature stress of the compensation transistor and improve the display uniformity of the display substrate.
  • the seventh time period t7 overlaps at least partially with the fifth time period t5 and the second time period t2, respectively, the eighth time period t8 overlaps at least partially with the first time period t1, and the sixth time period t6 occurs after the eighth time period t8.
  • the fifth time period t5 and the sixth time period t6 are time periods in which the data unit provides an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit, and the fifth time period t5 occurs before the sixth time period t6, the seventh time period t7 and the eighth time period t8 are time periods in which the data unit provides an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit, and the seventh time period t7 occurs before the eighth time period t8.
  • the duration of the seventh time period t7 is greater than the sum of the duration of the fifth time period t5 and the duration of the second time period t2, and the duration of the eighth time period t8 is greater than the duration of the first time period t1.
  • the second time period t2 and the fifth time period t5 are within the seventh time period t7, and the first time period t1 is within the eighth time period t8.
  • the start time of the seventh time period t7 occurs before the start time of the fifth time period t5
  • the end time of the seventh time period t7 occurs after the end time of the second time period t2
  • the start time of the eighth time period t8 occurs before the start time of the first time period t1
  • the end time of the eighth time period t8 occurs after the end time of the first time period t1 and before the start time of the sixth time period t6
  • the end time of the sixth time period t6 is the start time of the fourth time period t4.
  • the duration of the seventh time period t7 is greater than four times the duration of the eighth time period t8 and greater than four times the duration of the ninth time period t9
  • the start time of the ninth time period t9 is the end time of the seventh time period t7
  • the end time of the ninth time period t9 is the start time of the eighth time period t8.
  • the duration of the seventh time period t7 can be 26H
  • the duration of the eighth time period t8 can be 6H
  • the duration of the ninth time period t9 can be 6H.
  • the working process of the pixel driving circuit provided in FIG6 provides a valid level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit in two discontinuous time periods through a data unit, which can reduce the positive bias temperature stress of the compensation transistor and improve the display uniformity of the display substrate.
  • the signal of the first reset signal line Reset1 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the second reset signal line Reset2 connected to at least one pixel driving circuit is a double pulse signal
  • the signal of the first scanning signal line Gate1 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the second scanning signal line Gate2 connected to at least one pixel driving circuit is a double pulse signal
  • the signal of the light-emitting signal line EM connected to at least one pixel driving circuit is a single pulse signal.
  • the data unit provides an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit in two time periods, and provides an effective level signal to at least one pixel driving circuit in two time periods.
  • the seventh time period t7 at least partially overlaps with the fifth time period t5
  • the eighth time period t8 at least partially overlaps with the second time period t2
  • the ninth time period t9 at least partially overlaps with the first time period t1
  • the sixth time period t6 occurs between the ninth time period t9 and the fourth time period t4.
  • the fifth time period t5 and the sixth time period t6 are time periods in which the data unit provides an effective level signal to the second reset signal line Reset2 connected to at least one pixel driving circuit, and the fifth time period t5 occurs before the sixth time period t6, the seventh time period t7, the eighth time period t8 and the ninth time period t9 are time periods in which the data unit provides an effective level signal to the second scanning signal line Gate2 connected to at least one pixel driving circuit, and the seventh time period t7 occurs before the eighth time period t8, and the eighth time period t8 occurs before the ninth time period t9.
  • the duration of the seventh time period t7 is greater than the duration of the fifth time period t5
  • the duration of the eighth time period t8 is greater than the duration of the second time period t2
  • the duration of the ninth time period t9 is greater than the duration of the first time period t1.
  • the fifth time period t5 is within the seventh time period t7
  • the second time period t2 is within the eighth time period t8
  • the first time period t1 is within the ninth time period t9.
  • the start time of the seventh time period t7 occurs before the start time of the fifth time period t5, and the end time of the seventh time period t7 occurs after the end time of the fifth time period t5.
  • the start time of the eighth time period t8 occurs before the start time of the second time period t2, and the end time of the eighth time period t8 occurs after the end time of the second time period t2.
  • the start time of the ninth time period t9 occurs before the start time of the first time period t1, and the end time of the ninth time period t9 occurs after the end time of the first time period t1 and before the start time of the sixth time period t6.
  • the end time of the sixth time period t6 is the start time of the fourth time period t4.
  • the duration of at least one of the seventh time period t7 and the eighth time period t8 is greater than the duration of the ninth time period t9, and greater than the duration of at least one of the tenth time period t10 and the eleventh time period t11
  • the start time of the tenth time period t10 is the end time of the seventh time period t7
  • the end time of the tenth time period t10 is the start time of the eighth time period t8
  • the start time of the eleventh time period t11 is the end time of the eighth time period t8
  • the end time of the eleventh time period t11 is the start time of the ninth time period t9.
  • the duration of the seventh time period t7 when the duration between the start time of the seventh time period t7 and the end time of the eighth time period t8 is 38H, the duration of the seventh time period t7 may be 10H, the duration of the tenth time period t10 may be 6H, the duration of the eighth time period t8 may be 10H, the duration of the eleventh time period t11 may be 6H, and the duration of the ninth time period t9 may be 6H.
  • the duration of the seventh time period t7 may be greater than 10 hours
  • the duration of the tenth time period t10 may be greater than 6 hours
  • the duration of the eighth time period t8 may be greater than 10 hours
  • the duration of the eleventh time period t11 may be greater than 6 hours
  • the duration of the ninth time period t9 may be greater than 6 hours.
  • the data unit provides an invalid level signal to the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the light emitting signal line EM connected to at least one pixel driving circuit in the tenth time period t10 and the eleventh time period t11.
  • the signal of the first reset signal line Reset1 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the second reset signal line Reset2 connected to at least one pixel driving circuit is a two-pulse signal
  • the signal of the first scanning signal line Gate1 connected to at least one pixel driving circuit is a single pulse signal
  • the signal of the second scanning signal line Gate2 connected to at least one pixel driving circuit is a three-pulse signal
  • the signal of the light-emitting signal line EM connected to at least one pixel driving circuit is a single pulse signal.
  • FIG7 provides a working process of the pixel driving circuit, in which a data unit provides an effective level signal to a second scanning signal line Gate2 connected to at least one pixel driving circuit in three discontinuous time periods, thereby reducing the number of compensation transistors.
  • the positive bias temperature stress improves the display uniformity of the display substrate.
  • the data unit is further configured to provide an invalid level signal to the first reset signal line Reset1, the second reset signal line Reset2 and the light emitting signal line EM connected to the at least one pixel driving circuit in a first time period t1, provide an invalid level signal to the second reset signal line Reset2, the first scan signal line Gate1 and the light emitting signal line EM connected to the at least one pixel driving circuit in a second time period t2, provide an invalid level signal to the first reset signal line Reset1, the second reset signal line Reset2, the first scan signal line Gate1 and the second scan signal line Gate2 connected to the at least one pixel driving circuit in a third time period t3, provide an invalid level signal to the first reset signal line Reset1, the first scan signal line Gate1 and the light emitting signal line EM connected to the at least one pixel driving circuit in a fifth time period t5, and provide an invalid level signal to the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2 and
  • the compensation transistor T2 is an N-type transistor
  • the first reset transistor T1, the driving transistor T3, the writing transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the second reset transistor T7 and the eighth reset transistor T8 are P-type transistors as an example to illustrate the working process of the pixel driving circuit provided by an exemplary embodiment. As shown in FIG.
  • the working process of at least one pixel driving circuit may include: a first stage S11, a second stage S12, a third stage S13, a fourth stage S14, a fifth stage S15 and a sixth stage S16, wherein the first stage S11 is a stage where the fifth time period t5 is located, the second stage S12 is a stage where the second time period t2 is located, the third stage S13 is a stage where the first time period t1 is located, the fourth stage S14 is a stage where the sixth time period t6 is located, the fifth stage S15 is a stage where the fourth time period t4 is located, and the sixth stage S16 is a stage where the third time period t3 is located.
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, the first reset signal line Reset1, and the light-emitting signal line EM are all high-level signals, and the signal of the second reset signal line Reset2 is a low-level signal.
  • the signal of the second reset signal line Reset2 is a low-level signal, the second reset transistor T7 and the third reset transistor T8 are turned on, the second initial signal of the second initial signal line Vinit2 is written into the fourth node N4, the fourth node N4 (i.e., the first pole of the light-emitting device) is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the driving transistor T3 Since the driving transistor T3 is turned on, the third initial signal of the third initial signal line Vinit3 is written into the second node N2 and the third node N3, the second node N2 and the third node N3 are initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signal of the second scanning signal line Gate2 is a high-level signal
  • the compensation transistor T2 is turned on
  • the signal of the third node N3 is written into the first node N1
  • the first node N1 is initialized (reset)
  • the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the driving transistor T3 is turned on.
  • the signals of the first scanning signal line Gate1, the second reset signal line Reset2 and the light-emitting signal line EM are high-level signals, and the write transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the second reset transistor T7 and the third reset transistor T8 are turned off. In this stage, the light-emitting element L does not emit light.
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the signals of the first reset signal line Reset1 and the first reset signal line Reset2 are low-level signals.
  • the signal of the first reset signal line Reset1 is a low-level signal
  • the first reset transistor T1 is turned on
  • the first initial signal of the first initial signal line Vinit1 is written into the third node N3
  • the third node N3 is initialized (reset)
  • the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the compensation transistor T2 Since the signal of the second scanning signal line Gate2 is a high-level signal, the compensation transistor T2 is turned on, the signal of the third node N3 is continuously written into the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signals of the first scanning signal line Gate1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the write transistor T4, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are turned off. In this stage, the light-emitting element L does not emit light.
  • the signals of the second scanning signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2 and the light emitting signal line EM are all high-level signals, the signal of the first scanning signal line Gate1 is a low-level signal, and the data signal line Data writes the data voltage.
  • the signal of the first scanning signal line Gate1 is a low-level signal
  • the write transistor T4 is turned on
  • the signal of the second scanning signal line Gate2 is a high-level signal
  • the compensation transistor T2 is turned on
  • the data voltage output by the data signal line Data is written to the first node N1 through the turned-on write transistor T4, the second node N2, the turned-on drive transistor T3, the third node N3, and the turned-on compensation transistor T2, and the difference between the second data voltage output by the data signal line Data and the threshold voltage of the drive transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vdata-
  • the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the first reset transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are turned off. At this stage, the light-emitting element L does not emit light. At this stage, the light-emitting element L does not emit light.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, and the light-emitting signal line EM are all high-level signals, and the signals of the second scanning signal line Gate2 and the second reset signal line Reset2 are low-level signals.
  • the signal of the second reset signal line Reset2 is a low-level signal
  • the second reset transistor T7 and the third reset transistor T8 are turned on
  • the second initial signal of the second initial signal line Vinit2 is written into the fourth node N4
  • the fourth node N4 that is, the first pole of the light-emitting device
  • the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the driving transistor T3 Since the driving transistor T3 is turned on, the third initial signal of the third initial signal line Vinit3 is written into the second node N2 and the third node N3, the second node N2 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed.
  • the signals of the first reset signal line Reset1, the first scanning signal line Gate1 and the light-emitting signal line EM are all high-level signals
  • the signal of the second scanning signal line Gate2 is a high-level signal
  • the compensation transistor T2, the write transistor T4, the first reset transistor T1, the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are disconnected.
  • the light-emitting element L does not emit light.
  • the light-emitting element L does not emit light.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the signal of the second scanning signal line Gate2 is a low-level signal.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the signal of the second scanning signal line Gate2 is a low-level signal.
  • the first reset transistor T1, the compensation transistor T2, the write transistor T4, the first light-emitting transistor T5, the sixth light-emitting transistor T6, the second reset transistor T7 and the third reset transistor T8 are disconnected.
  • the driving transistor T3 is turned on, so that the third initial signal of the third initial signal line Vinit3 has enough time to act on the first and second electrodes of the driving transistor T3.
  • the voltage value of the signal of the first node N1 is greater than the voltage value of the signal of the second node N2, so that the driving transistor T3 can be in a bias state for a long time, thereby improving the hysteresis state of the driving transistor T3, and further improving the low-frequency flicker problem of the display substrate.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are all high-level signals, and the signals of the second scanning signal line Gate2 and the light-emitting signal line EM are low-level signals.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are turned on, and the power supply voltage output by the first power line VDD provides a driving voltage to the fourth node N4 through the turned-on first light-emitting transistor T5, the driving transistor T3, and the sixth light-emitting transistor T6, driving the light-emitting device L to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K*[(Vdd-Vdata] 2
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light emitting device L
  • K is a constant
  • Vgs is a voltage difference between the control electrode and the first electrode of the driving transistor T3
  • Vth is a threshold voltage of the driving transistor T3
  • Vdata is a second data voltage output by the data signal line Data
  • Vdd is a power supply voltage output by the first power supply terminal VDD.
  • the driving method of the pixel driving circuit provided in Figures 6 and 7 is the same as the driving method of the pixel driving circuit provided in Figure 5.
  • the signals of the first scanning signal line, the second scanning signal line, the first reset signal line, the second reset signal line and the light-emitting signal line connected to the pixel driving circuit are the same. Therefore, the working processes of the pixel driving circuits are the same, and the present disclosure does not make any limitation on this.
  • the compensation transistor T2 is an N-type transistor
  • the first reset transistor T1, the driving transistor T3, the write transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the second reset transistor T7 and the eighth reset transistor T8 are P-type transistors as an example to illustrate the working process of the pixel driving circuit provided by an exemplary embodiment. As shown in FIG.
  • the working process of at least one pixel driving circuit may include: a first stage S21, a second stage S22, a third stage S23, a fourth stage S24 and a fifth stage S25, wherein the first stage S21 is a stage where the second time period t2 is located, the second stage S22 is a stage where the first time period t1 is located, the third stage S23 is a stage where the fifth time period t5 is located, the fourth stage S24 is a stage where the fourth time period t4 is located, and the fifth stage S25 is a stage where the third time period t3 is located.
  • the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the signals of the first reset signal line Reset1 and the first reset signal line Reset2 are low-level signals.
  • the signal of the first reset signal line Reset1 is a low-level signal
  • the first reset transistor T1 is turned on
  • the first initial signal of the first initial signal line Vinit1 is written into the third node N3
  • the third node N3 is initialized (reset)
  • the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the compensation transistor T2 Since the signal of the second scanning signal line Gate2 is a high-level signal, the compensation transistor T2 is turned on, the signal of the third node N3 is continuously written into the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the signals of the first scanning signal line Gate1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the write transistor T4, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are turned off. In this stage, the light-emitting element L does not emit light.
  • the signals of the second scanning signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2 and the light emitting signal line EM are all high-level signals, the signal of the first scanning signal line Gate1 is a low-level signal, and the data signal line Data writes the data voltage.
  • the signal of the first scanning signal line Gate1 is a low-level signal
  • the write transistor T4 is turned on
  • the signal of the second scanning signal line Gate2 is a high-level signal
  • the compensation transistor T2 is turned on
  • the data voltage output by the data signal line Data is written to the first node N1 through the turned-on write transistor T4, the second node N2, the turned-on drive transistor T3, the third node N3, and the turned-on compensation transistor T2, and the difference between the second data voltage output by the data signal line Data and the threshold voltage of the drive transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vdata-
  • the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the first reset transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are turned off. At this stage, the light-emitting element L does not emit light. At this stage, the light-emitting element L does not emit light.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, and the luminous signal line EM are all high-level signals, and the signals of the second scanning signal line Gate2 and the second reset signal line Reset2 are low-level signals.
  • the signal of the second reset signal line Reset2 is a low-level signal, the second reset transistor T7 and the third reset transistor T8 are turned on, and the second initial signal of the second initial signal line Vinit2 is written into the fourth stage S24.
  • Point N4 the fourth node N4 (that is, the first pole of the light-emitting device) is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed.
  • the driving transistor T3 Since the driving transistor T3 is turned on, the third initial signal of the third initial signal line Vinit3 is written into the second node N2 and the third node N3, the second node N2 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed.
  • the signals of the first reset signal line Reset1, the first scanning signal line Gate1 and the light-emitting signal line EM are all high-level signals
  • the signal of the second scanning signal line Gate2 is a high-level signal
  • the compensation transistor T2, the write transistor T4, the first reset transistor T1, the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are disconnected.
  • the light-emitting element L does not emit light.
  • the light-emitting element L does not emit light.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the signal of the second scanning signal line Gate2 is a low-level signal.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2 and the light-emitting signal line EM are all high-level signals, and the signal of the second scanning signal line Gate2 is a low-level signal.
  • the first reset transistor T1, the compensation transistor T2, the write transistor T4, the first light-emitting transistor T5, the sixth light-emitting transistor T6, the second reset transistor T7 and the third reset transistor T8 are disconnected.
  • the driving transistor T3 is turned on, so that the third initial signal of the third initial signal line Vinit3 has enough time to act on the first and second electrodes of the driving transistor T3.
  • the voltage value of the signal of the first node N1 is greater than the voltage value of the signal of the second node N2, so that the driving transistor T3 can be in a bias state for a long time, thereby improving the hysteresis state of the driving transistor T3, and further improving the low-frequency flicker problem of the display substrate.
  • the signals of the first scanning signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are all high-level signals, and the signals of the second scanning signal line Gate2 and the light-emitting signal line EM are low-level signals.
  • the signal of the light-emitting signal line EM is a low-level signal
  • the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the fourth node N4 through the turned-on first light-emitting transistor T5, the driving transistor T3, and the sixth light-emitting transistor T6, driving the light-emitting device L to emit light.
  • the driving current flowing through the driving transistor T3 is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-
  • )-Vth] 2 K*[(Vdd-Vdata] 2
  • I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the driving transistor T3
  • Vth is the threshold voltage of the driving transistor T3
  • Vdata is the second data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the first power supply terminal VDD.
  • the display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.
  • the embodiment of the present disclosure further provides a method for driving a display substrate, which is configured to drive the display substrate.
  • the method for driving the display substrate may include:
  • a valid level signal is provided to a second reset signal line connected to at least one pixel driving circuit in a time period, and a valid level signal is provided to a second scanning signal line connected to at least one pixel driving circuit in a time period, or a valid level signal is provided to a second reset signal line connected to at least one pixel driving circuit in at least two time periods, and a valid level signal is provided to a second scanning signal line connected to at least one pixel driving circuit in at least two time periods.
  • the embodiment of the present disclosure further provides a display device, including: a display substrate.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.
  • the display device may be a display, a television, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or any product or component having a display function.
  • the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种显示基板及其驱动方法、显示装置，显示基板所显示内容包括多个显示帧，显示基板包括：数据单元、阵列排布的像素驱动电路、多条第二复位信号线(Reset2)和多条第二扫描信号线(Gate2)，在至少一个显示帧，数据单元被配置为在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线(Reset2)提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线(Gate2)提供有效电平信号，或者，在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线(Reset2)提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线(Gate2)提供有效电平信号。

Description

显示基板及其驱动方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，特别涉及一种显示基板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光元件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，显示基板所显示内容包括多个显示帧，所述显示基板包括：数据单元、阵列排布的像素驱动电路、多条第二复位信号线和多条第二扫描信号线，至少一个像素驱动电路包括：驱动晶体管、补偿晶体管和第三复位晶体管，其中，所述驱动晶体管分别与第一节点、第二节点和第三节点连接，所述补偿晶体管分别与第二扫描信号线、第一节点和第三节点连接，所述第三复位晶体管分别与第二复位信号线和第二节点连接；
在至少一个显示帧，所述数据单元被配置为在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号，或者，在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号。
在示例性实施方式中，还包括：多条第一扫描信号线、多条第一复位信号线和多条发光信号线，至少一个像素驱动电路还包括：写入晶体管、第一复位晶体管和第一发光晶体管，其中，所述写入晶体管分别与第一扫描信号线和第二节点连接，所述第一复位晶体管分别与第一复位信号线和第三节点连接，所述第一发光晶体管分别与发光信号线和第二节点连接；
在至少一个显示帧，所述数据单元被配置为在第一时间段向至少一个像素驱动电路所连接的第一扫描信号线提供有效电平信号，在第二时间段向至少一个像素驱动电路所连接的第一复位信号线提供有效电平信号，在第三时间段向至少一个像素驱动电路所连接的发光信号线提供有效电平信号，在第四时间段向至少一个像素驱动电路所连接的第一扫描信号线、第二扫描信号线、第一复位信号线、第二复位信号线和发光信号线提供无效电平信号；
所述第二时间段发生在所述第一时间段之前，且所述第二时间段的结束时间发生在所述第一时间段的开始时间之前，所述第一时间段发生在所述第四时间段之前，且所述第一时间段的结束时间发生在所述第四时间段的开始之前，所述第四时间段发生在所述第三时间段之前，且所述第四时间段的结束时间为所述第三时间段的开始时间。
在示例性实施方式中，至少一个像素驱动电路所连接的第二扫描信号线的信号为有效电平信号的至少一个时间段与所述第一时间段和所述第二时间段中的至少一个时间段至少部分交叠，且与第三时间段和第四时间段中的至少一个时间段不交叠；
至少一个像素驱动电路所连接的第二复位信号线的信号的有效电平信号的至少一个时间段与第一时间段、所述第二时间段、所述第三时间段和所述第四时间段中的至少一个时间段不交叠。
在示例性实施方式中，在数据单元在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第六时间段分别与所述第一时间段和所述第二时间段至少部分交叠，第五时间段发生在所述第六时间段之后；
其中，所述第五时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，所述第六时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段。
在示例性实施方式中，所述第六时间段的持续时间大于所述第一时间段的持续时间，且大于所述第二时间段的持续时间；
所述第一时间段和所述第二时间段位于所述第六时间段之内。
在示例性实施方式中，所述第六时间段的开始时间发生在所述第二时间段的开始时间之前，所述第六时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第五时间段的开始时间之前，所述第五时间段的结束时间为所述第四时间段的开始时间。
在示例性实施方式中，所述数据单元还被配置为在第一时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线和发光信号线提供无效电平信号，在第二时间段向至少一个像素驱动电路所连接的第二复位信号线、第一扫描信号线和发光信号线提供无效电平信号，在第三时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线、第一扫描信号线和第二扫描信号线提供无效电平信号，在第五时间段向至少一个像素驱动电路所连接的第一复位信号线、第一扫描信号线、第二扫描信号线和发光信号线提供无效电平信号。
在示例性实施方式中，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第七时间段与第五时间段至少部分交叠，第八时间段分别与所述第一时间段和所述第二时间段至少部分交叠，所述第六时间段发生在所述第八时间段之后；
其中，所述第五时间段和第六时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，且所述第五时间段发生在所述第六时间段之前，所述第七时间段和所述第八时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段，且所述第七时间段发生在所述第八时间段之前。
在示例性实施方式中，所述第七时间段的持续时间大于所述第五时间段的持续时间，所述第八时间段的持续时间大于所述第一时间段的持续时间和所述第二时间段的持续时间之和；
所述第五时间段位于所述第七时间段之内，所述第一时间段和所述第二时间段位于所述第八时间段之内。
在示例性实施方式中，所述第七时间段的开始时间发生在所述第五时间段的开始时间 之前，所述第七时间段的结束时间发生在所述第五时间段的开始时间之后，所述第八时间段的开始时间发生在所述第二时间段的开始时间之前，所述第八时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第六时间段的开始时间之前，所述第六时间段的结束时间为所述第四时间段的开始时间。
在示例性实施方式中，所述第八时间段的持续时间大于所述第七时间段的持续时间，所述第七时间段的持续时间大于第九时间段的持续时间的两倍，所述第九时间段的开始时间为第七时间段的结束时间，第九时间段的结束时间为第八时间段的开始时间；
所述数据单元在所述第九时间段向至少一个像素驱动电路所连接的第一扫描信号线、第二扫描信号线、第一复位信号线、第二复位信号线和发光信号线提供无效电平信号。
在示例性实施方式中，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第七时间段分别与第五时间段和所述第二时间段至少部分交叠，第八时间段与所述第一时间段至少部分交叠，所述第六时间段发生在所述第八时间段之后；
其中，所述第五时间段和第六时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，且所述第五时间段发生在所述第六时间段之前，所述第七时间段和所述第八时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段，且所述第七时间段发生在所述第八时间段之前。
在示例性实施方式中，所述第七时间段的持续时间大于所述第五时间段的持续时间和所述第二时间段的持续时间之和，所述第八时间段的持续时间大于所述第一时间段的持续时间；
所述第二时间段和所述第五时间段位于所述第七时间段之内，所述第一时间段位于所述第八时间段之内。
在示例性实施方式中，所述第七时间段的开始时间发生在所述第五时间段的开始时间之前，所述第七时间段的结束时间发生在所述第二时间段的结束时间之后，所述第八时间段的开始时间发生在所述第一时间段的开始时间之前，所述第八时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第六时间段的开始时间之前，所述第六时间段的结束时间为所述第四时间段的开始时间。
在示例性实施方式中，所述第七时间段的持续时间大于所述第八时间段的持续时间的四倍，且大于第九时间段的持续时间的四倍，所述第九时间段的开始时间为所述第七时间段的结束时间，所述第九时间段的结束时间为所述第八时间段的开始时间。
在示例性实施方式中，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第七时间段与第五时间段至少部分交叠，第八时间段与所述第二时间段至少部分交叠，所述第九时间段与所述第一时间段至少部分交叠，所述第六时间段发生在所述第九时间段和所述第四时间段之间；
其中，所述第五时间段和第六时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，且所述第五时间段发生在所述第六时间段之前，所述第七时间段、所述第八时间段和所述第九时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段，且所述第七时间段发生在所述第八时间段之前，所述第八时间段发生在所述第九时间段之前。
在示例性实施方式中，所述第七时间段的持续时间大于所述第五时间段的持续时间，所述第八时间段的持续时间大于所述第二时间段的持续时间，第九时间段的持续时间大于第一时间段的持续时间；
所述第五时间段位于所述第七时间段之内，所述第二时间段位于第八时间段之内，所述第一时间段位于所述第九时间段之内。
在示例性实施方式中，所述第七时间段的开始时间发生在所述第五时间段的开始时间之前，所述第七时间段的结束时间发生在所述第五时间段的结束时间之后，所述第八时间段的开始时间发生在所述第二时间段的开始时间之前，所述第八时间段的结束时间发生在所述第二时间段的结束时间之后，所述第九时间段的开始时间发生在所述第一时间段的开始时间之前，所述第九时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第六时间段的开始时间之前，所述第六时间段的结束时间为所述第四时间段的开始时间。
在示例性实施方式中，所述第七时间段和所述第八时间段中的至少一个时间段的持续时间大于所述第九时间段的持续时间，且大于第十时间段和第十一时间段中的至少一个时间段的持续时间，第十时间段的开始时间为第七时间段的结束时间，第十时间段的结束时间为第八时间段的开始时间，第十一时间段的开始时间为第八时间段的结束时间，第十一时间段的结束时间为第九时间段的开始时间；
所述数据单元在所述第十时间段和所述第十一时间段向至少一个像素驱动电路所连接的第一扫描信号线、第二扫描信号线、第一复位信号线、第二复位信号线和发光信号线提供无效电平信号。
在示例性实施方式中，所述数据单元还被配置为在第一时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线和发光信号线提供无效电平信号，在第二时间段向至少一个像素驱动电路所连接的第二复位信号线、第一扫描信号线和发光信号线提供无效电平信号，在第三时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线、第一扫描信号线和第二扫描信号线提供无效电平信号，在第五时间段向至少一个像素驱动电路所连接的第一复位信号线、第一扫描信号线和发光信号线提供无效电平信号，在第六时间段向至少一个像素驱动电路所连接的第一复位信号线、第一扫描信号线、第二扫描信号线和发光信号线提供无效电平信号。
在示例性实施方式中，还包括：多条发光信号线、多条第一复位信号线、多条第一初始信号线、多条第二初始信号线、多条第三初始信号线、多条第一扫描信号线和多条第一电源线，至少一个像素驱动电路还包括：第一复位晶体管、第二复位晶体管、写入晶体管、第一发光晶体管、第二发光晶体管和电容；
所述补偿晶体管的控制极与第二扫描信号线连接，所述补偿晶体管的第一极与第一节点连接，所述补偿晶体管的第二极与第三节点连接；
所述驱动晶体管的控制极与第一节点连接，所述驱动晶体管的第一极与第二节点连接，所述驱动晶体管的第二极与第三节点连接；
所述写入晶体管的控制极与第一扫描信号线连接，所述写入晶体管的第一极与数据信号线连接，所述写入晶体管的第二极与第二节点连接；
所述第一复位晶体管的控制极与第一复位信号线连接，所述第一复位晶体管的第一极与第一初始信号线连接，所述第一复位晶体管的第二极与第三节点连接；
所述第二复位晶体管的控制极与第二复位信号线连接，所述第二复位晶体管的第一极与第二初始信号线连接，所述第二复位晶体管的第二极与第四节点连接；
所述第三复位晶体管的控制极与第二复位信号线连接，所述第三复位晶体管的第一极与第三初始信号线连接，所述第三复位晶体管的第二极与第二节点连接；
所述第一发光晶体管的控制极与发光信号线连接，所述第一发光晶体管的第一极与第一电源线连接，所述第一发光晶体管的第二极与第二节点连接；
所述第二发光晶体管的控制极与发光信号线连接，所述第二发光晶体管的第一极与第三节点连接，所述第二发光晶体管的第二极与第四节点连接；
所述电容的一端与第一电源线连接，所述电容的另一端与第一节点连接。
在示例性实施方式中，至少一个像素驱动电路中的至少一个晶体管为P型晶体管或者N型晶体管，所述第一发光晶体管和第二发光晶体管的晶体管类型相同，所述第二复位晶体管和所述第三复位晶体管的晶体管类型相同。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
第三方面，本公开还提供了一种显示基板的驱动方法，被配置为驱动上述显示基板，所述方法包括：
在至少一个显示帧，在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号，或者，在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为一种显示基板的结构示意图；
图2A为一种显示基板的平面结构示意图一；
图2B为一种显示基板的平面结构示意图二；
图2C为一种显示基板的平面结构示意图三；
图3为一种显示基板的剖面结构示意图；
图4为本公开实施例提供的显示基板的像素驱动电路的等效电路图；
图5为图4提供的像素驱动电路的工作时序图一；
图6为图4提供的像素驱动电路的工作时序图二；
图7为图4提供的像素驱动电路的工作时序图三；
图8为图4提供的像素驱动电路的工作时序图四。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围 的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
图1为一种显示基板的结构示意图。如图1所示，显示基板可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线连接，扫描驱动器分别与多个扫描信号线连接，发光驱动器分别与多个发光信号线连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路可以分别与扫描信号线、发光信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号。
图2A为一种显示基板的平面结构示意图一，图2B为一种显示基板的平面结构示意图二，图2C为一种显示基板的平面结构示意图三。如图2A至图2C所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。
在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。图2A是像素单元包括三个子像素，且三个子像素采用水平并列的方式排列为例进行说明的，图2B是像素单元包括三个子像素，且三个子像素采用品字方式排列为例进行说明的。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列、正方形或者钻石型等排列，本公开在此不做限定。图2C是像素单元包括四个子像素，且四个子像素采用正方形的方式排列为例进行说明的。
在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
图3为一种显示基板的剖面结构示意图，示意了显示基板三个子像素的结构。如图3所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。每个子像素的驱动电路层102可以包括构成像素驱动电路的多个晶体管和存储电容，图3中仅以一个晶体管101和一个电容101A作为示例。发光结构层103可以包括阳极301、像素定义层302、有机发光层303和阴极304，阳极301通过过孔与驱动晶体管210的漏电极连接，有机发光层303与阳极301连接，阴极304与有机发光层303连接，有机发光层303在阳极301和阴极304驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层401、第二封装层402和第三封装层403，第一封装层401和第三封装层403可以采用无机材料，第二封装层402可以采用有机材料，第二封装层402设置在第一封装层401和第三封装层403之间，可以保证外界水汽无法进入发光结构层103。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，有机发光层303可以包括发光层(EML)以及如下任意一层或多层：空穴注入层HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，每个子像素的触控结构层可以包括设置在封装结构层上的第一触控绝缘层、设置在第一触控绝缘层上的第一触控金属层、覆盖第一触控金属层的第二触控绝缘层、设置在第二触控绝缘层上的第二触控金属层和覆盖第二触控金属层的触控保护层，第一触控金属层可以包括多个桥接电极，第二触控金属层可以包括多个第一触控电极和第二触控电极，第一触控电极或第二触控电极可以通过过孔与桥接电极连接。
显示基板中像素驱动电路可以包括：驱动晶体管和补偿晶体管，补偿晶体管分别与驱动晶体管的栅电极和漏电极连接，以对驱动晶体管的栅电极进行充电补偿。补偿晶体管为金属氧化物晶体管。显示基板在长时间高温运行后会出现信赖性横纹，而出现信赖性横纹的原因是由于金属氧化物晶体管的正偏置温度应力的影响，使得不同像素驱动电路对驱动晶体管的充电程度不同，进而导致显示基板出现信赖性横纹，使得显示基板的显示效果不均一，影响了显示基板的显示效果。
图4为本公开实施例提供的显示基板的像素驱动电路的等效电路图，图5为图4提供的像素驱动电路的工作时序图一，图6为图4提供的像素驱动电路的工作时序图二，图7为图4提供的像素驱动电路的工作时序图三，图8为图4提供的像素驱动电路的工作时序图四。如图4至图8所示，本公开实施例提供了一种显示基板，显示基板所显示内容包括多个显示帧，显示基板包括：数据单元、阵列排布的像素驱动电路、多条第二复位信号线Reset2和多条第二扫描信号线Gate2。至少一个像素驱动电路包括：驱动晶体管T3、补偿 晶体管T2和第三复位晶体管T8，其中，驱动晶体管T3分别与第一节点N1、第二节点N2和第三节点N3连接，补偿晶体管T2分别与第二扫描信号线Gate2、第一节点N1和第三节点N3连接，第三复位晶体管T8分别与第二复位信号线Reset2和第二节点N2连接。在至少一个显示帧，数据单元被配置为在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号，或者，在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号。图5至图7是以数据单元被配置为在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号为例进行说明的。图8是以数据单元被配置为在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号为例进行说明的。
在示例性实施方式中，信号线的有效电平信号指的是可以使得信号线所连接的晶体管处于导通状态的信号。信号线的无效电平信号指的是可以使得信号线所连接的晶体管处于断开状态的信号。
本公开实施例提供的显示基板包括：第一驱动模式和第二驱动模式，第一驱动模式的刷新率小于第二驱动模式的刷新率，例如：第一驱动模式的刷新率可以为1HZ-60HZ，第二驱动模式的刷新率可以为60HZ-480HZ。显示基板所显示内容包括多个显示帧，在第一驱动模式下，显示帧包括：刷新帧和至少一个保持帧。在第二驱动模式下，显示帧仅包括：刷新帧。
在示例性实施方式中，第一驱动模式可被称为低频驱动模式，第二驱动模式可被称为高频驱动模式。
在示例性实施方式中，刷新率指显示基板一秒内刷新数据的次数。同一个显示基板设置的第一驱动模式的刷新率是固定的，不同的显示基板设置的第一驱动模式的刷新率可能不同。其中，显示基板在第一驱动模式下的刷新率的范围可以为1Hz～60Hz，示例性地，第一驱动模式下的刷新率可以约为10Hz。
在示例性实施方式中，显示基板为了降低产品功耗，会采用第一驱动模式和第二驱动模式交替显示功能。在第一驱动模式中，显示基板在刷新帧中刷新显示数据，在保持帧中保持在刷新帧中刷新的显示数据。在第二驱动模式中，一个显示帧可以包括一个刷新帧而不包括保持帧。在第二驱动模式中，显示基板在刷新帧中刷新显示数据。显示基板在第二驱动模式下的刷新率的范围可以为60Hz～480Hz，示例性地，第一驱动模式下的刷新率可以约为120Hz。
在示例性实施方式中，数据单元被配置为在刷新帧提供信号。
在示例性实施方式中，数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的时间段与数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的至少一个时间段不交叠。
在示例性实施方式中，数据单元被配置为在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号，可以通过减少数据单元向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号的时间来减少向至 少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的时间，也就是减少了补偿晶体管的导通时间，或者，数据单元被配置为在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号，可以通过在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号，减少向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的时间，也就是减少了补偿晶体管的导通时间，进而减少显示基板高温运行时导致的补偿晶体管的正偏置温度应力，保证至少一个像素驱动电路的第一节点的信号的一致性，避免显示基板产生信赖性横纹，保证了显示基板的显示均一性，提升了显示基板的显示效果图4为本公开实施例提供的显示基板的像素驱动电路的等效电路图，图5为图4提供的像素驱动电路的工作时序图一，图6为图4提供的像素驱动电路的工作时序图二，图7为图4提供的像素驱动电路的工作时序图三，图8为图4提供的像素驱动电路的工作时序图四。
如图4所示，像素驱动电路可以包括8个晶体管(第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光晶体管T5、第二发光晶体管T6、第二复位晶体管T7和第三复位晶体管T4)和一个电容C。
在示例性实施方式中，显示基板还可以包括：多条第二扫描信号线Gate2、多条第一复位信号线Reset1、多条第二复位信号线Reset2、多条发光信号线EM、多条第一初始信号线Vinit1、多条第二初始信号线Vinit2、多条第三初始信号线Vinit3和多条第一电源线VDD。
在示例性实施方式中，扫描信号线可以包括：第一扫描信号线Gate1、第二扫描信号线Gate2、第一复位信号线Reset1和第二复位信号线Reset2。
在示例性实施方式中，如图4所示，电容C的一端与第一节点N1电连接，电容C的另一端与第一电源线VDD电连接。第一复位晶体管T1的控制极与第一复位信号线Reset1电连接，第一复位晶体管T1的第一极与第一初始信号线Vinit1电连接，第一复位晶体管T1的第二极与三节点N3电连接。补偿晶体管T2的控制极与第二扫描信号线Gate2电连接，补偿晶体管T2的第一极与第一节点N1电连接，补偿晶体管T2的第二极与第二节点N2电连接。驱动晶体管T3的控制极与第一节点N1电连接，驱动晶体管T3的第一极与第二节点N2电连接，驱动晶体管T3的第二极与第三节点N3电连接。写入晶体管T4的控制极与第一扫描信号线Gate1电连接，写入晶体管T4的第一极与数据信号线Data电连接，写入晶体管T4的第二极与第二节点N2电连接。第一发光晶体管T5的控制极与发光信号线EM电连接，第一发光晶体管T5的第一极与第一电源线VDD电连接，第一发光晶体管T5的第二极与第二节点N2电连接。第二发光晶体管T6的控制极与发光信号线EM电连接，第二发光晶体管T6的第一极与第三节点N3电连接，第二发光晶体管T6的第二极与第四节点N4电连接。第二复位晶体管T7的控制极与第二复位信号线Reset2电连接，第二复位晶体管T7的第一极与第二初始信号线Vinit2电连接，第二复位晶体管T7的第二极与第四节点N4电连接。第三复位晶体管T8的控制极与第二复位信号线Reset2电连接，第三复位晶体管T8的第一极与第三初始信号线Vinit3电连接，第三复位晶体管T8的第二极与第二节点N2电连接。
在示例性实施方式中，第二复位晶体管T7所连接的第二复位信号线Reset2和第三复位晶体管T8所连接的第二复位信号线Reset2可以为同一信号线，或者可以为信号相同的不同信号线，本公开对此不做任何限定。
在示例性实施方式中，如图4所示，显示基板还可以包括：第二电源线VSS。发光器件L可以与第四节点N4和第二电源线VSS电连接。
在示例性实施方式中，发光元件L可以是有机电致发光二极管(OLED)或者量子点发光二极管(QLED)。其中，OLED可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，OLED的第一极与第四节点N4连接，OLED的第二极与第二电源线VSS电连接。
在示例性实施方式中，第一电源线VDD的信号为持续提供高电平信号，第二电源线VSS的信号为低电平信号。
在示例性实施方式中，当第一复位信号线Reset1提供有效电平信号时，第一复位晶体管T1将第一初始信号线Vinit1的第一初始信号后传输到第三节点N3，以使第三节点N3的电荷量初始化。
在示例性实施方式中，当第二扫描信号线Gate2提供有效电平信号时，补偿晶体管T2将第三节点N3的信号传输至第一节点N1，可以对驱动晶体管T3进行阈值补偿或者对第一节点N1的电荷量初始化。
在示例性实施方式中，驱动晶体管T3根据控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流。
在示例性实施方式中，当第一扫描信号线Gate1输入有效电平信号时，写入晶体管T4使数据信号线Data的数据电压输入到第二节点N2
在示例性实施方式中，当发光信号线EM输入有效电平信号时，第一发光晶体管T5和第二发光晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光元件发光。
在示例性实施方式中，第二复位晶体管T7可以称为阳极复位晶体管，当第二复位信号线Reset2提供有效电平信号时，第二复位晶体管T7将第二初始信号线Vinit2的第二初始信号传输到发光元件L的阳极，以使发光元件的阳极的电荷量初始化。
在示例性实施方式中，第三复位晶体管T8可以称为第二节点复位晶体管，当第二复位信号线Reset2提供有效电平信号时，第三复位晶体管T8将第三初始信号线Vinit3的第三初始信号传输至第二节点N2，可以将第二节点N2的电荷量初始化。
在示例性实施方式中，按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，至少一个像素驱动电路中的至少一个晶体管为P型晶体管或者N型晶体管，第一发光晶体管T5和第二发光晶体管T6的晶体管类型相同，第二复位晶体管T71和第三复位晶体管T8的晶体管类型相同。图4是以补偿晶体管T2为N型晶体管，其余晶体管为P型晶体管为例进行说明的。
在示例性实施方式中，第一复位晶体管T1可以为P型晶体管或者N型晶体管。示例性地，P型晶体管可以为低温多晶硅晶体管，N型晶体管可以为金属氧化物晶体管。
在示例性实施方式中，补偿晶体管T2可以为N型晶体管，N型晶体管可以减少漏电流，提升像素驱动电路的性能，可以降低像素驱动电路的功耗。
在示例性实施方式中，像素驱动电路中的所有晶体管为P型晶体管和N型晶体管时，显示基板中所用的是低温多晶氧化物结合(Low Temperature+Poly-Silicon，简称LTPS)技术，相比于LTPS技术，LTPO技术的漏电流更小，像素反应更快，显示基板多加了一 层氧化物，降低了激发像素所需的能耗，从而降低屏幕显示时的功耗。
在示例性实施方式中，至少一个像素驱动电路所连接的第一初始信号线Vinit1在刷新帧和保持帧提供第一初始信号，第一初始信号为直流信号，且第一初始信号的电压值恒定。
在示例性实施方式中，至少一个像素驱动电路所连接的第二初始信号线Vinit2在刷新帧和保持帧提供第二初始信号，第二初始信号为直流信号，且第二初始信号的电压值恒定。
在示例性实施方式中，至少一个像素驱动电路所连接的第三初始信号线Vinit3在刷新帧和保持帧提供第三初始信号，第三初始信号为直流信号，且第三初始信号的电压值恒定。示例性地，第三初始信号线Vinit3提供的第三初始信号的电压值可以约为第一电源线VDD的信号的电压值。第三初始信号的电压值可以约为5伏特至8伏特。
在示例性实施方式中，如图5至图8所示，在至少一个显示帧，数据单元被配置为在第一时间段t1向至少一个像素驱动电路所连接的第一扫描信号线Gate1提供有效电平信号，在第二时间段t2向至少一个像素驱动电路所连接的第一复位信号线Reset1提供有效电平信号，在第三时间段t3向至少一个像素驱动电路所连接的发光信号线EM提供有效电平信号，在第四时间段t4向至少一个像素驱动电路所连接的第一扫描信号线Gate1、第二扫描信号线Gate2、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM提供无效电平信号。其中，第二时间段t2发生在第一时间段t1之前，且第二时间段t2的结束时间发生在第一时间段t1的开始时间之前，第一时间段t1发生在第四时间段t4之前，且第一时间段t1的结束时间发生在第四时间段t4的开始之前，第四时间段t4发生在第三时间段t3之前，且第四时间段t4的结束时间为第三时间段t3的开始时间。
在示例性实施方式中，如图5至图8所示，至少一个像素驱动电路所连接的第二扫描信号线Gate2的信号为有效电平信号的至少一个时间段与第一时间段t1和第二时间段t2中的至少一个时间段至少部分交叠，且与第三时间段t3和第四时间段t4中的至少一个时间段不交叠；
在示例性实施方式中，如图5至图8所示，至少一个像素驱动电路所连接的第二复位信号线Reset2的信号的有效电平信号的至少一个时间段与第一时间段t1、第二时间段t2、第三时间段t3和第四时间段t4中的至少一个时间段不交叠。
在示例性实施方式中，如图8所示，在数据单元在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的状态下，第六时间段t6分别与第一时间段t1和第二时间段t2至少部分交叠，第五时间段t5发生在第六时间段t6之后。其中，第五时间段t5为数据单元向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号的时间段，第六时间段t6为数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的时间段。
在示例性实施方式中，如图8所示，第六时间段t6的持续时间大于第一时间段t1的持续时间和第二时间段t2的持续时间之和；第一时间段t1和第二时间段t2位于第六时间段t6之内。
在示例性实施方式中，如图8所示，第六时间段t6的开始时间发生在第二时间段t2的开始时间之前，第六时间段t6的结束时间发生在第一时间段t1的结束时间之后，且在第五时间段t5的开始时间之前，第五时间段t5的结束时间为第四时间段t4的开始时间。
在示例性实施方式中，第六时间段的持续时长可以大于18H。
在示例性实施方式中，如图8所示，数据单元还被配置为在第一时间段t1向至少一个像素驱动电路所连接的第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM提供无效电平信号，在第二时间段t2向至少一个像素驱动电路所连接的第二复位信号线Reset2、第一扫描信号线Gate1和发光信号线EM提供无效电平信号，在第三时间段t3向至少一个像素驱动电路所连接的第一复位信号线Reset1、第二复位信号线Reset2、第一扫描信号线Gate1和第二扫描信号线Gate2提供无效电平信号，在第五时间段t5向至少一个像素驱动电路所连接的第一复位信号线Reset1、第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM提供无效电平信号。
本公开通过减少数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段来减少向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平的信号的时间，可以减少补偿晶体管的的正偏置温度应力，提升显示基板的显示均一性，还可以不影响显示基板的显示效果的前提下，提升显示基板显示低灰阶显示画面的显示效果。
在示例性实施方式中，如图8所示，在至少一个显示帧，至少一个像素驱动电路所连接的第一复位信号线Reset1的信号为单次脉冲信号，至少一个像素驱动电路所连接的第二复位信号线Reset2的信号为单次脉冲信号，至少一个像素驱动电路所连接的第一扫描信号线Gate1的信号为单次脉冲信号，至少一个像素驱动电路所连接的第二扫描信号线Gate2的信号为单次脉冲信号，至少一个像素驱动电路所连接的发光信号线EM的信号为单次脉冲信号。
在示例性实施方式中，如图5所示，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的状态下，第七时间段t7与第五时间段t5至少部分交叠，第八时间段t8分别与第一时间段t1和第二时间段t2至少部分交叠，第六时间段t6发生在第八时间段t8之后。其中，第五时间段t5和第六时间段t6为数据单元向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号的时间段，且第五时间段t5发生在第六时间段t6之前，第七时间段t7和第八时间段t8为数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的时间段，且第七时间段t7发生在第八时间段t8之前。
在示例性实施方式中，如图5所示，第七时间段t7的持续时间大于第五时间段t5的持续时间，第八时间段t8的持续时间大于第一时间段t1的持续时间和第二时间段t2的持续时间之和；第五时间段t5位于第七时间段t7之内，第一时间段t1和第二时间段t2位于第八时间段t8之内。
在示例性实施方式中，如图5所示，第七时间段t7的开始时间发生在第五时间段t5的开始时间之前，第七时间段t7的结束时间发生在第五时间段t5的开始时间之后，第八时间段t8的开始时间发生在第二时间段t2的开始时间之前，第八时间段t8的结束时间发生在第一时间段t1的结束时间之后，且在第六时间段t6的开始时间之前，第六时间段t6的结束时间为第四时间段t4的开始时间。
在示例性实施方式中，如图5所示，第八时间段t8的持续时间大于第七时间段t7的持续时间，第七时间段t7的持续时间大于第九时间段t9的持续时间的两倍，第九时间段t9的开始时间为第七时间段t7的结束时间，第九时间段t9的结束时间为第八时间段t8的开始时间。数据单元在第九时间段t9向至少一个像素驱动电路所连接的第一扫描信号线Gate1、第二扫描信号线Gate2、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM提供无效电平信号。
在示例性实施方式中，在第七时间段t7的开始时间与第八时间段t8的结束时间之间的持续时间为38H的状态下，第七时间段t7的持续时间可以为14H，第八时间段t8的持续时间可以为18H，第九时间段的持续时长可以为6H，第七时间段、第八时间段和第九时间段的时长可以根据显示基板的显示状态限定，本公开对此不做任何限定。
图5提供的像素驱动电路的工作过程，通过数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2在两个不连续的时间段提供有效电平信号，可以减少补偿晶体管的的正偏置温度应力，提升显示基板的显示均一性。
在示例性实施方式中，如图6所示，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的状态下，第七时间段t7分别与第五时间段t5和第二时间段t2至少部分交叠，第八时间段t8与第一时间段t1至少部分交叠，第六时间段t6发生在第八时间段t8之后。其中，第五时间段t5和第六时间段t6为数据单元向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号的时间段，且第五时间段t5发生在第六时间段t6之前，第七时间段t7和第八时间段t8为数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的时间段，且第七时间段t7发生在第八时间段t8之前。
在示例性实施方式中，如图6所示，第七时间段t7的持续时间大于第五时间段t5的持续时间和第二时间段t2的持续时间之和，第八时间段t8的持续时间大于第一时间段t1的持续时间。第二时间段t2和第五时间段t5位于第七时间段t7之内，第一时间段t1位于第八时间段t8之内。
在示例性实施方式中，如图6所示，第七时间段t7的开始时间发生在第五时间段t5的开始时间之前，第七时间段t7的结束时间发生在第二时间段t2的结束时间之后，第八时间段t8的开始时间发生在第一时间段t1的开始时间之前，第八时间段t8的结束时间发生在第一时间段t1的结束时间之后，且在第六时间段t6的开始时间之前，第六时间段t6的结束时间为第四时间段t4的开始时间。
在示例性实施方式中，如图6所示，第七时间段t7的持续时间大于第八时间段t8的持续时间的四倍，且大于第九时间段t9的持续时间的四倍，第九时间段t9的开始时间为第七时间段t7的结束时间，第九时间段t9的结束时间为第八时间段t8的开始时间。
在示例性实施方式中，如图6所示，在第七时间段t7的开始时间与第八时间段t8的结束时间之间的持续时间为38H的状态下，第七时间段t7的持续时间可以为26H，第八时间段t8的持续时间可以为6H，第九时间段t9的持续时间可以为6H。
图6提供的像素驱动电路的工作过程，通过数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2在两个不连续的时间段提供有效电平信号，可以减少补偿晶体管的的正偏置温度应力，提升显示基板的显示均一性。
在示例性实施方式中，如图5和图6所示，在至少一个显示帧，至少一个像素驱动电路所连接的第一复位信号线Reset1的信号为单次脉冲信号，至少一个像素驱动电路所连接的第二复位信号线Reset2的信号为两次脉冲信号，至少一个像素驱动电路所连接的第一扫描信号线Gate1的信号为单次脉冲信号，至少一个像素驱动电路所连接的第二扫描信号线Gate2的信号为两次脉冲信号，至少一个像素驱动电路所连接的发光信号线EM的信号为单次脉冲信号。
在示例性实施方式中，如图7所示，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号，且在两个时间段内向至少一个 像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的状态下，第七时间段t7与第五时间段t5至少部分交叠，第八时间段t8与第二时间段t2至少部分交叠，第九时间段t9与第一时间段t1至少部分交叠，第六时间段t6发生在第九时间段t9和第四时间段t4之间。其中，第五时间段t5和第六时间段t6为数据单元向至少一个像素驱动电路所连接的第二复位信号线Reset2提供有效电平信号的时间段，且第五时间段t5发生在第六时间段t6之前，第七时间段t7、第八时间段t8和第九时间段t9为数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2提供有效电平信号的时间段，且第七时间段t7发生在第八时间段t8之前，第八时间段t8发生在第九时间段t9之前。
在示例性实施方式中，如图7所示，第七时间段t7的持续时间大于第五时间段t5的持续时间，第八时间段t8的持续时间大于第二时间段t2的持续时间，第九时间段t9的持续时间大于第一时间段t1的持续时间。第五时间段t5位于第七时间段t7之内，第二时间段t2位于第八时间段t8之内，第一时间段t1位于第九时间段t9之内。
在示例性实施方式中，如图7所示，第七时间段t7的开始时间发生在第五时间段t5的开始时间之前，第七时间段t7的结束时间发生在第五时间段t5的结束时间之后，第八时间段t8的开始时间发生在第二时间段t2的开始时间之前，第八时间段t8的结束时间发生在第二时间段t2的结束时间之后，第九时间段t9的开始时间发生在第一时间段t1的开始时间之前，第九时间段t9的结束时间发生在第一时间段t1的结束时间之后，且在第六时间段t6的开始时间之前，第六时间段t6的结束时间为第四时间段t4的开始时间。
在示例性实施方式中，如图7所示，第七时间段t7和第八时间段t8中的至少一个时间段的持续时间大于第九时间段t9的持续时间，且大于第十时间段t10和第十一时间段t11中的至少一个时间段的持续时间，第十时间段t10的开始时间为第七时间段t7的结束时间，第十时间段t10的结束时间为第八时间段t8的开始时间，第十一时间段t11的开始时间为第八时间段t8的结束时间，第十一时间段t11的结束时间为第九时间段t9的开始时间。
在示例性实施方式中，在第七时间段t7的开始时间与第八时间段t8的结束时间之间的持续时间为38H的状态下，第七时间段t7的持续时间可以为10H，第十时间段t10的持续时间可以为6H，第八时间段t8的持续时间可以为10H，第十一时间段t11的持续时间可以为6H，第九时间段t9的持续时间可以为6H。
在示例性实施方式中，第七时间段t7的持续时间可以大于10H。第十时间段t10的持续时间可以大于6H，第八时间段t8的持续时间可以大于10H，第十一时间段t11的持续时间可以大于6H，第九时间段t9的持续时间可以大于6H。
在示例性实施方式中，如图7所示，数据单元在第十时间段t10和第十一时间段t11向至少一个像素驱动电路所连接的第一扫描信号线Gate1、第二扫描信号线Gate2、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM提供无效电平信号。
在示例性实施方式中，如图7所示，在至少一个显示帧，至少一个像素驱动电路所连接的第一复位信号线Reset1的信号为单次脉冲信号，至少一个像素驱动电路所连接的第二复位信号线Reset2的信号为两次脉冲信号，至少一个像素驱动电路所连接的第一扫描信号线Gate1的信号为单次脉冲信号，至少一个像素驱动电路所连接的第二扫描信号线Gate2的信号为三次脉冲信号，至少一个像素驱动电路所连接的发光信号线EM的信号为单次脉冲信号。
图7提供的像素驱动电路的工作过程，通过数据单元向至少一个像素驱动电路所连接的第二扫描信号线Gate2在三个不连续的时间段提供有效电平信号，可以减少补偿晶体管 的的正偏置温度应力，提升显示基板的显示均一性。
在示例性实施方式中，如图5至图7所示，数据单元还被配置为在第一时间段t1向至少一个像素驱动电路所连接的第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM提供无效电平信号，在第二时间段t2向至少一个像素驱动电路所连接的第二复位信号线Reset2、第一扫描信号线Gate1和发光信号线EM提供无效电平信号，在第三时间段t3向至少一个像素驱动电路所连接的第一复位信号线Reset1、第二复位信号线Reset2、第一扫描信号线Gate1和第二扫描信号线Gate2提供无效电平信号，在第五时间段t5向至少一个像素驱动电路所连接的第一复位信号线Reset1、第一扫描信号线Gate1和发光信号线EM提供无效电平信号，在第六时间段t6向至少一个像素驱动电路所连接的第一复位信号线Reset1、第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM提供无效电平信号。
在示例性实施方式中，以像素驱动电路为图4为例，结合图4至图5所示，补偿晶体管T2为N型晶体管、第一复位晶体管T1、驱动晶体管T3、写入晶体管T4、第一发光晶体管T5、第二发光晶体管T6、第二复位晶体管T7和第八复位晶体管T8为P型晶体管为例说明一种示例性实施例提供的像素驱动电路的工作过程，如图5所示，在至少一个显示帧的刷新帧中，至少一个像素驱动电路的工作过程可以包括：第一阶段S11、第二阶段S12、第三阶段S13、第四阶段S14、第五阶段S15和第六阶段S16，其中，第一阶段S11为第五时间段t5所在的阶段，第二阶段S12为第二时间段t2所在的阶段，第三阶段S13为第一时间段t1所在的阶段，第四阶段S14为第六时间段t6所在的阶段，第五阶段S15为第四时间段t4所在的阶段，第六阶段S16为第三时间段t3所在的阶段。
第一阶段S11、即第一初始化阶段，第一扫描信号线Gate1、第二扫描信号线Gate2、第一复位信号线Reset1和发光信号线EM的信号均为高电平信号，第二复位信号线Reset2的信号为低电平信号。第二复位信号线Reset2的信号为低电平信号，第二复位晶体管T7和第三复位晶体管T8导通，第二初始信号线Vinit2的第二初始信号写入第四节点N4，对第四节点N4(也就是发光器件的第一极)进行初始化(复位)，清空其内部的预存电压，完成初始化，由于驱动晶体管T3导通，第三初始信号线Vinit3的第三初始信号写入第二节点N2和第三节点N3，对第二节点N2和第三节点N3进行初始化(复位)，清空其内部的预存电压，完成初始化。第二扫描信号线Gate2信号为高电平信号，补偿晶体管T2导通，第三节点N3的信号写入第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压，完成初始化，本阶段，驱动晶体管T3导通。第一扫描信号线Gate1、第二复位信号线Reset2和发光信号线EM的信号为高电平信号，写入晶体管T4、第一发光晶体管T5、第二发光晶体管T6、第二复位晶体管T7和第三复位晶体管T8断开。此阶段，发光元件L不发光。
第二阶段S12、即第二初始化阶段，第一扫描信号线Gate1、第二扫描信号线Gate2、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第一复位信号线Reset1、的信号为低电平信号。第一复位信号线Reset1的信号为低电平信号，第一复位晶体管T1导通，第一初始信号线Vinit1的第一初始信号写入第三节点N3，对第三节点N3进行初始化(复位)，清空其内部的预存电压，完成初始化，由于第二扫描信号线Gate2的信号为高电平信号，补偿晶体管T2导通，第三节点N3的信号持续写入第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压，完成初始化。第一扫描信号线Gate1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，写入晶体管T4、第二复位晶体管T7、第三复位晶体管T8、第一发光晶体管T5和第六发光晶体管T6断开。此阶段，发光元件L不发光。
第三阶段13、即数据写入阶段，第二扫描信号线Gate2、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第一扫描信号线Gate1的信号为低电平信号，数据信号线Data写入数据电压。第一扫描信号线Gate1的信号为低电平信号，写入晶体管T4导通，第二扫描信号线Gate2的信号为高电平信号，补偿晶体管T2导通，数据信号线Data输出的数据电压经过导通的写入晶体管T4、第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的补偿晶体管T2写入至第一节点N1，并将数据信号线Data输出的第二数据电压与驱动晶体管T3的阈值电压之差充入电容C，直至第一节点N1的电压为Vdata-|Vth|，Vdata为数据信号线Data输出的数据电压，Vth为驱动晶体管T3的阈值电压。第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第一复位晶体管T1、第二复位晶体管T7、第三复位晶体管T8、第一发光晶体管T5和第六发光晶体管T6断开。此阶段，发光元件L不发光。此阶段，发光元件L不发光。
第四阶段S14、即第三初始化阶段，第一扫描信号线Gate1、第一复位信号线Reset1和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2和第二复位信号线Reset2的信号为低电平信号。第二复位信号线Reset2的信号为低电平信号，第二复位晶体管T7和第三复位晶体管T8导通，第二初始信号线Vinit2的第二初始信号写入第四节点N4，对第四节点N4(也就是发光器件的第一极)进行初始化(复位)，清空其内部的预存电压，完成初始化，由于驱动晶体管T3导通，第三初始信号线Vinit3的第三初始信号写入第二节点N2和第三节点N3，对第二节点N2和第三节点N3进行初始化(复位)，清空其内部的预存电压，完成初始化。第一复位信号线Reset1、第一扫描信号线Gate1和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2的信号为高电平信号，补偿晶体管T2、写入晶体管T4、第一复位晶体管T1、第一发光晶体管T5和第六发光晶体管T6断开。此阶段，发光元件L不发光。此阶段，发光元件L不发光。
第五阶段S15、即保持阶段，第一扫描信号线Gate1、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2的信号为低电平信号。第一扫描信号线Gate1、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2的信号为低电平信号，第一复位晶体管T1、补偿晶体管T2、写入晶体管T4、第一发光晶体管T5、第六发光晶体管T6、第二复位晶体管T7和第三复位晶体管T8断开，本阶段，驱动晶体管T3导通，可以使得第三初始信号线Vinit3的第三初始信号有足够的时间可以作用到驱动晶体管T3的第一极和第二极，本阶段，第一节点N1的信号的电压值大于第二节点N2的信号的电压值，使得驱动晶体管T3可以长时间处于偏压状态，从而改善驱动晶体管T3的磁滞状态，进而改善显示基板的低频闪烁问题。
第六阶段S16、即发光阶段，第一扫描信号线Gate1、第一复位信号线Reset1和第二复位信号线Reset2的信号均为高电平信号，第二扫描信号线Gate2和发光信号线EM的信号为低电平信号。发光信号线EM的信号为低电平信号，第一发光晶体管T5和第六发光晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第一发光晶体管T5、驱动晶体管T3和第六发光晶体管T6向第四节点N4提供驱动电压，驱动发光器件L发光。
在像素驱动电路刷新帧的驱动过程中，流过驱动晶体管T3的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vdata+|Vth|)-Vth]2＝K*[(Vdd-Vdata]2
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光器件L的驱动电流，K 为常数，Vgs为驱动晶体管T3的控制极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据信号线Data输出的第二数据电压，Vdd为第一电源端VDD输出的电源电压。
在示例性实施方式中，图6和图7提供的像素驱动电路的驱动方法与图5提供的像素驱动电路的驱动方法，在第五时间段、第二时间段、第一时间段、第六时间段、第四时间段和第三时间段，像素驱动电路所连接的第一扫描信号线、第二扫描信号线、第一复位信号线、第二复位信号线和发光信号线的信号相同，因此，像素驱动电路的工作过程均相同，本公开对此不做任何限定。
在示例性实施方式中，以像素驱动电路为图4为例，结合图4和图8所示，补偿晶体管T2为N型晶体管、第一复位晶体管T1、驱动晶体管T3、写入晶体管T4、第一发光晶体管T5、第二发光晶体管T6、第二复位晶体管T7和第八复位晶体管T8为P型晶体管为例说明一种示例性实施例提供的像素驱动电路的工作过程，如图8所示，在至少一个显示帧的刷新帧中，至少一个像素驱动电路的工作过程可以包括：第一阶段S21、第二阶段S22、第三阶段S23、第四阶段S24和第五阶段S25，其中，第一阶段S21为第二时间段t2所在的阶段，第二阶段S22为第一时间段t1所在的阶段，第三阶段S23为第五时间段t5所在的阶段，第四阶段S24为第四时间段t4所在的阶段，第五阶段S25为第三时间段t3所在的阶段。
第一阶段S21、即第一初始化阶段，第一扫描信号线Gate1、第二扫描信号线Gate2、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第一复位信号线Reset1、的信号为低电平信号。第一复位信号线Reset1的信号为低电平信号，第一复位晶体管T1导通，第一初始信号线Vinit1的第一初始信号写入第三节点N3，对第三节点N3进行初始化(复位)，清空其内部的预存电压，完成初始化，由于第二扫描信号线Gate2的信号为高电平信号，补偿晶体管T2导通，第三节点N3的信号持续写入第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压，完成初始化。第一扫描信号线Gate1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，写入晶体管T4、第二复位晶体管T7、第三复位晶体管T8、第一发光晶体管T5和第六发光晶体管T6断开。此阶段，发光元件L不发光。
第二阶段22、即数据写入阶段，第二扫描信号线Gate2、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第一扫描信号线Gate1的信号为低电平信号，数据信号线Data写入数据电压。第一扫描信号线Gate1的信号为低电平信号，写入晶体管T4导通，第二扫描信号线Gate2的信号为高电平信号，补偿晶体管T2导通，数据信号线Data输出的数据电压经过导通的写入晶体管T4、第二节点N2、导通的驱动晶体管T3、第三节点N3、导通的补偿晶体管T2写入至第一节点N1，并将数据信号线Data输出的第二数据电压与驱动晶体管T3的阈值电压之差充入电容C，直至第一节点N1的电压为Vdata-|Vth|，Vdata为数据信号线Data输出的数据电压，Vth为驱动晶体管T3的阈值电压。第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第一复位晶体管T1、第二复位晶体管T7、第三复位晶体管T8、第一发光晶体管T5和第六发光晶体管T6断开。此阶段，发光元件L不发光。此阶段，发光元件L不发光。
第三阶段S23、即第二初始化阶段，第一扫描信号线Gate1、第一复位信号线Reset1和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2和第二复位信号线Reset2的信号为低电平信号。第二复位信号线Reset2的信号为低电平信号，第二复位晶体管T7和第三复位晶体管T8导通，第二初始信号线Vinit2的第二初始信号写入第四节 点N4，对第四节点N4(也就是发光器件的第一极)进行初始化(复位)，清空其内部的预存电压，完成初始化，由于驱动晶体管T3导通，第三初始信号线Vinit3的第三初始信号写入第二节点N2和第三节点N3，对第二节点N2和第三节点N3进行初始化(复位)，清空其内部的预存电压，完成初始化。第一复位信号线Reset1、第一扫描信号线Gate1和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2的信号为高电平信号，补偿晶体管T2、写入晶体管T4、第一复位晶体管T1、第一发光晶体管T5和第六发光晶体管T6断开。此阶段，发光元件L不发光。此阶段，发光元件L不发光。
第四阶段S24、即保持阶段，第一扫描信号线Gate1、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2的信号为低电平信号。第一扫描信号线Gate1、第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号均为高电平信号，第二扫描信号线Gate2的信号为低电平信号，第一复位晶体管T1、补偿晶体管T2、写入晶体管T4、第一发光晶体管T5、第六发光晶体管T6、第二复位晶体管T7和第三复位晶体管T8断开，本阶段，驱动晶体管T3导通，可以使得第三初始信号线Vinit3的第三初始信号有足够的时间可以作用到驱动晶体管T3的第一极和第二极，本阶段，第一节点N1的信号的电压值大于第二节点N2的信号的电压值，使得驱动晶体管T3可以长时间处于偏压状态，从而改善驱动晶体管T3的磁滞状态，进而改善显示基板的低频闪烁问题。
第五阶段S25、即发光阶段，第一扫描信号线Gate1、第一复位信号线Reset1和第二复位信号线Reset2的信号均为高电平信号，第二扫描信号线Gate2和发光信号线EM的信号为低电平信号。发光信号线EM的信号为低电平信号，第一发光晶体管T5和第六发光晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第一发光晶体管T5、驱动晶体管T3和第六发光晶体管T6向第四节点N4提供驱动电压，驱动发光器件L发光。
在像素驱动电路刷新帧的驱动过程中，流过驱动晶体管T3的驱动电流由控制极和第一极之间的电压差决定。由于第一节点N1的电压为Vdata-|Vth|，因而驱动晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vdata+|Vth|)-Vth]2＝K*[(Vdd-Vdata]2
其中，I为流过驱动晶体管T3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为驱动晶体管T3的控制极和第一极之间的电压差，Vth为驱动晶体管T3的阈值电压，Vdata为数据信号线Data输出的第二数据电压，Vdd为第一电源端VDD输出的电源电压。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
本公开实施例还提供了一种显示基板的驱动方法，被配置为驱动显示基板，显示基板的驱动方法可以包括：
在至少一个显示帧，在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号，或者，在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号。
本公开实施例还提供了一种显示装置，包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似在，在此不再赘述。
在示例性实施方式中，显示装置可以为显示器、电视、手机、平板电脑、导航仪、数码相框、可穿戴显示产品具有任何显示功能的产品或者部件。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (24)

  1. 一种显示基板，显示基板所显示内容包括多个显示帧，所述显示基板包括：数据单元、阵列排布的像素驱动电路、多条第二复位信号线和多条第二扫描信号线，至少一个像素驱动电路包括：驱动晶体管、补偿晶体管和第三复位晶体管，其中，所述驱动晶体管分别与第一节点、第二节点和第三节点连接，所述补偿晶体管分别与第二扫描信号线、第一节点和第三节点连接，所述第三复位晶体管分别与第二复位信号线和第二节点连接；
    在至少一个显示帧，所述数据单元被配置为在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号，或者，在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号。
  2. 根据权利要求1所述的显示基板，还包括：多条第一扫描信号线、多条第一复位信号线和多条发光信号线，至少一个像素驱动电路还包括：写入晶体管、第一复位晶体管和第一发光晶体管，其中，所述写入晶体管分别与第一扫描信号线和第二节点连接，所述第一复位晶体管分别与第一复位信号线和第三节点连接，所述第一发光晶体管分别与发光信号线和第二节点连接；
    在至少一个显示帧，所述数据单元被配置为在第一时间段向至少一个像素驱动电路所连接的第一扫描信号线提供有效电平信号，在第二时间段向至少一个像素驱动电路所连接的第一复位信号线提供有效电平信号，在第三时间段向至少一个像素驱动电路所连接的发光信号线提供有效电平信号，在第四时间段向至少一个像素驱动电路所连接的第一扫描信号线、第二扫描信号线、第一复位信号线、第二复位信号线和发光信号线提供无效电平信号；
    所述第二时间段发生在所述第一时间段之前，且所述第二时间段的结束时间发生在所述第一时间段的开始时间之前，所述第一时间段发生在所述第四时间段之前，且所述第一时间段的结束时间发生在所述第四时间段的开始之前，所述第四时间段发生在所述第三时间段之前，且所述第四时间段的结束时间为所述第三时间段的开始时间。
  3. 根据权利要求2所述的显示基板，其中，至少一个像素驱动电路所连接的第二扫描信号线的信号为有效电平信号的至少一个时间段与所述第一时间段和所述第二时间段中的至少一个时间段至少部分交叠，且与第三时间段和第四时间段中的至少一个时间段不交叠；
    至少一个像素驱动电路所连接的第二复位信号线的信号的有效电平信号的至少一个时间段与第一时间段、所述第二时间段、所述第三时间段和所述第四时间段中的至少一个时间段不交叠。
  4. 根据权利要求3所述的显示基板，其中，在数据单元在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第六时间段分别与所述第一时间段和所述第二时间段至少部分交叠，第五时间段发生在所述第六时间段之后；
    其中，所述第五时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，所述第六时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段。
  5. 根据权利要求4所述的显示基板，其中，所述第六时间段的持续时间大于所述第一时间段的持续时间和所述第二时间段的持续时间之和；
    所述第一时间段和所述第二时间段位于所述第六时间段之内。
  6. 根据权利要求5所述的显示基板，其中，所述第六时间段的开始时间发生在所述第二时间段的开始时间之前，所述第六时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第五时间段的开始时间之前，所述第五时间段的结束时间为所述第四时间段的开始时间。
  7. 根据权利要求6所述的显示基板，其中，所述数据单元还被配置为在第一时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线和发光信号线提供无效电平信号，在第二时间段向至少一个像素驱动电路所连接的第二复位信号线、第一扫描信号线和发光信号线提供无效电平信号，在第三时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线、第一扫描信号线和第二扫描信号线提供无效电平信号，在第五时间段向至少一个像素驱动电路所连接的第一复位信号线、第一扫描信号线、第二扫描信号线和发光信号线提供无效电平信号。
  8. 根据权利要求3所述的显示基板，其中，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第七时间段与第五时间段至少部分交叠，第八时间段分别与所述第一时间段和所述第二时间段至少部分交叠，所述第六时间段发生在所述第八时间段之后；
    其中，所述第五时间段和第六时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，且所述第五时间段发生在所述第六时间段之前，所述第七时间段和所述第八时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段，且所述第七时间段发生在所述第八时间段之前。
  9. 根据权利要求8所述的显示基板，其中，所述第七时间段的持续时间大于所述第五时间段的持续时间，所述第八时间段的持续时间大于所述第一时间段的持续时间和所述第二时间段的持续时间之和；
    所述第五时间段位于所述第七时间段之内，所述第一时间段和所述第二时间段位于所述第八时间段之内。
  10. 根据权利要求9所述的显示基板，其中，所述第七时间段的开始时间发生在所述第五时间段的开始时间之前，所述第七时间段的结束时间发生在所述第五时间段的开始时间之后，所述第八时间段的开始时间发生在所述第二时间段的开始时间之前，所述第八时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第六时间段的开始时间之前，所述第六时间段的结束时间为所述第四时间段的开始时间。
  11. 根据权利要求10所述的显示基板，其中，所述第八时间段的持续时间大于所述第七时间段的持续时间，所述第七时间段的持续时间大于第九时间段的持续时间的两倍，所述第九时间段的开始时间为第七时间段的结束时间，第九时间段的结束时间为第八时间段的开始时间；
    所述数据单元在所述第九时间段向至少一个像素驱动电路所连接的第一扫描信号线、第二扫描信号线、第一复位信号线、第二复位信号线和发光信号线提供无效电平信号。
  12. 根据权利要求3所述的显示基板，其中，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在两个时间段内向至少一个 像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第七时间段分别与第五时间段和所述第二时间段至少部分交叠，第八时间段与所述第一时间段至少部分交叠，所述第六时间段发生在所述第八时间段之后；
    其中，所述第五时间段和第六时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，且所述第五时间段发生在所述第六时间段之前，所述第七时间段和所述第八时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段，且所述第七时间段发生在所述第八时间段之前。
  13. 根据权利要求12所述的显示基板，其中，所述第七时间段的持续时间大于所述第五时间段的持续时间和所述第二时间段的持续时间之和，所述第八时间段的持续时间大于所述第一时间段的持续时间；
    所述第二时间段和所述第五时间段位于所述第七时间段之内，所述第一时间段位于所述第八时间段之内。
  14. 根据权利要求13所述的显示基板，其中，所述第七时间段的开始时间发生在所述第五时间段的开始时间之前，所述第七时间段的结束时间发生在所述第二时间段的结束时间之后，所述第八时间段的开始时间发生在所述第一时间段的开始时间之前，所述第八时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第六时间段的开始时间之前，所述第六时间段的结束时间为所述第四时间段的开始时间。
  15. 根据权利要求14所述的显示基板，其中，所述第七时间段的持续时间大于所述第八时间段的持续时间的四倍，且大于第九时间段的持续时间的四倍，所述第九时间段的开始时间为所述第七时间段的结束时间，所述第九时间段的结束时间为所述第八时间段的开始时间。
  16. 根据权利要求3所述的显示基板，其中，在数据单元在两个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的状态下，第七时间段与第五时间段至少部分交叠，第八时间段与所述第二时间段至少部分交叠，所述第九时间段与所述第一时间段至少部分交叠，所述第六时间段发生在所述第九时间段和所述第四时间段之间；
    其中，所述第五时间段和第六时间段为数据单元向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号的时间段，且所述第五时间段发生在所述第六时间段之前，所述第七时间段、所述第八时间段和所述第九时间段为数据单元向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号的时间段，且所述第七时间段发生在所述第八时间段之前，所述第八时间段发生在所述第九时间段之前。
  17. 根据权利要求16所述的显示基板，其中，所述第七时间段的持续时间大于所述第五时间段的持续时间，所述第八时间段的持续时间大于所述第二时间段的持续时间，第九时间段的持续时间大于第一时间段的持续时间；
    所述第五时间段位于所述第七时间段之内，所述第二时间段位于第八时间段之内，所述第一时间段位于所述第九时间段之内。
  18. 根据权利要求17所述的显示基板，其中，所述第七时间段的开始时间发生在所述第五时间段的开始时间之前，所述第七时间段的结束时间发生在所述第五时间段的结束时间之后，所述第八时间段的开始时间发生在所述第二时间段的开始时间之前，所述第八时间段的结束时间发生在所述第二时间段的结束时间之后，所述第九时间段的开始时间发生在所述第一时间段的开始时间之前，所述第九时间段的结束时间发生在所述第一时间段的结束时间之后，且在所述第六时间段的开始时间之前，所述第六时间段的结束时间为所 述第四时间段的开始时间。
  19. 根据权利要求18所述的显示基板，其中，所述第七时间段和所述第八时间段中的至少一个时间段的持续时间大于所述第九时间段的持续时间，且大于第十时间段和第十一时间段中的至少一个时间段的持续时间，第十时间段的开始时间为第七时间段的结束时间，第十时间段的结束时间为第八时间段的开始时间，第十一时间段的开始时间为第八时间段的结束时间，第十一时间段的结束时间为第九时间段的开始时间；
    所述数据单元在所述第十时间段和所述第十一时间段向至少一个像素驱动电路所连接的第一扫描信号线、第二扫描信号线、第一复位信号线、第二复位信号线和发光信号线提供无效电平信号。
  20. 根据权利要求8、12和16中的至少一项所述的显示基板，其中，所述数据单元还被配置为在第一时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线和发光信号线提供无效电平信号，在第二时间段向至少一个像素驱动电路所连接的第二复位信号线、第一扫描信号线和发光信号线提供无效电平信号，在第三时间段向至少一个像素驱动电路所连接的第一复位信号线、第二复位信号线、第一扫描信号线和第二扫描信号线提供无效电平信号，在第五时间段向至少一个像素驱动电路所连接的第一复位信号线、第一扫描信号线和发光信号线提供无效电平信号，在第六时间段向至少一个像素驱动电路所连接的第一复位信号线、第一扫描信号线、第二扫描信号线和发光信号线提供无效电平信号。
  21. 根据权利要求1所述的显示基板，还包括：多条发光信号线、多条第一复位信号线、多条第一初始信号线、多条第二初始信号线、多条第三初始信号线、多条第一扫描信号线和多条第一电源线，至少一个像素驱动电路还包括：第一复位晶体管、第二复位晶体管、写入晶体管、第一发光晶体管、第二发光晶体管和电容；
    所述补偿晶体管的控制极与第二扫描信号线连接，所述补偿晶体管的第一极与第一节点连接，所述补偿晶体管的第二极与第三节点连接；
    所述驱动晶体管的控制极与第一节点连接，所述驱动晶体管的第一极与第二节点连接，所述驱动晶体管的第二极与第三节点连接；
    所述写入晶体管的控制极与第一扫描信号线连接，所述写入晶体管的第一极与数据信号线连接，所述写入晶体管的第二极与第二节点连接；
    所述第一复位晶体管的控制极与第一复位信号线连接，所述第一复位晶体管的第一极与第一初始信号线连接，所述第一复位晶体管的第二极与第三节点连接；
    所述第二复位晶体管的控制极与第二复位信号线连接，所述第二复位晶体管的第一极与第二初始信号线连接，所述第二复位晶体管的第二极与第四节点连接；
    所述第三复位晶体管的控制极与第二复位信号线连接，所述第三复位晶体管的第一极与第三初始信号线连接，所述第三复位晶体管的第二极与第二节点连接；
    所述第一发光晶体管的控制极与发光信号线连接，所述第一发光晶体管的第一极与第一电源线连接，所述第一发光晶体管的第二极与第二节点连接；
    所述第二发光晶体管的控制极与发光信号线连接，所述第二发光晶体管的第一极与第三节点连接，所述第二发光晶体管的第二极与第四节点连接；
    所述电容的一端与第一电源线连接，所述电容的另一端与第一节点连接。
  22. 根据权利要求21所述的显示基板，其中，至少一个像素驱动电路中的至少一个晶体管为P型晶体管或者N型晶体管，所述第一发光晶体管和第二发光晶体管的晶体管 类型相同，所述第二复位晶体管和所述第三复位晶体管的晶体管类型相同。
  23. 一种显示装置，包括：如权利要求1至22任一项所述的显示基板。
  24. 一种显示基板的驱动方法，被配置为驱动如权利要求1至22任一项所述的显示基板，所述方法包括：
    在至少一个显示帧，在一个时间段内向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在一个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号，或者，在至少两个时间段向至少一个像素驱动电路所连接的第二复位信号线提供有效电平信号，且在至少两个时间段内向至少一个像素驱动电路所连接的第二扫描信号线提供有效电平信号。
PCT/CN2023/140232 2023-12-20 2023-12-20 显示基板及其驱动方法、显示装置 Pending WO2025129495A1 (zh)

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KR101408809B1 (ko) * 2013-04-30 2014-07-02 금오공과대학교 산학협력단 유기발광다이오드 표시장치의 문턱전압 보상 화소회로
CN115691408A (zh) * 2021-07-30 2023-02-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板及显示装置
CN115691411A (zh) * 2021-07-30 2023-02-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN116110338A (zh) * 2023-01-29 2023-05-12 京东方科技集团股份有限公司 一种像素驱动电路及其控制方法、显示装置

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Publication number Priority date Publication date Assignee Title
KR101408809B1 (ko) * 2013-04-30 2014-07-02 금오공과대학교 산학협력단 유기발광다이오드 표시장치의 문턱전압 보상 화소회로
CN115691408A (zh) * 2021-07-30 2023-02-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板及显示装置
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