WO2025118331A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2025118331A1
WO2025118331A1 PCT/CN2023/138777 CN2023138777W WO2025118331A1 WO 2025118331 A1 WO2025118331 A1 WO 2025118331A1 CN 2023138777 W CN2023138777 W CN 2023138777W WO 2025118331 A1 WO2025118331 A1 WO 2025118331A1
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Prior art keywords
layer
channel
gap
stacked structure
gate electrode
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English (en)
French (fr)
Inventor
唐怡
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CXMT Corp
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CXMT Corp
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Priority to KR1020267021130A priority Critical patent/KR20260118516A/ko
Publication of WO2025118331A1 publication Critical patent/WO2025118331A1/zh
Priority to US19/251,792 priority patent/US20250324573A1/en
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/33—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same.
  • the size of the memory needs to be scaled.
  • scaling the size of the memory may lead to degradation of the electrical performance of the memory.
  • an embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:
  • the stacked structure includes semiconductor layers and interlayer insulating layers stacked alternately;
  • a channel layer, a second gate dielectric layer and a gate electrode covering the sidewalls of the channel hole are formed in sequence; wherein the channel layer, the second gate dielectric layer and the gate electrode together form a transistor, and the back gate electrode is used to adjust the threshold voltage of the transistor.
  • the manufacturing method before forming a plurality of channel holes penetrating the stacked structure, the manufacturing method further includes:
  • a plurality of groove groups are formed which penetrate the stacked structure and are arranged along a first direction, each of the groove groups comprises a first groove and a second groove which are arranged in parallel along a second direction; the remaining stacked structure comprises a first sub-stacked structure located between the first groove and the second groove, a second sub-stacked structure located between adjacent first grooves, a third sub-stacked structure located between adjacent second grooves, a fourth sub-stacked structure located between adjacent first sub-stacked structures, and a fifth sub-stacked structure located on one side of the first groove and the second sub-stacked structure; wherein the first direction and the second direction are both parallel to the substrate and the first direction and the second direction intersect;
  • An isolation material is filled in the first groove and the second groove to form an isolation structure.
  • forming a plurality of channel holes penetrating the stacked structure includes:
  • At least the fourth sub-stacked structure in the remaining stacked structure is etched to form a plurality of channel holes penetrating the stacked structure and arranged along the first direction.
  • the manufacturing method further includes:
  • the first gap exposes a portion of the channel layer that is relatively arranged along the first direction;
  • An isolation material is filled in the first gap to form a first interlayer isolation layer.
  • removing the interlayer insulating layer in the first sub-stacked structure to form a first gap includes:
  • the remaining semiconductor layer between the holes and between adjacent channel holes serves as a back gate electrode;
  • the interlayer insulating layer is removed by transverse etching along the threshold voltage adjustment hole to form a first gap; the threshold voltage adjustment hole is connected to the first gap.
  • filling the first gap with an isolation material to form a first interlayer isolation layer includes:
  • a conductive material is filled in the threshold voltage adjustment hole to form a threshold voltage adjustment structure electrically connected to the back gate electrode; wherein the threshold voltage adjustment structure is used to adjust the threshold voltage of the transistor.
  • the manufacturing method further includes:
  • the second gap exposes a portion of the channel layer that is oppositely arranged along the second direction;
  • first interlayer isolation layer and the second interlayer isolation layer isolate the remaining channel layer in each of the channel holes into channel portions of a plurality of transistors; two side walls of the channel portion that are arranged opposite to each other along the second direction form a first source and a drain and a second source and a drain, respectively; a plurality of transistors arranged along a third direction are connected to the same gate electrode; and the third direction is perpendicular to the substrate.
  • the manufacturing method further includes:
  • a conductive material is filled in the third gap to form a plurality of bit lines extending along the first direction and electrically connected to the first source and drain.
  • the manufacturing method further includes:
  • a storage capacitor electrically connected to the second source and drain is formed in the fourth gap.
  • the manufacturing method further includes:
  • Conductive material is simultaneously filled in the third gap and the threshold voltage adjustment hole to respectively form a plurality of bit lines extending along the first direction and electrically connected to the first source and drain, and a threshold voltage adjustment structure electrically connected to the back gate electrode; wherein the threshold voltage adjustment structure is used to adjust the threshold voltage of the transistor.
  • an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:
  • a plurality of channel portions arranged in an array along a first direction and a third direction, wherein the first direction is parallel to the substrate, and the third direction is perpendicular to the substrate;
  • a gate electrode extending along the third direction and penetrating the channel portion
  • a second gate dielectric layer located between the channel portion and the gate electrode; the channel portion, the second gate dielectric layer and the gate electrode together constitute a transistor;
  • a first gate dielectric layer covering two side walls of each channel portion that are opposite to each other along the first direction;
  • a back gate electrode located between adjacent transistors arranged along the first direction; wherein the back gate electrode is in contact with the first gate dielectric layer; and the back gate electrode is used to adjust the threshold voltage of the transistor.
  • two side walls of the channel portion disposed opposite to each other along a second direction respectively constitute a first source and a drain and a second source and a drain; the second direction is parallel to the substrate and intersects with the first direction; the semiconductor device further comprises:
  • a bit line extending along the first direction, and a plurality of the first source and drain electrodes arranged along the first direction are connected to the same bit line. Wire;
  • a plurality of storage capacitors are provided, and the storage capacitors are connected to the second source and drain.
  • the semiconductor device further comprises:
  • a threshold voltage adjustment structure is located between adjacent back gate electrodes of adjacent channel portions arranged along the first direction, wherein the threshold voltage adjustment structure extends along the third direction and electrically connects a plurality of back gate electrodes arranged along the third direction.
  • the channel portion is a ring-shaped structure parallel to the substrate
  • a size of the channel portion along the second direction is greater than or equal to a size of the back gate electrode along the second direction.
  • the present disclosure provides a semiconductor device and a method for manufacturing the same.
  • multiple channel holes are formed through the stacked structure, gate electrodes are formed in the channel holes, and the semiconductor layer in the stacked structure is used as a back gate electrode, so that the threshold voltage of the transistor can be adjusted by the back gate electrode.
  • FIG1 is a schematic diagram of a three-dimensional structure of a semiconductor device provided by an example
  • FIG2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure
  • 3A to 3P are schematic diagrams of a three-dimensional structure of a semiconductor device during a manufacturing process provided by an example
  • 4A to 4F are schematic cross-sectional views of a semiconductor device during a manufacturing process provided by an example
  • 5A and 5B are schematic structural diagrams of a semiconductor device provided by an example
  • 6A and 6B are schematic structural diagrams of a semiconductor device provided in another example.
  • first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.
  • FIG1 is a schematic diagram of a three-dimensional structure of a semiconductor device provided by an example.
  • the semiconductor device 100 includes: a substrate (not shown in FIG1 ) and a plurality of semiconductor pillars 101 located on the substrate, the semiconductor pillars 101 extending along the Y direction and arranged in an array along the X direction and the Z direction; wherein the semiconductor pillars 101 include a source, a drain, and a channel region between the source and the drain along the extending direction; a word line 102 surrounding the channel region of the semiconductor pillar 101, the word line 102 extending along the Z direction and a plurality of semiconductor pillars 101 arranged along the Z direction connected to the same word line 102; a bit line 104 connected to the source or drain of the semiconductor pillar 101, the bit line 104 extending along the X direction and a plurality of semiconductor pillars 101 arranged along the X direction connected to the same bit line 104; and a storage capacitor 106 connected to
  • the angle between the X direction and the Y direction is 90 degrees, and both the X direction and the Y direction are perpendicular to the Z direction.
  • the angle between the X direction and the Y direction may also be other angles, for example, 30 degrees, 45 degrees or 90 degrees, and this example does not constitute a limitation on the angle between the X direction, the Y direction and the Z direction.
  • the semiconductor device 100 further includes: a plurality of word line extension lines 103, the word line extension lines 103 extending along the Z direction and arranged along the X direction, and the bottoms of different word line extension lines 103 are connected to different word lines 102; and a plurality of bit line extension lines 105, the bit line extension lines 105 extending along the Z direction and arranged along the X direction, and the bottoms of different bit line extension lines 105 are connected to different bit lines 104.
  • the semiconductor device 100 further includes an isolation layer 107 extending in the X direction, the word line 102 being located between adjacent isolation layers 107 in the Y direction, and the semiconductor column 101 passing through the isolation layer 107 in the Y direction.
  • the isolation layer 107 can separate the word line 102 from the source and drain of the semiconductor column 101, thereby preventing leakage between the source or drain and the channel region of the transistor formed by the semiconductor column, thereby preventing the performance of the semiconductor device from being affected.
  • the semiconductor device 100 in the above example is a three-dimensional dynamic random access memory (3D DRAM) with a structure of one transistor and one storage capacitor (1T1C).
  • 3D DRAM three-dimensional dynamic random access memory
  • IGZO indium gallium zinc oxide
  • the manufacturing process of the above DRAM is relatively simple and low-cost, and has become a key research object in the current industry.
  • the threshold voltage of IGZO is more biased towards negative voltage. But for DRAM, a positive threshold voltage is more conducive to reducing leakage, thereby extending the retention time of stored data.
  • embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.
  • FIG. 2 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:
  • Step S201 providing a substrate and a stacked structure on the substrate, wherein the stacked structure includes alternately stacked semiconductor layers and interlayer insulating layers;
  • Step S202 forming a plurality of channel holes penetrating the stacked structure; wherein the semiconductor layer between adjacent channel holes is used to form a back gate electrode;
  • Step S203 performing oxidation treatment on the semiconductor layer exposed by the sidewalls of the channel hole to form a first gate dielectric layer
  • Step S204 sequentially forming a channel layer, a second gate dielectric layer and a gate electrode covering the sidewalls of the channel hole; wherein the channel layer, the second gate dielectric layer and the gate electrode together form a transistor, and the back gate electrode is used to adjust the threshold voltage of the transistor.
  • a plurality of channel holes are formed penetrating the stacked structure, and a first gate dielectric layer, a channel layer, a second gate dielectric layer and a gate electrode are sequentially formed in the channel holes, wherein the channel layer, the second gate dielectric layer and the gate electrode together form a transistor; and the original semiconductor layer in the stacked structure is used as a back gate electrode, so that the back gate electrode can be used to adjust the threshold voltage of the transistor.
  • Figures 3A to 3P are schematic diagrams of a three-dimensional structure of a semiconductor device provided in an example during the manufacturing process.
  • Figures 4A to 4F are schematic diagrams of a cross-sectional structure of a semiconductor device provided in an example during the manufacturing process. The manufacturing process of the semiconductor device will be described in detail below in conjunction with Figures 3A to 3P and Figures 4A to 4F.
  • step S201 a substrate 201 and a stacked structure 202 located on the substrate 201 are provided, and the stacked structure 202 includes semiconductor layers 203 and interlayer insulating layers 204 that are alternately stacked.
  • semiconductor layers 203 and interlayer insulating layers 204 are alternately stacked in sequence and formed on a substrate 201 , wherein the alternately stacked semiconductor layers 203 and interlayer insulating layers 204 together form a stacked structure 202 ; and a capping layer 205 is formed on the stacked structure 202 .
  • the substrate 201 may be a semiconductor substrate; specifically, it may include at least one single semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, etc.)
  • the invention may also include substrates containing other semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, etc.
  • the material of the semiconductor layer 203 may include but is not limited to polysilicon material; the material of the interlayer insulating layer 204 may include but is not limited to silicon oxide material.
  • the present disclosure has no particular limitation on the number and thickness of the semiconductor layer and the interlayer insulating layer.
  • the material of the capping layer 205 may include but is not limited to silicon nitride material.
  • the process of forming the semiconductor layer 203, the interlayer insulating layer 204 and the covering layer 205 may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the thickness direction of the substrate is defined as the third direction, i.e., the Z direction.
  • the direction perpendicular to the surface of the substrate is defined as the third direction, i.e., the Z direction.
  • a first direction and a second direction intersecting each other are defined in a plane perpendicular to the third direction, wherein the first direction is the X direction and the second direction is the Y direction.
  • the X direction, the Y direction, and the Z direction may be perpendicular to each other.
  • the manufacturing method further includes: etching the cover layer 205 and the stacked structure 202 in sequence along the Z direction to form a plurality of groove groups 206 that penetrate the stacked structure and are arranged along the first direction (i.e., the X direction), and each groove group 206 includes a first groove 207 and a second groove 208 that are arranged in parallel along the second direction (i.e., the Y direction).
  • FIG3B schematically shows three groove groups 206 that are sequentially arranged along the X direction, and each groove group 206 includes a first groove 207 and a second groove 208 that are arranged in parallel along the Y direction.
  • the process of forming the first groove 207 and the second groove 208 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • the first groove 207 and the second groove 208 divide the stacked structure 202 into multiple components, and the remaining stacked structure 202 includes: a first sub-stacked structure 209 located between the first groove 207 and the second groove 208, a second sub-stacked structure 210 located between two adjacent first grooves 207 along the X direction (as shown in the dotted circle in FIG. 3B ), a third sub-stacked structure 211 located between two adjacent second grooves 208 along the X direction, a fourth sub-stacked structure 212 located between two adjacent first sub-stacked structures 209 along the X direction (as shown in the dotted square in FIG. 3B ), and a fifth sub-stacked structure 213 located on one side of the first groove 207 and the second sub-stacked structure 210.
  • the fourth sub-stacked structure 212 is also located between the second sub-stacked structure 210 and the third sub-stacked structure 211 arranged along the Y direction, and the region where the fourth sub-stacked structure 212 is located is used to form a transistor of a semiconductor device.
  • the remaining stacked structures are divided to facilitate the description of the manufacturing process of the semiconductor device, and the difference between different sub-stacked structures is only the relative position relationship between the first groove and the second groove.
  • the substrate is not shown in FIGS. 3B to 3P .
  • an isolation material is filled in the first groove 207 and the second groove 208 to form an isolation structure 214 .
  • the process of forming the semiconductor layer 203 and the interlayer insulating layer 204 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.
  • the material of the isolation structure 214 may include a low dielectric constant material, for example, silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride or silicon oxynitride.
  • the materials of the cover layer 205 and the isolation structure 214 may be the same or different.
  • FIG. 3C illustrates that the cover layer 205 and the isolation structure 214 are the same, that is, both are silicon nitride materials.
  • the top surface of the cover layer 205 may be flush with the top surface of the isolation structure 214.
  • step S202 a plurality of channel holes 215 penetrating the stacked structure 202 are formed; wherein the semiconductor layer 203 located between adjacent channel holes 215 is used to form a back gate electrode 222 .
  • step S202 includes: etching the capping layer 205 and at least the fourth sub-stacked structure 212 in the stacked structure 202 in sequence along the Z direction to form a plurality of channel holes 215 that penetrate the stacked structure 202 and are arranged along the first direction (i.e., the X direction).
  • the orthographic projection area of the channel hole 215 on the substrate i.e., the XY plane
  • the orthographic projection area of the fourth sub-stacked structure 212 on the substrate i.e., the XY plane
  • the orthographic projection area of the formed channel hole 215 on the XY plane is equal to the orthographic projection area of the fourth sub-stack structure 212 on the XY plane.
  • the fourth sub-stack structure 212 and at least a portion of the first sub-stack structure 209 in the stack structure 202 are etched simultaneously, and the size of the formed channel hole 215 along the X direction is greater than the size of the fourth sub-stack structure 212 along the X direction, and the orthographic projection area of the channel hole 215 on the XY plane is greater than the orthographic projection area of the fourth sub-stack structure 212 on the XY plane.
  • the fourth sub-stack structure 212 and at least a portion of the second sub-stack structure 210 and/or at least a portion of the third sub-stack structure 211 in the stack structure 202 are etched simultaneously, so that the size of the formed channel hole 215 along the Y direction is larger than the size of the fourth sub-stack structure 212 along the Y direction, and the orthographic projection area of the channel hole 215 on the XY plane is larger than the orthographic projection area of the fourth sub-stack structure 212 on the XY plane.
  • the space occupied by the second sub-stacked structure 210 can be used to form a bit line contact structure later.
  • the process of forming the channel hole 215 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • the orthographic projection of the channel hole 215 on the XY plane can be a quadrilateral, and the channel hole 215 includes four side walls, wherein two side walls are arranged oppositely along the X direction, and the other two side walls are arranged oppositely along the Y direction.
  • the orthographic projection of the channel hole 215 on the XY plane can also be a circle, an ellipse, etc., and the channel hole 215 at least includes two ends arranged oppositely along the Y direction.
  • the present disclosure has no special limitation on the shape of the orthographic projection of the channel hole 215 on the XY plane.
  • step S203 the semiconductor layer 203 exposed by the sidewalls of the channel hole 215 is oxidized to form a first gate dielectric layer 216 .
  • FIG3D cannot schematically illustrate the internal structure of the channel hole 215, and FIG4A is referred to here, which is a schematic diagram of the XZ cross-sectional structure along the A-A section in FIG3D.
  • the bottom of the channel hole 215 formed by etching exposes the substrate 201, and the sidewalls of the channel hole 215 expose the sidewalls of the semiconductor layer 203 and the interlayer insulating layer 204 that are alternately stacked and arranged, as well as the sidewalls of the capping layer 205.
  • the semiconductor layer 203 exposed by the sidewalls of the channel hole 215 is oxidized to form a first gate dielectric layer 216.
  • the material of the semiconductor layer 203 may include but is not limited to polysilicon material, which may be formed into silicon oxide material after oxidation treatment.
  • a channel layer 217, a second gate dielectric layer 218 and a gate electrode 219 covering the sidewalls of the channel hole 215 are sequentially formed; wherein the channel layer 217, the second gate dielectric layer 218 and the gate electrode 219 together form a transistor 220, and the back gate electrode 222 is used to adjust the threshold voltage of the transistor 220.
  • the semiconductor layer 203 may be a P-type heavily doped polysilicon material with a doping concentration of 1E21 to 1E23 cm -3 and a work function of 4 to 5.5 eV.
  • a channel layer 217 is formed to cover the sidewalls of the channel hole 215 .
  • the channel layer 217 and the first gate dielectric layers 216 and the interlayer insulating layer 204 exposed by the sidewalls of the channel hole 215 are in direct contact with each other.
  • the material of the channel layer 217 may include but is not limited to oxide semiconductor materials, such as IGZO, zinc tin oxide (Zinc Tin Oxide, ZTO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide, indium gallium silicon oxide (Indium Gallium Silicon Oxide, IGSO) and indium oxide.
  • oxide semiconductor materials such as IGZO, zinc tin oxide (Zinc Tin Oxide, ZTO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide, indium gallium silicon oxide (Indium Gallium Silicon Oxide, IGSO) and indium oxide.
  • a second gate dielectric layer 218 is formed to cover the sidewalls of the channel hole 215 .
  • the second gate dielectric layer 218 is in direct contact with the channel layer 217 in the channel hole 215 .
  • the material of the second gate dielectric layer 218 may include, but is not limited to, a high dielectric constant material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or a combination thereof.
  • the channel hole 215 is filled with a conductive material to form a gate electrode 219 .
  • the gate electrode 219 is in direct contact with the second gate dielectric layer 218 in the channel hole 215 .
  • a conductive material is filled in the channel hole 215, and the conductive material may also be located on the surface of the covering layer 205 while filling the channel hole 215; the conductive material is planarized so that the surface of the conductive material in the channel hole 215 and the surface of the covering layer 205 are basically flush to expose the surface of the covering layer 205; wherein the conductive material located in the channel hole 215 forms a gate electrode 219.
  • the material of the gate electrode 219 may include but is not limited to metal, metal compound or alloy.
  • the metal may be, for example, copper, aluminum, tungsten, gold or silver;
  • the metal compound may be, for example, tantalum nitride or titanium nitride;
  • the alloy may be an alloy formed by at least two metal elements of copper, aluminum, tungsten, gold or silver.
  • the process of forming the channel layer 217 , the second gate dielectric layer 218 , and the gate electrode 219 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.
  • FIG. 4B is a schematic diagram of the XZ cross-sectional structure along the B-B cross section in FIG. 3G .
  • the channel hole 215 includes a first gate dielectric layer 216, a channel layer 217, a second gate dielectric layer 218, and a gate electrode 219 in the radially inward direction.
  • the semiconductor layer 203 and the interlayer insulating layer 204 alternately stacked in the stacked structure surround the channel hole 215, and the semiconductor layer 203 is in direct contact with the first gate dielectric layer 216.
  • transistor 220 can be a transistor of a vertical annular channel structure (Channel All Around, CAA), wherein the second gate dielectric layer 218 surrounds the gate electrode 219, and the channel layer 217 surrounds the second gate dielectric layer 218.
  • CAA Vertical All Around
  • the substrate is not shown in FIGS. 4B to 4F .
  • the manufacturing method further includes:
  • the interlayer insulating layer 204 in the first sub-stacked structure 209 is removed to form a first gap 223; the first gap 223 exposes a portion of the channel layer 217 that is oppositely disposed along the first direction;
  • An isolation material is filled in the first gap 223 to form a first interlayer isolation layer 224 .
  • the interlayer insulating layer 204 in the first sub-stack structure 209 is removed to form a first interlayer insulating layer.
  • the gap 223 includes: etching the cover layer 205 and the first sub-stacked structure 209 in the stacked structure 202 in sequence along the Z direction to form a threshold voltage adjustment hole 221 that penetrates the first sub-stacked structure 209; the threshold voltage adjustment hole 221 is located between adjacent channel holes 215 along the X direction, and the remaining semiconductor layer 203 between adjacent channel holes 215 along the X direction is used as a back gate electrode 222; through the threshold voltage adjustment hole 221, the interlayer insulating layer 204 in the first sub-stacked structure 209 is etched and removed along the threshold voltage adjustment hole 221 in the transverse direction (i.e., X direction) to form a first gap 223; the threshold voltage adjustment hole 221 and the first gap 223 are connected.
  • the process of forming the threshold voltage adjustment hole 221 and the first gap 223 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • FIG4C is a schematic diagram of the XZ cross-sectional structure along the C-C cross section in FIG3H.
  • the first gap 223 exposes a portion of the channel layer 217 that is oppositely arranged along the X direction.
  • the first gap 223 exposes the channel layer 217 located on two side walls of the channel hole 215 that are oppositely arranged along the X direction.
  • the remaining semiconductor layer between adjacent channel holes 215 along the X direction serves as a back gate electrode 222
  • the first gate dielectric layer 216 is located between the channel layer 217 and the back gate electrode 222
  • the second gate dielectric layer 218 is located between the channel layer 217 and the gate electrode 219 .
  • a semiconductor layer and an interlayer insulating layer are formed which are alternately stacked, and then the remaining semiconductor layer between adjacent channel holes is used as a back gate electrode by etching, without the need to form an additional back gate electrode, thereby simplifying the manufacturing process of the semiconductor device.
  • the back gate electrode can be used to adjust the threshold voltage of the transistor, reduce the leakage current of the semiconductor device, and thus improve the electrical performance of the semiconductor device.
  • FIG4D is a schematic diagram of the XZ cross-sectional structure along the D-D cross section in FIG3I.
  • the channel layer 217 exposed by the first gap 223 is removed by lateral etching, and the first gap 223 exposes a portion of the second gate dielectric layer 218 that is oppositely disposed along the X direction.
  • the first gap 223 exposes the second gate dielectric layer 218 located on two sidewalls of the channel hole 215 that are oppositely disposed along the X direction.
  • the process of removing the channel layer 217 exposed by the first gap 223 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • FIG4E is a schematic diagram of the XZ cross-sectional structure along the E-E section in FIG3J.
  • filling the first gap 223 with an isolation material to form a first interlayer isolation layer 224 includes: filling the first gap 223 and the threshold voltage adjustment hole 221 with an isolation material through the threshold voltage adjustment hole 221, so that at least the first gap 223 is filled with the isolation material; wherein the isolation material in the first gap 223 forms the first interlayer isolation layer 224.
  • the first interlayer isolation layer 224 is in direct contact with the second gate dielectric layer 218 on two sidewalls of the channel hole 215 that are oppositely disposed along the X direction.
  • FIG4E schematically shows that the channel layer 217 on two sidewalls of the channel hole 215 that are oppositely disposed along the X direction is isolated by a plurality of first interlayer isolation layers 224, so that the channel layer 217 is isolated by the first interlayer isolation layers 224 in the XZ cross-sectional structural schematic diagram.
  • the material of the first interlayer isolation layer 224 may include, but is not limited to, a low dielectric constant material, for example, at least one of silicon oxide, silicon nitride, silicon carbide, silicon nitride carbon, or silicon oxynitride.
  • the isolation material in the threshold voltage adjustment hole 221 is removed; a conductive material is filled in the threshold voltage adjustment hole 221 to form a threshold voltage adjustment structure 225 electrically connected to the back gate electrode 222 ; wherein the threshold voltage adjustment structure 225 is used to adjust the threshold voltage of the transistor 220 .
  • two side walls of the threshold voltage adjustment structure 225 that are opposite to each other along the Z direction are in contact with the back gate electrode.
  • a threshold voltage adjustment structure can also be formed. While the back gate electrode is used to adjust the threshold voltage of the transistor, the threshold voltage adjustment structure can also be used to further adjust the threshold voltage of the transistor, thereby enhancing the adjustment effect on the threshold voltage of the transistor.
  • the material of the threshold voltage adjustment structure 225 may include but is not limited to metal, metal compound or alloy.
  • the metal may be, for example, copper, aluminum, tungsten, gold or silver;
  • the metal compound may be, for example, tantalum nitride or titanium nitride;
  • the alloy may be an alloy formed by at least two metal elements of copper, aluminum, tungsten, gold or silver.
  • the process of forming the first interlayer isolation layer 224 and the threshold voltage adjustment structure 225 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.
  • the manufacturing method further includes: etching and removing the interlayer insulating layer 204 in the second sub-stacked structure 210, the third sub-stacked structure 211, and the fifth sub-stacked structure 213 to form a second gap 226; at this time, the second gap 226 exposes a portion of the channel layer 217 that is oppositely disposed along the Y direction. In other words, at this time, the second gap 226 exposes the channel layer 217 located on two sidewalls of the channel hole 215 that are oppositely disposed along the Y direction.
  • the process of forming the second gap 226 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • the channel layer 217 exposed by the second gap 226 is removed.
  • the second gap 226 exposes the corresponding In other words, the second gap 226 exposes the second gate dielectric layer 218 located on two sidewalls of the channel hole 215 that are opposite to each other along the Y direction.
  • the process of removing the channel layer 217 exposed by the second gap 226 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • the channel layer 217 between the transistors 220 is self-alignedly disconnected along the Z direction to form a channel portion 228 , thereby avoiding mutual interference between adjacent transistors 220 , thereby reducing leakage of the transistor 220 .
  • the isolation material is filled in the second gap 226 to form a second interlayer isolation layer 227; the first interlayer isolation layer 224 and the second interlayer isolation layer 227 isolate the remaining channel layer 217 in each channel hole 215 into channel portions 228 of multiple transistors 220, so that the channel layer 217 in the XZ cross-sectional structural schematic diagram and the YZ cross-sectional structural schematic diagram are isolated by the first interlayer isolation layer 224 and the second interlayer isolation layer 227.
  • FIG. 4F is a schematic diagram of the YZ cross-sectional structure along the F-F cross section in FIG. 3L.
  • the second interlayer isolation layer 227 contacts the second gate dielectric layer 218 on the two side walls of the channel hole 215 that are oppositely arranged along the Y direction.
  • the channel layer 217 on the two side walls of the channel hole 215 that are oppositely arranged along the X direction is isolated by a plurality of first interlayer isolation layers 224, that is, the first interlayer isolation layer 224 and the second interlayer isolation layer 227 together isolate the channel layer 217 in each channel hole 215 into a channel portion 228 of a plurality of transistors 220, thereby forming a plurality of transistors 220 arranged along the Z direction.
  • the plurality of transistors 220 arranged along the Z direction are connected to the same gate electrode 219, and the plurality of transistors 220 arranged along the X direction are connected to different gate electrodes 219.
  • the material of the second interlayer isolation layer 227 may include, but is not limited to, a low dielectric constant material, for example, at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride.
  • the process of forming the second interlayer isolation layer 227 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.
  • the interlayer insulating layer 204 in the first sub-stack structure 209 is first etched away to form a first gap 223, and then the interlayer insulating layer 204 in the second sub-stack structure 210, the third sub-stack structure 211 and the fifth sub-stack structure 213 is etched away to form a second gap 226; that is, the first interlayer isolation layer 224 is formed first and then the second interlayer isolation layer 227 is formed.
  • the second gap may be formed first and then the first gap, that is, the second isolation layer may be formed first and then the first isolation layer.
  • the second gap and the first gap may be formed at the same time, and the exposed channel layer may be partially removed through the second gap and the first gap at the same time.
  • the present disclosure does not have any special restrictions on the process sequence of forming the first gap and the second gap, as long as the channel layer can be isolated into a plurality of channel portions arranged along the Z direction.
  • transistors are arranged in an array along the X direction and the Z direction.
  • the first interlayer isolation layer and the second interlayer isolation layer isolate the transistors arranged along the Z direction.
  • the occupied area of a single transistor is reduced, which is beneficial to improving the integration density of the semiconductor device.
  • two sidewalls of the channel portion 228 that are opposite to each other along the second direction form a first source-drain 229 and a second source-drain 230 , respectively.
  • the first source-drain 229 is used to connect the bit line
  • the second source-drain 230 is used to connect the storage capacitor.
  • the corresponding second source-drain is used as the drain of the transistor; when the first source-drain is used as the drain of the transistor, the corresponding second source-drain is used as the source of the transistor.
  • the manufacturing method further includes: etching and removing the semiconductor layer 203 in the fifth sub-stacked structure 213 to form a third gap 231 ; at this time, the third gap 231 exposes the first source and drain 229 .
  • the semiconductor layer 203 in the second sub-stacked structure 210 needs to be removed at this time, and a bit line contact structure is formed in the space occupied by the semiconductor layer 203 in the second sub-stacked structure 210. If the fourth sub-stacked structure 212 and the second sub-stacked structure 210 in the stacked structure 202 have been etched during the process of forming the channel hole 215, then only the semiconductor layer 203 in the fifth sub-stacked structure 213 needs to be removed at this time to form the third gap 231.
  • the process of forming the third gap 231 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • a conductive material is filled in the third gap 231 to form a plurality of bit lines 232 extending along the first direction (ie, the X direction) and electrically connected to the first source and drain 229 , and a plurality of first source and drain electrodes 229 arranged along the X direction are connected to the same bit line 232 .
  • the material of the bit line 232 may include but is not limited to metal, metal compound or alloy.
  • the metal may be, for example, copper, aluminum, tungsten, gold or silver;
  • the metal compound may be, for example, tantalum nitride or titanium nitride;
  • the alloy may be an alloy formed by at least two metal elements of copper, aluminum, tungsten, gold or silver.
  • the process of forming the bit line 232 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • bit line extension lines may be further formed, and bottoms of different bit line extension lines are connected to different bit lines.
  • the materials of the bit line and the bit line extension line may be the same or different.
  • the manufacturing method further includes: etching and removing the semiconductor layer 203 in the third sub-stack structure 211 to form a fourth gap 233 ; at this time, the fourth gap 233 exposes the second source and drain 230 .
  • the process of forming the fourth gap 233 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • a storage capacitor 234 electrically connected to the second source and drain 230 is formed in the fourth gap 233.
  • the storage capacitors 234 are arranged in an array along the X direction and the Z direction, and each storage capacitor 234 extends along the Y direction. This is conducive to increasing the aspect ratio of the storage capacitor, that is, the ratio of length to width or diameter, so that the distance between the storage capacitors of adjacent transistors is increased, and the generation of integrated capacitance between the storage capacitors is avoided.
  • the present disclosure has no special limitation on the specific structure of the storage capacitor, and the storage capacitor structure in any related technical solution can be used in this solution.
  • the semiconductor layer 203 in the fifth sub-stacked structure 213 is first etched away to form the third gap 231, and then the semiconductor layer 203 in the third sub-stacked structure 211 is etched away to form the fourth gap 233; that is, the bit line 232 is formed first and then the storage capacitor 234 is formed.
  • the fourth gap may be formed first and then the third gap, that is, the storage capacitor may be formed first and then the bit line may be formed.
  • the present disclosure has no special limitation on the process sequence of forming the third gap and the fourth gap.
  • a threshold voltage adjustment structure 225 is formed in the threshold voltage adjustment hole 221 after the first interlayer isolation layer 224 is formed in the first gap 223 .
  • a sacrificial structure can be formed in the threshold voltage adjustment hole, a bit line can be formed in the third gap, and a storage capacitor can be formed in the fourth gap, and then a threshold voltage adjustment hole can be formed by etching, and a threshold voltage adjustment structure can be formed in the threshold voltage adjustment hole.
  • a sacrificial structure may be formed in the threshold voltage adjustment hole after the first interlayer isolation layer is formed in the first gap, and a conductive material may be subsequently filled in the third gap and the threshold voltage adjustment hole at the same time to form a bit line in the third gap and a threshold voltage adjustment structure in the threshold voltage adjustment hole, respectively.
  • the manufacturing method further includes:
  • the semiconductor layer 203 in the fifth sub-stacked structure 213 is removed to form a third gap 231 ; the third gap 231 exposes the first source and drain 229 ;
  • a threshold voltage adjustment hole 221 penetrating the first sub-stacked structure 209 is formed by etching; the threshold voltage adjustment hole 221 is located between adjacent channel holes 215, and the remaining semiconductor layer 203 between the adjacent channel holes 215 serves as a back gate electrode 222;
  • Conductive material is simultaneously filled in the third gap 231 and the threshold voltage adjustment hole 221 to respectively form a plurality of bit lines 232 extending along the first direction (i.e., the X direction) and electrically connected to the first source and drain 229 and a threshold voltage adjustment structure 225 electrically connected to the back gate electrode 222; wherein the threshold voltage adjustment structure 225 is used to adjust the threshold voltage of the transistor 220.
  • the process of forming the third gap 231 and the threshold voltage adjustment hole 221 may include, but is not limited to, wet etching, dry etching, or a combination thereof.
  • the third gap 231 and the threshold voltage adjustment hole 221 are filled with conductive material at the same time, which can save manufacturing time and reduce manufacturing cost.
  • FIG. 5A is a schematic diagram of a three-dimensional structure of a semiconductor device provided in an example
  • FIG. 5B is a schematic diagram of an XY cross-sectional structure of a semiconductor device provided in an example.
  • an embodiment of the present disclosure provides a semiconductor device 200, which includes: a substrate (not shown in FIG. 5A and FIG.
  • the material of the channel portion 228 may include, but is not limited to, an oxide semiconductor material, for example, IGZO, ZTO, IZO, zinc oxide, IGSO, and indium oxide.
  • an oxide semiconductor material for example, IGZO, ZTO, IZO, zinc oxide, IGSO, and indium oxide.
  • the back gate electrode 222 may be a P-type heavily doped polysilicon material with a doping concentration of 1E21-1E23 cm -3 and a work function of 4-5.5 eV. Since the threshold voltage of a transistor formed of IGZO material is usually negative, the threshold voltage of the transistor 220 may be adjusted to a positive voltage by providing the back gate electrode 222, thereby reducing transistor leakage and prolonging the retention time of stored data.
  • the second gate dielectric layer 218 surrounds the gate electrode 219
  • the channel portion 228 surrounds the second gate dielectric layer 218 .
  • two side walls of the channel portion 228 that are arranged opposite to each other along the Y direction respectively constitute a first source and drain 229 (as indicated by the dotted box in FIG. 5B ) and a second source and drain 230 (as indicated by the dotted box in FIG. 5B );
  • the semiconductor device 200 also includes: a bit line 232 extending along the X direction, and a plurality of first source and drain electrodes 229 arranged along the X direction are connected to the same bit line 232; and a plurality of storage capacitors 234, and the storage capacitors 234 are connected to the second source and drain 230.
  • a plurality of first source and drain electrodes 229 arranged along the Z direction are connected to different bit lines 232 .
  • the first source and drain 229 and the second source and drain 230 are aligned with two sidewalls of the back gate electrode 222 that are oppositely disposed along the Y direction, that is, in the Y direction, the size of the back gate electrode 222 is equal to the spacing between the first source and drain 229 and the second source and drain 230.
  • the plurality of first source and drain electrodes 229 arranged along the Z direction are connected to different bit lines 232 through a bit line contact structure.
  • a plurality of first source drains 229 arranged along the Z direction are directly connected to different bit lines 232, the first source drains 229 protrude from the sidewalls of the back gate electrode 222 along the Y direction along the Y direction, and an isolation structure 214 is provided between the back gate electrode 222 and the bit line.
  • the material of the isolation structure 214 may include a low dielectric constant material, for example, silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride.
  • the isolation structure 214 may reduce the coupling between the bit line 232 and the back gate electrode 222, and reduce the parasitic capacitance between the two.
  • the first source drain 229 and the second source drain 230 are not aligned with the two side walls of the back gate electrode 222 that are relatively arranged along the Y direction.
  • the first source drain 229 protrudes from the side wall of the back gate electrode 222 along the Y direction and toward the bit line 232
  • the second source drain 230 protrudes from the side wall of the back gate electrode 222 along the Y direction and away from the bit line 232, thereby increasing the channel length of the channel portion 228 and reducing the short channel effect.
  • FIG. 6A is a schematic diagram of a three-dimensional structure of a semiconductor device provided by an example
  • FIG. 6B is a schematic diagram of an XY cross-sectional structure of a semiconductor device provided by an example.
  • the semiconductor device 200 further includes: a threshold voltage adjustment structure 225 located between adjacent back gate electrodes 222 of adjacent channel portions 228 arranged along the X direction, the threshold voltage adjustment structure 225 extending along the Z direction and electrically connecting a plurality of back gate electrodes 222 arranged along the Z direction.
  • the threshold voltage adjustment structure 225 can be used to apply a voltage to the back gate electrode 222 to further adjust the threshold voltage of the transistor 220.
  • the channel portion 228 is in a ring-shaped structure parallel to the substrate; the dimension of the channel portion 228 along the Y direction is greater than or equal to the dimension of the back gate electrode 222 along the Y direction.
  • each channel portion 228 is arranged in an array along the X direction and the Z direction, and each channel portion 228 is a ring structure parallel to the XY plane.
  • the present disclosure provides a semiconductor device and a method for manufacturing the same.
  • multiple channel holes are formed through the stacked structure, gate electrodes are formed in the channel holes, and the semiconductor layer in the stacked structure is used as a back gate electrode, so that the threshold voltage of the transistor can be adjusted by the back gate electrode.

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Abstract

本公开实施例提供一种半导体器件及其制造方法。所述制造方法包括：提供衬底和位于所述衬底上的叠层结构，所述叠层结构包括交替堆叠的半导体层和层间绝缘层；形成贯穿所述叠层结构的多个沟道孔；其中，位于相邻所述沟道孔之间的半导体层用于形成背栅电极；对所述沟道孔侧壁暴露出的半导体层进行氧化处理，以形成第一栅介质层；依次形成覆盖所述沟道孔侧壁的沟道层、第二栅介质层和栅电极；其中，所述沟道层、所述第二栅介质层和所述栅电极共同形成晶体管，所述背栅电极用于调节所述晶体管的阈值电压。

Description

一种半导体器件及其制造方法
相关申请的交叉引用
本公开基于申请号为202311686249.8、申请日为2023年12月04日、发明名称为“一种半导体器件及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
随着存储器朝向更高的集成密度方向发展，需要对存储器的尺寸进行微缩(Scaling)。然而，在当前存储器的尺寸极小的情况下，存储器的尺寸微缩可能导致存储器的电学性能劣化(Degradation)。
因此，目前存储器的结构和性能均有待于进一步的改进。
发明内容
有鉴于此，本公开实施例提供一种半导体器件及其制造方法。
为达到上述目的，本公开的技术方案是这样实现的：
第一方面，本公开实施例提供一种半导体器件的制造方法，所述制造方法包括：
提供衬底和位于所述衬底上的叠层结构，所述叠层结构包括交替堆叠的半导体层和层间绝缘层；
形成贯穿所述叠层结构的多个沟道孔；其中，位于相邻所述沟道孔之间的半导体层用于形成背栅电极；
对所述沟道孔侧壁暴露出的半导体层进行氧化处理，以形成第一栅介质层；
依次形成覆盖所述沟道孔侧壁的沟道层、第二栅介质层和栅电极；其中，所述沟道层、所述第二栅介质层和所述栅电极共同形成晶体管，所述背栅电极用于调节所述晶体管的阈值电压。
在一些实施例中，所述形成贯穿所述叠层结构的多个沟道孔之前，所述制造方法还包括：
形成贯穿所述叠层结构且沿第一方向排列的多个凹槽组，每个所述凹槽组包括沿第二方向并列设置的第一凹槽和第二凹槽；剩余的所述叠层结构包括位于所述第一凹槽和所述第二凹槽之间的第一子叠层结构、位于相邻所述第一凹槽之间的第二子叠层结构、位于相邻所述第二凹槽之间的第三子叠层结构、位于相邻所述第一子叠层结构之间的第四子叠层结构以及位于所述第一凹槽和所述第二子叠层结构一侧的第五子叠层结构；其中，所述第一方向和所述第二方向均平行于所述衬底且所述第一方向和所述第二方向相交；
在所述第一凹槽和所述第二凹槽内填充隔离材料，以形成隔离结构。
在一些实施例中，所述形成贯穿所述叠层结构的多个沟道孔，包括：
刻蚀剩余的所述叠层结构中的至少所述第四子叠层结构，以形成贯穿所述叠层结构且沿所述第一方向排列的多个沟道孔。
在一些实施例中，所述依次形成覆盖所述沟道孔侧壁的沟道层、第二栅介质层和栅电极之后，所述制造方法还包括：
去除所述第一子叠层结构内的层间绝缘层，以形成第一间隙；所述第一间隙暴露出沿所述第一方向上相对设置的部分所述沟道层；
去除所述第一间隙暴露出的所述沟道层；
在所述第一间隙内填充隔离材料，以形成第一层间隔离层。
在一些实施例中，所述去除所述第一子叠层结构内的层间绝缘层，以形成第一间隙，包括：
刻蚀形成贯穿所述第一子叠层结构的阈值电压调节孔；所述阈值电压调节孔位于相邻所述沟道 孔之间，且位于相邻所述沟道孔之间剩余的半导体层作为背栅电极；
沿所述阈值电压调节孔横向刻蚀去除所述层间绝缘层，以形成第一间隙；所述阈值电压调节孔和所述第一间隙相连通。
在一些实施例中，所述在所述第一间隙内填充隔离材料，以形成第一层间隔离层，包括：
在所述第一间隙和所述阈值电压调节孔内填充隔离材料；
去除所述阈值电压调节孔内的隔离材料；其中，位于所述第一间隙内的隔离材料形成第一层间隔离层；
在所述阈值电压调节孔内填充导电材料，以形成电连接所述背栅电极的阈值电压调节结构；其中，所述阈值电压调节结构用于调节所述晶体管的阈值电压。
在一些实施例中，所述依次形成覆盖所述沟道孔侧壁的沟道层、第二栅介质层和栅电极之后，所述制造方法还包括：
去除所述第二子叠层结构、所述第三子叠层结构和所述第五子叠层结构内的层间绝缘层，以形成第二间隙；所述第二间隙暴露出沿所述第二方向上相对设置的部分所述沟道层；
去除所述第二间隙暴露出的所述沟道层；
在所述第二间隙内填充隔离材料，以形成第二层间隔离层；其中，所述第一层间隔离层和所述第二层间隔离层将每一所述沟道孔内剩余的沟道层隔离为多个晶体管的沟道部；所述沟道部沿所述第二方向上相对设置的两个侧壁分别形成第一源漏极和第二源漏极；沿第三方向排列的多个晶体管连接至同一栅电极；所述第三方向垂直于所述衬底。
在一些实施例中，所述在所述第二间隙内填充隔离材料，以形成第二层间隔离层之后，所述制造方法还包括：
去除所述第五子叠层结构内的半导体层，以形成第三间隙；所述第三间隙暴露出所述第一源漏极；
在所述第三间隙内填充导电材料，以形成沿所述第一方向延伸且与所述第一源漏极电连接的多个位线。
在一些实施例中，所述在所述第二间隙内填充隔离材料，以形成第二层间隔离层之后，所述制造方法还包括：
去除所述第三子叠层结构内的半导体层，以形成第四间隙；所述第四间隙暴露出所述第二源漏极；
在所述第四间隙内形成与所述第二源漏极电连接的存储电容。
在一些实施例中，所述在所述第二间隙内填充隔离材料，以形成第二层间隔离层之后，所述制造方法还包括：
去除所述第五子叠层结构内的半导体层，以形成第三间隙；所述第三间隙暴露出所述第一源漏极；
刻蚀形成贯穿所述第一子叠层结构的阈值电压调节孔；所述阈值电压调节孔位于相邻所述沟道孔之间，且位于相邻所述沟道孔之间剩余的半导体层作为背栅电极；
在所述第三间隙和所述阈值电压调节孔内同时填充导电材料，以分别形成沿所述第一方向延伸且与所述第一源漏极电连接的多个位线和电连接所述背栅电极的阈值电压调节结构；其中，所述阈值电压调节结构用于调节所述晶体管的阈值电压。
第二方面，本公开实施例提供一种半导体器件，所述半导体器件包括：
衬底；
沿第一方向和第三方向呈阵列排布的多个沟道部，所述第一方向平行于所述衬底，所述第三方向垂直于所述衬底；
沿所述第三方向延伸且贯穿所述沟道部的栅电极；
位于所述沟道部和所述栅电极之间的第二栅介质层；所述沟道部、所述第二栅介质层和所述栅电极共同构成晶体管；
覆盖每个所述沟道部沿所述第一方向上相对设置的两个侧壁的第一栅介质层；
位于沿所述第一方向排列的相邻所述晶体管之间的背栅电极；其中，所述背栅电极和所述第一栅介质层接触；所述背栅电极用于调节所述晶体管的阈值电压。
在一些实施例中，所述沟道部沿第二方向上相对设置的两个侧壁分别构成第一源漏极和第二源漏极；所述第二方向平行于所述衬底且和所述第一方向相交；所述半导体器件还包括：
沿所述第一方向延伸的位线，且沿所述第一方向排列的多个所述第一源漏极连接至同一所述位 线；
多个存储电容，且所述存储电容和所述第二源漏极连接。
在一些实施例中，所述半导体器件还包括：
位于沿所述第一方向排列的相邻所述沟道部的相邻背栅电极之间的阈值电压调节结构，所述阈值电压调节结构沿所述第三方向延伸且电连接沿第三方向排列的多个背栅电极。
在一些实施例中，所述沟道部呈平行于所述衬底的环状结构；
所述沟道部沿第二方向的尺寸大于或等于所述背栅电极沿所述第二方向的尺寸。
本公开实施例提供一种半导体器件及其制造方法。本公开实施例中，形成贯穿叠层结构的多个沟道孔，在沟道孔内形成栅电极并且将叠层结构内的半导体层作为背栅电极，如此可以利用背栅电极调节晶体管的阈值电压。
附图说明
图1为一示例提供的半导体器件的三维结构示意图；
图2为本公开实施例提供的半导体器件的制造方法的流程示意图；
图3A至图3P为一示例提供的半导体器件在制造过程中的三维结构示意图；
图4A至图4F为一示例提供的半导体器件在制造过程中的剖面结构示意图；
图5A和图5B为一示例提供的半导体器件的结构示意图；
图6A和图6B为另一示例提供的半导体器件的结构示意图。
具体实施方式
下面将结合本公开实施方式及附图，对本公开实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本公开的一部分实施方式，而不是全部的实施方式。基于本公开中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本公开保护的范围。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件 和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
参考图1，图1为一示例提供的半导体器件的三维结构示意图。如图1所示，半导体器件100包括：衬底(图1中未示意出)以及位于衬底上的多个半导体柱101，半导体柱101沿Y方向延伸，且沿X方向和Z方向呈阵列排布；其中，半导体柱101沿延伸方向包括源极、漏极以及位于源极和漏极之间的沟道区；围绕半导体柱101的沟道区的字线102，字线102沿Z方向延伸且沿Z方向排列的多个半导体柱101连接至同一字线102；和半导体柱101的源极或者漏极连接的位线104，位线104沿X方向延伸且沿X方向排列的多个半导体柱101的源极或者漏极连接至同一位线104；和半导体柱101的漏极或者源极连接的存储电容106，存储电容106沿Y方向延伸。
上述示例中，X方向和Y方向之间的夹角为90度，且X方向、Y方向均垂直于Z方向。在其他示例中，X方向和Y方向之间的夹角也可以是其他角度，例如，30度、45度或者90度，本示例并不构成对X方向、Y方向和Z方向之间的夹角角度的限定。
如图1所示，半导体器件100还包括：多个字线延伸线103，字线延伸线103沿Z方向延伸且沿X方向排列，不同字线延伸线103底部连接至不同字线102；多个位线延伸线105，位线延伸线105沿Z方向延伸且沿X方向排列，不同位线延伸线105底部连接至不同的位线104。
上述半导体器件100还包括：隔离层107，隔离层107沿X方向延伸，字线102位于沿Y方向相邻隔离层107之间，半导体柱101沿Y方向穿过隔离层107，隔离层107可以将字线102和半导体柱101的源极、漏极分隔开，避免半导体柱形成的晶体管中源极或者漏极与沟道区发生漏电，从而避免半导体器件的性能受到影响。
上述示例中的半导体器件100为1个晶体管和1个存储电容(1T1C)结构的三维动态随机存取存储器(3D Dynamic Random Access Memory，3D DRAM)。使用铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)作为上述DRAM的沟道材料，可以进一步减小漏电以提高DRAM的电学性能，并且上述DRAM的制造工艺相对简单且成本较低，已经成为目前行业内的重点研究对象。
然而，IGZO作为N型半导体材料，其阈值电压更偏向于负电压，但对于DRAM而言，正电压的阈值电压更有利于减小漏电，从而可以延长存储数据的保持时间(Retention Time)。
有鉴于此，本公开实施例提供一种半导体器件及其制造方法。
参考图2，图2为本公开实施例提供的半导体器件的制造方法的流程示意图。如图2所示，本公开实施例提供一种半导体器件的制造方法，该制造方法包括：
步骤S201：提供衬底和位于衬底上的叠层结构，叠层结构包括交替堆叠的半导体层和层间绝缘层；
步骤S202：形成贯穿叠层结构的多个沟道孔；其中，位于相邻沟道孔之间的半导体层用于形成背栅电极；
步骤S203：对沟道孔侧壁暴露出的半导体层进行氧化处理，以形成第一栅介质层；
步骤S204：依次形成覆盖沟道孔侧壁的沟道层、第二栅介质层和栅电极；其中，沟道层、第二栅介质层和栅电极共同形成晶体管，背栅电极用于调节晶体管的阈值电压。
本公开实施例中，形成贯穿叠层结构的多个沟道孔，在沟道孔内依次形成第一栅介质层、沟道层、第二栅介质层和栅电极，其中，沟道层、第二栅介质层和栅电极共同形成晶体管；并且将叠层结构内原本的半导体层作为背栅电极，如此可以利用背栅电极调节晶体管的阈值电压。
参考图3A至图3P，图3A至图3P为一示例提供的半导体器件在制造过程中的三维结构示意图。参考图4A至图4F，图4A至图4F为一示例提供的半导体器件在制造过程中的剖面结构示意图。下面将结合图3A至图3P以及图4A至图4F，详细地说明半导体器件的制造过程。
本公开实施例中，在步骤S201中，提供衬底201和位于衬底201上的叠层结构202，叠层结构202包括交替堆叠的半导体层203和层间绝缘层204。
如图3A所示，在衬底201上形成依次交替堆叠的半导体层203和层间绝缘层204，其中，交替堆叠设置的半导体层203和层间绝缘层204共同形成叠层结构202；在叠层结构202上形成覆盖层205。
这里，衬底201可以是半导体衬底；具体包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底等)、至少一个III-V化合物半导体材料(例如为氮化镓(GaN)衬底、砷化镓(GaAs) 衬底、磷化铟(InP)衬底等)、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料，还可以包括其他含半导体材料的衬底，例如绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底、绝缘层上的多晶半导体层、硅锗衬底等。
这里，半导体层203的材料可以包括但不限于多晶硅材料；层间绝缘层204的材料可以包括但不限于氧化硅材料。本公开对半导体层和层间绝缘层的数量和厚度并无特殊的限定。
这里，覆盖层205的材料可以包括但不限于氮化硅材料。
这里，形成半导体层203、层间绝缘层204和覆盖层205的工艺可以包括但不限于化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)、原子层沉积(Atomic Layer Deposition，ALD)或其任意组合。
本公开实施例中，将衬底的厚度方向定义为第三方向，即Z方向。或者，将垂直于衬底表面的方向定义为第三方向，即Z方向。在垂直于第三方向的平面中定义出相交的第一方向和第二方向，其中，第一方向即为X方向，第二方向即为Y方向。在一示例中，X方向、Y方向和Z方向可以两两相互垂直。
如图3B所示，在一些实施例中，在步骤S202之前，该制造方法还包括：沿Z方向，依次刻蚀覆盖层205和叠层结构202，形成贯穿叠层结构且沿第一方向(即X方向)排列的多个凹槽组206，每个凹槽组206包括沿第二方向(即Y方向)并列设置的第一凹槽207和第二凹槽208。图3B示意出沿X方向依次排列的三个凹槽组206，每个凹槽组206包括沿Y方向并列设置的第一凹槽207和第二凹槽208。
这里，形成第一凹槽207和第二凹槽208的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
第一凹槽207和第二凹槽208将叠层结构202划分为多个组成部分，剩余的叠层结构202包括：位于第一凹槽207和第二凹槽208之间的第一子叠层结构209、位于沿X方向相邻的两个第一凹槽207之间的第二子叠层结构210(如图3B中虚线圆框所示)、位于沿X方向相邻的两个第二凹槽208之间的第三子叠层结构211、位于沿X方向相邻的两个第一子叠层结构209之间的第四子叠层结构212(如3B中虚线方框所示)以及位于第一凹槽207和第二子叠层结构210一侧的第五子叠层结构213。其中，第四子叠层结构212也位于沿Y方向排列的第二子叠层结构210和第三子叠层结构211之间，第四子叠层结构212所在的区域用于形成半导体器件的晶体管。
这里，对剩余的叠层结构进行划分以便于描述半导体器件的制造过程，不同子叠层结构之间的仅区别在于和第一凹槽、第二凹槽之间的相对位置关系不同。
此外，为了便于附图示意，图3B至图3P均未示意出衬底。
如图3B和图3C所示，在第一凹槽207和第二凹槽208内填充隔离材料，以形成隔离结构214。
这里，形成半导体层203和层间绝缘层204的工艺可以包括但不限于CVD、PVD、ALD或其任意组合。
这里，隔离结构214的材料可以包括低介电常数材料，例如，氧化硅、氮化硅、碳化硅、氮碳化硅或氮氧化硅。在一些实施例中，覆盖层205和隔离结构214的材料可以相同或者不同。图3C示意出覆盖层205和隔离结构214相同，即均为氮化硅材料。覆盖层205的顶面可以平齐于隔离结构214的顶面。
本公开实施例中，在步骤S202中，形成贯穿叠层结构202的多个沟道孔215；其中，位于相邻沟道孔215之间的半导体层203用于形成背栅电极222。
如图3D所示，在一些实施例中，步骤S202，包括：沿Z方向，依次刻蚀覆盖层205和叠层结构202中的至少第四子叠层结构212，以形成贯穿叠层结构202且沿第一方向(即X方向)排列的多个沟道孔215。这里，沟道孔215在衬底(即XY平面)上的正投影面积大于或者等于第四子叠层结构212在衬底(即XY平面)上的正投影面积。
在一些示例中，仅刻蚀叠层结构202中的第四子叠层结构212，那么形成的沟道孔215在XY平面上的正投影面积等于第四子叠层结构212在XY平面上的正投影面积。在一些示例中，同时刻蚀叠层结构202中的第四子叠层结构212和至少部分第一子叠层结构209，那么形成的沟道孔215沿X方向上的尺寸大于第四子叠层结构212沿X方向上的尺寸，并且沟道孔215在XY平面上的正投影面积大于第四子叠层结构212在XY平面上的正投影面积。在一些示例中，同时刻蚀叠层结构202中的第四子叠层结构212以及至少部分第二子叠层结构210和/或至少部分第三子叠层结构211，那么形成的沟道孔215沿Y方向上的尺寸大于第四子叠层结构212沿Y方向上的尺寸，并且沟道孔215在XY平面上的正投影面积大于第四子叠层结构212在XY平面上的正投影面积。
需要说明的是，当仅刻蚀叠层结构202中的第四子叠层结构212，后续可以利用第二子叠层结构210所占据的空间形成位线接触结构。
这里，形成沟道孔215的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
本公开实施例中，沟道孔215在XY平面上的正投影可以为四边形，沟道孔215包括四个侧壁，其中，两个侧壁沿X方向相对设置，另外两个侧壁沿Y方向相对设置。在其他实施例中，沟道孔215在XY平面上的正投影还可以是圆形、椭圆形等，则沟道孔215至少包括沿Y方向相对设置的两个端部。本公开对沟道孔215在XY平面上的正投影的形状并无特殊的限定。
本公开实施例中，在步骤S203中，对沟道孔215侧壁暴露出的半导体层203进行氧化处理，以形成第一栅介质层216。
图3D无法示意出沟道孔215的内部结构，这里结合参考图4A，图4A为沿图3D中A-A截面的XZ剖面结构示意图。如图4A所示，刻蚀形成的沟道孔215底部暴露出衬底201，沟道孔215侧壁暴露出交替堆叠设置的半导体层203和层间绝缘层204的侧壁以及覆盖层205的侧壁。对沟道孔215侧壁暴露出的半导体层203进行氧化处理，以形成第一栅介质层216。
这里，半导体层203的材料可以包括但不限于多晶硅材料，进行氧化处理后可以形成氧化硅材料。
本公开实施例中，在步骤S204中，依次形成覆盖沟道孔215侧壁的沟道层217、第二栅介质层218和栅电极219；其中，沟道层217、第二栅介质层218和栅电极219共同形成晶体管220，背栅电极222用于调节晶体管220的阈值电压。在一些示例中，半导体层203可以为P型重掺杂多晶硅材料，掺杂浓度为1E21～1E23cm-3，功函数为4～5.5eV。
如图3E所示，形成覆盖沟道孔215侧壁的沟道层217。沟道层217和沟道孔215侧壁暴露出的交替设置的第一栅介质层216和层间绝缘层204直接接触。
这里，沟道层217的材料可以包括但不限于氧化物半导体材料，例如，IGZO、氧化锌锡(Zinc Tin Oxide，ZTO)、氧化铟锌(Indium Zinc Oxide，IZO)、氧化锌、氧化铟镓硅(Indium Gallium Silicon Oxide，IGSO)和氧化铟。
如图3F所示，形成覆盖沟道孔215侧壁的第二栅介质层218。第二栅介质层218和沟道孔215内的沟道层217直接接触。
这里，第二栅介质层218的材料可以包括但不限于高介电常数材料、氧化硅材料、氮化硅材料、氮氧化硅材料等，或其组合。
如图3G所示，在沟道孔215内填充满导电材料，以形成栅电极219。栅电极219和沟道孔215内的第二栅介质层218直接接触。
示例性地，在沟道孔215内填充导电材料，导电材料填充满沟道孔215的同时也可能位于覆盖层205表面；对导电材料进行平坦化处理，使得沟道孔215内的导电材料表面和覆盖层205表面基本齐平，以暴露出覆盖层205表面；其中，位于沟道孔215内的导电材料形成栅电极219。
这里，栅电极219的材料可以包括但不限于金属、金属化合物或者合金。其中，金属可以例如为铜、铝、钨、金或者银等；金属化合物可以例如为氮化钽或者氮化钛；合金可以为铜、铝、钨、金或者银中至少两种金属元素形成的合金。
这里，形成沟道层217、第二栅介质层218和栅电极219的工艺可以包括但不限于CVD、PVD、ALD或其任意组合。
参考图4B，图4B为沿图3G中B-B截面的XZ剖面结构示意图。如图4B所示，沟道孔215沿径向向内的方向依次包括第一栅介质层216、沟道层217、第二栅介质层218和栅电极219。叠层结构中交替堆叠设置的半导体层203和层间绝缘层204围绕沟道孔215，且半导体层203和第一栅介质层216直接接触。图3G和图4B示意出的沟道层217、第二栅介质层218和栅电极219共同形成晶体管220，晶体管220可以是垂直环形沟道结构(Channel All Around，CAA)的晶体管，其中，第二栅介质层218围绕栅电极219，沟道层217围绕第二栅介质层218。
此外，为了便于附图示意，图4B至图4F均未示意出衬底。
在一些实施例中，在步骤S204之后，该制造方法还包括：
去除第一子叠层结构209内的层间绝缘层204，以形成第一间隙223；第一间隙223暴露出沿第一方向上相对设置的部分沟道层217；
去除第一间隙223暴露出的沟道层217；
在第一间隙223内填充隔离材料，以形成第一层间隔离层224。
如图3H所示，在一些实施例中，去除第一子叠层结构209内的层间绝缘层204，以形成第一间 隙223，包括：沿Z方向，依次刻蚀覆盖层205和叠层结构202中的第一子叠层结构209，形成贯穿第一子叠层结构209的阈值电压调节孔221；阈值电压调节孔221位于沿X方向相邻沟道孔215之间，且位于沿X方向相邻沟道孔215之间剩余的半导体层203作为背栅电极222；通过阈值电压调节孔221，沿阈值电压调节孔221横向(即X方向)刻蚀去除第一子叠层结构209内的层间绝缘层204，以形成第一间隙223；阈值电压调节孔221和第一间隙223相连通。
这里，形成阈值电压调节孔221和第一间隙223的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
参考图4C，图4C为沿图3H中C-C截面的XZ剖面结构示意图。结合图3H和图4C所示，形成阈值电压调节孔221和第一间隙223之后，此时第一间隙223暴露出沿X方向上相对设置的部分沟道层217。换言之，此时第一间隙223暴露位于沟道孔215沿X方向上相对设置的两个侧壁上的沟道层217。
这里，位于沿X方向相邻沟道孔215之间剩余的半导体层作为背栅电极222，第一栅介质层216位于沟道层217和背栅电极222之间，第二栅介质层218位于沟道层217和栅电极219之间。
本公开实施例中，形成包括交替堆叠设置的半导体层和层间绝缘层，后续通过刻蚀将位于相邻沟道孔之间剩余的半导体层作为背栅电极，无需额外形成背栅电极，如此可以简化半导体器件的制造工艺。并且，利用背栅电极可以调节晶体管的阈值电压，减小半导体器件的漏电流，从而提高半导体器件的电学性能。
参考图3I和图4D，图4D为沿图3I中D-D截面的XZ剖面结构示意图。如图3I和图4D所示，侧向刻蚀以去除第一间隙223暴露出的沟道层217，此时第一间隙223暴露出沿X方向上相对设置的部分第二栅介质层218。换言之，此时第一间隙223暴露出位于沟道孔215沿X方向上相对设置的两个侧壁上的第二栅介质层218。
这里，去除第一间隙223暴露出的沟道层217的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
参考图3J和图4E，图4E为沿图3J中E-E截面的XZ剖面结构示意图。如图3J和图4E所示，在一些实施例中，在第一间隙223内填充隔离材料，以形成第一层间隔离层224，包括：通过阈值电压调节孔221，在第一间隙223和阈值电压调节孔221内填充隔离材料，使得至少第一间隙223内填充满隔离材料；其中，位于第一间隙223内的隔离材料形成第一层间隔离层224。
这里，第一层间隔离层224和沟道孔215沿X方向上相对设置的两个侧壁上的第二栅介质层218直接接触。图4E示意出沟道孔215沿X方向上相对设置的两个侧壁上的沟道层217被多个第一层间隔离层224所隔离开，使得XZ剖面结构示意图中沟道层217被第一层间隔离层224所隔离开。
这里，第一层间隔离层224的材料可以包括但不限于低介电常数材料，例如，氧化硅、氮化硅、碳化硅、氮碳化硅或氮氧化硅中的至少一种。
如图3J和图4E所示，去除阈值电压调节孔221内的隔离材料；在阈值电压调节孔221内填充导电材料，以形成电连接背栅电极222的阈值电压调节结构225；其中，阈值电压调节结构225用于调节晶体管220的阈值电压。
这里，阈值电压调节结构225沿Z方向上相对设置的两个侧壁均和背栅电极接触。
本公开实施例中，还可以形成阈值电压调节结构，利用背栅电极调节晶体管的阈值电压的同时，还可以利用阈值电压调节结构进一步对晶体管的阈值电压进行调节，增强对晶体管的阈值电压的调节效果。
这里，阈值电压调节结构225的材料可以包括但不限于金属、金属化合物或者合金。其中，金属可以例如为铜、铝、钨、金或者银等；金属化合物可以例如为氮化钽或者氮化钛；合金可以为铜、铝、钨、金或者银中至少两种金属元素形成的合金。
这里，形成第一层间隔离层224和阈值电压调节结构225的工艺可以包括但不限于CVD、PVD、ALD或其任意组合。
如图3K所示，在一些实施例中，依次形成覆盖沟道孔215侧壁的沟道层217、第二栅介质层218和栅电极219之后，该制造方法还包括：刻蚀去除第二子叠层结构210和第三子叠层结构211和第五子叠层结构213内的层间绝缘层204，以形成第二间隙226；此时第二间隙226暴露出沿Y方向上相对设置的部分沟道层217。换言之，此时第二间隙226暴露出位于沟道孔215沿Y方向上相对设置的两个侧壁上的沟道层217。
这里，形成第二间隙226的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
如图3K所示，去除第二间隙226暴露出的沟道层217，此时第二间隙226暴露出沿Y方向上相 对设置的部分第二栅介质层218。换言之，此时第二间隙226暴露出位于沟道孔215沿Y方向上相对设置的两个侧壁上的第二栅介质层218。
这里，去除第二间隙226暴露出的沟道层217的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
通过去除与层间绝缘层204对应的部分沟道层217，自对准地将各晶体管220之间的沟道层217沿Z方向上断开形成沟道部228，能够避免相邻晶体管220之间的相互干扰，从而降低晶体管220的漏电。
仍如图3L所示，在第二间隙226内填充隔离材料，以形成第二层间隔离层227；第一层间隔离层224和第二层间隔离层227将每一沟道孔215内剩余的沟道层217隔离为多个晶体管220的沟道部228，使得XZ剖面结构示意图和YZ剖面结构示意图中沟道层217均被第一层间隔离层224和第二层间隔离层227所隔离开。
参考图4F，图4F为沿图3L中F-F截面的YZ剖面结构示意图。结合图3L和图4F所示，第二层间隔离层227和沟道孔215沿Y方向上相对设置的两个侧壁上的第二栅介质层218接触。沟道孔215沿X方向上相对设置的两个侧壁上的沟道层217被多个第一层间隔离层224所隔离开，即第一层间隔离层224和第二层间隔离层227共同将每一沟道孔215内的沟道层217隔离为多个晶体管220的沟道部228，进而形成沿Z方向排列的多个晶体管220。沿Z方向排列的多个晶体管220连接至同一栅电极219，沿X方向排列的多个晶体管220连接至不同栅电极219。
这里，第二层间隔离层227的材料可以包括但不限于低介电常数材料，例如，氧化硅、氮化硅、碳化硅、氮碳化硅或氮氧化硅中的至少一种。
这里，形成第二层间隔离层227的工艺可以包括但不限于CVD、PVD、ALD或其任意组合。
本公开实施例中，先刻蚀去除第一子叠层结构209内的层间绝缘层204，以形成第一间隙223，后刻蚀去除第二子叠层结构210和第三子叠层结构211和第五子叠层结构213内的层间绝缘层204，以形成第二间隙226；即先形成第一层间隔离层224后形成第二层间隔离层227。
在其他实施例中，也可以先形成第二间隙后形成第一间隙，即也可以先形成第二隔离层后形成第一隔离层。在另一些实施例中，可以同时形成第二间隙和第一间隙，并同时通过第二间隙和第一间隙将暴露的沟道层进行部分去除。本公开对形成第一间隙和第二间隙的工艺顺序并无特殊的限定，只要能够将沟道层隔离为沿Z方向排列的多个沟道部即可。
本公开实施例中，晶体管沿X方向和Z方向呈阵列排布，第一层间隔离层和第二层间隔离层将沿Z方向排列的晶体管隔离开，沿X方向排列的多个晶体管之间没有额外的隔离结构，单个晶体管的占用面积减小，有利于提高半导体器件的集成密度。
仍如图4F所示，在一些实施例中，沟道部228沿第二方向(即Y方向)上相对设置的两个侧壁分别形成第一源漏极229和第二源漏极230。
需要说明的是，本公开实施例中，第一源漏极229用于连接位线，第二源漏极230用于连接存储电容。当第一源漏极作为晶体管的源极时，对应的第二源漏极作为晶体管的漏极；当第一源漏极作为晶体管的漏极时，对应的第二源漏极作为晶体管的源极。
如图3M所示，在一些实施例中，在第二间隙226内填充隔离材料，以形成第二层间隔离层227之后，该制造方法还包括：刻蚀去除第五子叠层结构213内的半导体层203，以形成第三间隙231；此时第三间隙231暴露出第一源漏极229。
需要说明的是，如前所述，如果形成沟道孔215的过程中仅刻蚀叠层结构202中的第四子叠层结构212，那么此时还需要去除第二子叠层结构210内的半导体层203，在第二子叠层结构210内的半导体层203所占据的空间形成位线接触结构。如果形成沟道孔215的过程中已经刻蚀叠层结构202中的第四子叠层结构212和第二子叠层结构210，那么此时仅需要去除第五子叠层结构213内的半导体层203，以形成第三间隙231。
这里，形成第三间隙231的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
如图3N所示，在一些实施例中，在第三间隙231内填充导电材料，以形成沿第一方向(即X方向)延伸且与第一源漏极229电连接的多个位线232，沿X方向排列的多个第一源漏极229连接至同一位线232。
这里，位线232的材料可以包括但不限于金属、金属化合物或者合金。其中，金属可以例如为铜、铝、钨、金或者银等；金属化合物可以例如为氮化钽或者氮化钛；合金可以为铜、铝、钨、金或者银中至少两种金属元素形成的合金。
这里，形成位线232的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
在一些实施例中，还可以形成位线延伸线，不同位线延伸线底部连接至不同位线。
这里，位线和位线延伸线的材料可以相同或者不同。
如图3O所示，在一些实施例中，在第二间隙226内填充隔离材料，以形成第二层间隔离层227之后，该制造方法还包括：刻蚀去除第三子叠层结构211内的半导体层203，以形成第四间隙233；此时第四间隙233暴露出第二源漏极230。
这里，形成第四间隙233的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
如图3P所示，在一些实施例中，在第四间隙233内形成与第二源漏极230电连接的存储电容234。存储电容234沿X方向和Z方向呈阵列排布，每一存储电容234沿Y方向延伸。这有利于增大存储电容的纵横比，即长度与宽度或者直径之比，从而使得相邻晶体管之间的存储电容的距离增加，避免存储电容之间产生集成电容。本公开对存储电容的具体结构并无特殊的限定，任何相关技术方案中的存储电容结构均可以用于本方案中。
本公开实施例中，先刻蚀去除第五子叠层结构213内的半导体层203，以形成第三间隙231，后刻蚀去除第三子叠层结构211内的半导体层203，以形成第四间隙233；即先形成位线232后形成存储电容234。
在其他实施例中，也可以先形成第四间隙后形成第三间隙，即也可以先形成存储电容后形成位线。本公开对形成第三间隙和第四间隙的工艺顺序并无特殊的限定。
图3A至图3P示意出的实施例中在第一间隙223内形成第一层间隔离层224之后即在阈值电压调节孔221内形成阈值电压调节结构225。
在一些实施例中，还可以在第一间隙内形成第一层间隔离层之后即在阈值电压调节孔内形成牺牲结构，在第三间隙内形成位线以及在第四间隙内形成存储电容之后，再刻蚀形成阈值电压调节孔，并且在阈值电压调节孔内形成阈值电压调节结构。
在另一些实施例中，还可以在第一间隙内形成第一层间隔离层之后即在阈值电压调节孔内形成牺牲结构，后续可以在第三间隙和阈值电压调节孔内同时填充导电材料，以分别在第三间隙内形成位线且在阈值电压调节孔内形成阈值电压调节结构。
在上述实施例中，在第二间隙226内填充隔离材料，以形成第二层间隔离层227之后，该制造方法还包括：
去除第五子叠层结构213内的半导体层203，以形成第三间隙231；第三间隙231暴露出第一源漏极229；
刻蚀形成贯穿第一子叠层结构209的阈值电压调节孔221；阈值电压调节孔221位于相邻沟道孔215之间，且位于相邻沟道孔215之间剩余的半导体层203作为背栅电极222；
在第三间隙231和阈值电压调节孔221内同时填充导电材料，以分别形成沿第一方向(即X方向)延伸且与第一源漏极229电连接的多个位线232和电连接背栅电极222的阈值电压调节结构225；其中，阈值电压调节结构225用于调节晶体管220的阈值电压。
这里，形成第三间隙231和阈值电压调节孔221的工艺可以包括但不限于湿法刻蚀、干法刻蚀或其组合。
本公开实施例中，在第三间隙231和阈值电压调节孔221内同时填充导电材料，可以节省制造时间且降低制造成本。
参考图5A和图5B，图5A为一示例提供的半导体器件的三维结构示意图，图5B为一示例提供的半导体器件的XY剖面结构示意图。如图5A和图5B所示，本公开实施例提供一种半导体器件200，该半导体器件200包括：衬底(图5A和图5B未示意出)；沿第一方向(即X方向)和第三方向(即Z方向)呈阵列排布的多个沟道部228，沿Z方向延伸且贯穿沟道部228的栅电极219；位于沟道部228和栅电极219之间的第二栅介质层218；沟道部228、第二栅介质层218和栅电极219共同构成晶体管220；覆盖每个沟道部228沿X方向上相对设置的两个侧壁的第一栅介质层216；位于沿即X方向排列的相邻晶体管220之间的背栅电极222；其中，背栅电极222和第一栅介质层216直接接触；背栅电极222用于调节晶体管220的阈值电压。
在一些实施例中，沟道部228的材料可以包括但不限于氧化物半导体材料，例如，IGZO、ZTO、IZO、氧化锌、IGSO和氧化铟。
在一些实施例中，背栅电极222可以为P型重掺杂多晶硅材料，掺杂浓度为1E21～1E23cm-3，功函数为4～5.5eV。由于IGZO材料形成的晶体管的阈值电压通常偏负电压，通过设置背栅电极222可以调节晶体管220的阈值电压为正电压，从而能够有利于减小晶体管漏电，从而可以延长存储数据的保持时间(Retention Time)。
通过在沿X方向排列的相邻晶体管220之间设置的背栅电极222以将晶体管220间隔开，无需设置额外的隔离结构，从而能够提升晶体管220的集成度。
这里，第二栅介质层218围绕栅电极219，沟道部228围绕第二栅介质层218。
在一些实施例中，沟道部228沿Y方向上相对设置的两个侧壁分别构成第一源漏极229(如图5B中虚线方框示意出)和第二源漏极230(如图5B中虚线方框示意出)；该半导体器件200还包括：沿X方向延伸的位线232，且沿X方向排列的多个第一源漏极229连接至同一位线232；多个存储电容234，且存储电容234和第二源漏极230连接。
这里，沿Z方向排列的多个第一源漏极229连接至不同位线232。
在一些实施例中，第一源漏极229和第二源漏极230与背栅电极222沿Y方向上相对设置的两个侧壁分别对齐，即，在Y方向上，背栅电极222的尺寸等于第一源漏极229和第二源漏极230之间的间距。沿Z方向排列的多个第一源漏极229通过位线接触结构连接至不同位线232。
在一些实施例中，沿Z方向排列的多个第一源漏极229直接连接至不同位线232，第一源漏极229沿Y方向凸出于背栅电极222沿Y方向上的侧壁，背栅电极222和位线之间设置有隔离结构214。隔离结构214的材料可以包括低介电常数材料，例如，氧化硅、氮化硅、碳化硅、氮碳化硅或氮氧化硅。隔离结构214可降低位线232和背栅电极222之间的耦合，减小两者之间的寄生电容。
在一些实施例中，第一源漏极229和第二源漏极230与背栅电极222沿Y方向上相对设置的两个侧壁均不对齐，第一源漏极229沿Y方向且朝向位线232的方向凸出于背栅电极222沿Y方向上的靠近位线232的侧壁，第二源漏极230沿Y方向且背离位线232的方向凸出于背栅电极222沿Y方向上的远离位线232的侧壁，从而能够增大沟道部228的沟道长度，降低短沟道效应。
参考图6A和图6B，图6A为一示例提供的半导体器件的三维结构示意图，图6B为一示例提供的半导体器件的XY剖面结构示意图。在一些实施例中，该半导体器件200还包括：位于沿X方向排列的相邻沟道部228的相邻背栅电极222之间的阈值电压调节结构225，阈值电压调节结构225沿Z方向延伸且电连接沿Z方向排列的多个背栅电极222。阈值电压调节结构225可用于对背栅电极222施加电压以进一步调节晶体管220的阈值电压。
在一些实施例中，沟道部228呈平行于衬底的环状结构；沟道部228沿Y方向的尺寸大于或等于背栅电极222沿Y方向的尺寸。
这里，沟道部228沿X方向和Z方向呈阵列排布，每一沟道部228均为平行于XY平面的环状结构。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
以上所述仅为本公开的优选实施方式，并非因此限制本公开的专利范围，凡是在本公开的发明构思下，利用本公开说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本公开的专利保护范围内。
工业实用性
本公开实施例提供一种半导体器件及其制造方法。本公开实施例中，形成贯穿叠层结构的多个沟道孔，在沟道孔内形成栅电极并且将叠层结构内的半导体层作为背栅电极，如此可以利用背栅电极调节晶体管的阈值电压。

Claims (18)

  1. 一种半导体器件(200)的制造方法，所述制造方法包括：
    提供衬底(201)和位于所述衬底(201)上的叠层结构(202)，所述叠层结构(202)包括交替堆叠的半导体层(203)和层间绝缘层(204)；
    形成贯穿所述叠层结构(202)的多个沟道孔(215)；其中，位于相邻所述沟道孔(215)之间的半导体层(203)用于形成背栅电极(222)；
    对所述沟道孔(215)侧壁暴露出的半导体层(203)进行氧化处理，以形成第一栅介质层(216)；
    依次形成覆盖所述沟道孔(215)侧壁的沟道层(217)、第二栅介质层(218)和栅电极(219)；其中，所述沟道层(217)、所述第二栅介质层(218)和所述栅电极(219)共同形成晶体管(220)，所述背栅电极(222)用于调节所述晶体管(220)的阈值电压。
  2. 根据权利要求1所述的半导体器件(200)的制造方法，其中，所述形成贯穿所述叠层结构(202)的多个沟道孔(215)之前，所述制造方法还包括：
    形成贯穿所述叠层结构(202)且沿第一方向排列的多个凹槽组(206)，每个所述凹槽组(206)包括沿第二方向并列设置的第一凹槽(207)和第二凹槽(208)；剩余的所述叠层结构(202)包括位于所述第一凹槽(207)和所述第二凹槽(208)之间的第一子叠层结构(209)、位于相邻所述第一凹槽(207)之间的第二子叠层结构(210)、位于相邻所述第二凹槽(208)之间的第三子叠层结构(211)、位于相邻所述第一子叠层结构(209)之间的第四子叠层结构(212)以及位于所述第一凹槽(207)和所述第二子叠层结构(210)一侧的第五子叠层结构(213)；其中，所述第一方向和所述第二方向均平行于所述衬底(201)且所述第一方向和所述第二方向相交；
    在所述第一凹槽(207)和所述第二凹槽(208)内填充隔离材料，以形成隔离结构(214)。
  3. 根据权利要求2所述的半导体器件(200)的制造方法，其中，所述形成贯穿所述叠层结构(202)的多个沟道孔(215)，包括：
    刻蚀剩余的所述叠层结构(202)中的至少所述第四子叠层结构(212)，以形成贯穿所述叠层结构(214)且沿所述第一方向排列的多个沟道孔(215)。
  4. 根据权利要求3所述的半导体器件(200)的制造方法，其中，所述依次形成覆盖所述沟道孔(215)侧壁的沟道层(217)、第二栅介质层(218)和栅电极(219)之后，所述制造方法还包括：
    去除所述第一子叠层结构(209)内的层间绝缘层(204)，以形成第一间隙(223)；所述第一间隙(223)暴露出沿所述第一方向上相对设置的部分所述沟道层(217)；
    去除所述第一间隙(223)暴露出的所述沟道层(217)；
    在所述第一间隙(223)内填充隔离材料，以形成第一层间隔离层(224)。
  5. 根据权利要求4所述的半导体器件(200)的制造方法，其中，所述去除所述第一子叠层结构(209)内的层间绝缘层(204)，以形成第一间隙(223)，包括：
    刻蚀形成贯穿所述第一子叠层结构(209)的阈值电压调节孔(221)；所述阈值电压调节孔(221)位于相邻所述沟道孔(215)之间，且位于相邻所述沟道孔(215)之间剩余的半导体层(203)作为背栅电极(222)；
    沿所述阈值电压调节孔(221)横向刻蚀去除所述层间绝缘层(204)，以形成第一间隙(223)；所述阈值电压调节孔(221)和所述第一间隙(223)相连通。
  6. 根据权利要求5所述的半导体器件(200)的制造方法，其中，所述在所述第一间隙(223)内填充隔离材料，以形成第一层间隔离层(224)，包括：
    在所述第一间隙(223)和所述阈值电压调节孔(221)内填充隔离材料；
    去除所述阈值电压调节孔(221)内的隔离材料；其中，位于所述第一间隙(223)内的隔离材料形成第一层间隔离层(224)；
    在所述阈值电压调节孔(221)内填充导电材料，以形成电连接所述背栅电极(222)的阈值电压调节结构(225)；其中，所述阈值电压调节结构(225)用于调节所述晶体管(220)的阈值电压。
  7. 根据权利要求4至6中任一项所述的半导体器件(200)的制造方法，其中，所述依次形成覆盖所述沟道孔(215)侧壁的沟道层(217)、第二栅介质层(218)和栅电极(219)之后，所述制造方法还包括：
    去除所述第二子叠层结构(210)、所述第三子叠层结构(211)和所述第五子叠层结构(213)内的层间绝缘层(204)，以形成第二间隙(226)；所述第二间隙(226)暴露出沿所述第二方向上相对设置的部分所述沟道层(217)；
    去除所述第二间隙(226)暴露出的所述沟道层(217)；
    在所述第二间隙(226)内填充隔离材料，以形成第二层间隔离层(227)；其中，所述第一层间隔离层(224)和所述第二层间隔离层(227)将每一所述沟道孔(215)内剩余的沟道层(217)隔离为多个晶体管(220)的沟道部(228)；所述沟道部(228)沿所述第二方向上相对设置的两个侧壁分别形成第一源漏极(229)和第二源漏极(230)；沿第三方向排列的多个晶体管(220)连接至同一栅电极(219)；所述第三方向垂直于所述衬底(201)。
  8. 根据权利要求7所述的半导体器件(200)的制造方法，其中，所述在所述第二间隙(226)内填充隔离材料，以形成第二层间隔离层(227)之后，所述制造方法还包括：
    去除所述第五子叠层结构(213)内的半导体层(203)，以形成第三间隙(231)；所述第三间隙(231)暴露出所述第一源漏极(229)；
    在所述第三间隙(231)内填充导电材料，以形成沿所述第一方向延伸且与所述第一源漏极(229)电连接的多个位线(232)。
  9. 根据权利要求7或8所述的半导体器件(200)的制造方法，其中，所述在所述第二间隙(226)内填充隔离材料，以形成第二层间隔离层(227)之后，所述制造方法还包括：
    去除所述第三子叠层结构(211)内的半导体层(203)，以形成第四间隙(233)；所述第四间隙(233)暴露出所述第二源漏极(230)；
    在所述第四间隙(223)内形成与所述第二源漏极(230)电连接的存储电容(234)。
  10. 根据权利要求7至9中任一项所述的半导体器件(200)的制造方法，其中，所述在所述第二间隙(226)内填充隔离材料，以形成第二层间隔离层(227)之后，所述制造方法还包括：
    去除所述第五子叠层结构内(213)的半导体层(203)，以形成第三间隙(231)；所述第三间隙(231)暴露出所述第一源漏极(229)；
    刻蚀形成贯穿所述第一子叠层结构(209)的阈值电压调节孔(221)；所述阈值电压调节孔(221)位于相邻所述沟道孔(215)之间，且位于相邻所述沟道孔(215)之间剩余的半导体层(203)作为背栅电极(222)；
    在所述第三间隙(231)和所述阈值电压调节孔(221)内同时填充导电材料，以分别形成沿所述第一方向延伸且与所述第一源漏极(229)电连接的多个位线(232)和电连接所述背栅电极(222)的阈值电压调节结构(225)；其中，所述阈值电压调节结构(225)用于调节所述晶体管(220)的阈值电压。
  11. 一种半导体器件(200)，所述半导体器件(200)包括：
    衬底(201)；
    沿第一方向和第三方向呈阵列排布的多个沟道部(228)，所述第一方向平行于所述衬底(201)，所述第三方向垂直于所述衬底(201)；
    沿所述第三方向延伸且贯穿所述沟道部(228)的栅电极(219)；
    位于所述沟道部(228)和所述栅电极(219)之间的第二栅介质层(218)；所述沟道部(228)、所述第二栅介质层(218)和所述栅电极(219)共同构成晶体管(220)；
    覆盖每个所述沟道部(228)沿所述第一方向上相对设置的两个侧壁的第一栅介质层(216)；
    位于沿所述第一方向排列的相邻所述晶体管(220)之间的背栅电极(222)；其中，所述背栅电极(222)和所述第一栅介质层(216)接触；所述背栅电极(222)用于调节所述晶体管(220)的阈值电压。
  12. 根据权利要求11所述的半导体器件(200)，其中，所述沟道部(228)沿第二方向上相对设置的两个侧壁分别构成第一源漏极(229)和第二源漏极(230)；所述第二方向平行于所述衬底(201)且和所述第一方向相交；所述半导体器件(200)还包括：
    沿所述第一方向延伸的位线(232)，且沿所述第一方向排列的多个所述第一源漏极(229)连接至同一所述位线(232)；
    多个存储电容(234)，且所述存储电容(234)和所述第二源漏极(230)连接。
  13. 根据权利要求11或12所述的半导体器件(200)，其中，所述半导体器件(200)还包括：
    位于沿所述第一方向排列的相邻所述沟道部(228)的相邻背栅电极(222)之间的阈值电压调节结构(225)，所述阈值电压调节结构(225)沿所述第三方向延伸且电连接沿第三方向排列的多个背栅电极(222)。
  14. 根据权利要求11至13中任一项所述的半导体器件(200)，其中，所述沟道部(228)呈平行于所述衬底(201)的环状结构；
    所述沟道部(228)沿第二方向的尺寸大于或等于所述背栅电极(222)沿所述第二方向的尺寸。
  15. 根据权利要求11至13中任一项所述的半导体器件(200)，其中，所述背栅电极(222)的材料包括多晶硅。
  16. 根据权利要求16所述的半导体器件(200)，其中，所述背栅电极(222)的掺杂浓度为1E21～1E23cm-3。
  17. 根据权利要求12所述的半导体器件(200)，其中，所述背栅电极(222)和所述位线(232)之间设置有隔离结构(214)。
  18. 根据权利要求17所述的半导体器件(200)，其中，所述隔离结构(214)的材料可以包括低介电常数材料。
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