WO2025102728A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2025102728A1
WO2025102728A1 PCT/CN2024/099668 CN2024099668W WO2025102728A1 WO 2025102728 A1 WO2025102728 A1 WO 2025102728A1 CN 2024099668 W CN2024099668 W CN 2024099668W WO 2025102728 A1 WO2025102728 A1 WO 2025102728A1
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Prior art keywords
signal
gate driving
driving unit
output
control signal
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Pending
Application number
PCT/CN2024/099668
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English (en)
French (fr)
Inventor
李明月
田超
王超
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Publication of WO2025102728A1 publication Critical patent/WO2025102728A1/zh
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Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • the present application relates to the field of display technology.
  • Increasing the display refresh frequency will directly lead to problems such as doubling the amount of display transmission data and insufficient pixel charging, which will in turn increase the number of data transmission interfaces, data transmission bandwidth, and display device power consumption, seriously affecting the user's immersive experience in the display device.
  • an embodiment of the present application provides a display panel, including:
  • a gate driving module comprising a first gate driving unit and a second gate driving unit, wherein the first gate driving unit is configured to receive an initial trigger signal and output a scanning signal according to the initial trigger signal;
  • a signal selection circuit electrically connected to the first gate driving unit and the second gate driving unit, respectively, the signal selection circuit being configured to receive an inversion signal, a scanning signal output by the first gate driving unit, and a low-level signal, and output a control signal to the second gate driving unit, the control signal being the scanning signal output by the first gate driving unit or the low-level signal;
  • the control signal is a scanning signal output by the first gate driving unit; when the initial trigger signal is a trigger signal of the next frame of the first frame, based on the inversion signal, the control signal is the low level signal;
  • the display panel further includes a first selection circuit electrically connected to the first gate driving unit, the first selection circuit is configured to receive the inversion signal, the initial trigger signal and the low-level signal, and output a first control signal to the first gate driving unit, the first gate driving unit is configured to output a first scanning signal according to the first control signal, and the first control signal is the initial trigger signal or the low-level signal;
  • the signal selection circuit is configured to receive the inversion signal, the first scanning signal output by the first gate driving unit, and the initial trigger signal, and output a second control signal to the second gate driving unit, the second gate driving unit is configured to output a second scanning signal according to the second control signal, and the second control signal is the scanning signal output by the first gate driving unit or the initial trigger signal;
  • the second control signal is the first scanning signal output by the first gate driving unit; when the first control signal is the low level signal, the second control signal is the initial trigger signal;
  • the display panel further includes a third selection circuit
  • the gate driving module further includes a fourth gate driving unit
  • the third selection circuit is electrically connected to the first gate driving unit, the second gate driving unit, and the fourth gate driving unit respectively;
  • the third selection circuit is configured to receive the inversion signal, the scanning signal output by the second gate driving unit, and the scanning signal output by the first gate driving unit, and output a fourth control signal to the fourth gate driving unit, wherein the fourth control signal is the scanning signal output by the second gate driving unit or the scanning signal output by the first gate driving unit;
  • the control signal is a scanning signal output by the first gate drive unit
  • the fourth control signal is a scanning signal output by the second gate drive unit
  • the control signal is the low-level signal
  • the fourth control signal is a scanning signal output by the first gate drive unit
  • an embodiment of the present application provides a display panel, including:
  • a gate driving module comprising a first gate driving unit and a second gate driving unit, wherein the first gate driving unit is configured to receive an initial trigger signal and output a scanning signal according to the initial trigger signal;
  • a signal selection circuit electrically connected to the first gate driving unit and the second gate driving unit, respectively, the signal selection circuit being configured to receive an inversion signal, a scanning signal output by the first gate driving unit, and a low-level signal, and output a control signal to the second gate driving unit, the control signal being the scanning signal output by the first gate driving unit or the low-level signal;
  • the display panel and the display device provided in the embodiments of the present application divide the display panel into areas where the first gate driving unit and the second gate driving unit respectively control refresh by setting a signal selection circuit. By controlling the display order of the partitions, different refresh frequency control of the areas respectively controlled by the first gate driving unit and the second gate driving unit can be achieved, thereby achieving higher resolution and higher frequency display.
  • FIG8 is a schematic diagram of the structure of a display panel driven by interlace scanning in one embodiment of the present application.
  • gate driving module 110, first gate driving unit; 120, second gate driving unit; 130, third gate driving unit; 140, fourth gate driving unit; 210, signal selection circuit; 211, first control module; 212, second control module; 213, inverting module; 220, first selection circuit; 230, second selection circuit; 240, third selection circuit.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • An embodiment of the present application provides a display panel, which includes a gate driving module 100 and a signal selection circuit 210.
  • the scanning signal output by the gate driving module 100 is used to control the pixels of the display panel to refresh.
  • the gate driving module 100 includes a first gate driving unit 110 and a second gate driving unit 120.
  • the first gate driving unit 110 and the second gate driving unit 120 control some pixel rows of the display panel to refresh.
  • Different pixel rows controlled by the same gate driving unit can be adjacent and continuous pixel rows or pixel rows arranged at intervals.
  • the number of pixel rows controlled by different gate driving units can be the same or different, which is not specifically limited in this embodiment.
  • the signal selection circuit 210 is electrically connected to the first gate driving unit 110 and the second gate driving unit 120 respectively, that is, the scanning signal output by the first gate driving unit 110 is input to the signal selection circuit 210, and the control signal output by the signal selection circuit 210 is output to the second gate driving unit 120.
  • the signal selection circuit 210 receives the inversion signal, the scanning signal output by the first gate driving unit 110, and the low-level signal, and outputs the scanning signal or the low-level signal output by the first gate driving unit 110 as a control signal to the second gate driving unit 120 according to the inversion signal. If the control signal is the scanning signal output by the first gate driving unit 110, the pixel row controlled by the second gate driving unit 120 will be refreshed, and if the control signal is a low-level signal, the pixel row controlled by the second gate driving unit 120 will not be refreshed.
  • the inversion signal includes a high level and a low level, and the inversion signal alternates between adjacent frames, that is, when the inversion signal of the first frame is at a high level, the inversion signal of the next frame of the first frame is switched to a low level, and then the inversion signal of the next frame is switched to a high level, and the cycle is repeated alternately.
  • the first gate driving unit 110 receives an initial trigger signal to start refreshing the picture.
  • the initial trigger signal is a trigger signal for the first frame of the picture
  • the control signal is a scanning signal output by the first gate driving unit 110.
  • the pixel rows controlled by the first gate driving unit 110 and the second driving unit are refreshed, and the data voltage corresponding to the first frame of the picture is written to realize the display of the first frame of the picture.
  • the control signal is a low-level signal, and the pixel row controlled by the first gate driving unit 110 will be refreshed, and the pixel row controlled by the second gate driving unit 120 will not be refreshed. Therefore, the pixel row controlled by the first gate driving unit 110 will be written with the data voltage corresponding to the second frame, and the pixel row controlled by the second gate driving unit 120 will still display the content displayed in the first frame.
  • the pixel rows controlled by the first gate driving unit 110 will be refreshed twice, and the pixel rows controlled by the second gate driving unit 120 will only be refreshed once.
  • the refresh rate of the pixel rows controlled by the first gate driving unit 110 is twice the refresh rate of the pixel rows controlled by the second gate driving unit 120.
  • the display panel is partitioned and controlled by adding a signal selection circuit 210.
  • a signal selection circuit 210 By controlling the partition display order, different refresh frequency controls can be implemented for different partitions, thereby achieving higher resolution and higher frequency display. Compared with the same resolution, the power consumption and transmission bandwidth requirements are reduced.
  • the display panel includes a first display area A and a second display area B.
  • the sizes of the first display area A and the second display area B may be the same or different, which is not specifically limited in this embodiment.
  • the first gate driving unit 110 controls the pixel rows in the first display area A to refresh
  • the second gate driving unit 120 controls the pixel rows in the second display area B to refresh.
  • the control signal is the scanning signal output by the first gate driving unit 110, and the first display area A and the second display area B refresh and display the first frame image.
  • the initial trigger signal is the trigger signal of the next frame of the first frame
  • the control signal is a low-level signal
  • the first display area A is refreshed to the corresponding image of the next frame of the first frame
  • the second display area B still maintains the corresponding image of the first frame, that is, the refresh rate of the first display area A is twice the refresh rate of the second display area B.
  • the first gate driving unit 110 and the second gate driving unit 120 each include at least one gate driving circuit, and the driving mode of the at least one gate driving circuit is any one of single-side driving, double-side driving and cross-double-side driving.
  • a signal selection circuit 210 is provided between the first gate driving unit 110 and the second gate driving unit 120. If it is a double-sided drive or a cross double-sided drive, the gate driving circuits of the first gate driving unit 110 and the second gate driving unit 120 are distributed on the left and right sides of the display panel, and the signal selection circuit 210 includes a first side selection circuit and a second side selection circuit, the first side selection circuit is respectively connected to the gate driving circuit on the first side of the first gate driving unit 110 and the gate driving circuit on the first side of the second gate driving unit 120, and the second side selection circuit is respectively connected to the gate driving circuit on the second side of the first gate driving unit 110 and the gate driving circuit on the second side of the second gate driving unit 120.
  • the first side selection circuit and the second side selection circuit have the same structure and signal connection, and the first side selection circuit and the second side selection circuit synchronously control the gate drive circuits on the left and right sides to achieve the same refresh mode of the pixel rows controlled by the same gate drive unit.
  • the same two circuits need to be set to synchronously control the gate drive circuits on the left and right sides during bilateral driving or cross bilateral driving.
  • the display panel further includes a first selection circuit 220 electrically connected to the first gate driving unit 110, the first selection circuit 220 receives an inversion signal, an initial trigger signal, and a low level signal, and outputs the initial trigger signal or the low level signal as a first control signal to the first gate driving unit 110 according to the inversion signal. If the first control signal is an initial trigger signal, the pixel row controlled by the first gate driving unit 110 will be refreshed, and if the first control signal is a low level signal, the pixel row controlled by the first gate driving unit 110 will not be refreshed.
  • the first control signal of the first frame is the initial trigger signal
  • the second control signal is the first scanning signal output by the first gate driving unit 110
  • the first display area A and the second display area B cooperate to display the first frame.
  • the first control signal is a low-level signal
  • the second control signal is an initial trigger signal
  • the first display area A is not refreshed
  • the corresponding image of the first frame is kept displayed
  • the second display area B refreshes and displays the corresponding image of the next frame of the first frame.
  • the refresh rate of the second display area B is twice the refresh rate of the first display area A, and the area with a faster refresh rate is adjusted relative to the above embodiment.
  • the display panel further includes a second selection circuit 230
  • the gate driving module 100 further includes a third gate driving unit 130
  • the third gate driving unit 130 is used to control the pixel row refresh of the third display area C
  • the second selection circuit 230 is electrically connected to the second gate driving unit 120 and the third gate driving unit 130 respectively.
  • the second selection circuit 230 receives the inversion signal, the low level signal and the second scanning signal output by the second gate driving unit 120, and outputs the low level signal or the second scanning signal output by the second gate driving unit 120 as the third control signal to the third gate driving unit 130 according to the inversion signal.
  • the pixel row controlled by the third gate driving unit 130 i.e., the third display area C
  • the third control signal is the second scanning signal output by the second gate driving unit 120
  • the pixel row controlled by the third gate driving unit 130 i.e., the third display area C
  • the first control signal is an initial trigger signal
  • the second control signal is a first scanning signal output by the first gate driving unit 110
  • the third control signal is a low-level signal, that is, the first display area A and the second display area B are refreshed to the corresponding image of the first frame, and the third display area C maintains the corresponding image of the previous frame of the first frame.
  • the first control signal is a low-level signal
  • the second control signal is an initial trigger signal
  • the third control signal is a second scanning signal output by the second gate driving unit 120, that is, the first display area A maintains the corresponding image of the first frame, and the second display area B and the third display area C are refreshed to the corresponding image of the next frame of the first frame. That is, in two adjacent frames, the image of the second display area B is refreshed twice, and the images of the first display area A and the third display area C are refreshed once.
  • the third display area C remains in a dark state when the first frame is written. Since this embodiment is applied to a high-refresh display panel and the third display area C is only a partial display area of the display panel, the human eye cannot perceive the dark state of the third display area C in the first frame.
  • the first control signal is the initial trigger signal
  • the second control signal is the first scanning signal output by the first gate driving unit 110
  • the third control signal is the second scanning signal output by the second gate driving unit 120, that is, the first display area A, the second display area B, and the third display area C are all refreshed to the corresponding image of the first frame.
  • the first control signal is a low-level signal in the next frame of the first frame
  • the second control signal is the initial trigger signal
  • the third control signal is a low-level signal, that is, the first display area A and the third display area C maintain the corresponding image of the first frame
  • the second display area B is refreshed to the corresponding image of the next frame of the first frame. That is, in two adjacent frames, the image of the second display area B is refreshed twice, and the images of the first display area A and the third display area C are refreshed once.
  • the display panel also includes a third selection circuit 240
  • the gate driving module 100 also includes a fourth gate driving unit 140
  • the fourth gate driving unit 140 is used to control the pixel row refresh of the fourth display area D
  • the third selection circuit 240 is electrically connected to the first gate driving unit 110, the second gate driving unit 120, and the fourth gate driving unit 140, respectively.
  • the third selection circuit 240 receives the inversion signal, the scan signal output by the second gate driving unit 120, and the scan signal output by the first gate driving unit 110, and outputs the scan signal output by the second gate driving unit 120 and the scan signal output by the first gate driving unit 110 as a fourth control signal to the fourth gate driving unit 140 according to the inversion signal.
  • the control signal is the scanning signal output by the first gate driving unit 110
  • the fourth control signal is the scanning signal output by the second gate driving unit 120, that is, the first display area A, the second display area B and the fourth display area D are all refreshed to the corresponding images of the first frame image.
  • the control signal is a low level signal
  • the fourth control signal is a scanning signal output by the first gate driving unit 110, that is, the first display area A and the fourth display area D are refreshed to the corresponding image of the next frame of the first frame, and the second display area B maintains the corresponding image of the first frame. That is, in two adjacent frames, the images of the first display area A and the fourth display area D are refreshed twice, and the image of the second display area B is refreshed once.
  • the signal selection circuit 210, the first selection circuit 220, the second selection circuit 230, and the third selection circuit 240 in the above embodiment can be set to the same selection circuit, all of which use one of the two input signals as the output signal based on the inversion signal, and the inversion signal is alternated in adjacent frames, so the output signal is also alternated between the two input signals.
  • the difference between the signal selection circuit 210, the first selection circuit 220, the second selection circuit 230, and the third selection circuit 240 is only that the two input signals are different.
  • This embodiment takes the signal selection circuit 210 as an example for description, and other selection circuits are not described one by one.
  • the signal selection circuit 210 includes a first second control module 0211, a second second control module 0212 and an inverting module 213, the second second control module 0212 and the inverting module 213 are connected, the first second control module 0211 receives the scanning signal output by the first gate driving unit 110, the second second control module 0212 receives the low level signal, and the first second control module 0211 and the inverting module 213 are connected to the inversion signal.
  • the inversion signal is switched alternately in adjacent frames.
  • the inversion signal is at a high level, and the signal selection circuit 210 outputs the scanning signal output by the first gate driving unit 110.
  • the inversion signal is switched to a low level, and the signal selection circuit 210 outputs a low level signal.
  • the inversion signal is switched to a high level, and the signal selection circuit 210 outputs the scanning signal output by the first gate driving unit 110, and the alternating cycle is performed.
  • the first second control module 0211 includes a first switch transistor, the gate of the first switch transistor is connected to the inversion signal, one of the source and drain of the first switch transistor is connected to the scan signal output by the first gate driving unit 110, and the other of the source and drain of the first switch transistor is connected to the second gate driving unit 120.
  • One end of the inversion module is connected to the inversion signal, and the other end of the inversion module is connected to the second second control module 0212.
  • the second second control module 0212 includes a second switch transistor, the gate of the second switch transistor is connected to the other end of the inversion module, one of the source and drain of the second switch transistor is connected to the low level signal, and the other of the source and drain of the second switch transistor is connected to the second gate driving unit 120.
  • the inversion module When the inversion signal is at a high level, the inversion module outputs a low level to the gate of the second switch transistor, the second switch transistor is turned off, the first switch transistor is turned on, and the control signal is the scan signal output by the first gate driving unit 110 .
  • the inversion module When the inversion signal is at a low level, the inversion module outputs a high level to the gate of the second switch transistor, the second switch transistor is turned on, the first switch transistor is turned off, and the control signal is a low level signal.
  • the display panel is partitioned and controlled by setting a selection circuit.
  • different refresh frequency controls can be achieved for different partitions, thereby achieving higher resolution and higher frequency display. Compared with the same resolution, the power consumption and transmission bandwidth requirements are reduced.
  • the existing drive scheme is that after the drive circuit GOA receives the trigger signal STV0, it is transmitted from the G_1 level to the G4N level in sequence, and the display area data is refreshed synchronously, and the display area A is not partitioned.
  • the present application provides a display panel, and the driving circuit is divided into the following division schemes: G_1 to GN are the first part (the first part is equivalent to the first gate driving unit), which controls the display area A; G_N+1 to 2GN are the second part, which controls the display B; G_2N+1 to G3N are the third part (the second part and the third part are equivalent to the second gate driving unit), which controls the display area C; G_3N+1 to G4N are the fourth part (the fourth part is equivalent to the third gate driving unit), which controls the display area D; in addition, in order to achieve normal driving, it is necessary to add a first control circuit 1, a second control circuit 2, and a third control circuit 3.
  • the first control circuit 1 is the first selection circuit in the above embodiment
  • the second control circuit 2 is the signal selection circuit in the above embodiment
  • the third control circuit 3 is the second selection circuit in the above embodiment.
  • the first control circuit 1, the second control circuit 2, and the third control circuit 3 all include a first control module 01 and a second control module 02.
  • FIG9 is a schematic diagram of the structure of the control circuit 1, which has 14 T2C in total.
  • the gate and source of NTA1 are short-circuited and connected to the FHL signal.
  • the drain of NT1A is connected to the QA1 node.
  • the gate of NT9A is connected to the QA1 node, the source is connected to STV0, and the drain is connected to the circuit output terminal STV1.
  • the gate and source of NT8A are short-circuited and connected to VGH, and the drain is connected to the PA1 node.
  • the gate of NT5A is connected to the PA1 node, the source is connected to the QA1 node, and the drain is connected to VGL.
  • the gate of NT6A is connected to FHL, the source is connected to the PA1 node, and the drain is connected to VGL.
  • the gate of NT10A is connected to the PA1 node, and the source is connected to VGL.
  • the drain is connected to the output terminal STV1;
  • the gate and source of NT1B are short-circuited and connected to the PC1 signal, and the drain of NT1B is connected to the QB1 node;
  • the gate and source of NT9B are short-circuited and connected to the QB1 node, the source is connected to VGL, and the drain is connected to the circuit output terminal STV1;
  • the gate and source of NT8B are short-circuited and connected to VGH, and the drain is connected to the PB1 node;
  • the gate of NT5B is connected to the PB1 node, the source is connected to the QB1 node, and the drain is connected to VGL;
  • the gate of NT6B is connected to
  • FIG10 is a schematic diagram of the structure of the control circuit 2: a total of 14T2C, the gate and source of NTA1 are short-circuited and connected to the FHL signal, the drain of NT1A is connected to the QA2 node; the gate of NT9A is connected to the QA2 node, the source is connected to Gate_N, and the drain is connected to the circuit output terminal STV2; the gate and source of NT8A are short-circuited and connected to VGH, and the drain is connected to the PA2 node; the gate of NT5A is connected to the PA2 node, the source is connected to the QA2 node, and the drain is connected to VGL, the gate of NT6A is connected to FHL, the source is connected to the PA2 node, and the drain is connected to VGL, and the gate of NT10A is connected to the PA2 node, and the source is connected to VG L, drain connected to output terminal STV2; gate and source of NTB1 are short-circ
  • FIG11 is a schematic diagram of the structure of the third control circuit 3: a total of 14T2C, the gate and source of NTA1 are short-circuited and connected to the FHL signal, the drain of NT1A is connected to the QA3 node; the gate of NT9A is connected to the QA3 node, the source is connected to VGL, and the drain is connected to the circuit output terminal STV3; the gate and source of NT8A are short-circuited and connected to VGH, and the drain is connected to the PA3 node; the gate of NT5A is connected to the PA3 node, the source is connected to the QA3 node, and the drain is connected to VGL; the gate of NT6A is connected to FHL, the source is connected to the PA3 node, and the drain is connected to VGL; the gate of NT10A is connected to the PA3 node, the source is connected to VGL, The drain is connected to the output terminal STV3; the gate and source of NTB1 are short-
  • a reversal signal FHL is newly added, and the display drive is controlled by inverting and inputting signals and selectively outputting signals;
  • STV0 supplies an initial trigger signal to the IC, and by selecting the control circuit 1, the output signal of the control circuit 1 outputs a signal in phase with STV0 when FHL is a high potential, and outputs a low level when FHL is a low level;
  • the control circuit 2 is selected to output a signal in phase with GN when FHL is a high level, and outputs a signal in phase with the second frame STV0 when FHL is an L signal;
  • the control circuit 3 is selected: when FHL is a high level, no output is performed, and when FHL is a low level, a signal in phase with the G3N level output is output.
  • the present application provides a display device, which includes a display panel as described in any of the above embodiments.

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Abstract

一种显示面板，包括根据初始触发信号输出扫描信号的第一栅极驱动单元（110）、与第一栅极驱动单元（110）和第二栅极驱动单元（120）电连接的信号选择电路（210），信号选择电路（210）用于接收反转信号、第一栅极驱动单元（110）输出的扫描信号和低电平信号，并输出控制信号至第二栅极驱动单元（120），控制信号为第一栅极驱动单元（110）输出的扫描信号或低电平信号。

Description

显示面板及显示装置
本申请要求于2023年11月16日提交的申请号为202311541468.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域。
 背景技术
随着显示行业的发展，用户对显示质量的要求越来越高，尤其是虚拟现实 (Virtual Reality，VR)、增强现实(Augmented Reality，AR)、沉浸式游戏、竞速运动等特定的显示场景下，对显示设备的画面刷新速度要求非常高。目前常规显示频率下动态模糊、显示拖影等问题比较严重，高分辨率、高频驱动可有效降低运动模糊、显示拖影问题，而提高显示刷新频率又会直接导致显示传输数据量倍增、像素充电不足等问题，进而增加数据传输接口数、数据传输带宽以及显示设备功耗等，严重影响用户在显示设备中的沉浸式体验。
 发明概述
提高显示刷新频率又会直接导致显示传输数据量倍增、像素充电不足等问题，进而增加数据传输接口数、数据传输带宽以及显示设备功耗等，严重影响用户在显示设备中的沉浸式体验。
第一方面，本申请实施例提供一种显示面板，包括：
栅极驱动模块，包括第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元被配置为接收初始触发信号，并根据所述初始触发信号输出扫描信号；
信号选择电路，分别与所述第一栅极驱动单元、所述第二栅极驱动单元电连接，所述信号选择电路被配置为接收反转信号、所述第一栅极驱动单元输出的扫描信号以及低电平信号，并输出控制信号至所述第二栅极驱动单元，所述控制信号为所述第一栅极驱动单元输出的扫描信号或所述低电平信号；
当所述初始触发信号为第一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述第一栅极驱动单元输出的扫描信号；当所述初始触发信号为所述第一帧画面的下一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述低电平信号；
其中，所述显示面板还包括与所述第一栅极驱动单元电连接的第一选择电路，所述第一选择电路被配置为接收所述反转信号、所述初始触发信号以及所述低电平信号，并输出第一控制信号至所述第一栅极驱动单元，所述第一栅极驱动单元被配置为根据所述第一控制信号输出第一扫描信号，所述第一控制信号为所述初始触发信号或所述低电平信号；
所述信号选择电路被配置为接收所述反转信号、所述第一栅极驱动单元输出的第一扫描信号以及所述初始触发信号，并输出第二控制信号至所述第二栅极驱动单元，所述第二栅极驱动单元被配置为根据所述第二控制信号输出第二扫描信号，所述第二控制信号为第一栅极驱动单元输出的扫描信号或所述初始触发信号；
当所述第一控制信号为所述初始触发信号时，所述第二控制信号为所述第一栅极驱动单元输出的第一扫描信号；当所述第一控制信号为所述低电平信号时，所述第二控制信号为所述初始触发信号；
其中，所述显示面板还包括第三选择电路，所述栅极驱动模块还包括第四栅极驱动单元，所述第三选择电路分别与所述第一栅极驱动单元、所述第二栅极驱动单元、所述第四栅极驱动单元电连接；
所述第三选择电路被配置为接收所述反转信号、所述第二栅极驱动单元输出的扫描信号以及所述第一栅极驱动单元输出的扫描信号，并输出第四控制信号至所述第四栅极驱动单元，所述第四控制信号为所述第二栅极驱动单元输出的扫描信号或所述第一栅极驱动单元输出的扫描信号；
当所述初始触发信号为第一帧画面的触发信号时，所述控制信号为所述第一栅极驱动单元输出的扫描信号，所述第四控制信号为所述第二栅极驱动单元输出的扫描信号；当所述初始触发信号为所述第一帧画面的下一帧画面的触发信号时，所述控制信号为所述低电平信号，所述第四控制信号为所述第一栅极驱动单元输出的扫描信号。
第二方面，本申请实施例提供一种显示面板，包括：
栅极驱动模块，包括第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元被配置为接收初始触发信号，并根据所述初始触发信号输出扫描信号；
信号选择电路，分别与所述第一栅极驱动单元、所述第二栅极驱动单元电连接，所述信号选择电路被配置为接收反转信号、所述第一栅极驱动单元输出的扫描信号以及低电平信号，并输出控制信号至所述第二栅极驱动单元，所述控制信号为所述第一栅极驱动单元输出的扫描信号或所述低电平信号；
当所述初始触发信号为第一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述第一栅极驱动单元输出的扫描信号；当所述初始触发信号为所述第一帧画面的下一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述低电平信号。
第三方面，本申请提供一种显示装置，所述显示装置包括如上述任一所述的显示面板。
有益效果
本申请实施例提供的显示面板及显示装置，通过设置信号选择电路将显示面板分为第一栅极驱动单元和第二栅极驱动单元分别控制刷新的区域，通过控制分区显示顺序，可以实现第一栅极驱动单元和第二栅极驱动单元分别控制的区域不同刷新频率控制，实现更高分辨率、更高频的显示。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1至图5是本申请中多个实施例中显示面板的结构示意图；
图6是本申请另一实施例中信号选择电路的结构示意图；
图7是现有技术隔行扫描（Interlace）驱动的显示面板的结构图；
图8是本申请一实施例中隔行扫描（Interlace）驱动的显示面板的结构示意图；
图9至图11是本申请中多个实施例中控制电路的结构示意图；
图12和图13是本申请中多个实施例中控制电路的信号示意图；
图14和图15是本申请多个实施例中显示区刷新示意图；
图16是本申请一实施例中相邻两帧画面的时序图。
附图标号：
100、栅极驱动模块；110、第一栅极驱动单元；120、第二栅极驱动单元；130、第三栅极驱动单元；140、第四栅极驱动单元；210、信号选择电路；211、第一控制模块；212、第二控制模块；213、反相模块；220、第一选择电路；230、第二选择电路；240、第三选择电路。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。本领域的普通技术人员应当理解，可以对本申请的实施例进行修改或者等同替换，而不脱离本申请的精神和范围，这样的修改或者等同替换均应涵盖在本申请的范围当中。
请参阅图1，本申请实施例提供显示面板，显示面板包括栅极驱动模块100和信号选择电路210，栅极驱动模块100输出的扫描信号用于控制显示面板的像素进行刷新，栅极驱动模块100包括第一栅极驱动单元110和第二栅极驱动单元120，第一栅极驱动单元110和第二栅极驱动单元120控制显示面板的部分像素行进行刷新，同一栅极驱动单元控制的不同像素行可以是相邻连续的像素行，也可以是间隔设置的像素行，并且不同栅极驱动单元控制的像素行的行数可以相同也可以不相同，本实施例不作具体限定。
信号选择电路210分别与第一栅极驱动单元110、第二栅极驱动单元120电连接，即第一栅极驱动单元110输出的扫描信号输入到信号选择电路210，信号选择电路210输出的控制信号输出到第二栅极驱动单元120。
信号选择电路210接收反转信号、第一栅极驱动单元110输出的扫描信号以及低电平信号，并根据反转信号将第一栅极驱动单元110输出的扫描信号或低电平信号作为控制信号输出至第二栅极驱动单元120。如果控制信号是第一栅极驱动单元110输出的扫描信号，则第二栅极驱动单元120控制的像素行会进行刷新，如果控制信号是低电平信号，则第二栅极驱动单元120控制的像素行不会进行刷新。
由于反转信号包括高电平和低电平，并且反转信号在相邻帧之间交替变换，即当第一帧画面反转信号为高电平时，第一帧画面的下一帧画面反转信号切换为低电平，再下一帧画面反转信号又切换为高电平，依次交替循环。
第一栅极驱动单元110接收初始触发信号开始画面的刷新，当初始触发信号为第一帧画面的触发信号时，控制信号为第一栅极驱动单元110输出的扫描信号，第一栅极驱动单元110和第二驱动单元控制的像素行均进行刷新，并写入第一帧画面相应的数据电压，实现第一帧画面的显示。
基于上述反转信号的交替变化，当初始触发信号为第一帧画面的下一帧画面的触发信号时，控制信号为低电平信号，则第一栅极驱动单元110控制的像素行会进行刷新，第二栅极驱动单元120控制的像素行不会进行刷新，因此第一栅极驱动单元110控制的像素行会写入第二帧画面相应的数据电压，第二栅极驱动单元120控制的像素行显示的仍然是第一帧画面显示的内容。
每相邻的两帧画面中，第一栅极驱动单元110控制的像素行的画面会刷新两次，第二栅极驱动单元120控制的像素行的画面只会刷新一次，第一栅极驱动单元110控制的像素行的刷新率是第二栅极驱动单元120控制的像素行的刷新率的两倍。
本实施例中，通过增加信号选择电路210使得显示面板分区控制，通过控制分区显示顺序，可以实现不同分区的不同刷新频率控制，实现更高分辨率、更高频的显示，且相比于同等分辨率下，功耗及传输带宽需求降低。
在一个实施例中，同一栅极驱动单元控制的不同像素行是相邻连续的像素行，如图2所示，显示面板包括第一显示区A和第二显示区B，第一显示区A和第二显示区B的大小可以相同，也可以不相同，本实施例不作具体限定。第一栅极驱动单元110控制第一显示区A内的像素行进行刷新，第二栅极驱动单元120控制第二显示区B内的像素行进行刷新。
通过信号选择电路210中的反转信号的控制，当初始触发信号为第一帧画面的触发信号时，控制信号为第一栅极驱动单元110输出的扫描信号，则第一显示区A和第二显示区B刷新显示第一帧画面。
当初始触发信号为第一帧画面的下一帧画面的触发信号时，控制信号为低电平信号，则第一显示区A刷新为第一帧画面的下一帧画面的对应图像，第二显示区B仍保持第一帧画面的对应图像，即第一显示区A的刷新率是第二显示区B的刷新率的两倍。
第一栅极驱动单元110和第二栅极驱动单元120均包含至少一个栅极驱动电路，至少一个栅极驱动电路的驱动方式为单边驱动、双边驱动以及交叉双边驱动中任意一种。
在一个实施例中，如果是单边驱动，则在第一栅极驱动单元110和第二栅极驱动单元120中间设置一个信号选择电路210即可。如果是双边驱动或者交叉双边驱动，第一栅极驱动单元110和第二栅极驱动单元120的栅极驱动电路分布在显示面板左右两侧，则信号选择电路210包括第一侧选择电路和第二侧选择电路，第一侧选择电路分别连接第一栅极驱动单元110第一侧的栅极驱动电路和第二栅极驱动单元120第一侧的栅极驱动电路，第二侧选择电路分别连接第一栅极驱动单元110第二侧的栅极驱动电路和第二栅极驱动单元120第二侧的栅极驱动电路。
第一侧选择电路和第二侧选择电路的结构以及信号连接相同，第一侧选择电路和第二侧选择电路同步控制左右两侧的栅极驱动电路，以实现同一栅极驱动单元控制的像素行的刷新方式相同。此外，如果增加与信号选择电路210相同功能的选择电路，则双边驱动或者交叉双边驱动时同样需要设置相同的两个电路同步控制左右侧的栅极驱动电路。
在一个实施例中，如图3所示，显示面板还包括与所述第一栅极驱动单元110电连接的第一选择电路220，第一选择电路220接收反转信号、初始触发信号以及低电平信号，并根据反转信号将初始触发信号或低电平信号作为第一控制信号输出至第一栅极驱动单元110。如果第一控制信号是初始触发信号，则第一栅极驱动单元110控制的像素行会进行刷新，如果第一控制信号是低电平信号，则第一栅极驱动单元110控制的像素行不会进行刷新。
此外，在增加了第一选择电路220之后，信号选择电路210连接的信号需要进行调整，信号选择电路210接收反转信号、第一栅极驱动单元110输出的第一扫描信号以及初始触发信号，并根据反转信号将第一栅极驱动单元110输出的第一扫描信号或初始触发信号作为第二控制信号输出至第二栅极驱动单元120。无论第二控制信号是第一栅极驱动单元110输出的第一扫描信号还是低电平信号，第二栅极驱动单元120控制的像素行都会进行刷新，区别在于第一栅极驱动单元110控制的像素行不进行刷新时，第二栅极驱动单元120需要通过初始触发信号进行触发。
因此，第一帧画面第一控制信号为初始触发信号，第二控制信号为第一栅极驱动单元110输出的第一扫描信号，第一显示区A和第二显示区B配合显示第一帧画面。
第一帧画面的下一帧画面由于反转信号的切换，第一控制信号为低电平信号，第二控制信号为初始触发信号，第一显示区A不刷新，保持显示第一帧画面的对应图像，第二显示区B刷新显示第一帧画面的下一帧画面的对应图像，第二显示区B的刷新率是第一显示区A的刷新率的两倍，相对上述实施例刷新率更快的区域进行了调整。
在一个实施例中，如图4所示，显示面板还包括第二选择电路230，所述栅极驱动模块100还包括第三栅极驱动单元130，第三栅极驱动单元130用于控制第三显示区C的像素行刷新，第二选择电路230分别与第二栅极驱动单元120、第三栅极驱动单元130电连接。第二选择电路230接收反转信号、低电平信号以及第二栅极驱动单元120输出的第二扫描信号，并根据反转信号将低电平信号或第二栅极驱动单元120输出的第二扫描信号作为第三控制信号输出至第三栅极驱动单元130。当第三控制信号为低电平信号时，第三栅极驱动单元130控制的像素行即第三显示区C不刷新，当第三控制信号为第二栅极驱动单元120输出的第二扫描信号时，第三栅极驱动单元130控制的像素行即第三显示区C刷新。
在一个实施例中，如图4所示，第一帧画面时第一控制信号为初始触发信号，第二控制信号为第一栅极驱动单元110输出的第一扫描信号，第三控制信号为低电平信号，即第一显示区A和第二显示区B刷新为第一帧画面的对应图像，第三显示区C保持第一帧画面的上一帧画面的对应图像。第一帧画面的下一帧画面时第一控制信号为低电平信号，第二控制信号为初始触发信号，第三控制信号为第二栅极驱动单元120输出的第二扫描信号，即第一显示区A保持第一帧画面的对应图像，第二显示区B和第三显示区C刷新为第一帧画面的下一帧画面的对应图像。即在相邻的两帧里第二显示区B的图像刷新两次，第一显示区A和第三显示区C的图像刷新一次。
需要说明的是，当第一帧画面为首帧画面，即第一帧画面没有上一帧画面时，第三显示区C在第一帧画面写入时保持暗态，当由于本实施例应用于高刷新了的显示面板，且第三显示区C仅仅是显示面板的部分显示区域，人眼无法感受到首帧画面第三显示区C的暗态。
第一帧画面时第一控制信号为初始触发信号，第二控制信号为第一栅极驱动单元110输出的第一扫描信号，第三控制信号为第二栅极驱动单元120输出的第二扫描信号，即第一显示区A、第二显示区B以及第三显示区C均刷新为第一帧画面的对应图像。第一帧画面的下一帧画面时第一控制信号为低电平信号时，第二控制信号为初始触发信号，第三控制信号为低电平信号，即第一显示区A和第三显示区C保持第一帧画面的对应图像，第二显示区B刷新为第一帧画面的下一帧画面的对应图像。即在相邻的两帧里第二显示区B的图像刷新两次，第一显示区A和第三显示区C的图像刷新一次。
在一个实施例中，如图5所示，显示面板还包括第三选择电路240，栅极驱动模块100还包括第四栅极驱动单元140，第四栅极驱动单元140用于控制第四显示区D的像素行刷新，所述第三选择电路240分别与第一栅极驱动单元110、第二栅极驱动单元120、第四栅极驱动单元140电连接。
第三选择电路240接收反转信号、第二栅极驱动单元120输出的扫描信号以及第一栅极驱动单元110输出的扫描信号，并根据反转信号将第二栅极驱动单元120输出的扫描信号和第一栅极驱动单元110输出的扫描信号作为第四控制信号输出至第四栅极驱动单元140。
当初始触发信号为第一帧画面的触发信号时，控制信号为第一栅极驱动单元110输出的扫描信号，第四控制信号为第二栅极驱动单元120输出的扫描信号，即第一显示区A、第二显示区B以及第四显示区D均刷新为第一帧画面的对应图像。
当初始触发信号为第一帧画面的下一帧画面的触发信号时，控制信号为低电平信号，第四控制信号为第一栅极驱动单元110输出的扫描信号，即第一显示区A和第四显示区D刷新为第一帧画面的下一帧画面的对应图像，第二显示区B保持第一帧画面的对应图像。即在相邻的两帧里第一显示区A和第四显示区D的图像刷新两次，第二显示区B的图像刷新一次。
在一个实施例中，上述实施例中信号选择电路210、第一选择电路220、第二选择电路230以及第三选择电路240可以设为相同的选择电路，都是基于反转信号将输入的两个信号其中之一作为输出信号，并且反转信号在相邻帧进行交替，因此输出信号也在输入的两个信号中进行交替。信号选择电路210、第一选择电路220、第二选择电路230以及第三选择电路240区别仅在于输入的两个信号不同，本实施例以信号选择电路210为例进行说明，其它选择电路不再一一赘述。
如图6所示，信号选择电路210包括第一第二控制模块0211、第二第二控制模块0212以及反相模块213，第二第二控制模块0212和反相模块213连接，第一第二控制模块0211接收第一栅极驱动单元110输出的扫描信号，第二第二控制模块0212接收低电平信号，第一第二控制模块0211和反相模块213连接反转信号。
反转信号在相邻帧交替切换，第一帧画面时反转信号为高电平，信号选择电路210输出第一栅极驱动单元110输出的扫描信号，第一帧画面的下一帧画面时反转信号切换为低电平，信号选择电路210输出低电平信号。再下一帧画面时反转信号切换为高电平，信号选择电路210输出第一栅极驱动单元110输出的扫描信号，以此进行交替循环。
在一个实施例中，第一第二控制模块0211包括第一开关晶体管，第一开关晶体管的栅极连接反转信号，第一开关晶体管源漏极的一者连接第一栅极驱动单元110输出的扫描信号，第一开关晶体管源漏极的另一者连接第二栅极驱动单元120。反相模块的一端连接反转信号，反相模块的另一端连接第二第二控制模块0212。第二第二控制模块0212包括第二开关晶体管，第二开关晶体管的栅极连接反相模块的另一端，第二开关晶体管源漏极的一者连接低电平信号，第二开关晶体管源漏极的另一者连接第二栅极驱动单元120。
当反转信号为高电平时，反相模块输出低电平至第二开关晶体管的栅极，第二开关晶体管关闭，第一开关晶体管导通，控制信号为第一栅极驱动单元110输出的扫描信号。
当反转信号为低电平时，反相模块输出高电平至第二开关晶体管的栅极，第二开关晶体管导通，第一开关晶体管关闭，控制信号为低电平信号。
本实施例中通过设置选择电路使得显示面板分区控制，通过控制分区显示顺序，可以实现不同分区的不同刷新频率控制，实现更高分辨率、更高频的显示，且相比于同等分辨率下，功耗及传输带宽需求降低。
如图7所示，以4N×M分辨率&Interlace驱动示意，现有驱动方案为驱动电路GOA接收到触发信号STV0后，由G_1级依次级传至G4N级，同步完成显示区数据刷新，且显示区A不进行分区拆分。
如图8所示，本申请提供一种显示面板，将驱动电路进行划分，划分方案为G_1级至GN级为第一部分（第一部分相当于第一栅极驱动单元），控制显示区A；G_N+1级至2GN级为第二部分，控制显示B； G_2N+1级至G3N级为第三部分（第二部分和第三部分相当于第二栅极驱动单元），控制显示区C；G_3N+1级至G4N级为第四部分（第四部分相当于第三栅极驱动单元），控制显示区D；另外，为实现正常驱动，需要新增第一控制电路1、第二控制电路2、第三控制电路3，第一控制电路1为上述实施例中的第一选择电路，第二控制电路2为上述实施例中的信号选择电路，第三控制电路3为上述实施例中的第二选择电路。第一控制电路1、第二控制电路2、第三控制电路3均包括第一控制模块01和第二控制模块02。
图9为控制电路1的结构示意图，共计14T2C,NTA1的栅极与源极短接，并与FHL信号连接，NT1A的漏极接QA1节点；NT9A的栅极接QA1节点，源极接STV0,漏极接电路输出端STV1；NT8A的栅极与源极短接，且连接至VGH,漏极接PA1节点；NT5A的栅极接PA1节点，源极接QA1节点，漏极接VGL,NT6A的栅极接FHL,源极接PA1节点，漏极接VGL，NT10A的栅极接PA1节点，源极接VGL,漏极接输出端STV1;NT1B的栅极与源极短接，并与PC1信号连接，NT1B的漏极接QB1节点；NT9B的栅极接QB1节点，源极接VGL,漏极接电路输出端STV1；NT8B的栅极与源极短接，且连接至VGH,漏极接PB1节点；NT5B的栅极接PB1节点，源极接QB1节点，漏极接VGL,NT6B的栅极接PC1,源极接PB1节点，漏极接VGL，NT10B的栅极接PB1节点，源极接VGL,漏极接输出端STV1。NT6C和NT8C构成反相器，将与FHL相反的电位输入至PC2。
图10为控制电路2的结构示意图：共计14T2C,NTA1的栅极与源极短接，并与FHL信号连接，NT1A的漏极接QA2节点；NT9A的栅极接QA2节点，源极接Gate_N,漏极接电路输出端STV2；NT8A的栅极与源极短接，且连接至VGH,漏极接PA2节点；NT5A的栅极接PA2节点，源极接QA2节点，漏极接VGL,NT6A的栅极接FHL,源极接PA2节点，漏极接VGL，NT10A的栅极接PA2节点，源极接VGL,漏极接输出端STV2;NTB1的栅极与源极短接，并与PC2信号连接，NT1B的漏极接QB2节点；NT9B的栅极接QB2节点，源极接STV0,漏极接电路输出端STV2；NT8B的栅极与源极短接，且连接至VGH,漏极接PB2节点；NT5B的栅极接PB2节点，源极接QB2节点，漏极接VGL,NT6B的栅极接PC2,源极接PB2节点，漏极接VGL，NT10B的栅极接PB2节点，源极接VGL,漏极接输出端STV2。NT6C和NT8C构成反相器，将与FHL相反的电位输入至PC2。
图11为第三控制电路3的结构示意图：共计14T2C,NTA1的栅极与源极短接，并与FHL信号连接，NT1A的漏极接QA3节点；NT9A的栅极接QA3节点，源极接VGL,漏极接电路输出端STV3；NT8A的栅极与源极短接，且连接至VGH,漏极接PA3节点；NT5A的栅极接PA3节点，源极接QA3节点，漏极接VGL,NT6A的栅极接FHL,源极接PA3节点，漏极接VGL，NT10A的栅极接PA3节点，源极接VGL,漏极接输出端STV3;NTB1的栅极与源极短接，并与PC3信号连接，NT1B的漏极接QB3节点；NT9B的栅极接QB3节点，源极接Gate_3N,漏极接电路输出端STV3；NT8B的栅极与源极短接，且连接至VGH,漏极接PB3节点；NT5B的栅极接PB3节点，源极接QB3节点，漏极接VGL,NT6B的栅极接PC3,源极接PB3节点，漏极接VGL，NT10B的栅极接PB3节点，源极接VGL,漏极接输出端STV3。NT6C和NT8C构成反相器，将与FHL相反的电位输入至PC2。
如图12和图13所示，反转信号为H时，控制电路1输出STV0，控制电路2输出GateN，控制电路3输出VGL，控制信号为L时，控制电路1输出VGL，控制电路2输出STV0，控制电路3输出Gate3N。
如图14和图15所示：通过控制控制电路的输入信号，可以实现第(N-1)帧A/B/C区刷新，D区不刷新，第N帧B/C/D区刷新，A区不刷新。或者，可以实现第(N-1)帧B/C/D区刷新，A区不刷新，第N帧A/B/C区刷新，D区不刷新。均可以实现B/C区刷新频率为A/D区刷新频率的两倍，进而实现分区高频的目的。
图16为相邻两帧画面的时序图，本实施例新增反转信号FHL, 通过反转和输入信号，选择性的输出信号来控制显示驱动；STV0为IC供给初始触发信号，通过选择控制电路1，使得控制电路1的输出信号在FHL为高电位时输出与STV0同相位的信号，FHL为底电平时输出低电平；选择控制电路2在FHL为高电平时输出与GN同相位的信号，FHL为L信号时输出与第二帧STV0同相位的信号；选择控制电路3：在 FHL为高电平时，不输出，在FHL为低电平时输出与G3N级输出同相位的信号。
本申请提供显示装置，所述显示装置包括如上述任一实施例所述的显示面板。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上对本申请实施例所提供的一种显示面板及显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，包括：
    栅极驱动模块，包括第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元被配置为接收初始触发信号，并根据所述初始触发信号输出扫描信号；
    信号选择电路，分别与所述第一栅极驱动单元、所述第二栅极驱动单元电连接，所述信号选择电路被配置为接收反转信号、所述第一栅极驱动单元输出的扫描信号以及低电平信号，并输出控制信号至所述第二栅极驱动单元，所述控制信号为所述第一栅极驱动单元输出的扫描信号或所述低电平信号；
    当所述初始触发信号为第一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述第一栅极驱动单元输出的扫描信号；当所述初始触发信号为所述第一帧画面的下一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述低电平信号；
    其中，所述显示面板还包括与所述第一栅极驱动单元电连接的第一选择电路，所述第一选择电路被配置为接收所述反转信号、所述初始触发信号以及所述低电平信号，并输出第一控制信号至所述第一栅极驱动单元，所述第一栅极驱动单元被配置为根据所述第一控制信号输出第一扫描信号，所述第一控制信号为所述初始触发信号或所述低电平信号；
    所述信号选择电路被配置为接收所述反转信号、所述第一栅极驱动单元输出的第一扫描信号以及所述初始触发信号，并输出第二控制信号至所述第二栅极驱动单元，所述第二栅极驱动单元被配置为根据所述第二控制信号输出第二扫描信号，所述第二控制信号为第一栅极驱动单元输出的扫描信号或所述初始触发信号；
    当所述第一控制信号为所述初始触发信号时，所述第二控制信号为所述第一栅极驱动单元输出的第一扫描信号；当所述第一控制信号为所述低电平信号时，所述第二控制信号为所述初始触发信号；
    其中，所述显示面板还包括第三选择电路，所述栅极驱动模块还包括第四栅极驱动单元，所述第三选择电路分别与所述第一栅极驱动单元、所述第二栅极驱动单元、所述第四栅极驱动单元电连接；
    所述第三选择电路被配置为接收所述反转信号、所述第二栅极驱动单元输出的扫描信号以及所述第一栅极驱动单元输出的扫描信号，并输出第四控制信号至所述第四栅极驱动单元，所述第四控制信号为所述第二栅极驱动单元输出的扫描信号或所述第一栅极驱动单元输出的扫描信号；
    当所述初始触发信号为第一帧画面的触发信号时，所述控制信号为所述第一栅极驱动单元输出的扫描信号，所述第四控制信号为所述第二栅极驱动单元输出的扫描信号；当所述初始触发信号为所述第一帧画面的下一帧画面的触发信号时，所述控制信号为所述低电平信号，所述第四控制信号为所述第一栅极驱动单元输出的扫描信号。
  2. 如权利要求1所述的显示面板，其中，所述显示面板还包括第二选择电路，所述栅极驱动模块还包括第三栅极驱动单元，所述第二选择电路分别与所述第二栅极驱动单元、所述第三栅极驱动单元电连接；
    所述第二选择电路被配置为接收所述反转信号、所述低电平信号以及所述第二栅极驱动单元输出的第二扫描信号，并输出第三控制信号至所述第三栅极驱动单元，所述第三控制信号为所述低电平信号或所述第二栅极驱动单元输出的第二扫描信号。
  3. 如权利要求2所述的显示面板，其中，当所述第一控制信号为所述初始触发信号时，所述第二控制信号为所述第一栅极驱动单元输出的第一扫描信号，所述第三控制信号为所述低电平信号；当所述第一控制信号为所述低电平信号时，所述第二控制信号为所述初始触发信号，所述第三控制信号为所述第二栅极驱动单元输出的第二扫描信号；或，
    当所述第一控制信号为所述初始触发信号时，所述第二控制信号为所述第一栅极驱动单元输出的第一扫描信号，所述第三控制信号为所述第二栅极驱动单元输出的第二扫描信号；当所述第一控制信号为所述低电平信号时，所述第二控制信号为所述初始触发信号，所述第三控制信号为所述低电平信号。
  4. 如权利要求1所述的显示面板，其中，所述信号选择电路包括第一控制模块、第二控制模块以及反相模块，所述第二控制模块和所述反相模块连接，所述第一控制模块接收所述第一栅极驱动单元输出的扫描信号，所述第二控制模块接收所述低电平信号，所述第一控制模块和所述反相模块连接所述反转信号；
    当所述反转信号为高电平时，所述信号选择电路输出所述第一栅极驱动单元输出的扫描信号；当所述反转信号为低电平时，所述信号选择电路输出所述低电平信号。
  5. 如权利要求4所述的显示面板，其中，所述第一控制模块包括第一开关晶体管，所述第一开关晶体管的栅极连接所述反转信号，所述第一开关晶体管源漏极的一者连接所述第一栅极驱动单元输出的扫描信号，所述第一开关晶体管源漏极的另一者连接所述第二栅极驱动单元；
    所述反相模块的一端连接所述反转信号，所述反相模块的另一端连接所述第二控制模块；
    所述第二控制模块包括第二开关晶体管，所述第二开关晶体管的栅极连接所述反相模块的另一端，所述第二开关晶体管源漏极的一者连接所述低电平信号，所述第二开关晶体管源漏极的另一者连接所述第二栅极驱动单元。
  6. 如权利要求1所述的显示面板，其中，所述显示面板包括第一显示区和第二显示区，所述第一栅极驱动单元控制所述第一显示区内的像素行进行刷新，所述第二栅极驱动单元控制所述第二显示区内的像素行进行刷新；所述第一栅极驱动单元和所述第二栅极驱动单元均包含至少一个栅极驱动电路，所述至少一个栅极驱动电路的驱动方式为单边驱动、双边驱动以及交叉双边驱动中任意一种。
  7. 如权利要求6所述的显示面板，其中，所述至少一个栅极驱动电路的驱动方式为双边驱动或交叉双边驱动时，所述信号选择电路包括第一侧选择电路和第二侧选择电路，所述第一侧选择电路分别连接所述第一栅极驱动单元第一侧的栅极驱动电路和所述第二栅极驱动单元第一侧的栅极驱动电路，所述第二侧选择电路分别连接所述第一栅极驱动单元第二侧的栅极驱动电路和所述第二栅极驱动单元第二侧的栅极驱动电路。
  8. 如权利要求1至7任一所述的显示面板，其中，所述第一栅极驱动单元输出的扫描信号输入到所述信号选择电路，所述信号选择电路输出的控制信号输出到所述第二栅极驱动单元。
  9. 一种显示面板，其中，包括：
    栅极驱动模块，包括第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元被配置为接收初始触发信号，并根据所述初始触发信号输出扫描信号；
    信号选择电路，分别与所述第一栅极驱动单元、所述第二栅极驱动单元电连接，所述信号选择电路被配置为接收反转信号、所述第一栅极驱动单元输出的扫描信号以及低电平信号，并输出控制信号至所述第二栅极驱动单元，所述控制信号为所述第一栅极驱动单元输出的扫描信号或所述低电平信号；
    当所述初始触发信号为第一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述第一栅极驱动单元输出的扫描信号；当所述初始触发信号为所述第一帧画面的下一帧画面的触发信号时，基于所述反转信号，所述控制信号为所述低电平信号。
  10. 如权利要求9所述的显示面板，其中，所述显示面板还包括与所述第一栅极驱动单元电连接的第一选择电路，所述第一选择电路被配置为接收所述反转信号、所述初始触发信号以及所述低电平信号，并输出第一控制信号至所述第一栅极驱动单元，所述第一栅极驱动单元被配置为根据所述第一控制信号输出第一扫描信号，所述第一控制信号为所述初始触发信号或所述低电平信号；
    所述信号选择电路被配置为接收所述反转信号、所述第一栅极驱动单元输出的第一扫描信号以及所述初始触发信号，并输出第二控制信号至所述第二栅极驱动单元，所述第二栅极驱动单元被配置为根据所述第二控制信号输出第二扫描信号，所述第二控制信号为第一栅极驱动单元输出的扫描信号或所述初始触发信号；
    当所述第一控制信号为所述初始触发信号时，所述第二控制信号为所述第一栅极驱动单元输出的第一扫描信号；当所述第一控制信号为所述低电平信号时，所述第二控制信号为所述初始触发信号。
  11. 如权利要求10所述的显示面板，其中，所述显示面板还包括第二选择电路，所述栅极驱动模块还包括第三栅极驱动单元，所述第二选择电路分别与所述第二栅极驱动单元、所述第三栅极驱动单元电连接；
    所述第二选择电路被配置为接收所述反转信号、所述低电平信号以及所述第二栅极驱动单元输出的第二扫描信号，并输出第三控制信号至所述第三栅极驱动单元，所述第三控制信号为所述低电平信号或所述第二栅极驱动单元输出的第二扫描信号。
  12. 如权利要求11所述的显示面板，其中，当所述第一控制信号为所述初始触发信号时，所述第二控制信号为所述第一栅极驱动单元输出的第一扫描信号，所述第三控制信号为所述低电平信号；当所述第一控制信号为所述低电平信号时，所述第二控制信号为所述初始触发信号，所述第三控制信号为所述第二栅极驱动单元输出的第二扫描信号；或，
    当所述第一控制信号为所述初始触发信号时，所述第二控制信号为所述第一栅极驱动单元输出的第一扫描信号，所述第三控制信号为所述第二栅极驱动单元输出的第二扫描信号；当所述第一控制信号为所述低电平信号时，所述第二控制信号为所述初始触发信号，所述第三控制信号为所述低电平信号。
  13. 如权利要求9所述的显示面板，其中，所述显示面板还包括第三选择电路，所述栅极驱动模块还包括第四栅极驱动单元，所述第三选择电路分别与所述第一栅极驱动单元、所述第二栅极驱动单元、所述第四栅极驱动单元电连接；
    所述第三选择电路被配置为接收所述反转信号、所述第二栅极驱动单元输出的扫描信号以及所述第一栅极驱动单元输出的扫描信号，并输出第四控制信号至所述第四栅极驱动单元，所述第四控制信号为所述第二栅极驱动单元输出的扫描信号或所述第一栅极驱动单元输出的扫描信号；
    当所述初始触发信号为第一帧画面的触发信号时，所述控制信号为所述第一栅极驱动单元输出的扫描信号，所述第四控制信号为所述第二栅极驱动单元输出的扫描信号；当所述初始触发信号为所述第一帧画面的下一帧画面的触发信号时，所述控制信号为所述低电平信号，所述第四控制信号为所述第一栅极驱动单元输出的扫描信号。
  14. 如权利要求9所述的显示面板，其中，所述信号选择电路包括第一控制模块、第二控制模块以及反相模块，所述第二控制模块和所述反相模块连接，所述第一控制模块接收所述第一栅极驱动单元输出的扫描信号，所述第二控制模块接收所述低电平信号，所述第一控制模块和所述反相模块连接所述反转信号；
    当所述反转信号为高电平时，所述信号选择电路输出所述第一栅极驱动单元输出的扫描信号；当所述反转信号为低电平时，所述信号选择电路输出所述低电平信号。
  15. 如权利要求14所述的显示面板，其中，所述第一控制模块包括第一开关晶体管，所述第一开关晶体管的栅极连接所述反转信号，所述第一开关晶体管源漏极的一者连接所述第一栅极驱动单元输出的扫描信号，所述第一开关晶体管源漏极的另一者连接所述第二栅极驱动单元；
    所述反相模块的一端连接所述反转信号，所述反相模块的另一端连接所述第二控制模块；
    所述第二控制模块包括第二开关晶体管，所述第二开关晶体管的栅极连接所述反相模块的另一端，所述第二开关晶体管源漏极的一者连接所述低电平信号，所述第二开关晶体管源漏极的另一者连接所述第二栅极驱动单元。
  16. 如权利要求9所述的显示面板，其中，所述显示面板包括第一显示区和第二显示区，所述第一栅极驱动单元控制所述第一显示区内的像素行进行刷新，所述第二栅极驱动单元控制所述第二显示区内的像素行进行刷新；所述第一栅极驱动单元和所述第二栅极驱动单元均包含至少一个栅极驱动电路，所述至少一个栅极驱动电路的驱动方式为单边驱动、双边驱动以及交叉双边驱动中任意一种。
  17. 如权利要求16所述的显示面板，其中，所述至少一个栅极驱动电路的驱动方式为双边驱动或交叉双边驱动时，所述信号选择电路包括第一侧选择电路和第二侧选择电路，所述第一侧选择电路分别连接所述第一栅极驱动单元第一侧的栅极驱动电路和所述第二栅极驱动单元第一侧的栅极驱动电路，所述第二侧选择电路分别连接所述第一栅极驱动单元第二侧的栅极驱动电路和所述第二栅极驱动单元第二侧的栅极驱动电路。
  18. 如权利要求9至17任一所述的显示面板，其中，所述第一栅极驱动单元输出的扫描信号输入到所述信号选择电路，所述信号选择电路输出的控制信号输出到所述第二栅极驱动单元。
  19. 如权利要求9至17任一所述的显示面板，其中，所述反转信号包括高电平和低电平，所述反转信号在相邻两帧中一帧的电位为高电平、另一帧的电位为低电平。
  20. 一种显示装置，其中，所述显示装置包括如权利要求1至19任一所述的显示面板。
PCT/CN2024/099668 2023-11-16 2024-06-17 显示面板及显示装置 Pending WO2025102728A1 (zh)

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