WO2025035277A1 - 移位寄存器及其驱动方法、显示基板和显示装置 - Google Patents

移位寄存器及其驱动方法、显示基板和显示装置 Download PDF

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Publication number
WO2025035277A1
WO2025035277A1 PCT/CN2023/112593 CN2023112593W WO2025035277A1 WO 2025035277 A1 WO2025035277 A1 WO 2025035277A1 CN 2023112593 W CN2023112593 W CN 2023112593W WO 2025035277 A1 WO2025035277 A1 WO 2025035277A1
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Prior art keywords
transistor
electrode
electrically connected
node
terminal
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PCT/CN2023/112593
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English (en)
French (fr)
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WO2025035277A9 (zh
Inventor
徐倩
刘聪
宋江
李�赫
胡明
王梦奇
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to CN202380010109.0A priority Critical patent/CN119923683A/zh
Priority to PCT/CN2023/112593 priority patent/WO2025035277A1/zh
Priority to TW113113670A priority patent/TWI912739B/zh
Publication of WO2025035277A1 publication Critical patent/WO2025035277A1/zh
Anticipated expiration legal-status Critical
Publication of WO2025035277A9 publication Critical patent/WO2025035277A9/zh
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a shift register and a driving method thereof, a display substrate, and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT thin film transistors
  • the present disclosure provides a shift register, comprising: a cascade output subcircuit and a scan output subcircuit;
  • the cascade output subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the cascade output terminal, the first node, and the second node, respectively, and is configured to provide signals to the first node and the second node under the control of signals from the signal input terminal, the first clock signal terminal, and the second clock signal terminal, and to provide signals from the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of signals from the first node and the second node;
  • the scan output sub-circuit is electrically connected to the scan control signal terminal, the first power supply terminal, the second power supply terminal, the scan output terminal, the first node and the second node, respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals from the first node, the second node and the scan control signal terminal.
  • the scan output subcircuit includes: a first output control subcircuit and a second output control subcircuit;
  • the first output control subcircuit is electrically connected to the second power supply terminal, the scan output terminal and the second node respectively, and is configured to provide a signal of the second power supply terminal to the scan output terminal under the control of a signal of the second node;
  • the second output control subcircuit is electrically connected to the scan control signal terminal, the first power supply terminal, the scan output terminal and the first node, respectively, and is configured to provide a signal from the first power supply terminal to the scan output terminal under the control of the signal from the scan control signal terminal and the first node.
  • the scan output subcircuit further includes: a storage subcircuit;
  • the storage sub-circuit is electrically connected to the scan output terminal and the first power supply terminal respectively, and is configured to store a voltage difference between the signal at the scan output terminal and the signal at the first power supply terminal.
  • the first output control subcircuit includes: a seventeenth transistor
  • the control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal.
  • the second output control subcircuit includes: an eighteenth transistor and a nineteenth transistor;
  • the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;
  • the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the scan output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node.
  • the second output control subcircuit includes: an eighteenth transistor and a nineteenth transistor;
  • the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the scan output terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;
  • the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node.
  • the storage subcircuit includes: a fifth capacitor
  • the first electrode plate of the fifth capacitor is electrically connected to the scan output terminal, and the second electrode plate of the fifth capacitor is electrically connected to the first power supply terminal.
  • the cascade output subcircuit includes: a first transistor to a sixteenth transistor and a first capacitor to a fourth capacitor, and any capacitor of the first capacitor to the fourth capacitor includes: a first plate and a second plate;
  • the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the fourth node;
  • the control electrode of the second transistor is electrically connected to the fourth node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the fifth node;
  • a control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fifth node;
  • the control electrode of the fourth transistor is electrically connected to the sixth node, the first electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fourth transistor is electrically connected to the seventh node;
  • a control electrode of the fifth transistor is electrically connected to the fifth node, a first electrode of the fifth transistor is electrically connected to the first power supply terminal, and a second electrode of the fifth transistor is electrically connected to the seventh node;
  • the control electrode of the sixth transistor is electrically connected to the ninth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the eighth node;
  • the control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the eighth node, and the second electrode of the seventh transistor is electrically connected to the first node;
  • the control electrode of the eighth transistor is electrically connected to the fourth node, the first electrode of the eighth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighth transistor is electrically connected to the first node;
  • the control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output terminal;
  • the control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the cascade output terminal;
  • the control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the fifth node, and the second electrode of the eleventh transistor is electrically connected to the ninth node;
  • the control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the second node;
  • the control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the fourth node;
  • the control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and the second electrode of the fourteenth transistor is electrically connected to the tenth node;
  • a control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor is electrically connected to the tenth node, and a second electrode of the fifteenth transistor is electrically connected to the sixth node;
  • the control electrode of the sixteenth transistor is electrically connected to the sixth node, the first electrode of the sixteenth transistor is electrically connected to the sixth node, and the second electrode of the sixteenth transistor is electrically connected to the second node;
  • the first plate of the first capacitor is electrically connected to the ninth node, and the second plate of the first capacitor is electrically connected to the eighth node;
  • a first plate of the second capacitor is electrically connected to the first node, and a second plate of the second capacitor is electrically connected to the first power supply terminal;
  • the first plate of the third capacitor is electrically connected to the sixth node, and the second plate of the third capacitor is electrically connected to the seventh node;
  • the first plate of the fourth capacitor is electrically connected to the second power supply terminal, and the second plate of the fourth capacitor is electrically connected to the cascade output terminal.
  • the scan output subcircuit includes: a seventeenth transistor to a nineteenth transistor, or includes: a seventeenth transistor to a nineteenth transistor and a fifth capacitor;
  • the control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal;
  • the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;
  • the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the scan output terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node;
  • the first electrode plate of the fifth capacitor is electrically connected to the scan output terminal, and the second electrode plate of the fifth capacitor is electrically connected to the first power supply terminal.
  • the scan output subcircuit includes: a seventeenth transistor to a nineteenth transistor, or includes: a seventeenth transistor to a nineteenth transistor and a fifth capacitor;
  • the control electrode of the seventeenth transistor is electrically connected to the second node, the first electrode of the seventeenth transistor is electrically connected to the second power supply terminal, and the second electrode of the seventeenth transistor is electrically connected to the scan output terminal;
  • the control electrode of the eighteenth transistor is electrically connected to the first node, the first electrode of the eighteenth transistor is electrically connected to the scan output terminal, and the second electrode of the eighteenth transistor is electrically connected to the third node;
  • the control electrode of the nineteenth transistor is electrically connected to the scan control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the nineteenth transistor is electrically connected to the third node;
  • the first electrode plate of the fifth capacitor is electrically connected to the scan output terminal, and the second electrode plate of the fifth capacitor is electrically connected to the first power supply terminal.
  • the present disclosure further provides a display substrate, comprising: a gate driving circuit located in the non-display area and array-arranged sub-pixels and a plurality of gate lines located in the display area, the sub-pixels comprising a pixel driving circuit and a light-emitting device, the gate lines at least partially extending along a first direction, the gate driving circuit comprising: a plurality of cascaded shift registers, the pixel driving circuit comprising: a plurality of transistors;
  • the cascade output terminal of at least one stage of the shift register is electrically connected to the signal input terminal of at least one stage of the shift register.
  • the gate line is electrically connected to the gate electrode of the at least one transistor, and any shift register is electrically connected to at least one gate line.
  • the display area is divided into a plurality of display sub-areas, at least one display sub-area includes: at least one gate line; the display mode of any display sub-area includes: a first display mode and a second display mode, the refresh frequency of the first display mode is greater than the refresh frequency of the second display mode;
  • the display mode of the display sub-area is the first display mode
  • the signal at the cascade output end is a first level signal
  • at least part of the time period of the signal at the scan control signal end is a valid level signal
  • the signal at the scan output end is a first level signal
  • the display mode of the display sub-area is the second display mode
  • the signal at the cascade output end is a first level signal
  • the signal at the scan control signal end is an invalid level signal
  • the signal at the scan output end is a second level signal
  • the voltage value of the first level signal is greater than the voltage value of the second level signal.
  • the invention further comprises: at least one scan control signal line located in the non-display area, the scan control signal line at least partially extending along a second direction, the first direction and the second direction intersecting;
  • the scanning control signal terminals connected to all the shift registers are electrically connected to the at least one scanning control signal line.
  • the number of the scanning control signal line is one
  • the scanning control signal terminals connected to all the shift registers are electrically connected to the same scanning control signal line.
  • the number of the scan control signal lines is at least two;
  • the scanning control signal end connected to any shift register from the M*(k-1)+K*M(a-1)+1th shift register to the k*M+K*M(a-1)th shift register is electrically connected to the kth scanning control signal line, 1 ⁇ k ⁇ K, 1 ⁇ a ⁇ N/M, M is the number of shift registers connected to a scanning control signal line, N is the total number of shift registers, and K is the number of scanning control signal lines.
  • L is the number of gate lines connected to any stage of shift register
  • h is the unit time, which is equal to the refresh interval time of adjacent rows of sub-pixels.
  • the invention further comprises: a first clock signal line, a second clock signal line, a first power line, a second power line and a third power line located in the non-display area; any one of the first clock signal line, the second clock signal line, the first power line, the second power line and the third power line at least partially extending along the second direction;
  • the first clock signal terminal connected to any stage of the shift register is electrically connected to one of the first clock signal line and the second clock signal line
  • the second clock signal terminal connected to any stage of the shift register is electrically connected to the other of the first clock signal line and the second clock signal line
  • the clock signal lines connected to the first clock signal terminals connected to adjacent shift registers are different
  • the clock signal lines connected to the second clock signal terminals connected to adjacent shift registers are different
  • the first power supply terminals connected to all the shift registers are electrically connected to the first power supply line
  • the second power supply terminals connected to all the shift registers are electrically connected to the second power supply line
  • the third power supply terminals connected to all the shift registers are electrically connected to the third power supply line.
  • the scan control signal line is located on a side of any one of the first clock signal line, the second clock signal line, the first power line, the second power line, and the third power line close to the display area.
  • the number of the second power lines is two, and the first clock signal line, the second clock signal line, the first second power line, the third power line, the second second power line and the first power line are arranged in sequence in a direction close to the display area.
  • the shift register includes: a seventeenth transistor to a nineteenth transistor; the seventeenth transistor to the nineteenth transistor are arranged along the second direction;
  • At least a portion of any one of the seventeenth to nineteenth transistors is located between the first power line and the scan control signal line.
  • any one of the transistors includes an active pattern, and an average length of the active pattern of the seventeenth transistor along the first direction is smaller than an average length of the active pattern of any one of the eighteenth transistor and the nineteenth transistor along the first direction.
  • a line width of any one of the first power line and the second power line is greater than a line width of the scan control signal line.
  • the present disclosure further provides a display device, comprising: the above-mentioned display substrate.
  • the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, and the method comprises:
  • the cascade output subcircuit provides signals to the first node and the second node under the control of signals at the signal input terminal, the first clock signal terminal and the second clock signal terminal, and provides signals at the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of signals at the first node and the second node;
  • the scan output subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals from the first node, the second node and the scan control signal terminal.
  • FIG1 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of the structure of a shift register provided by an exemplary embodiment
  • FIG3 is a schematic diagram of the structure of a shift register provided by an exemplary embodiment
  • FIG4 is an equivalent circuit diagram of a first output control subcircuit provided in an exemplary embodiment
  • FIG5 is an equivalent circuit diagram of a second output control subcircuit provided in an exemplary embodiment
  • FIG6 is an equivalent circuit diagram of a second output control subcircuit provided in another exemplary embodiment
  • FIG. 7 is an equivalent circuit diagram of a storage sub-circuit provided in an exemplary embodiment
  • FIG8 is an equivalent circuit diagram of a cascade output subcircuit provided in an exemplary embodiment
  • FIG9 is an equivalent circuit diagram 1 of a shift register
  • FIG10 is a second equivalent circuit diagram of a shift register
  • FIG11 is a third equivalent circuit diagram of a shift register
  • FIG12 is a fourth equivalent circuit diagram of a shift register
  • FIG13 is a timing diagram of the cascade output subcircuit in the shift register provided in FIGS. 9 to 12 ;
  • FIG14 is a timing diagram 1 of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;
  • FIG15 is a second timing diagram of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;
  • FIG16 is a third timing diagram of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;
  • FIG17 is a fourth timing diagram of the scan output subcircuit in the shift register provided in FIGS. 9 to 12 ;
  • FIG18 is a schematic structural diagram of a display substrate
  • FIG19 is a cascade schematic diagram 1 of a gate drive circuit
  • FIG20 is a second cascade schematic diagram of a gate drive circuit
  • FIG21 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG22 is a schematic diagram of an equivalent circuit of another pixel driving circuit
  • FIG23 is a working timing diagram of the pixel driving circuit provided in FIG21 and FIG22;
  • FIG24 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in FIG19;
  • FIG25 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in FIG20;
  • FIG26 is a partial schematic diagram of a non-display area of a display substrate
  • FIG27 is a schematic diagram of active patterns of seventeenth to nineteenth transistors.
  • FIG28 is a schematic diagram of FIG26 after a semiconductor layer pattern is formed
  • FIG29 is a schematic diagram of a first conductive layer pattern in FIG26 ;
  • FIG30 is a schematic diagram of FIG26 after the first conductive layer pattern is formed
  • FIG31 is a schematic diagram of a second conductive layer pattern in FIG26 ;
  • FIG32 is a schematic diagram of FIG26 after forming a second conductive layer pattern
  • FIG33 is a schematic diagram of FIG26 after forming a third insulating layer pattern
  • FIG34 is a schematic diagram of a third conductive layer pattern in FIG26.
  • FIG35 is a schematic diagram of FIG26 after forming a third conductive layer pattern
  • FIG36 is a schematic diagram of FIG26 after forming a fourth insulating layer pattern
  • FIG37 is a schematic diagram of a fourth conductive layer pattern in FIG26.
  • FIG. 38 is a schematic diagram of FIG. 26 after the fourth conductive layer pattern is formed.
  • the proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to a region where current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in this specification, the "source electrode” and the “drain electrode” may be interchanged.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the “element having some electrical function” as long as it can transmit and receive electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced by “conductive film”.
  • insulating film may be replaced by “insulating layer”.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • the display substrate includes: a pixel circuit, a light emitting device and a gate driving circuit, wherein the gate driving circuit is configured to provide a gate signal to the pixel circuit so that the pixel circuit can drive the light emitting device to emit light.
  • the driving capability of the gate driving circuit is relatively weak and cannot meet the display requirements.
  • LTPS low-temperature polysilicon
  • advantages such as high resolution, high response speed, high brightness, and high aperture ratio.
  • LTPS technology also has some defects, such as high production cost and high power consumption.
  • low-temperature polycrystalline oxide (LTPO) technology came into being.
  • LTPO technology Compared with LTPS technology, LTPO technology has smaller leakage current and faster pixel response.
  • the display substrate has an additional layer of oxide, which reduces the energy consumption required to excite the pixels, thereby reducing the power consumption when the screen is displayed.
  • the display product includes: a gate drive circuit and multiple sub-pixels.
  • the sub-pixels include a pixel drive circuit.
  • the gate drive circuit When the display product displays a picture, the gate drive circuit generates a drive signal, and the pixel drive circuit is initialized and data is written under the control of the drive signal to achieve display.
  • the display product displays it will refresh the surface in each frame, that is, the pixel drive circuit needs to be initialized and data written in each display frame.
  • the pixel drive circuit does not need to be initialized and data written in at least some display frames, and the original brightness can be maintained by a low-leakage pixel drive circuit.
  • a gate drive circuit of a display product generates a drive signal in each frame regardless of the picture displayed, and repeatedly initializes and writes data to the pixel drive circuit, which makes the power consumption of the display product higher.
  • Fig. 1 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure.
  • the shift register provided by an embodiment of the present disclosure may include: a cascade output subcircuit and a scan output subcircuit.
  • the cascade output sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the cascade output terminal COUT, the first node N1 and the second node N2, and is configured to provide signals to the first node N1 and the second node N2 under the control of the signals of the signal input terminal IN, the first clock signal terminal CK1 and the second clock signal terminal CK2, and to provide the signal of the first power supply terminal V1 or the second power supply terminal V2 to the cascade output terminal COUT under the control of the signals of the first node N1 and the second node N2;
  • the scan output sub-circuit is electrically connected to the scan control signal terminal MS, the first power supply terminal V1, the second power supply terminal V2, the scan output terminal NOUT, the first node N1 and the second node N2, and is configured to provide the signal of the first power supply terminal V1 or the second power supply terminal V2 to the scan output
  • the signal at the signal input terminal IN is a single pulse signal.
  • the signal of any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 may be a square wave signal that repeats a high voltage and a low voltage.
  • the signal of the first clock signal terminal CK1 and the second clock signal terminal CK2 may have the same period and may be configured as a phase-shifted signal.
  • the signal of the second clock signal terminal CK2 may be phase-shifted by half a period compared to the signal of the first clock signal terminal CK1.
  • the high voltage period of the signal of any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 in each period may be set to be longer than the low voltage period.
  • the high voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the low voltage period of the signal of the second clock signal terminal CK2, and the low voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the high voltage period of the signal of the second clock signal terminal CK2.
  • the signal of the first power terminal V1 is a constant voltage signal, and is a high level signal.
  • the signal of the second power supply terminal V2 is a constant voltage signal, and is a low level signal.
  • the signal at the scan control signal end when the display product displays a normal picture, in any display frame, the signal at the scan control signal end is a valid level signal when the signal at the cascade output end is a first level signal, so that the signal at the first power supply end V1 is written to the scan output end NOUT, and when the display product displays a special picture, in some display frames, the signal at the scan control signal end is an invalid level signal when the signal at the cascade output end is a first level signal, so that the signal at the second power supply end V2 is written to the scan output end NOUT.
  • the first level signal may be a high level signal, signal A being a valid level signal means that signal A can turn on the transistor connected to signal A, and signal A being an invalid level signal means that signal A can turn off the transistor connected to signal A.
  • the scan output subcircuit provided in the embodiment of the present disclosure can control the output within a display frame, and can also control the partial screen refresh of different display frames, thereby reducing the power consumption of the display product.
  • the shift register provided in the embodiment of the present disclosure is electrically connected to the scan control signal terminal through the scan output subcircuit, and can control whether to provide a drive signal to the scan output terminal through the scan control signal terminal.
  • the drive signal can be output in each display frame, and the pixel drive circuit can be repeatedly initialized and data written to ensure normal display.
  • the drive signal can be not output in some display frames, thereby reducing the number of times the pixel drive circuit is initialized and data is written, thereby reducing the power consumption of the display product and realizing low-power display of the display product.
  • Fig. 2 is a schematic diagram of the structure of a shift register provided in an exemplary embodiment.
  • the scan output subcircuit may include: a first output control subcircuit and a second output control subcircuit.
  • the first output control sub-circuit is electrically connected to the second power supply terminal V2, the scan output terminal NOUT and the second node N2, respectively, and is configured to provide a signal from the second power supply terminal V2 to the scan output terminal NOUT under the control of the signal from the second node N2;
  • the second output control sub-circuit is electrically connected to the scan control signal terminal MS, the first power supply terminal V1, the scan output terminal NOUT and the first node N1, respectively, and is configured to provide a signal from the first power supply terminal V1 to the scan output terminal NOUT under the control of the signal from the scan control signal terminal MS and the first node N1.
  • FIG3 is a schematic diagram of the structure of a shift register provided in an exemplary embodiment.
  • the scan output subcircuit may further include: a storage subcircuit.
  • the storage subcircuit is electrically connected to the scan output terminal NOUT and the first power supply terminal V1, respectively, and is configured to store the voltage difference between the signal of the scan output terminal NOUT and the first power supply terminal V1.
  • Fig. 4 is an equivalent circuit diagram of a first output control subcircuit provided in an exemplary embodiment. As shown in Fig. 4, in an exemplary embodiment, the first output control subcircuit may include: a seventeenth transistor T17.
  • a control electrode of the seventeenth transistor T17 is electrically connected to the second node N2
  • a first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal V2
  • a second electrode of the seventeenth transistor T17 is electrically connected to the scan output terminal NOUT.
  • FIG4 only shows an exemplary structure of the first output control subcircuit. It is easy for those skilled in the art to understand that the implementation of the first output control subcircuit is not limited thereto.
  • Fig. 5 is an equivalent circuit diagram of a second output control subcircuit provided in an exemplary embodiment
  • Fig. 6 is an equivalent circuit diagram of a second output control subcircuit provided in another exemplary embodiment.
  • the second output control subcircuit may include: an eighteenth transistor T18 and a nineteenth transistor T19.
  • control electrode of the eighteenth transistor T18 is electrically connected to the first node N1
  • the first electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1
  • the second electrode of the eighteenth transistor T18 is electrically connected to the third node N3
  • the control electrode of the nineteenth transistor T19 is electrically connected to the scan control signal terminal MS
  • the first electrode of the nineteenth transistor T19 is electrically connected to the scan output terminal NOUT
  • the second electrode of the nineteenth transistor T19 is electrically connected to the third node N3.
  • control electrode of the eighteenth transistor T18 is electrically connected to the first node N1
  • the first electrode of the eighteenth transistor T18 is electrically connected to the scan output terminal NOUT
  • the second electrode of the eighteenth transistor T18 is electrically connected to the third node N3
  • the control electrode of the nineteenth transistor T19 is electrically connected to the scan control signal terminal MS
  • the first electrode of the nineteenth transistor T19 is electrically connected to the first power supply terminal V1
  • the second electrode of the nineteenth transistor T19 is electrically connected to the third node N3.
  • FIG. 5 and FIG. 6 only show two exemplary structures of the second output control subcircuit. It is easy for those skilled in the art to understand that the implementation of the second output control subcircuit is not limited thereto.
  • FIG. 7 is an equivalent circuit diagram of a storage sub-circuit provided in an exemplary embodiment. As shown in FIG. 7 , in an exemplary embodiment, the storage sub-circuit may include: a fifth capacitor C5 .
  • the first plate C51 of the fifth capacitor C5 is electrically connected to the scan output terminal NOUT, and the second plate C52 of the fifth capacitor C5 is electrically connected to the first power supply terminal V1 .
  • the configuration of the storage sub-circuit can ensure the stability of the output signal of the scan output terminal NOUT and improve the reliability of the shift register.
  • FIG. 7 only shows an exemplary structure of a storage sub-circuit. Those skilled in the art will readily appreciate that the implementation of the storage sub-circuit is not limited thereto.
  • the cascade output sub-circuit may be a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C or 16T4C, which is not limited in the present disclosure.
  • the scan output subcircuit provided in the embodiment of the present disclosure includes only three transistors, has a simple structure, is conducive to the layout of the odor register, can also reduce the area occupied by the shift register, and can achieve a narrow frame.
  • FIG8 is an equivalent circuit diagram of a cascade output subcircuit provided in an exemplary embodiment.
  • FIG8 is illustrated by taking 16T4C as an example.
  • the cascade output subcircuit may include: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4, and any capacitor of the first capacitor C1 to the fourth capacitor C4 includes: a first plate and a second plate.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4;
  • the control electrode of the second transistor T2 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5;
  • the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the fifth node N5;
  • the control electrode of the fourth transistor T4 is electrically connected to the sixth node N6, the first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically
  • the second electrode of T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the second electrode of the sixth transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh transistor T7 is electrically connected to the eighth node N8, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the fourth node N4, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and the second
  • the cascade output sub-circuit when the cascade output sub-circuit is a circuit structure of 10T3C, the cascade output sub-circuit includes: first to tenth transistors T1 to T10 and first to third capacitors C1 to C3.
  • the cascade output sub-circuit when the cascade output sub-circuit is a circuit structure of 10T4C, the cascade output sub-circuit includes: first to tenth transistors T1 to T10 and first to fourth capacitors C1 to C4.
  • the cascade output sub-circuit when the cascade output sub-circuit is a 12T3C circuit structure, the cascade output sub-circuit includes: first to twelfth transistors T1 to T12 and first to third capacitors C1 to C3.
  • the cascade output sub-circuit when the cascade output sub-circuit is a 12T3C circuit structure, the cascade output sub-circuit includes: first to twelfth transistors T1 to T12 and first to fourth capacitors C1 to C4.
  • the cascade output sub-circuit when the cascade output sub-circuit is a circuit structure of 13T3C, the cascade output sub-circuit includes: first to thirteenth transistors T1 to T13 and first to third capacitors C1 to C3.
  • the cascade output sub-circuit when the cascade output sub-circuit is a circuit structure of 13T4C, the cascade output sub-circuit includes: first to thirteenth transistors T1 to T13 and first to fourth capacitors C1 to C4.
  • the cascade output sub-circuit when the cascade output sub-circuit is a 16T3C circuit structure, the cascade output sub-circuit includes: first to sixteenth transistors T1 to T16 and first to third capacitors C1 to C3.
  • FIG9 is an equivalent circuit diagram 1 of a shift register
  • FIG10 is an equivalent circuit diagram 2 of a shift register
  • the cascade output subcircuit may include: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4, any capacitor of the first capacitor C1 to the fourth capacitor C4 includes: a first plate and a second plate
  • the scan output subcircuit includes: a seventeenth transistor T17 to a nineteenth transistor T19, or includes: a seventeenth transistor to a nineteenth transistor T19 and a fifth capacitor C5.
  • FIG9 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19
  • FIG10 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19 and the fifth capacitor C5.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4;
  • the control electrode of the second transistor T2 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5;
  • the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the third transistor T4 is electrically connected to the fourth node N4.
  • the second electrode of the transistor T3 is electrically connected to the fifth node N5; the control electrode of the fourth transistor T4 is electrically connected to the sixth node N6, the first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the seventh node N7; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the sixth The second electrode of the transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh transistor T7 is electrically connected to the eighth node N
  • the first electrode of the fifteenth transistor T15 is electrically connected to the tenth node N10, and the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, the first electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, and the second electrode of the sixteenth transistor T16 is electrically connected to the second node N2; the first electrode plate C11 of the first capacitor C1 is electrically connected to the ninth node N9; the control electrode of the seventeenth transistor T17 is electrically connected to the second node N2, the first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal V2, and the tenth The second electrode of the seventh transistor T17 is electrically connected to the scan output terminal NOUT; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1, and the
  • FIG11 is a third equivalent circuit diagram of a shift register
  • FIG12 is a fourth equivalent circuit diagram of a shift register.
  • the cascade output subcircuit may include: a first transistor T1 to a sixteenth transistor T16 and a first capacitor C1 to a fourth capacitor C4, any capacitor of the first capacitor C1 to the fourth capacitor C4 includes: a first plate and a second plate, and the scan output subcircuit includes: a seventeenth transistor T17 to a nineteenth transistor T19, or includes: a seventeenth transistor T17 to a nineteenth transistor T19 and a fifth capacitor C5.
  • FIG11 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19
  • FIG12 is explained by taking the example that the scan output subcircuit includes: the seventeenth transistor T17 to the nineteenth transistor T19 and the fifth capacitor C5.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4;
  • the control electrode of the second transistor T2 is electrically connected to the fourth node N4, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the fifth node N5;
  • the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the third transistor T4 is electrically connected to the fourth node N5.
  • the second electrode of the transistor T3 is electrically connected to the fifth node N5; the control electrode of the fourth transistor T4 is electrically connected to the sixth node N6, the first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fourth transistor T4 is electrically connected to the seventh node N7; the control electrode of the fifth transistor T5 is electrically connected to the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the ninth node N9, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and the sixth The second electrode of the transistor T6 is electrically connected to the eighth node N8; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh transistor T7 is electrically connected to the eighth node N
  • the first electrode of the fifteenth transistor T15 is electrically connected to the tenth node N10, and the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, the first electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, and the second electrode of the sixteenth transistor T16 is electrically connected to the second node N2; the first electrode plate C11 of the first capacitor C1 is electrically connected to the ninth node N9; the control electrode of the seventeenth transistor T17 is electrically connected to the second node N2, the first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal V2, and the tenth The second electrode of the seventh transistor T17 is electrically connected to the scan output terminal NOUT; the control electrode of the eighteenth transistor T18 is electrically connected to the first node N1, the first electrode of the eighteenth transistor T18 is electrically connected to the scan output terminal NOUT, and the
  • any capacitor among the first capacitor C1 to the fifth capacitor C5 can be a capacitor device made by a process, for example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc.
  • any capacitor among the first capacitor C1 to the fifth capacitor C5 can be a parasitic capacitor between multiple devices, which can be realized by the transistor itself and other devices and circuits.
  • the connection method of any capacitor among the first capacitor C1 to the fifth capacitor C5 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored.
  • the exemplary embodiment of the present disclosure does not limit this.
  • FIG. 9 to FIG. 12 are explained by taking the circuit structure in which the cascade output sub-circuit is 16T4C as an example.
  • the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).
  • the first transistor T1 to the nineteenth transistor T19 may be P-type transistors.
  • the first transistor T1 to the nineteenth transistor T19 may be P-type transistors to simplify the manufacturing process of the shift register.
  • the first power terminal V1 continuously provides a high level signal
  • the second power terminal V2 continuously provides a low level signal. Since the second power terminal V2 continuously provides a low level signal, the eleventh transistor T11, the twelfth transistor T12, and the fifteenth transistor T15 are continuously turned on.
  • the third power supply terminal V3 is a low level signal in the power-on initialization stage to prevent the ninth transistor T9 and the tenth transistor T10 of the last stage control shift register from being turned on at the same time due to the delay of the output signal, or is a low level signal in the abnormal shutdown stage to prevent the ninth transistor T9 and the tenth transistor T10 from being turned on at the same time.
  • the third power supply terminal V3 continuously provides a high level signal in the normal display stage, that is, in the normal display stage, the thirteenth transistor T13 is turned off.
  • FIG13 is a timing diagram of the cascade output subcircuit in the shift register provided in FIG9 to FIG12.
  • FIG13 takes the first transistor T1 to the sixteenth transistor T16 as an example of P-type transistors.
  • the operation process of the cascade output subcircuit provided in an exemplary embodiment may include the following stages:
  • the signals of the signal input terminal IN and the second clock signal terminal CK2 are high-level signals, and the signal of the first clock signal terminal CK1 is a low-level signal.
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the first transistor T1, the third transistor T3 and the twelfth transistor T12 are turned on, the turned-on first transistor T1 transmits the high-level signal of the signal input terminal IN to the fourth node N4, the signal of the fourth node N4 is a high-level signal, the turned-on twelfth transistor T12 transmits the high-level signal of the fourth node N4 to the second node N2,
  • the turned-on fourteenth transistor T14 transmits the high-level signal of the signal input terminal IN to the tenth node N10, the signal of the tenth node N10 is a high-level signal, the turned-on fifteenth transistor T15 transmits the high-level signal of the tenth node N10 to the sixth node N6, and the
  • the turned-on third transistor T3 transmits the low-level signal of the second power supply terminal V2 to the fifth node N5, and the signal of the fifth node N5 is a low-level signal.
  • the turned-on eleventh transistor T11 transmits the low-level signal of the fifth node N5 to the ninth node N9, and the signal of the ninth node N9 is a low-level signal.
  • the fifth transistor T5 and the sixth transistor T6 are turned on. Although the signal of the second clock signal terminal CK2 is a high-level signal, since the seventh transistor T7 is disconnected, the signal of the first node N1 will not be pulled up and remain as a low-level signal.
  • the ninth transistor T9 is disconnected, and the signal of the cascade output terminal COUT maintains the previous low level.
  • the first node N1 is a low-level signal
  • the second node N2 is a high-level signal
  • the signal of the cascade output terminal COUT maintains the previous low-level signal.
  • the signal of the second clock signal terminal CK2 is a low level signal, and the signals of the signal input terminal IN and the first clock signal terminal CK1 are high level signals.
  • the signal of the second clock signal terminal CK2 is a low level signal, and the seventh transistor T7 is turned on.
  • the signal of the first clock signal terminal CK1 is a high level signal, and the first transistor T1 and the third transistor T3 are turned off.
  • the third capacitor C3, the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10 can continue to maintain the high level signal of the previous stage.
  • the fifth node N5 and the ninth node N9 can continue to maintain the low level signal of the previous stage, so the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are turned off.
  • the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7
  • the ninth transistor T9 is turned on
  • the high-level signal of the first power supply terminal V1 is transmitted to the cascade output terminal COUT through the turned-on ninth transistor T9. Therefore, in this stage, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the cascade output terminal COUT is a high-level signal.
  • the signal at the first clock signal terminal CK1 is a low-level signal
  • the signals at the signal input terminal IN and the second clock signal terminal CK2 are high-level signals.
  • the signal at the second clock signal terminal CK2 is a high-level signal
  • the seventh transistor T7 is turned off, and under the action of the second capacitor C2, the first node N1 maintains a low-level signal in the previous stage, the ninth transistor T is continuously turned on, and the high-level signal at the first power supply terminal V1 is transmitted to the cascade output terminal COUT through the turned-on ninth transistor T9.
  • the signal of the first clock signal terminal CK1 is a low-level signal
  • the first transistor T1, the third transistor T3 and the twelfth transistor T12 are turned on
  • the turned-on first transistor T1 transmits the high-level signal of the signal input terminal IN to the fourth node N4
  • the signal of the fourth node N4 is a high-level signal
  • the turned-on twelfth transistor T12 transmits the high-level signal of the fourth node N4 to the second node N2
  • the turned-on fourteenth transistor T14 transmits the high-level signal of the signal input terminal IN to the tenth node N10
  • the signal of the tenth node N10 is a high-level signal
  • the turned-on fifteenth transistor T15 transmits the high-level signal of the tenth node N10 to the sixth node N6, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10 and the sixteenth transistor T16 are disconnected.
  • the turned-on third transistor T3 transmits the low-level signal of the second power supply terminal V2 to the fifth node N5, and the signal of the fifth node N5 is a low-level signal.
  • the turned-on eleventh transistor T11 transmits the low-level signal of the fifth node N5 to the ninth node N9, and the signal of the ninth node N9 is a low-level signal.
  • the fifth transistor T5 and the sixth transistor T6 are turned on. In this stage, the first node N1 is a low-level signal, the second node N2 is a high-level signal, and the signal of the cascade output terminal COUT is a high-level signal.
  • the signals of the signal input terminal IN and the second clock signal terminal CK2 are low-level signals, and the signal of the first clock signal terminal CK1 is a high-level signal.
  • the signal of the first clock signal terminal CK1 is a high-level signal, and the first transistor T1 and the third transistor T3 are disconnected.
  • the signal of the second clock signal terminal CK2 is a low-level signal, and the seventh transistor T7 is turned on. Due to the storage function of the third capacitor C3, the signals of the fourth node N4, the second node N2, the sixth node N6 and the tenth node N10 maintain the high-level signals of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are disconnected.
  • the ninth node N9 continues to maintain the low-level signal of the previous stage, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the low-level signal of the second clock signal terminal CK2 is transmitted to the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, and the high-level signal of the first power supply terminal V1 is transmitted to the cascade output terminal COUT through the turned-on ninth transistor T9, and the signal of the cascade output terminal COUT is still a high-level signal.
  • the first node N1 is a high level signal
  • the second node N2 is a low level signal
  • the cascade output terminal COUT is a high level signal.
  • the signal of the second clock signal terminal CK2 is a high level signal, and the signals of the signal input terminal IN and the first clock signal terminal CK1 are low level signals.
  • the signal of the first clock signal terminal CK1 is a low level signal, and the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on.
  • the signal of the second clock signal terminal CK2 is a high level signal, and the seventh transistor T7 is turned off.
  • the turned-on first transistor T1 transmits the low level signal of the signal input terminal IN to the fourth node N4, and the signal of the fourth node N4 is a low level signal.
  • the turned-on twelfth transistor T12 transmits the low level signal of the fourth node N4 to the first node N1, and the signal of the first node N1 becomes a low level signal.
  • the turned-on fourteenth transistor T14 transmits the low level signal of the signal input terminal IN to the tenth node N10, and the signal of the tenth node N10 is a low level signal.
  • the turned-on fifteenth transistor T15 transmits the low level signal of the tenth node N10 to the sixth node N6, and the signal of the sixth node N6 is a low level signal.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are turned on.
  • the turned-on second transistor T2 transmits the low-level signal of the first clock signal terminal CK1 to the fifth node N5, so that the fifth node N5 is a low-level signal, so the fifth node N5 and the ninth node N9 continue to maintain the low-level signal of the previous stage, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the signal of the second clock signal terminal CK2 is a high-level signal, and the seventh transistor T7 is turned off.
  • the high-level signal of the first power supply terminal V1 is transmitted to the first node N1 through the turned-on eighth transistor T8, and the ninth transistor T9 is turned off.
  • the low-level signal of the second power supply terminal V2 is transmitted to the cascade output terminal COUT through the turned-on tenth transistor T10, and the signal of the cascade output terminal COUT becomes a low-level signal.
  • the first node N1 is a high-level signal
  • the second node N2 is a low-level signal
  • the cascade output terminal COUT is a low-level signal.
  • Fig. 14 is a timing diagram 1 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12
  • Fig. 15 is a timing diagram 2 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12
  • Fig. 16 is a timing diagram 3 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12,
  • Fig. 17 is a timing diagram 4 of the scan output subcircuit in the shift register provided in Fig. 9 to Fig. 12.
  • Fig. 14 to Fig. 17 are explained by taking the seventeenth transistor T17 to the nineteenth transistor T19 as P-type transistors as an example.
  • the first node N1 is a low-level signal
  • the second node N2 is a high-level signal
  • the seventeenth transistor T17 is disconnected.
  • the first node N1 is a low-level signal
  • the eighteenth transistor T18 is turned on, at least part of the time period of the scan control signal terminal MS is a low-level signal
  • the nineteenth transistor T19 is turned on, and the first power supply terminal V1 is transmitted to the scan output terminal NOUT through the turned-on eighteenth transistor T18 and the nineteenth transistor T19, and the signal of the scan output terminal NOUT is a high-level signal.
  • the first node N1 is a high-level signal
  • the second node N2 is a low-level signal.
  • the first node N1 is a high-level signal
  • the eighteenth transistor T18 is disconnected, and the high-level signal of the first power supply terminal V1 cannot be transmitted to the scan output terminal NOUT.
  • the second node N2 is a low-level signal
  • the seventeenth transistor T17 is turned on, and the low-level signal of the second power supply terminal V2 is transmitted to the scan output terminal NOUT, and the signal of the scan output terminal NOUT is a low-level signal.
  • the signal at the cascade output terminal COUT is a high level signal
  • the signal at the scan output terminal NOUT is a high level signal
  • the signal at the scan output terminal NOUT is a low level signal
  • the signal at the scan output terminal NOUT is a low level signal, that is, the signal at the cascade output terminal COUT and the signal at the scan output terminal NOUT are consistent, so that normal display of the display product can be achieved.
  • Figures 16 and 17 are explained by taking the display product displaying a special screen as an example.
  • the signal at the scanning control signal terminal MS is a high level signal when the signal at the cascade output terminal is a high level signal.
  • the first node N1 is a low level signal
  • the second node N2 is a high level signal
  • the seventeenth transistor T17 is disconnected.
  • the first node N1 is a low level signal
  • the eighteenth transistor T18 is turned on
  • the signal of the scan control signal terminal MS is a high level signal
  • the nineteenth transistor T19 is disconnected
  • the first power supply terminal V1 cannot be written to the scan output terminal NOUT
  • the scan output terminal NOUT maintains a low level signal.
  • the first node N1 is a high-level signal
  • the second node N2 is a low-level signal.
  • the first node N1 is a high-level signal
  • the eighteenth transistor T18 is disconnected
  • the signal of the scan control signal terminal MS is a high-level signal
  • the nineteenth transistor T19 is disconnected
  • the high-level signal of the first power supply terminal V1 cannot be transmitted to the scan output terminal NOUT.
  • the second node N2 is a low-level signal
  • the seventeenth transistor T17 is turned on, the low-level signal of the second power supply terminal V2 is transmitted to the scan output terminal NOUT, and the signal of the scan output terminal NOUT is a low-level signal.
  • the embodiment of the present disclosure further provides a shift register driving method, which is configured to drive the shift register.
  • the shift register driving method may include:
  • Step 100 the cascade output subcircuit provides signals to the first node and the second node under the control of signals at the signal input terminal, the first clock signal terminal and the second clock signal terminal, and provides signals at the first power supply terminal or the second power supply terminal to the cascade output terminal under the control of signals at the first node and the second node.
  • Step 200 The scan output sub-circuit provides a signal from the first power supply terminal or the second power supply terminal to the scan output terminal under the control of the signals from the first node, the second node and the scan control signal terminal.
  • FIG18 is a schematic diagram of the structure of a display substrate
  • FIG19 is a cascade schematic diagram 1 of a gate drive circuit
  • FIG20 is a cascade schematic diagram 2 of a gate drive circuit.
  • the display substrate has a display area AA and a non-display area AA'
  • the display substrate may include: a gate drive circuit located in the non-display area AA' and an array-arranged sub-pixel and a plurality of gate lines GL located in the display area AA
  • the sub-pixel includes: a pixel drive circuit P and a light-emitting device.
  • the gate line GL at least partially extends along the first direction D1
  • the gate drive circuit includes: a plurality of cascaded shift registers
  • the pixel drive circuit includes: a plurality of transistors.
  • the cascade output terminal of at least one shift register is electrically connected to the signal input terminal of at least one shift register
  • the gate line is electrically connected to the gate electrode of at least one transistor
  • any shift register is electrically connected to at least one gate line.
  • NScan(i) in FIG. 19 and FIG. 20 is the cascade output subcircuit of the i-th stage shift register
  • NGate(i) is the scan output subcircuit of the i-th stage shift register
  • NOUT(i) is the scan output terminal of the i-th stage shift register.
  • the shift register may be the shift register provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be described in detail here.
  • the display substrate may further include a timing controller and a data driving circuit located in the non-display area AA' and a plurality of data lines DL located in the display area AA, the data lines DL extending along the second direction D2, and the first direction D1 and the second direction D2 intersecting.
  • the pixel driving circuit is also electrically connected to the data lines DL.
  • the timing controller is respectively connected to the data driving circuit and the gate driving circuit, the data driving circuit is respectively connected to the plurality of data lines DL, and the gate driving circuit is respectively connected to the plurality of gate lines GL.
  • the display substrate also includes: light-emitting devices arranged in an array in the display area, the pixel driving circuit is configured to drive the light-emitting devices to emit light, and the pixel driving circuit and the light-emitting devices driven by the pixel driving circuit constitute sub-pixels.
  • the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driving circuit to the data driving circuit, and may provide a clock signal, a start signal, etc. suitable for the specifications of the gate driving circuit to the gate driving circuit.
  • the data driving circuit may generate a data voltage to be provided to the data DL using the grayscale value and the control signal received from the timing controller. For example, the data driving circuit may sample the grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data line DL in units of pixel rows.
  • the gate driving circuit may generate a scan signal to be provided to the gate line by receiving a clock signal, a start signal, etc. from the timing controller. For example, the gate driving circuit may sequentially provide a scan signal with a conduction level pulse to the gate line GL.
  • the display substrate may include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light, and the first sub-pixel, the second sub-pixel, and the third sub-pixel each include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the data line and the gate line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data line under the control of the gate line and output a corresponding current to the light-emitting device.
  • the light-emitting devices in the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.
  • the first sub-pixel may be a red sub-pixel (R) emitting red light
  • the second sub-pixel may be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel may be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels may be a rectangle, a rhombus, a pentagon, or a hexagon, which is not limited in the present disclosure.
  • a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern, which is not limited in the present disclosure.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.
  • each shift register drives several rows of sub-pixels, as long as a large-area device like this is changed, and after this change generates additional space, the possible simple translation and stretching of small devices are all within the scope of protection of this disclosure.
  • FIG. 21 is a schematic diagram of an equivalent circuit of a pixel driving circuit
  • FIG. 22 is a schematic diagram of an equivalent circuit of another pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (first transistor M1 to seventh transistor M7) and 1 capacitor C.
  • the gate electrode of the first transistor M1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1 or the third node N3;
  • the gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the third node N3;
  • the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3;
  • the gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, and the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data
  • the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor.
  • the active pattern of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active pattern of the oxide thin film transistor adopts an oxide semiconductor (Oxide).
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • the first transistor M1 and the second transistor M2 are opposite to the third transistor M3 to the seventh transistor M7 in transistor type.
  • the first transistor M1 and the second transistor M2 may be N-type transistors
  • the third transistor M3 to the seventh transistor M7 may be P-type transistors.
  • the first transistor M1 and the second transistor M2 may be oxide transistors, and the third to seventh transistors M3 to M7 may be low temperature polysilicon transistors.
  • the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal.
  • the voltage value of the signal of the first initial signal line INIT1 may be -3V.
  • the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal.
  • the voltage value of the signal of the second initial signal line INIT2 may be 0V.
  • the light emitting device L′ may be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.
  • the high-level power line VDD continuously provides a high-level signal
  • the low-level power line VSS continuously provides a low-level signal
  • FIG23 is a working timing diagram of the pixel driving circuit provided in FIG21 and FIG22.
  • the following is an exemplary embodiment of the present disclosure, which is described by the working process of the pixel driving circuit illustrated in FIG21 and FIG22 in the display stage.
  • FIG23 is illustrated by taking the first transistor M1 and the second transistor M2 as N-type transistors, and the third transistor M3 to the seventh transistor M7 as P-type transistors as an example.
  • the pixel driving circuit in FIG21 and FIG22 includes the first transistor M1 to the seventh transistor M7, a capacitor C and 8 signal lines (data signal line Data, a first scanning signal line Gate1, a second scanning signal line Gate2, a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, a light emitting signal line EM and a high-level power line VDD).
  • the operation process of the pixel driving circuit may include:
  • the first stage P1 is called the initialization stage.
  • the signal of the reset signal line Reset is a high-level signal
  • the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node N1 or the third node N3 through the turned-on first transistor M1, and the first node N1 or the third node N3 is initialized (reset), clearing the pre-stored voltage inside it, and completing the initialization.
  • the second stage P2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line Gate1 is a low level signal
  • the signal of the second scanning signal line Gate2 is a high level signal
  • the data signal line Data outputs a data voltage.
  • the third transistor M3 is turned on.
  • the signal of the first scanning signal line Gate1 is a low-level signal
  • the fourth transistor M4 is turned on and the seventh transistor M7 is turned on
  • the signal of the second scanning signal line Gate2 is a high-level signal
  • the second transistor M2 is turned on
  • the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-
  • the third stage P3 is called the light-emitting stage.
  • the signal of the light-emitting signal line EM is a low-level signal.
  • the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, thereby driving the light-emitting device L to emit light.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-
  • )-Vth] 2 K*(Vdd-Vd) 2
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the high-level power supply line VDD.
  • the gate line may include a first gate line and a second gate line
  • the first gate line may include a first scan signal line and a light emitting signal line
  • the second gate line may include a reset signal line and a second scan signal line.
  • the light-emitting device may include: any one of an organic light-emitting diode OLED, a quantum dot light-emitting diode, and an inorganic light-emitting diode.
  • the light-emitting device may be a micron-level light-emitting device, such as a micro light-emitting diode (Micro Light-Emitting Diode, Micro LED), a sub-millimeter light-emitting diode (Mini Light-Emitting Diode, Mini LED) or a micro organic light-emitting diode (Micro OLED), etc., and the embodiments of the present disclosure are not limited to this.
  • the light-emitting device L as an organic electroluminescent diode (OLED) as an example, the light-emitting device may include: a stacked first electrode (for example, as an anode), an organic light-emitting layer, and a second electrode (for example, as a cathode).
  • a stacked first electrode for example, as an anode
  • an organic light-emitting layer for example, an organic light-emitting layer
  • a second electrode for example, as a cathode
  • the display substrate of the present disclosure can be applied to a display device having a gate driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • a gate driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • At least one shift register provided by the embodiment of the present disclosure may be electrically connected to the second gate line.
  • the display substrate may further include: at least one scan control signal line located in the non-display area, the scan control signal line at least partially extending along the second direction D2.
  • the scan control signal terminals to which all the shift registers are connected are electrically connected to at least one scan control signal line.
  • FIG. 19 is illustrated by taking one scan control signal line MSL as an example
  • FIG. 20 is illustrated by taking four scan control signal lines MSL1 to MSL4 as an example.
  • the scan control signal terminals to which all the shift registers are connected are electrically connected to the same scan control signal line MSL.
  • the scan control signal terminal connected to any shift register from the M*(k-1)+K*M(a-1)+1th level shift register to the k*M+K*M(a-1)th level shift register is electrically connected to the kth scan control signal line, 1 ⁇ k ⁇ K, 1 ⁇ a ⁇ N/M
  • M is the number of shift registers connected to a scan control signal line
  • N is the total number of shift registers
  • K is the number of scan control signal lines
  • the scanning control signal end connected to the first-stage shift register to the seventh-stage shift register is electrically connected to the first scanning control signal line MSL1
  • the scanning control signal end connected to the eighth-stage shift register to the fourteenth-stage shift register is electrically connected to the second scanning control signal line MSL2
  • the scanning control signal end connected to the fifteenth-stage shift register to the twenty-first-stage shift register is electrically connected to the third scanning control signal line MSL3
  • the scanning control signal end connected to the twenty-second-stage shift register to the twenty-eighth-stage shift register is electrically connected to the fourth scanning control signal line MSL4.
  • the scanning control signal terminals connected to the twenty-ninth to thirty-fifth shift registers are electrically connected to the first scanning control signal line MSL1
  • the scanning control signal terminals connected to the thirty-sixth to forty-second shift registers are electrically connected to the second scanning control signal line MSL2
  • the scanning control signal terminals connected to the forty-third to forty-ninth shift registers are electrically connected to the third scanning control signal line MSL3
  • the scanning control signal terminals connected to the fiftieth to fifty-sixth shift registers are electrically connected to the fourth scanning control signal line MSL4, and so on.
  • L is the number of gate lines connected to any stage of shift register
  • h is the unit time, which is equal to the refresh interval time of adjacent rows of sub-pixels.
  • the display area can be divided into a plurality of display sub-areas, at least one display sub-area includes: at least one gate line.
  • the display mode of any display sub-area includes: a first display mode and a second display mode, and the refresh frequency of the first display mode is greater than the refresh frequency of the second display mode.
  • the display mode of the display sub-area when the display mode of the display sub-area is the first display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output terminal is a first level signal, at least part of the time period of the signal at the scan control signal terminal is a valid level signal, and the signal at the scan output terminal is a first level signal.
  • the display mode of the display sub-area is the second display mode, for the shift register connected to the gate line in the display sub-area, when the signal at the cascade output terminal is a first level signal, the signal at the scan control signal terminal is an invalid level signal, and the signal at the scan output terminal is a second level signal.
  • the voltage value of the first level signal is greater than the voltage value of the second level signal
  • the first level signal is a high level signal
  • the second level signal is a low level signal.
  • Fig. 24 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in Fig. 19. As shown in Fig. 24, in the time period t, since the signal of the scan control signal line MSL is a high-level signal, the signal of any output terminal from the scan output terminal NOUT(2) of the second-stage shift register to the scan output terminal NOUT(N-1) of the N-1-stage shift register is a low-level signal, that is, the pixel driving circuit connected to the gate line connected to the scan output terminal of the second-stage shift register to the scan output terminal of the N-1-stage shift register will not be initialized and data written, thereby realizing low-frequency display and low-power display of the display product.
  • Fig. 25 is a timing diagram of multiple scan output terminals of the gate driving circuit provided in Fig. 20. As shown in Fig. 25, in time periods t1 and t3, the signals of the first scan control signal line MSL1 to the fourth scan control signal line MSL4 are low level signals, and at this time, the scan output terminals of all shift registers sequentially output high level signals.
  • the first scanning control signal line MSL1 is a high-level signal in part of the time period, so that the scanning output ends of the first-stage shift register and the seventh-stage shift register output low-level signals.
  • the time period in which the first scanning control signal line MSL1 is a high-level signal is from the start time when the signal at the cascade output end of the first-stage shift register is a high-level signal to the end time when the signal at the cascade output end of the seventh shift register is a high-level signal.
  • the second scanning control signal line MSL2 is a high-level signal in part of the time period, so that the scanning output ends of the eighth-level shift register and the fourteenth-level shift register output low-level signals.
  • the time period in which the second scanning control signal line MSL2 is a high-level signal is from the start time when the signal at the cascade output end of the eighth-level shift register is a high-level signal to the end time when the signal at the cascade output end of the fourteenth shift register is a high-level signal.
  • the third scanning control signal line MSL3 is a high-level signal in part of the time period, so that the scanning output ends of the 43rd-level shift register and the 49th-level shift register output low-level signals, and the time period in which the third scanning control signal line MSL3 is a high-level signal is from the start time when the signal at the cascade output end of the 43rd-level shift register is a high-level signal to the end time when the signal at the cascade output end of the 49th-level shift register is a high-level signal.
  • the time period when the fourth scanning control signal line MSL4 is a high-level signal is from the start time when the signal at the cascade output end of the 50th shift register is a high-level signal to the end time when the signal at the cascade output end of the 56th shift register is a high-level signal
  • the time period when the fourth scanning control signal line MSL4 is a high-level signal is from the start time when the signal at the cascade output end of the 50th shift register is a high-level signal to the end time when the signal at the cascade output end of the 56th shift register is a high-level signal.
  • FIG26 is a partial schematic diagram of the non-display area of the display substrate.
  • the display substrate may further include: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL and a third power line VCX located in the non-display area.
  • the shift register in FIG26 is the shift register provided in FIG11, and FIG26 is described by taking one scanning control signal line as an example.
  • any one of the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the second power line VGL, and the third power line VCX at least partially extends along the second direction D2;
  • the first clock signal terminal connected to any stage of the shift register is electrically connected to one of the first clock signal line CLK1 and the second clock signal line CLK2
  • the second clock signal terminal connected to any stage of the shift register is electrically connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2
  • the clock signal lines connected to the first clock signal terminals connected to adjacent shift registers are different
  • the clock signal lines connected to the second clock signal terminals connected to adjacent shift registers are different
  • the first power supply terminals connected to all the shift registers are electrically connected to the first power supply line VGH
  • the second power supply terminals connected to all the shift registers are electrically connected to the second power supply line VGL
  • the third power supply terminals connected to all the shift registers are electrically connected to the third power supply line VCX.
  • the display substrate may further include: an initial signal line located in the non-display area, the signal input end of at least one shift register being electrically connected to the initial signal line.
  • the initial signal line may extend along the second direction and may be located on a side of the first clock signal line away from the display area.
  • the scan control signal line MSL may be located on a side of any one of the first clock signal line CLK1 , the second clock signal line CLK2 , the first power line VGH, the second power line VGL and the third power line VCX close to the display area.
  • the number of the second power lines VGL is two, and the first clock signal line CLK1, the second clock signal line CLK2, the first second power line VGL, the third power line VCX, the second second power line VGL and the first power line VGH are arranged in sequence in a direction close to the display area.
  • the shift register may include seventeenth to nineteenth transistors T17 to T19 ; the seventeenth to nineteenth transistors T17 to T19 may be arranged along the second direction D2 .
  • any one of the seventeenth to nineteenth transistors T17 to T19 is located between the first power line VGH and the scan control signal line MSL.
  • any transistor includes an active pattern
  • Figure 27 is a schematic diagram of active patterns of the seventeenth to nineteenth transistors. As shown in Figure 27, the average length of the active pattern 171 of the seventeenth transistor along the first direction D1 is less than the average length of any one of the active pattern 181 of the eighteenth transistor and the active pattern 191 of the nineteenth transistor along the first direction D1.
  • the line width of any one of the first power line VGH and the second power line VGL may be greater than the line width of the scan control signal line MSL.
  • the following is an exemplary explanation through the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials.
  • Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be any one or more of spraying, spin coating and inkjet printing
  • etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the "A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • Figures 11 to 18 are explained by taking the display substrate including the shift register provided in Figure 8, that is, the shift register includes: the first transistor T1 to the eighth transistor T8 and the tenth transistor T10 as an example.
  • Forming a semiconductor layer pattern on a substrate may include: depositing a semiconductor film on the substrate, and patterning the semiconductor film through a patterning process to form a semiconductor layer pattern.
  • FIG. 28 is a schematic diagram of FIG. 26 after forming a semiconductor layer pattern.
  • the semiconductor layer pattern of each shift register may include at least an active pattern 11 of a first transistor to an active pattern 191 of a nineteenth transistor.
  • the active pattern 51 of the fifth transistor, the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor, and the active pattern 131 of the thirteenth transistor are an integrated structure
  • the active pattern 121 of the twelfth transistor and the active pattern 161 of the sixteenth transistor are an integrated structure
  • the active pattern 171 of the seventeenth transistor, the active pattern 181 of the eighteenth transistor, and the active pattern 191 of the nineteenth transistor are an integrated structure
  • the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, the active pattern 91 of the ninth transistor, the active pattern 101 of the tenth transistor, the active pattern 111 of the eleventh transistor, the active pattern 141 of the fourteenth transistor, and the active pattern 151 of the fifteenth transistor are separately provided.
  • the active pattern 11 of the first transistor and the active pattern 141 of the fourteenth transistor are arranged along a first direction D1, and the active pattern 11 of the first transistor is located on a side of the active pattern 141 of the fourteenth transistor close to the display area, and the active pattern 21 of the second transistor is located on a side of the active pattern 11 of the first transistor close to the display area.
  • the active pattern 31 of the third transistor is arranged along the second direction D2 with the active pattern 11 of the first transistor, and the active pattern 31 of the third transistor of the shift register at this stage is located on the side of the active pattern 11 of the first transistor close to the next stage shift register, the active pattern 111 of the eleventh transistor and the active pattern 151 of the fifteenth transistor are arranged along the first direction D1, the active pattern 111 of the eleventh transistor and the active pattern 111 of the first transistor are arranged along the second direction D2, the active pattern 151 of the fifteenth transistor and the active pattern 141 of the fourteenth transistor are arranged along the second direction D2, the active pattern 111 of the eleventh transistor is located on the side of the active pattern 151 of the fifteenth transistor close to the display area, the active pattern 111 of the eleventh transistor of the shift register at this stage is located on the side of the active pattern 31 of the fifteenth transistor close to the next stage shift register.
  • the active pattern 41 of the fourth transistor of the shift register at this stage is located on the side of the active pattern 111 of the eleventh transistor close to the next stage shift register.
  • the active pattern 61 of the sixth transistor is located on the side of the active pattern 21 of the second transistor close to the display area.
  • the active pattern 71 of the seventh transistor is located on the side of the active pattern 61 of the sixth transistor close to the display area.
  • the active pattern 81 of the eighth transistor and the active pattern 131 of the thirteenth transistor are located on the side of the active pattern 21 of the second transistor close to the display area, and the active pattern 131 of the thirteenth transistor is located on the side of the active pattern 81 of the eighth transistor away from the display area.
  • the active pattern 51 of the fifth transistor is located on the side of the active pattern 111 of the eleventh transistor close to the display area.
  • the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor and the active pattern 51 of the fifth transistor are arranged along the second direction D2, and the active pattern 71 of the seventh transistor of the current stage shift register is located on the side of the active pattern 81 of the eighth transistor close to the previous stage shift register, and the active pattern 51 of the fifth transistor of the current stage shift register is located on the side of the active pattern 81 of the eighth transistor close to the next stage shift register.
  • the active pattern 161 of the sixteenth transistor is located on the side of the active pattern 41 of the fourth transistor close to the display area
  • the active pattern 121 of the twelfth transistor is located on the side of the active pattern 161 of the sixteenth transistor close to the display area
  • the active pattern 51 of the fifth transistor and the active pattern 121 of the twelfth transistor are arranged along the second direction D2
  • the active pattern 121 of the twelfth transistor of the current level shift register is located on the side of the active pattern 51 of the fifth transistor close to the next level shift register.
  • the active pattern 91 of the ninth transistor is located on the side of the active pattern 71 of the seventh transistor close to the display area, the active pattern 101 of the tenth transistor is located on the side of the active pattern 161 of the sixteenth transistor close to the display area, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are arranged along the second direction D2, and the active pattern 91 of the ninth transistor of the current level shift register can be located on the side of the active pattern 101 of the tenth transistor close to the previous level shift register.
  • the active pattern 171 of the seventeenth transistor (also the active pattern 181 of the eighteenth transistor and the active pattern 191 of the nineteenth transistor) is located on the side of the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor close to the display area, and the active pattern 171 of the seventeenth transistor to the active pattern 191 of the ninth transistor are arranged along the second direction D2.
  • the active pattern 171 of the seventeenth transistor of the current-stage shift register is located on the side of the active pattern 181 of the eighteenth transistor close to the next-stage shift register, and the active pattern 191 of the nineteenth transistor of the current-stage shift register is located on the side of the active pattern 181 of the eighteenth transistor close to the previous-stage shift register.
  • any one of the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, the active pattern 101 of the tenth transistor, the active pattern 131 of the thirteenth transistor, and the active pattern 161 of the sixteenth transistor has a strip shape and extends along the first direction D1.
  • the integrated structure of the active pattern 121 of the twelfth transistor and the active pattern 161 of the sixteenth transistor is in an inverted "T" shape
  • the integrated structure of the active pattern 51 of the fifth transistor, the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor and the active pattern 131 of the thirteenth transistor can be in a " ⁇ " shape
  • the integrated structure of the active pattern 171 of the seventeenth transistor, the active pattern 181 of the eighteenth transistor and the active pattern 191 of the nineteenth transistor is in a strip shape and extends along the second direction D2.
  • an average length of the active pattern 171 of the seventeenth transistor along the first direction D1 is smaller than an average length of any of the active patterns 181 and 191 of the eighteenth and nineteenth transistors along the first direction D1.
  • the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region.
  • the first region 51-1 of the active pattern 51 of the fifth transistor may serve as the first region 81-1 of the active pattern 81 of the eighth transistor and the first region 131-1 of the active pattern 131 of the thirteenth transistor
  • the second region 71-2 of the active pattern 71 of the seventh transistor may serve as the second region 81-2 of the active pattern 81 of the eighth transistor
  • the second region 121-2 of the active pattern 121 of the twelfth transistor may serve as the second region 161-2 of the active pattern 161 of the sixteenth transistor
  • the second region 171-2 of the active pattern 171 of the seventeenth transistor may serve as the first region 181-1 of the active pattern 181 of the eighteenth transistor
  • the second region 181-2 of the active pattern 181 of the eighteenth transistor may serve as the first region 191-2 of the active pattern 191 of the nineteenth transistor.
  • a first region 11-1 and a second region 11-2 of an active pattern 11 of a first transistor a first region 21-1 and a second region 21-2 of an active pattern 21 of a second transistor, a first region 31-1 and a second region 31-2 of an active pattern 31 of a third transistor, a first region 41-1 and a second region 41-2 of an active pattern 41 of a fourth transistor, a second region 51-2 of an active pattern 51 of a fifth transistor, a first region 61-1 and a second region 61-2 of an active pattern 61 of a sixth transistor, a first region 71-1 of an active pattern 71 of a seventh transistor, a first region 91-1 and a second region 91-2 of an active pattern 91 of a ninth transistor, and a first region 101 of an active pattern 101 of a tenth transistor.
  • the first area 111-1 and the second area 111-2 of the active pattern 111 of the eleventh transistor the first area 121-1 of the active pattern 121 of the twelfth transistor, the second area 131-2 of the active pattern 131 of the thirteenth transistor, the first area 141-1 and the second area 141-2 of the active pattern 141 of the fourteenth transistor, the first area 151-1 and the second area 151-2 of the active pattern 151 of the fifteenth transistor, the first area 161-1 of the active pattern 161 of the sixteenth transistor, the first area 171-1 of the active pattern 171 of the seventeenth transistor and the first area 191-1 of the active pattern 191 of the nineteenth transistor are separately set.
  • forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process, forming a first insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 29 and 30 , where FIG. 29 is a schematic diagram of the first conductive layer pattern in FIG. 26 , and FIG. 30 is a schematic diagram of FIG. 26 after the first conductive layer pattern is formed.
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each shift register may include at least: the gate electrode 12 of the first transistor to the gate electrode 192 of the nineteenth transistor, the first plate C11 of the first capacitor to the first plate C41 of the fourth capacitor, and the first connection portion L1.
  • the gate electrode 12 of the first transistor and the gate electrode 142 of the fourteenth transistor are an integrated structure, and the integrated structure of the gate electrode 12 of the first transistor and the gate electrode 142 of the fourteenth transistor is strip-shaped and extends along the first direction D1.
  • the gate electrode 22 of the second transistor and the gate electrode 82 of the eighth transistor are an integral structure.
  • the gate electrode 22 of the second transistor may be in an "n" shape with an opening toward the display area, and the gate electrode 82 of the eighth transistor may be in a zigzag shape and at least partially extend along the first direction D1.
  • the gate electrode 32 of the third transistor is separately provided and may have a shape of Font.
  • the gate electrode 42 of the fourth transistor, the gate electrode 162 of the sixteenth transistor, and the C31 of the third capacitor are an integrated structure.
  • the shape of the C31 of the third capacitor is rectangular.
  • the gate electrode 42 of the fourth transistor of the current shift register is located on the side of the C31 of the third capacitor close to the shift register of the next stage, and the shape of the gate electrode 42 of the fourth transistor is a strip and extends along the second direction D2.
  • the gate electrode 162 of the sixteenth transistor is located on the side of the C31 of the third capacitor close to the display area, and the shape of the gate electrode 162 of the sixteenth transistor is Font.
  • the gate electrode 52 of the fifth transistor is provided separately.
  • the gate electrode 52 of the fifth transistor has a zigzag shape and at least partially extends along the first direction D1.
  • the gate electrode 62 of the sixth transistor and the first plate C11 of the first capacitor are an integrated structure.
  • the gate electrode 62 of the sixth transistor of the current stage shift register is located on the side of the first plate C11 of the first capacitor close to the next stage shift register.
  • the shape of the first plate C11 of the first capacitor can be
  • the gate electrode 62 of the sixth transistor is in a zigzag shape, and at least partially extends along the second direction D2.
  • the gate electrode 72 of the seventh transistor is provided separately.
  • the gate electrode 72 of the seventh transistor is in a zigzag shape and at least partially extends along the first direction D1.
  • the gate electrode 92 of the ninth transistor, the gate electrode 182 of the eighteenth transistor, and the first plate C21 of the second capacitor are an integrated structure.
  • the gate electrode 92 of the ninth transistor and the gate electrode 182 of the eighteenth transistor are both located on the side of the first plate C21 of the second capacitor close to the display area, the gate electrode 92 of the ninth transistor is connected to the first plate C21 of the second capacitor close to the boundary of the display area, and the gate electrode 182 of the eighteenth transistor of the current shift register is connected to the first plate C21 of the second capacitor close to the boundary of the previous shift register.
  • the shape of the first plate C21 of the second capacitor can be rectangular, and the corners of the rectangle can be chamfered.
  • the gate electrode 92 of the ninth transistor is strip-shaped and extends along the first direction D1.
  • the gate electrode 182 of the eighteenth transistor includes: a first connection segment 182A and at least one first branch segment 182B, the first electrode plate C21 of the second capacitor is located on the side of the first connection segment 182A away from the display area, the first branch segment 182B is located on the side of the first connection segment 182A close to the display area, and the first connection segment 182A is electrically connected to the first electrode plate C21 of the second capacitor and the at least one first branch segment 182B.
  • the gate electrode 182 of the eighteenth transistor can be in a combing structure.
  • the shape of the first connection segment 182A can be
  • the first branch segment 182B may be in the shape of a strip and extend along the first direction D1, which is equivalent to a "comb tooth”. At least one first branch segment 182B is arranged along the second direction D2.
  • the gate electrode 102 of the tenth transistor and the gate electrode 172 of the seventeenth transistor are an integral structure.
  • the gate electrode 102 of the tenth transistor may be in the shape of an "F" shape rotated to the left, and the gate electrode 172 of the seventeenth transistor may include: a second connecting segment 172A and at least one second branch segment 172B.
  • the second branch segment 172B is located on the side of the second connecting segment 172A close to the display area.
  • the gate electrode 172 of the seventeenth transistor is in the shape of a comb-like structure, the second connecting segment 172A extends along the second direction D2, which is equivalent to a "comb back”, and the second branch segment 172B extends along the first direction D1, which is equivalent to a "comb tooth”, and at least one second branch segment 172B is arranged along the second direction D2.
  • the gate electrode 112 of the eleventh transistor and the gate electrode 152 of the fifteenth transistor are an integrated structure, and the shape of the integrated structure of the gate electrode 112 of the eleventh transistor and the gate electrode 152 of the fifteenth transistor is a strip and extends along the first direction D1.
  • the gate electrode 122 of the twelfth transistor is separately provided and may be shaped as Font.
  • the gate electrode 132 of the thirteenth transistor is separately provided.
  • the gate electrode 132 of the thirteenth transistor is in the shape of a stripe and extends along the second direction D2.
  • the gate electrode 192 of the nineteenth transistor is separately provided.
  • the gate electrode 192 of the nineteenth transistor includes: a third connection segment 192A and at least one third branch segment 192B.
  • the third branch segment 192B is located on a side of the third connection segment 192A away from the display area.
  • the gate electrode 192 of the nineteenth transistor may be in a comb-like structure, and the shape of the third connection segment 192A may be
  • the third branch segment 192B is in the shape of a strip and extends along the first direction D1, which is equivalent to a "comb tooth”.
  • At least one third branch segment 192B is arranged along the second direction D2.
  • the first plate C41 of the fourth capacitor is separately provided and is located between the gate electrode 52 of the fifth transistor and the gate electrode 182 of the eighteenth transistor.
  • the first plate C41 of the fourth capacitor includes: a main body and a raised portion, the main body may be rectangular, and the raised portion is located on a side of the main body away from the display area.
  • the first connection portion L1 is separately provided and is block-shaped. The first connection portion L1 is located on a side of the gate electrode 42 of the fourth transistor away from the display area, and is located on a side of the first plate C31 of the third capacitor of the current shift register close to the next shift register.
  • a gate electrode 12 of a first transistor is arranged across an active pattern of the first transistor
  • a gate electrode 22 of a second transistor is arranged across an active pattern of the second transistor
  • a gate electrode 32 of a third transistor is arranged across an active pattern of the third transistor
  • a gate electrode 42 of a fourth transistor is arranged across an active pattern of the fourth transistor
  • a gate electrode 52 of a fifth transistor is arranged across an active pattern of the fifth transistor
  • a gate electrode 62 of a sixth transistor is arranged across an active pattern of the sixth transistor
  • a gate electrode 72 of a seventh transistor is arranged across an active pattern of the seventh transistor
  • a gate electrode 82 of an eighth transistor is arranged across an active pattern of the eighth transistor
  • a gate electrode 92 of a ninth transistor is arranged across an active pattern of the ninth transistor
  • a gate electrode 102 of a tenth transistor is arranged across an active pattern of the tenth transistor
  • the gate electrode 122 of the twelfth transistor is arranged across the active pattern of the twelfth transistor
  • the gate electrode 132 of the thirteenth transistor is arranged across the active pattern of the thirteenth transistor
  • the gate electrode 142 of the fourteenth transistor is arranged across the active pattern of the fourteenth transistor
  • the gate electrode 152 of the fifteenth transistor is arranged across the active pattern of the fifteenth transistor
  • the gate electrode 162 of the sixteenth transistor is arranged across the active pattern of the sixteenth transistor
  • at least one second branch segment 172B of the gate electrode 172 of the seventeenth transistor is arranged across the active pattern of the seventeenth transistor
  • at least one first branch segment 182B of the gate electrode 182 of the eighteenth transistor is arranged across the active pattern of the eighteenth transistor
  • at least one third branch segment 192B of the gate electrode 192 of the nineteenth transistor is arranged across the active pattern of the nineteenth transistor, that is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of
  • the first conductive layer can be used as a shield to perform a conductorization process on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel area of the first transistor to the nineteenth transistor, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first transistor to the nineteenth transistor are both conductorized.
  • the first connection portion L1 in the present disclosure is processed into a conductorized layer to form a conductorized first connection portion L1.
  • forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on a substrate having the aforementioned pattern, patterning the second conductive film through a patterning process, and forming a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in FIGS. 31 and 32 , where FIG. 31 is a schematic diagram of the second conductive layer pattern in FIG. 26 , and FIG. 32 is a schematic diagram of FIG. 26 after the second conductive layer pattern is formed.
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern may include at least a second plate C12 of a first capacitor to a second plate C42 of a fourth capacitor located in each shift register and a second connection portion L2 .
  • the orthographic projection of the second electrode plate C12 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the first electrode plate of the first capacitor on the substrate.
  • the area of the second electrode plate C12 of the first capacitor is smaller than the area of the first electrode plate of the first capacitor.
  • the shape of the second electrode plate C12 of the first capacitor is the same as the shape of the first electrode plate of the first capacitor.
  • the orthographic projection of the second electrode plate C22 of the second capacitor on the substrate overlaps at least partially with the orthographic projection of the first electrode plate of the second capacitor on the substrate.
  • the area of the second electrode plate C22 of the second capacitor is smaller than the area of the first electrode plate of the second capacitor.
  • the shape of the second electrode plate C22 of the second capacitor may be rectangular, the corners of the rectangular shape may be chamfered, and extend along the second direction D2.
  • the orthographic projection of the second plate C32 of the third capacitor on the substrate overlaps at least partially with the orthographic projection of the first plate of the third capacitor on the substrate.
  • the area of the second plate C32 of the third capacitor is smaller than the area of the first plate of the third capacitor.
  • the shape of the second plate C32 of the third capacitor can be rectangular.
  • the second plate C32 of the third capacitor is provided with a groove K near the boundary of the second plate C32 of the first capacitor, and the orthographic projection of the groove K on the substrate overlaps at least partially with the orthographic projection of the first plate of the third capacitor on the substrate, and the first plate of the third capacitor is exposed.
  • the orthographic projection of the second electrode plate C42 of the fourth capacitor on the substrate is located at a position where the orthographic projection of the first electrode plate of the fourth capacitor on the substrate at least partially overlaps.
  • the shape of the second electrode plate C42 of the fourth capacitor is the same as the shape of the first electrode plate C41 of the fourth capacitor, and the area of the second electrode plate C42 of the fourth capacitor is smaller than the area of the first electrode plate of the fourth capacitor.
  • the second connection portion L2 is located between the second electrode plate C32 of the third capacitor and the second electrode plate C22 of the second capacitor, and is located on the side of the first capacitor C12 of the current stage shift register close to the next stage shift register.
  • the second connection portion L2 is in a zigzag shape and at least partially extends along the first direction D1.
  • forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in FIG. 33 , which is a schematic diagram of FIG. 26 after the third insulating layer pattern is formed.
  • the third insulation layer pattern of each shift register may include at least first to fifty-first via holes V1 to V51 .
  • the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the first transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first area of the active pattern of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor (also the first electrode of the fourteenth transistor) to the first area of the active pattern of the first transistor through the via hole.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the first transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the second via hole V2 are etched away to expose the surface of the second area of the active pattern of the first transistor, and the second via hole V2 is configured to connect the second electrode of the subsequently formed first transistor to the second area of the active pattern of the first transistor through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the second transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the third via hole V3 are etched away to expose the surface of the first area of the active pattern of the second transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of the active pattern of the second transistor through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the second transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fourth via hole V4 are etched away to expose the surface of the second area of the active pattern of the second transistor, and the fourth via hole V4 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of the active pattern of the second transistor through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the third transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the active pattern of the third transistor, and the fifth via hole V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of the active pattern of the third transistor through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the third transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of the active pattern of the third transistor, and the sixth via hole V6 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of the active pattern of the third transistor through the via hole.
  • the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the fourth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the seventh via V7 are etched away to expose the surface of the first area of the active pattern of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of the active pattern of the fourth transistor through the via.
  • the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the fourth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the eighth via V8 are etched away to expose the surface of the second area of the active pattern of the fourth transistor, and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second area of the active pattern of the fourth transistor through the via.
  • the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the fifth transistor (also the first area of the active pattern of the eighth transistor and the first area of the active pattern of the thirteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the ninth via V9 are etched away to expose the surface of the second area of the active pattern of the fourth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to the first area of the active pattern of the fifth transistor (also the first area of the active pattern of the eighth transistor and the first area of the active pattern of the thirteenth transistor) through the via.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the fifth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the second area of the active pattern of the fifth transistor, and the tenth via hole V10 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of the active pattern of the fifth transistor through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the sixth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first area of the active pattern of the sixth transistor, and the eleventh via hole V11 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of the active pattern of the sixth transistor through the via hole.
  • the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the sixth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twelfth via V12 are etched away to expose the surface of the second area of the active pattern of the sixth transistor, and the twelfth via V12 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the second area of the active pattern of the sixth transistor through the via.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the seventh transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first area of the active pattern of the seventh transistor, and the thirteenth via hole V13 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the first area of the active pattern of the seventh transistor through the via hole.
  • the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the seventh transistor (also the second area of the active pattern of the eighth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the second area of the active pattern of the seventh transistor (also the second area of the active pattern of the eighth transistor), and the fourteenth via V14 is configured to connect the second electrode of the subsequently formed seventh transistor (also the second electrode of the eighth transistor) to the second area of the active pattern of the seventh transistor (also the second area of the active pattern of the eighth transistor) through the via.
  • the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the ninth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fifteenth via V15 are etched away to expose the surface of the first area of the active pattern of the ninth transistor, and the fifteenth via V15 is configured to connect the first electrode of the subsequently formed fifth transistor (which is also the first electrode of the eighth transistor, the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to the first area of the active pattern of the ninth transistor through the via.
  • the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the ninth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the sixteenth via V16 are etched away to expose the surface of the second area of the active pattern of the ninth transistor, and the sixteenth via V16 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the tenth transistor) to the second area of the active pattern of the ninth transistor through the via.
  • the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the tenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the first area of the active pattern of the tenth transistor, and the seventeenth via hole V17 is configured to connect the first electrode of the subsequently formed tenth transistor to the first area of the active pattern of the tenth transistor through the via hole.
  • the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the tenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second area of the active pattern of the tenth transistor, and the eighteenth via hole V18 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the second area of the active pattern of the tenth transistor through the via hole.
  • the orthographic projection of the nineteenth via hole V19 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the eleventh transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the nineteenth via hole V19 are etched away to expose the surface of the first area of the active pattern of the eleventh transistor, and the nineteenth via hole V19 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the first area of the active pattern of the eleventh transistor through the via hole.
  • the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the eleventh transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twentieth via V20 are etched away to expose the surface of the second area of the active pattern of the eleventh transistor, and the twentieth via V20 is configured to connect the second electrode of the subsequently formed eleventh transistor to the second area of the active pattern of the eleventh transistor through the via.
  • the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the twelfth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-first via V21 are etched away to expose the surface of the first area of the active pattern of the twelfth transistor, and the twenty-first via V21 is configured to connect the first electrode of the subsequently formed twelfth transistor to the first area of the active pattern of the twelfth transistor through the via.
  • the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the twelfth transistor (also the second area of the active pattern of the sixteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-second via V22 are etched away to expose the surface of the second area of the active pattern of the twelfth transistor (also the second area of the active pattern of the sixteenth transistor), and the twenty-second via V22 is configured to connect the second electrode of the subsequently formed twelfth transistor (also the second electrode of the sixteenth transistor) to the second area of the active pattern of the twelfth transistor (also the second area of the active pattern of the sixteenth transistor) through the via.
  • the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the thirteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-third via V23 are etched away to expose the surface of the second area of the active pattern of the thirteenth transistor, and the twenty-third via V23 is configured to connect the second electrode of the subsequently formed thirteenth transistor to the second area of the active pattern of the thirteenth transistor through the via.
  • the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the fourteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-fourth via V24 are etched away to expose the surface of the first area of the active pattern of the fourteenth transistor, and the twenty-fourth via V24 is configured to connect the first electrode of the subsequently formed first transistor (which is also the first electrode of the fourteenth transistor) to the first area of the active pattern of the fourteenth transistor through the via.
  • the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the fourteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-fifth via V25 are etched away to expose the surface of the second area of the active pattern of the fourteenth transistor, and the twenty-fifth via V25 is configured to connect the second electrode of the subsequently formed fourteenth transistor (which is also the first electrode of the fifteenth transistor) to the second area of the active pattern of the fourteenth transistor through the via.
  • the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the fifteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-sixth via V26 are etched away to expose the surface of the first area of the active pattern of the fifteenth transistor, and the twenty-sixth via V26 is configured to connect the second electrode of the subsequently formed fourteenth transistor (which is also the first electrode of the fifteenth transistor) to the first area of the active pattern of the fifteenth transistor through the via.
  • the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the fifteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-seventh via V27 are etched away to expose the surface of the second area of the active pattern of the fifteenth transistor, and the twenty-seventh via V27 is configured to connect the second electrode of the subsequently formed fifteenth transistor to the second area of the active pattern of the fifteenth transistor through the via.
  • the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the sixteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-eighth via V28 are etched away to expose the surface of the first area of the active pattern of the sixteenth transistor, and the twenty-eighth via V28 is configured to connect the first electrode of the subsequently formed sixteenth transistor to the first area of the active pattern of the sixteenth transistor through the via.
  • the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the seventeenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the first area of the active pattern of the seventeenth transistor, and the twenty-ninth via V29 is configured to connect the first electrode of the seventeenth transistor formed subsequently to the first area of the active pattern of the seventeenth transistor through the via.
  • the orthographic projection of the thirtieth via V30 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the seventeenth transistor (also the first area of the active pattern of the eighteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirtieth via V30 are etched away to expose the surface of the second area of the active pattern of the seventeenth transistor (also the first area of the active pattern of the eighteenth transistor), and the thirtieth via V30 is configured to connect the second electrode of the seventeenth transistor (also the first electrode of the eighteenth transistor) formed subsequently to the second area of the active pattern of the seventeenth transistor (also the first area of the active pattern of the eighteenth transistor) through the via.
  • the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second area of the active pattern of the eighteenth transistor (also the second area of the active pattern of the nineteenth transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirty-first via V31 are etched away to expose the surface of the second area of the active pattern of the eighteenth transistor (also the second area of the active pattern of the nineteenth transistor), and the thirty-first via V31 is configured to connect the second electrode of the subsequently formed eighteenth transistor (also the second electrode of the nineteenth transistor) to the second area of the active pattern of the eighteenth transistor (also the second area of the active pattern of the nineteenth transistor) through the via.
  • the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the first area of the active pattern of the nineteenth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the thirty-second via V32 are etched away to expose the surface of the first area of the active pattern of the nineteenth transistor, and the thirty-second via V32 is configured to connect the first electrode of the subsequently formed nineteenth transistor to the first area of the active pattern of the nineteenth transistor through the via.
  • the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) on the substrate, the second insulating layer and the third insulating layer in the thirty-third via V33 are etched away to expose the surface of the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor), and the thirty-third via V33 is configured to connect the subsequently formed third connecting portion and the first electrode of the second transistor to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the via.
  • the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor (also the gate electrode of the eighth transistor) on the substrate, the second insulating layer and the third insulating layer in the thirty-fourth via V34 are etched away to expose the surface of the gate electrode of the second transistor (also the gate electrode of the eighth transistor), and the thirty-fourth via V34 is configured to connect the second electrode of the first transistor and the second electrode of the thirteenth transistor to be formed subsequently to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the via.
  • the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the gate electrode of the third transistor on the substrate, the second insulating layer and the third insulating layer in the thirty-fifth via V35 are etched away to expose the surface of the gate electrode of the third transistor, and the thirty-fifth via V35 is configured to connect a subsequently formed fifth connecting portion to the gate electrode of the third transistor through the via.
  • the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) on the substrate, the second insulating layer and the third insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor), and the thirty-sixth via V36 is configured to connect the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor to be formed subsequently to the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through the via.
  • the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth transistor on the substrate, the second insulating layer and the third insulating layer in the thirty-seventh via V37 are etched away to expose the surface of the gate electrode of the fifth transistor, and the thirty-seventh via V37 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the gate electrode of the fifth transistor through the via.
  • the orthographic projection of the thirty-eighth via V38 on the substrate is located within the range of the orthographic projection of the gate electrode of the sixth transistor (the first plate of the first capacitor) on the substrate, the second insulating layer and the third insulating layer in the thirty-eighth via V38 are etched away to expose the surface of the gate electrode of the sixth transistor (the first plate of the first capacitor), and the thirty-eighth via V38 is configured to connect the second electrode of the subsequently formed eleventh transistor to the gate electrode (the first plate of the first capacitor) of the sixth transistor through the via.
  • the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the gate electrode of the seventh transistor on the substrate, the second insulating layer and the third insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the gate electrode of the seventh transistor, and the thirty-ninth via V39 is configured to connect the subsequently formed fourth connecting portion and the first electrode of the sixth transistor to the gate electrode of the seventh transistor through the via.
  • the orthographic projection of the fortieth via V40 on the substrate is located within the range of the orthographic projection of the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) on the substrate, the second insulating layer and the third insulating layer in the fortieth via V40 are etched away to expose the surface of the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor), and the fortieth via V40 is configured to connect the second electrode of the seventh transistor and the second electrode of the eighth transistor to be subsequently formed to the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) through the via.
  • the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) on the substrate, the second insulating layer and the third insulating layer in the forty-first via V41 are etched away to expose the surface of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor), and the forty-first via V41 is configured to connect the second electrode of the twelfth transistor and the second electrode of the sixteenth transistor to be subsequently formed to the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) through the via.
  • the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) on the substrate, the second insulating layer and the third insulating layer in the forty-second via V42 are etched away to expose the surface of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor), and the forty-second via V42 is configured to connect the first electrode of the subsequently formed third transistor to the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) through the via.
  • the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the gate electrode of the twelfth transistor on the substrate, the second insulating layer and the third insulating layer in the forty-third via V43 are etched away to expose the surface of the gate electrode of the twelfth transistor, and the forty-third via V43 is configured to connect the first electrode of the subsequently formed tenth transistor to the gate electrode of the twelfth transistor through the via.
  • the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the gate electrode of the thirteenth transistor on the substrate, the second insulating layer and the third insulating layer in the forty-fourth via V44 are etched away to expose the surface of the gate electrode of the thirteenth transistor, and the forty-fourth via V44 is configured to connect the subsequently formed seventh connecting portion to the gate electrode of the thirteenth transistor through the via.
  • the orthographic projection of the forty-fifth via hole V45 on the substrate is located within the range of the orthographic projection of the gate electrode of the nineteenth transistor on the substrate, the second insulating layer and the third insulating layer in the forty-fifth via hole V45 are etched away to expose the surface of the gate electrode of the nineteenth transistor, and the forty-fifth via hole V45 is configured to connect the subsequently formed eighth connecting portion to the gate electrode of the nineteenth transistor through the via hole.
  • the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the first plate of the fourth capacitor on the substrate, the second insulating layer and the third insulating layer in the forty-sixth via V46 are etched away to expose the surface of the first plate of the fourth capacitor, and the forty-sixth via V46 is configured to connect the first electrode of the subsequently formed tenth transistor to the first plate of the fourth capacitor through the via.
  • the orthographic projection of the forty-seventh via V47 on the substrate is located within the range of the orthographic projection of the first connecting portion on the substrate, the second insulating layer and the third insulating layer in the forty-seventh via V47 are etched away to expose the surface of the first connecting portion, and the forty-seventh via V47 is configured to connect the first electrode of the subsequently formed fourth transistor to the first connecting portion through the via.
  • the orthographic projection of the forty-eight via V48 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate, the forty-eight via V48 exposes the surface of the second plate of the first capacitor, and the forty-eight via V48 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the second plate of the first capacitor through the via.
  • the orthographic projection of the forty-ninth via V49 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the forty-ninth via V49 exposes the surface of the second plate of the second capacitor, and the forty-ninth via V49 is configured to connect the first electrode of the subsequently formed fifth transistor (which is also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) to the second plate of the second capacitor through the via.
  • the orthographic projection of the fiftieth via V50 on the substrate is located within the range of the orthographic projection of the second plate of the third capacitor on the substrate, the fiftieth via V50 exposes the surface of the second plate of the third capacitor, and the fiftieth via V50 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second plate of the third capacitor through the via.
  • the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the second electrode plate of the fourth capacitor on the substrate, the fifty-first via V51 exposes the surface of the second electrode plate of the fourth capacitor, and the fifty-first via V51 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the tenth transistor) to the second electrode plate of the fourth capacitor through the via.
  • the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the second connecting portion on the substrate, the fifty-second via V52 exposes the surface of the second connecting portion, and the fifty-second via V52 is configured to connect the first electrode of the subsequently formed twelfth transistor to the second connecting portion through the via.
  • forming the third conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the third insulating layer, as shown in FIGS. 34 and 35 , where FIG. 34 is a schematic diagram of the third conductive layer pattern in FIG. 26 , and FIG. 35 is a schematic diagram of FIG. 26 after the third conductive layer pattern is formed.
  • the third conductive layer may be referred to as a first source-drain metal (SD1) layer.
  • the third conductive layer pattern may include at least first and second electrodes 13 and 14 of the first transistor to first and second electrodes 193 and 194 of the nineteenth transistor, and third to eighth connection portions L3 to L8 .
  • the first electrode 13 of the first transistor and the first electrode 143 of the fourteenth transistor are an integral structure.
  • the first electrode 13 of the first transistor (also the first electrode 143 of the fourteenth transistor) is in the shape of “ ⁇ ”.
  • the first electrode 13 of the first transistor (also the first electrode 143 of the fourteenth transistor) is connected to the first region of the active pattern of the first transistor through the first via hole, and is connected to the first region of the active pattern of the fourteenth transistor through the twenty-fourth via hole.
  • the second electrode 14 of the first transistor is separately provided.
  • the second electrode 14 of the first transistor is in the shape of a strip and extends along the second direction D2.
  • the second electrode 14 of the first transistor is connected to the second region of the active pattern of the first transistor through the second via hole, and is connected to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the thirty-fourth via hole.
  • the first electrode 23 of the second transistor is separately provided.
  • the first electrode 23 of the second transistor is in the shape of a strip and extends along the second direction D2.
  • the first electrode 23 of the second transistor is connected to the first region of the active pattern of the second transistor through the third via hole, and is connected to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the thirty-third via hole.
  • the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 113 of the eleventh transistor are an integrated structure.
  • the integrated structure of the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 113 of the eleventh transistor is in a zigzag shape and at least partially extends along the second direction D2.
  • the second electrode 24 of the second transistor (also the second electrode 34 of the third transistor and the first electrode 113 of the eleventh transistor) is connected to the second region of the active pattern of the second transistor through the fourth via, connected to the second region of the active pattern of the third transistor through the sixth via, connected to the first region of the active pattern of the eleventh transistor through the nineteenth via, and connected to the gate electrode of the fifth transistor through the thirty-seventh via.
  • the first electrode 33 of the third transistor is separately provided.
  • the first electrode 33 of the third transistor is in the shape of a strip and extends along the second direction D2.
  • the first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through the fifth via hole, and is connected to the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) through the forty-second via hole.
  • the first electrode 43 of the fourth transistor is separately provided.
  • the first electrode 43 of the fourth transistor is in the shape of a strip and at least partially extends along the second direction D2.
  • the first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through the seventh via hole and is connected to the first connection portion through the forty-seventh via hole.
  • the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor are separately provided as an integral structure.
  • the shape of the integral structure of the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor is a broken line, and at least partially extends along the second direction D2.
  • the second electrode 44 of the fourth transistor (also the second electrode 54 of the fifth transistor) is connected to the second area of the active pattern of the fourth transistor through the eighth via hole, connected to the second area of the active pattern of the fifth transistor through the tenth via hole, and connected to the second plate of the third capacitor through the fiftieth via hole.
  • the first electrode 53 of the fifth transistor, the first electrode 83 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 133 of the thirteenth transistor are an integrated structure, and the integrated structure of the first electrode 53 of the fifth transistor, the first electrode 83 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 133 of the thirteenth transistor is a zigzag shape, and at least partially extends along the second direction D2.
  • the first electrode 53 of the fifth transistor (also the first electrode 83 of the eighth transistor, the first electrode 83 of the ninth transistor, and the first electrode 133 of the thirteenth transistor) is connected to the first area of the active pattern of the fifth transistor (also the first area of the active pattern of the eighth transistor and the first area of the active pattern of the thirteenth transistor) through the ninth via hole, connected to the first area of the active pattern of the ninth transistor through the fifteenth via hole, and connected to the second plate of the second capacitor through the forty-ninth via hole.
  • the first electrode 63 of the sixth transistor is separately provided.
  • the first electrode 63 of the sixth transistor is in an “I” shape.
  • the first electrode 63 of the sixth transistor is connected to the first region of the active pattern of the sixth transistor through the eleventh via hole, and is connected to the gate electrode of the seventh transistor through the thirty-ninth via hole.
  • the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor are an integrated structure.
  • the shape of the integrated structure of the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor is The second electrode 64 of the sixth transistor (also the first electrode 73 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor through the twelfth via hole, connected to the first region of the active pattern of the seventh transistor through the thirteenth via hole, and connected to the second plate of the first capacitor through the forty-eighth via hole.
  • the second electrode 74 of the seventh transistor and the first electrode 84 of the eighth transistor are an integrated structure.
  • the integrated structure of the second electrode 74 of the seventh transistor and the first electrode 84 of the eighth transistor is in the shape of a strip and extends along the first direction D1.
  • the second electrode 74 of the seventh transistor (also the first electrode 84 of the eighth transistor) is connected to the second region of the active pattern of the seventh transistor (also the second region of the active pattern of the eighth transistor) through the fourteenth via hole, and is connected to the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) through the fortieth via hole.
  • the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor are an integrated structure.
  • the shape of the integrated structure of the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor is a “ ⁇ ” shape.
  • the second electrode 94 of the ninth transistor (also the first electrode 104 of the tenth transistor) is connected to the second region of the active pattern of the ninth transistor through the sixteenth via, connected to the second region of the active pattern of the tenth transistor through the eighteenth via, and connected to the second plate of the fourth capacitor through the fifty-first via.
  • the first electrode 103 of the tenth transistor may be provided separately.
  • the first electrode 103 of the tenth transistor is in a zigzag shape and at least partially extends along the second direction D2.
  • the first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor through the seventeenth via hole, connected to the gate electrode of the twelfth transistor through the forty-third via hole, and connected to the first plate of the fourth capacitor through the forty-sixth via hole.
  • the second electrode 114 of the eleventh transistor may be provided separately.
  • the second electrode 114 of the eleventh transistor is in the shape of a broken line and at least partially extends along the second direction D2.
  • the second electrode 114 of the eleventh transistor is connected to the second region of the active pattern of the eleventh transistor through the twentieth via hole, and is connected to the gate electrode (the first plate of the first capacitor) of the sixth transistor through the thirty-eighth via hole.
  • the first electrode 123 of the twelfth transistor may be provided separately.
  • the first electrode 123 of the twelfth transistor is in a strip shape and extends along the first direction D1.
  • the first electrode 123 of the twelfth transistor is connected to the first region of the active pattern of the twelfth transistor through the twenty-first via hole, and is connected to the second connection portion through the fifty-second via hole.
  • the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor are an integrated structure.
  • the integrated structure of the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor is in a strip shape and extends along the first direction D1.
  • the second electrode 124 of the twelfth transistor (also the first electrode 164 of the sixteenth transistor) is connected to the second region of the active pattern of the twelfth transistor (also the second region of the active pattern of the sixteenth transistor) through the twenty-second via hole, and is connected to the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) through the forty-first via hole.
  • the second electrode 134 of the thirteenth transistor may be provided separately.
  • the second electrode 134 of the thirteenth transistor is in the shape of a strip and extends along the first direction D1.
  • the second electrode 134 of the thirteenth transistor is connected to the second region of the active pattern of the thirteenth transistor through the twenty-third via hole, connected to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the thirty-fourth via hole, and connected to the second connection portion through the fifty-second via hole.
  • the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor are an integrated structure.
  • the integrated structure of the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor is in the shape of a right-rotated “J”.
  • the second electrode 144 of the fourteenth transistor (also the first electrode 153 of the fifteenth transistor) is connected to the second region of the active pattern of the fourteenth transistor through the twenty-fifth via hole, and is connected to the first region of the active pattern of the fifteenth transistor through the twenty-sixth via hole.
  • the second electrode 154 of the fifteenth transistor may be provided separately.
  • the second electrode 154 of the fifteenth transistor is in the shape of a strip and extends along the second direction D2.
  • the second electrode 154 of the fifteenth transistor is connected to the second region of the active pattern of the fifteenth transistor through the twenty-seventh via hole, and is connected to the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through the thirty-sixth via hole.
  • the first electrode 163 of the sixteenth transistor may be provided separately.
  • the first electrode 163 of the sixteenth transistor is in the shape of a strip and extends along the first direction D1.
  • the first electrode 163 of the sixteenth transistor is connected to the first region of the active pattern of the sixteenth transistor through the twenty-eighth via hole, and is connected to the gate electrode of the fourth transistor (also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through the thirty-sixth via hole.
  • the first electrode 173 of the seventeenth transistor may be provided separately.
  • the first electrode 173 of the seventeenth transistor includes: a fourth connection segment 173A and at least one fourth branch segment 173B, at least one fourth branch segment 173B is located on the side of the fourth connection segment 173A close to the display area and is connected to the fourth connection segment 173A.
  • the first electrode 173 of the seventeenth transistor is in a comb-like structure, the shape of the fourth connection segment 173A is a " ⁇ " shape, which is equivalent to a "comb back", the fourth branch segment 173B extends along the first direction D1, and at least one fourth branch segment 173B is arranged along the second direction D2, which is equivalent to a "comb tooth”.
  • the first electrode 173 of the seventeenth transistor is connected to the first area of the active pattern of the seventeenth transistor through the twenty-ninth via.
  • the second electrode 174 of the seventeenth transistor and the first electrode 183 of the eighteenth transistor are an integrated structure.
  • the shape of the integrated structure of the second electrode 174 of the seventeenth transistor and the first electrode 183 of the eighteenth transistor is a comb-like structure.
  • the integrated structure of the second electrode 174 of the seventeenth transistor and the first electrode 183 of the eighteenth transistor includes: a fifth connecting segment 174A and at least one fifth branch segment 174B, at least one fifth branch segment 174B is connected to the fifth connecting segment 174A, and is located on the side of the fifth connecting segment 174A away from the display area, the fifth connecting segment 174A is in the shape of a strip and extends along the second direction D2, which is equivalent to a "comb back", at least one fifth branch segment 174B is in the shape of a strip and extends along the first direction D1, and at least one fifth branch segment 174B is arranged along the second direction D2, which is equivalent to a "comb tooth".
  • the second electrode 174 of the seventeenth transistor (also the first electrode 183 of the eighteenth transistor) is connected to the second region of the active pattern of the seventeenth transistor (also the first region of the active pattern of the eighteenth transistor) through the thirtieth via hole.
  • the second electrode 184 of the eighteenth transistor and the second electrode 194 of the nineteenth transistor are an integrated structure.
  • the shape of the integrated structure of the second electrode 184 of the eighteenth transistor and the second electrode 194 of the nineteenth transistor is a comb-like structure.
  • the integrated structure of the second electrode 184 of the eighteenth transistor and the second electrode 194 of the nineteenth transistor includes: a sixth connecting segment 184A and at least one sixth branch segment 184B, at least one sixth branch segment 184B is connected to the sixth connecting segment 184A and is located on the side of the sixth connecting segment 184A close to the display area, the sixth connecting segment 184A is in the shape of a strip and extends along the second direction D2, which is equivalent to a "comb back", and at least one sixth branch segment 184B is in the shape of a strip and extends along the first direction D1, and at least one sixth branch segment 184B is arranged along the second direction D2, which is equivalent to a "comb tooth”.
  • the second electrode 184 of the eighteenth transistor (also the second electrode 194 of the nineteenth transistor) is connected to the second region of the active pattern of the eighteenth transistor (also the second region of the active pattern of the nineteenth transistor) through the thirty-first via hole.
  • the first electrode 193 of the nineteenth transistor may be provided separately.
  • the first electrode 193 of the nineteenth transistor is shaped like an “n” rotated to the left, and its opening is away from the display area.
  • the first electrode 193 of the nineteenth transistor is connected to the first area of the active pattern of the nineteenth transistor through the thirty-second via hole.
  • the third connection portion L3 is provided separately.
  • the third connection portion L3 is in the shape of a strip and extends along the second direction D2.
  • the third connection portion L3 is connected to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the thirty-third via hole.
  • the fourth connection portion L4 is provided separately.
  • the fourth connection portion L4 is in a strip shape and extends along the second direction D2.
  • the fourth connection portion L4 is connected to the gate electrode of the seventh transistor through the thirty-ninth via hole.
  • the fifth connection portion L5 is provided separately.
  • the fifth connection portion L5 is in a strip shape and extends along the second direction D2.
  • the fifth connection portion L5 is connected to the gate electrode of the third transistor through the thirty-fifth via hole.
  • the sixth connection portion L6 is provided separately.
  • the sixth connection portion L6 is in a strip shape and extends along the second direction D2.
  • the sixth connection portion L6 is connected to the gate electrode of the seventh transistor through the thirty-ninth via hole.
  • the seventh connection portion L7 is provided separately.
  • the seventh connection portion L7 is in a strip shape and extends along the first direction D1.
  • the seventh connection portion L7 is connected to the gate electrode of the thirteenth transistor through the forty-fourth via hole.
  • the eighth connection portion L8 is provided separately.
  • the eighth connection portion L8 is in a strip shape and extends along the second direction D2.
  • the eighth connection portion L8 is connected to the gate electrode of the nineteenth transistor through the forty-fifth via hole.
  • Forming a fourth insulating layer pattern may include:
  • a fourth insulating film is deposited on the substrate formed with the aforementioned pattern, and the fourth insulating film is composed through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure.
  • the fourth insulating layer is provided with a plurality of via patterns, as shown in FIG36 , which is a schematic diagram after the fourth insulating layer pattern is formed in FIG26 .
  • the fourth insulation layer pattern of each shift register may include at least a fifty-second via hole V52 to a sixty-fourth via hole V64 .
  • the orthographic projection of the fifty-second via hole V52 on the substrate is located within the range of the orthographic projection of the third connection portion on the substrate, the fifty-second via hole V52 exposes the surface of the third connection portion, and the fifty-second via hole V52 is configured to connect one of the first clock signal line and the second clock signal line formed subsequently to the third connection portion through the via hole.
  • FIG36 is described by taking the fifty-second via hole V52 configured to connect the first clock signal line formed subsequently to the third connection portion through the via hole as an example.
  • the orthographic projection of the fifty-third via hole V53 on the substrate is located within the range of the orthographic projection of the fifth connecting portion on the substrate, the fifty-third via hole V53 exposes the surface of the fifth connecting portion, and the fifty-third via hole V53 is configured to connect one of the first clock signal line and the second clock signal line formed subsequently to the fifth connecting portion through the via hole.
  • FIG36 is described by taking the fifty-third via hole V53 configured to connect the first clock signal line formed subsequently to the fifth connecting portion through the via hole as an example.
  • the orthographic projection of the fifty-fourth via hole V54 on the substrate is located within the range of the orthographic projection of the first electrode of the fourth transistor on the substrate, the fifty-fourth via hole V54 exposes the surface of the first electrode of the fourth transistor, and the fifty-fourth via hole V54 is configured to connect the other signal line of the first clock signal line and the second clock signal line formed subsequently to the first electrode of the fourth transistor through the via hole.
  • FIG36 is described by taking the fifty-fourth via hole V54 as an example in which the second clock signal line formed subsequently is connected to the first electrode of the fourth transistor through the via hole.
  • the orthographic projection of the fifty-fifth via hole V55 on the substrate is located within the range of the orthographic projection of the fourth connection portion on the substrate, the fifty-fifth via hole V55 exposes the surface of the fourth connection portion, and the fifty-fifth via hole V55 is configured to connect the other signal line of the first clock signal line and the second clock signal line formed subsequently to the fourth connection portion through the via hole.
  • FIG36 is described by taking the fifty-fifth via hole V55 as an example in which the second clock signal line formed subsequently is connected to the fourth connection portion through the via hole.
  • the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the first electrode of the third transistor on the substrate, the fifty-sixth via V56 exposes the surface of the first electrode of the third transistor, and the fifty-sixth via V56 is configured to connect a subsequently formed first second power line to the first electrode of the third transistor through the via.
  • the orthographic projection of the fifty-seventh via V57 on the substrate is located within the range of the orthographic projection of the second pole of the fourth transistor (also the second pole of the fifth transistor) on the substrate, the fifty-seventh via V57 exposes the surface of the second pole of the fourth transistor (also the second pole of the fifth transistor), and the fifty-seventh via V57 is configured to connect the subsequently formed ninth connection portion to the second pole of the fourth transistor (also the second pole of the fifth transistor) through the via.
  • the orthographic projection of the fifty-eighth via V58 on the substrate is located within the range of the orthographic projection of the sixth connecting portion on the substrate, the fifty-eighth via V58 exposes the surface of the sixth connecting portion, and the fifty-eighth via V58 is configured to connect a subsequently formed third power line to the sixth connecting portion through the via.
  • the orthographic projection of the fifty-ninth via V59 on the substrate is located within the range of the orthographic projection of the seventh connecting portion on the substrate, the fifty-ninth via V59 exposes the surface of the seventh connecting portion, and the fifty-ninth via V59 is configured to connect a subsequently formed third power line to the seventh connecting portion through the via.
  • the orthographic projection of the sixtieth via hole V60 on the substrate is located within the range of the orthographic projection of the first electrode of the tenth transistor on the substrate, the sixtieth via hole V60 exposes the surface of the first electrode of the tenth transistor, and the sixtieth via hole V60 is configured to connect a second second power line formed subsequently to the first electrode of the tenth transistor through the via hole.
  • the orthographic projection of the sixty-first via V61 on the substrate is located within the range of the orthographic projection of the first electrode of the seventeenth transistor on the substrate, the sixty-first via V61 exposes the surface of the first electrode of the seventeenth transistor, and the sixty-first via V61 is configured to connect a subsequently formed second second power line to the first electrode of the seventeenth transistor through the via.
  • the orthographic projection of the sixty-second via V62 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) on the substrate, the sixty-second via V62 exposes the surface of the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor), and the sixty-second via V62 is configured to connect a subsequently formed first power line to the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) through the via.
  • the orthographic projection of the sixty-third via V63 on the substrate is located within the range of the orthographic projection of the first electrode of the nineteenth transistor on the substrate, the sixty-third via V63 exposes the surface of the first electrode of the nineteenth transistor, and the sixty-third via V63 is configured to connect a subsequently formed first power line to the first electrode of the nineteenth transistor through the via.
  • the orthographic projection of the sixty-fourth via hole V64 on the substrate is located within the range of the orthographic projection of the eighth connecting portion on the substrate, the sixty-fourth via hole V64 exposes the surface of the eighth connecting portion, and the sixty-fourth via hole V64 is configured to connect a subsequently formed scanning control signal line to the eighth connecting portion through the via hole.
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 37 and 38 , where FIG. 37 is a schematic diagram of the fourth conductive layer pattern in FIG. 26 , and FIG. 38 is a schematic diagram of FIG. 26 after the fourth conductive layer pattern is formed.
  • the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.
  • SD2 second source-drain metal
  • the fourth conductive layer pattern located in each shift register may include at least: a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, two second power lines VGL, a third power line VCX, a scan control signal line MSL and a ninth connection portion L9.
  • the first clock signal line CLK1, the second clock signal line CLK2, the first second power line VGL, the third power line VCX, the second second power line VGL, the first power line VGH and the scan control signal line MSL are sequentially arranged in a direction close to the display area.
  • the ninth connection portion L9 is located between the first second power line VGL and the third power line VCX.
  • the first clock signal line CLK1 may be in a line shape with a main portion extending along the second direction D2.
  • the first clock signal line CLK1 is connected to the third connection portion through the fifty-second via hole and to the fifth connection portion through the fifty-third via hole.
  • the second clock signal line CLK2 may be in the shape of a line whose main portion extends along the second direction D2.
  • the second clock signal line CLK2 is connected to the first electrode of the fourth transistor through the fifty-fourth via hole and to the fourth connection portion through the fifty-fifth via hole.
  • the shape of the first second power line VGL may be a line shape in which the main body portion extends along the second direction D2.
  • the first second power line VGL is connected to the first electrode of the fourth transistor through the fifty-sixth via hole and is connected to the first electrode of the third transistor through the fifty-fifth via hole.
  • the third power line VCX may be in a line shape with a main portion extending along the second direction D2.
  • the third power line VCX is connected to the sixth connection portion through the fifty-eighth via hole and to the seventh connection portion through the fifty-ninth via hole.
  • the second second power line VGL may be in the shape of a line whose main body portion extends along the second direction D2.
  • the second second power line VGL is connected to the first electrode of the tenth transistor through the sixtieth via hole and to the first electrode of the seventeenth transistor through the sixty-first via hole.
  • the shape of the first power line VGH may be a line shape in which the main body portion extends along the second direction D2.
  • the first power line VGH is connected to the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) through the sixty-second via hole, and is connected to the first electrode of the nineteenth transistor through the sixty-third via hole.
  • the shape of the scan control signal line MSL may be a line shape in which a main portion extends along the second direction D2.
  • the scan control signal line MSL is connected to the eighth connection portion through the sixty-fourth via hole.
  • the line width of the scan control signal line MSL is smaller than the line width of any one of the first power line VGH and the second power line VGL.
  • the line width of the third power line VCX is smaller than the line width of any one signal line of the first power line VGH and the second power line VGL.
  • the line width of the first clock signal line CLK1 and the second clock signal line CLK2 is smaller than the line width of any one of the first power line VGH and the second power line VGL.
  • Forming a planar layer may include: depositing a fifth insulating film on the substrate having the aforementioned pattern, coating a planar film, and patterning the fifth insulating film and the planar film by a patterning process to form a fifth insulating layer pattern covering the aforementioned structure and a planar layer pattern covering the fifth insulating layer pattern.
  • the drive circuit layer is prepared on the substrate.
  • the drive circuit layer may include a plurality of shift registers, and the shift registers are electrically connected to the first clock signal line, the second clock signal line, the first power line, the second power line, the third power line and the scan control signal line.
  • the drive circuit layer may be arranged on the substrate, and the substrate may include a first flexible layer, a barrier layer, a substrate conductive layer and a second flexible layer stacked.
  • the drive circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer and a flat layer sequentially arranged on the substrate.
  • the semiconductor layer may include at least active patterns of the first transistor to the nineteenth transistor, the first conductive layer may include at least gate electrodes of the first transistor to the nineteenth transistor and the first plate of the first capacitor to the first plate of the fourth capacitor, the second conductive layer may include at least the second plate of the first capacitor to the second plate of the fourth capacitor, the third conductive layer may include at least the first electrode and the second electrode of any transistor among the first transistor to the nineteenth transistor, and the fourth conductive layer may include at least: a first clock signal line, a second clock signal line, a first power line, a second power line, a third power line and a scan control signal line.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc.
  • the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, the first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).
  • its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.
  • PI1 first flexible
  • a-si amorphous silicon
  • the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer.
  • the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc.
  • the metal oxide layer may be a single layer, a double layer, or a multilayer.
  • the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • metal materials such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.
  • the first insulating layer and the second insulating layer may be referred to as a gate insulating (GI) layer
  • the third insulating layer may be referred to as an interlayer insulating (ILD) layer
  • the fourth insulating layer may be referred to as a passivation (PVX) layer.
  • the planar layer and the planar layer may employ an organic material such as a resin or the like.
  • a light emitting structure layer is prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode conductive layer pattern arranged on the second flat layer;
  • a pixel definition film is deposited, and the pixel definition film is patterned by a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern;
  • an organic light-emitting material is coated, and the organic light-emitting material is patterned by a patterning process to form an organic structure layer pattern;
  • a cathode conductive film is deposited, and the cathode conductive film is patterned by a patterning process to form a cathode conductive layer.
  • the light-emitting structure layer is prepared on the substrate.
  • the anode conductive layer includes at least a plurality of anode patterns, wherein the plurality of anode patterns may include an anode of a first light emitting device, an anode of a second light emitting device, an anode of a third light emitting device, and an anode of a fourth light emitting device, wherein the anode of the first light emitting device is located at a red sub-pixel emitting red light, the anode of the second light emitting device may be located at a blue sub-pixel emitting blue light, the anode of the third light emitting device may be located at a first green sub-pixel emitting green light, and the anode of the fourth light emitting device may be located at a second green sub-pixel emitting green light.
  • the plurality of anode patterns may include an anode of a first light emitting device, an anode of a second light emitting device, an anode of a third light emitting device, and an anode of a fourth light
  • the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed along the first direction D1
  • the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed along the first direction D1.
  • the anode of the first light emitting device and the anode of the second light emitting device may be alternately disposed along the second direction D2
  • the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately disposed along the second direction D2.
  • the shapes and areas of anode electrodes of four sub-pixels in one pixel unit may be the same, or may be different.
  • the anode conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • the organic structure layer may include at least: an organic light emitting layer of a light emitting device.
  • the cathode conductive layer may include at least: cathodes of a plurality of light emitting devices.
  • the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo/Cu/Mo, etc.
  • the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.
  • the display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.
  • the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.
  • the embodiment of the present disclosure further provides a display device, which may include: a display substrate.
  • the display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.
  • the display device may be any product or component having a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.
  • the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element may be “directly” “on” or “under” the other element, or there may be intermediate elements.

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Abstract

一种移位寄存器及其驱动方法、显示基板和显示装置，移位寄存器包括：级联输出子电路和扫描输出子电路；级联输出子电路被配置为在信号输入端(IN)、第一时钟信号端(CK1)和第二时钟信号端(CK2)的信号的控制下，向第一节点(N1)和第二节点(N2)提供信号，在第一节点(N1)和第二节点(N2)的信号的控制下，向级联输出端(COUT)提供第一电源端(V1)或第二电源端(V2)的信号；扫描输出子电路被配置为在第一节点(N1)、第二节点(N2)和扫描控制信号端(MS)的信号的控制下，向扫描输出端(NOUT)提供第一电源端(V1)或者第二电源端(V2)的信号。

Description

移位寄存器及其驱动方法、显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种移位寄存器及其驱动方法、显示基板和显示装置。
 背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film TransiTor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种移位寄存器，包括：级联输出子电路和扫描输出子电路；
所述级联输出子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一电源端、第二电源端、级联输出端、第一节点和第二节点电连接，被配置为在信号输入端、第一时钟信号端和第二时钟信号端的信号的控制下，向第一节点和第二节点提供信号，在第一节点和第二节点的信号的控制下，向级联输出端提供第一电源端或第二电源端的信号；
所述扫描输出子电路，分别与扫描控制信号端、第一电源端、第二电源端、扫描输出端、第一节点和第二节点电连接，被配置为在第一节点、第二节点和扫描控制信号端的信号的控制下，向扫描输出端提供第一电源端或者第二电源端的信号。
在示例性实施方式中，所述扫描输出子电路包括：第一输出控制子电路和第二输出控制子电路；
所述第一输出控制子电路，分别与第二电源端、扫描输出端和第二节点电连接，被配置为在第二节点的信号的控制下，向扫描输出端提供第二电源端的信号；
所述第二输出控制子电路，分别与扫描控制信号端、第一电源端、扫描输出端和第一节点电连接，被配置为在扫描控制信号端和第一节点的信号的控制下，向扫描输出端提供第一电源端的信号。
在示例性实施方式中，所述扫描输出子电路还包括：存储子电路；
存储子电路，分别与扫描输出端和第一电源端电连接，被配置为存储扫描输出端和第一电源端的信号之间的电压差。
在示例性实施方式中，所述第一输出控制子电路包括：第十七晶体管；
第十七晶体管的控制极与第二节点电连接，第十七晶体管的第一极与第二电源端电连接，第十七晶体管的第二极与扫描输出端电连接。
在示例性实施方式中，所述第二输出控制子电路包括：第十八晶体管和第十九晶体管；
第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与第一电源端电连接，第十八晶体管的第二极与第三节点电连接；
第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与扫描输出端电连接，第十九晶体管的第二极与第三节点电连接。
在示例性实施方式中，所述第二输出控制子电路包括：第十八晶体管和第十九晶体管；
第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与扫描输出端电连接，第十八晶体管的第二极与第三节点电连接；
第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与第一电源端电连接，第十九晶体管的第二极与第三节点电连接。
在示例性实施方式中，所述存储子电路包括：第五电容；
第五电容的第一极板与扫描输出端电连接，第五电容的第二极板与第一电源端电连接。
在示例性实施方式中，所述级联输出子电路包括：第一晶体管至第十六晶体管以及第一电容至第四电容，第一电容至第四电容中的任一电容包括：第一极板和第二极板；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第四节点电连接；
第二晶体管的控制极与第四节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第五节点电连接；
第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第五节点电连接；
第四晶体管的控制极与第六节点电连接，第四晶体管的第一极与第二时钟信号端电连接，第四晶体管的第二极与第七节点电连接；
第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一电源端电连接，第五晶体管的第二极与第七节点电连接；
第六晶体管的控制极与第九节点电连接，第六晶体管的第一极与第二时钟信号端电连接，第六晶体管的第二极与第八节点电连接；
第七晶体管的控制极与第二时钟信号端电连接，第七晶体管的第一极与第八节点电连接，第七晶体管的第二极与第一节点电连接；
第八晶体管的控制极与第四节点电连接，第八晶体管的第一极与第一电源端电连接，第八晶体管的第二极与第一节点电连接；
第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第一电源端电连接，第九晶体管的第二极与级联输出端电连接；
第十晶体管的控制极与第二节点电连接，第十晶体管的第一极与第二电源端电连接，第十晶体管的第二极与级联输出端电连接；
第十一晶体管的控制极与第二电源端电连接，第十一晶体管的第一极与第五节点电连接，第十一晶体管的第二极与第九节点电连接；
第十二晶体管的控制极与第二电源端电连接，第十二晶体管的第一极与第四节点电连接，第十二晶体管的第二极与第二节点电连接；
第十三晶体管的控制极与第三电源端电连接，第十三晶体管的第一极与第一电源端电连接，第十三晶体管的第二极与第四节点电连接；
第十四晶体管的控制极与第一时钟信号端电连接，第十四晶体管的第一极与信号输入端电连接，第十四晶体管的第二极与第十节点电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第十节点电连接，第十五晶体管的第二极与第六节点电连接；
第十六晶体管的控制极与第六节点电连接，第十六晶体管的第一极与第六节点电连接，第十六晶体管的第二极与第二节点电连接；
第一电容的第一极板与第九节点电连接，第一电容的第二极板与第八节点电连接；
第二电容的第一极板与第一节点电连接，第二电容的第二极板与第一电源端电连接；
第三电容的第一极板与第六节点电连接，第三电容的第二极板与第七节点电连接；
第四电容的第一极板与第二电源端电连接，第四电容的第二极板与级联输出端电连接。
在示例性实施方式中，所述扫描输出子电路包括：第十七晶体管至第十九晶体管，或者，包括：十七晶体管至第十九晶体管和第五电容；
第十七晶体管的控制极与第二节点电连接，第十七晶体管的第一极与第二电源端电连接，第十七晶体管的第二极与扫描输出端电连接；
第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与第一电源端电连接，第十八晶体管的第二极与第三节点电连接；
第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与扫描输出端电连接，第十九晶体管的第二极与第三节点电连接；
第五电容的第一极板与扫描输出端电连接，第五电容的第二极板与第一电源端电连接。
在示例性实施方式中，所述扫描输出子电路包括：第十七晶体管至第十九晶体管，或者包括：十七晶体管至第十九晶体管和第五电容；
第十七晶体管的控制极与第二节点电连接，第十七晶体管的第一极与第二电源端电连接，第十七晶体管的第二极与扫描输出端电连接；
第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与扫描输出端电连接，第十八晶体管的第二极与第三节点电连接；
第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与第一电源端电连接，第十九晶体管的第二极与第三节点电连接；
第五电容的第一极板与扫描输出端电连接，第五电容的第二极板与第一电源端电连接。
第二方面，本公开还提供了一种显示基板，包括：位于所述非显示区的栅极驱动电路和位于所述显示区的阵列排布的子像素和多条栅线，所述子像素包括像素驱动电路和发光器件，所述栅线至少部分沿第一方向延伸，所述栅极驱动电路包括：多个级联的上述移位寄存器，所述像素驱动电路包括：多个晶体管；
至少一级移位寄存器的级联输出端与至少一级移位寄存器的信号输入端电连接。
所述栅线与所述至少一个晶体管的栅电极电连接，任一移位寄存器与至少一条栅线电连接。
在示例性实施方式中，所述显示区被划分为多个显示子区，至少一个显示子区包括：至少一条栅线；任一个显示子区的显示模式包括：第一显示模式和第二显示模式，第一显示模式的刷新频率大于第二显示模式的刷新频率；
在显示子区的显示模式为第一显示模式的状态下，对于与显示子区内的栅线所连接的移位寄存器，级联输出端的信号为第一电平信号时，扫描控制信号端的信号的至少部分时间段为有效电平信号，扫描输出端的信号为第一电平信号；
在显示子区的显示模式为第二显示模式的状态下，对于与显示子区内的栅线所连接的移位寄存器，级联输出端的信号为第一电平信号时，扫描控制信号端的信号为无效电平信号，扫描输出端的信号为第二电平信号；
其中，所述第一电平信号的电压值大于所述第二电平信号的电压值。
在示例性实施方式中，还包括：位于所述非显示区的至少一条扫描控制信号线，所述扫描控制信号线至少部分沿第二方向延伸，所述第一方向和所述第二方向相交；
所有移位寄存器所连接的扫描控制信号端与所述至少一条扫描控制信号线电连接。
在示例性实施方式中，所述扫描控制信号线的数量为一条，
所有移位寄存器所连接的扫描控制信号端与同一扫描控制信号线电连接。
在示例性实施方式中，所述扫描控制信号线的数量为至少两条；
第M*(k-1)+K*M(a-1)+1级移位寄存器至k*M+K*M(a-1)级移位寄存器中的任一移位寄存器所连接的扫描控制信号端与第k条扫描控制信号线电连接，1≤k≤K，1≤a≤N/M，M为一条扫描控制信号线所连接的移位寄存器的级数，N为移位寄存器的总级数，K为扫描控制信号线的数量。
在示例性实施方式中，显示基板所显示画面包括：多个显示帧，在任一显示帧，所述移位寄存器的扫描输出端的输出信号为脉冲信号，且脉冲信号的持续时间H满足如下关系式；H＝L*[M*K-(M-1)]*h
其中，L为任一级移位寄存器所连接的栅线的数量，h为单位时间，且等于相邻行子像素的刷新间隔时间。
在示例性实施方式中，还包括：位于所述非显示区的第一时钟信号线、第二时钟信号线、第一电源线、第二电源线和第三电源线；所述第一时钟信号线、所述第二时钟信号线、所述第一电源线、所述第二电源线和所述第三电源线中的任一条至少部分沿所述第二方向延伸；
任一级移位寄存器所连接的第一时钟信号端与第一时钟信号线和第二时钟信号线的其中一条电连接，任一级移位寄存器所连接的第二时钟信号端与第一时钟信号线和第二时钟信号线的另一条电连接，相邻移位寄存器所连接的第一时钟信号端所连接的时钟信号线不同，相邻移位寄存器所连接的第二时钟信号端所连接的时钟信号线不同，所有移位寄存器所连接的第一电源端与所述第一电源线电连接，所有移位寄存器所连接的第二电源端与所述第二电源线电连接，所有移位寄存器所连接的第三电源端与所述第三电源线电连接。
在示例性实施方式中，所述扫描控制信号线位于所述第一时钟信号线、所述第二时钟信号线、所述第一电源线、所述第二电源线和所述第三电源线中的任一条靠近所述显示区的一侧。
在示例性实施方式中，所述第二电源线的数量为两条，所述第一时钟信号线、所述第二时钟信号线、第一条第二电源线、所述第三电源线、第二条第二电源线和所述第一电源线沿靠近所述显示区的方向依次排布。
在示例性实施方式中，所述移位寄存器包括：第十七晶体管至第十九晶体管；第十七晶体管至第十九晶体管沿所述第二方向排布；
所述第十七晶体管至第十九晶体管中的任一个晶体管的至少部分位于所述第一电源线和所述扫描控制信号线之间。
在示例性实施方式中，任一晶体管包括：有源图案，所述第十七晶体管的有源图案沿第一方向的平均长度小于所述第十八晶体管和所述第十九晶体管的任一晶体管的有源图案沿第一方向的平均长度。
在示例性实施方式中，所述第一电源线和所述第二电源线中的任一电源线的线宽大于所述扫描控制信号线的线宽。
第三方面，本公开还提供了一种显示装置，包括：上述显示基板。
第四方面，本公开还提供了一种移位寄存器的驱动方法，被配置为驱动上述移位寄存器，所述方法包括：
级联输出子电路在信号输入端、第一时钟信号端和第二时钟信号端的信号的控制下，向第一节点和第二节点提供信号，在第一节点和第二节点的信号的控制下，向级联输出端提供第一电源端或第二电源端的信号；
扫描输出子电路在第一节点、第二节点和扫描控制信号端的信号的控制下，向扫描输出端提供第一电源端或者第二电源端的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的移位寄存器的结构示意图；
图2为一种示例性实施方式提供的移位寄存器的结构示意图；
图3为一种示例性实施方式提供的移位寄存器的结构示意图；
图4为一种示例性实施方式提供的第一输出控制子电路的等效电路图；
图5为一种示例性实施方式提供的第二输出控制子电路的等效电路图；
图6为另一示例性实施方式提供的第二输出控制子电路的等效电路图；
图7为一种示例性实施方式提供的存储子电路的等效电路图；
图8为一种示例性实施方式提供的级联输出子电路的等效电路图；
图9为一种移位寄存器的等效电路图一；
图10为一种移位寄存器的等效电路图二；
图11为一种移位寄存器的等效电路图三；
图12为一种移位寄存器的等效电路图四；
图13为图9至图12提供的移位寄存器中的级联输出子电路的时序图；
图14为图9至图12提供的移位寄存器中的扫描输出子电路的时序图一；
图15为图9至图12提供的移位寄存器中的扫描输出子电路的时序图二；
图16为图9至图12提供的移位寄存器中的扫描输出子电路的时序图三；
图17为图9至图12提供的移位寄存器中的扫描输出子电路的时序图四；
图18为一种显示基板的结构示意图；
图19为栅极驱动电路的级联示意图一；
图20为栅极驱动电路的级联示意图二；
图21为一种像素驱动电路的等效电路示意图；
图22为另一像素驱动电路的等效电路示意图；
图23为图21和图22提供的像素驱动电路的工作时序图；
图24为图19提供的栅极驱动电路的多个扫描输出端的时序图；
图25为图20提供的栅极驱动电路的多个扫描输出端的时序图；
图26为显示基板的非显示区的局部示意图；
图27为第十七晶体管至第十九晶体管的有源图案的示意图；
图28为图26形成半导体层图案后的示意图；
图29为图26中第一导电层图案的示意图；
图30为图26形成第一导电层图案后的示意图；
图31为图26中的第二导电层图案的示意图；
图32为图26形成第二导电层图案后的示意图；
图33为图26形成第三绝缘层图案后的示意图；
图34为图26中的第三导电层图案的示意图；
图35为图26形成第三导电层图案后的示意图；
图36为图26形成第四绝缘层图案后的示意图；
图37为图26中的第四导电层图案的示意图；
图38为图26形成第四导电层图案后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
显示基板包括：像素电路、发光器件和栅极驱动电路，其中，栅极驱动电路设置为向像素电路提供栅极信号，以使得像素电路可以驱动发光器件发光。栅极驱动电路的驱动能力较弱，无法满足显示需求。
在显示市场中，大多数显示基板中所用的是低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)技术，LTPS技术拥有高分辨率、高反应速度、高亮度、高开口率等优势。尽管受到了市场欢迎，但LTPS技术也存在一些缺陷，如生产成本较高，所需功耗较大等，此时，低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)技术方案应运而生。相比于LTPS技术，LTPO技术的漏电流更小，像素点反应更快，显示基板多加了一层氧化物，降低了激发像素点所需的能耗，从而降低屏幕显示时的功耗。
显示产品包括：栅极驱动电路和多个子像素。子像素包括像素驱动电路，显示产品显示画面时，栅极驱动电路生成驱动信号，像素驱动电路在驱动信号的控制下，进行初始化和数据写入，从而实现显示。显示产品显示时会在每一帧刷新面面，即在每一显示帧都需要对像素驱动电路进行初始化和数据写入。而对于一些特殊画面下(例如：熄屏显示画面、静态画面或较少更新的画面等)，在至少部分显示帧中并不需要对像素驱动电路进行初始化和数据写入，可以通过低漏电的像素驱动电路即可维持原有的亮度。一种显示产品的栅极驱动电路无论在显示哪种画面都会在每一帧生成驱动信号，对像素驱动电路进行反复初始化和数据写入，使得显示产品的功耗较高。
图1为本公开实施例提供的移位寄存器的结构示意图。如图1所示，本公开实施例提供的移位寄存器可以包括：级联输出子电路和扫描输出子电路。
如图1所示，级联输出子电路，分别与信号输入端IN、第一时钟信号端CK1、第二时钟信号端CK2、第一电源端V1、第二电源端V2、级联输出端COUT、第一节点N1和第二节点N2电连接，被配置为在信号输入端IN、第一时钟信号端CK1和第二时钟信号端CK2的信号的控制下，向第一节点N1和第二节点N2提供信号，在第一节点N1和第二节点N2的信号的控制下，向级联输出端COUT提供第一电源端V1或第二电源端V2的信号；扫描输出子电路，分别与扫描控制信号端MS、第一电源端V1、第二电源端V2、扫描输出端NOUT、第一节点N1和第二节点N2电连接，被配置为在第一节点N1、第二节点N2和扫描控制信号端MS的信号的控制下，向扫描输出端NOUT提供第一电源端V1或者第二电源端V2的信号。
在示例性实施方式中，信号输入端IN的信号为单次脉冲信号。
在示例性实施方式中，第一时钟信号端CK1和第二时钟信号端CK2中的任一信号端的信号可以为重复高电压和低电压的方波信号。示例性地，第一时钟信号端CK1的信号和第二时钟信号端CK2可以具有相同的周期，并且可以被配置为相移信号。此处，与第一时钟信号端CK1的信号相比，第二时钟信号端CK2的信号可相移半个周期。第一时钟信号端CK1和第二时钟信号端CK2中任一信号端的信号在的每个周期中的高电压时段可设置为长于低电压时段。
在示例性实施方式中，第一时钟信号端CK1的信号的高电压时段可以设置为使得其宽度与第二时钟信号端CK2的信号的低电压时段重叠，第一时钟信号端CK1的信号的低电压时段可以设置为使得其宽度与第二时钟信号端CK2的信号的高电压时段重叠。
在示例性实施方式中，第一电源端V1的信号为恒压信号，且为高电平信号。
在示例性实施方式中，第二电源端V2的信号为恒压信号，且为低电平信号。
在示例性实施方式中，在显示产品显示正常画面时，在任一显示帧，扫描控制信号端的信号在级联输出端的信号为第一电平信号时为有效电平信号，使得第一电源端V1的信号写入扫描输出端NOUT，在显示产品显示特殊画面时，在部分显示帧，扫描控制信号端的信号在级联输出端的信号为第一电平信号时为无效电平信号，使得第二电源端V2的信号写入扫描输出端NOUT。其中，第一电平信号可以为高电平信号，信号A为有效电平信号指的是信号A可以使得信号A所连接的晶体管导通，信号A为无效电平信号指的是信号A可以使得信号A所连接的晶体管断开。
本公开实施例提供的扫描输出子电路可以控制一个显示帧内的输出，还可以控制不同显示帧的局部画面刷新，从而降低显示产品的功耗。
本公开实施例提供的移位寄存器通过扫描输出子电路与扫描控制信号端电连接，可以通过扫描控制信号端控制是否向扫描输出端提供驱动信号，可以在显示正常画面时，在每一显示帧输出驱动信号，对像素驱动电路进行反复初始化和数据写入，保证正常显示，还可以在显示特殊画面时，在部分显示帧不输出驱动信号，减少对像素驱动电路进行初始化和数据写入的次数，进而减少了显示产品的功耗，实现了显示产品的低功耗显示。
图2为一种示例性实施方式提供的移位寄存器的结构示意图。如图2所示，在示例性实施方式中，扫描输出子电路可以包括：第一输出控制子电路和第二输出控制子电路。
如图2所示，第一输出控制子电路，分别与第二电源端V2、扫描输出端NOUT和第二节点N2电连接，被配置为在第二节点N2的信号的控制下，向扫描输出端NOUT提供第二电源端V2的信号；第二输出控制子电路，分别与扫描控制信号端MS、第一电源端V1、扫描输出端NOUT和第一节点N1电连接，被配置为在扫描控制信号端MS和第一节点N1的信号的控制下，向扫描输出端NOUT提供第一电源端V1的信号。
图3为一种示例性实施方式提供的移位寄存器的结构示意图。如图3所示，在示例性实施方式中，扫描输出子电路还可以包括：存储子电路。其中，存储子电路，分别与扫描输出端NOUT和第一电源端V1电连接，被配置为存储扫描输出端NOUT和第一电源端V1的信号之间的电压差。
图4为一种示例性实施方式提供的第一输出控制子电路的等效电路图。如图4所示，在示例性实施方式中，第一输出控制子电路可以包括：第十七晶体管T17。
如图4所示，第十七晶体管T17的控制极与第二节点N2电连接，第十七晶体管T17的第一极与第二电源端V2电连接，第十七晶体管T17的第二极与扫描输出端NOUT电连接。
图4中仅示出了第一输出控制子电路的一种示例性结构，本领域技术人员容易理解是，第一输出控制子电路的实现方式不限于此。。
图5为一种示例性实施方式提供的第二输出控制子电路的等效电路图，图6为另一示例性实施方式提供的第二输出控制子电路的等效电路图。如图5和图6所示，在示例性实施方式中，第二输出控制子电路可以包括：第十八晶体管T18和第十九晶体管T19。
如图5所示，第十八晶体管T18的控制极与第一节点N1电连接，第十八晶体管T18的第一极与第一电源端V1电连接，第十八晶体管T18的第二极与第三节点N3电连接；第十九晶体管T19的控制极与扫描控制信号端MS电连接，第十九晶体管T19的第一极与扫描输出端NOUT电连接，第十九晶体管T19的第二极与第三节点N3电连接。
如图6所示，第十八晶体管T18的控制极与第一节点N1电连接，第十八晶体管T18的第一极与扫描输出端NOUT电连接，第十八晶体管T18的第二极与第三节点N3电连接；第十九晶体管T19的控制极与扫描控制信号端MS电连接，第十九晶体管T19的第一极与第一电源端V1电连接，第十九晶体管T19的第二极与第三节点N3电连接。
图5和图6中仅示出了第二输出控制子电路的两种示例性结构，本领域技术人员容易理解是，第二输出控制子电路的实现方式不限于此。。
图7为一种示例性实施方式提供的存储子电路的等效电路图，如图7所示，在示例性实施方式中，存储子电路可以包括：第五电容C5。
如图7所示，第五电容C5的第一极板C51与扫描输出端NOUT电连接，第五电容C5的第二极板C52与第一电源端V1电连接。
在示例性实施方式中，存储子电路的设置可以保证扫描输出端NOUT的输出信号的稳定性，可以提升移位寄存器的可靠性。
图7中仅示出了存储子电路的一种示例性结构，本领域技术人员容易理解是，存储子电路的实现方式不限于此。
在示例性实施方式中，级联输出子电路可以为10T3C、10T4C、12T3C、12T4C、13T3C、13T4C、16T3C或者16T4C的电路结构，本公开对此不做任何限定。
本公开实施例提供的扫描输出子电路仅包括：三个晶体管，结构简单，有利于异味寄存器的布局，还可以减少移位寄存器所占用的面积，可以实现窄边框。
图8为一种示例性实施方式提供的级联输出子电路的等效电路图。图8是以16T4C为例进行说明的。如图8所示，在示例性实施方式中，级联输出子电路可以包括：第一晶体管T1至第十六晶体管T16以及第一电容C1至第四电容C4，第一电容C1至第四电容C4中的任一电容包括：第一极板和第二极板。
如图8所示，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第四节点N4电连接；第二晶体管T2的控制极与第四节点N4电连接，第二晶体管T2的第一极与第一时钟信号端CK1电连接，第二晶体管T2的第二极与第五节点N5电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2电连接，第三晶体管T3的第二极与第五节点N5电连接；第四晶体管T4的控制极与第六节点N6电连接，第四晶体管T4的第一极与第二时钟信号端CK2电连接，第四晶体管T4的第二极与第七节点N7电连接；第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一电源端V1电连接，第五晶体管T5的第二极与第七节点N7电连接；第六晶体管T6的控制极与第九节点N9电连接，第六晶体管T6的第一极与第二时钟信号端CK2电连接，第六晶体管T6的第二极与第八节点N8电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第一极与第八节点N8电连接，第七晶体管T7的第二极与第一节点N1电连接；第八晶体管T8的控制极与第四节点N4电连接，第八晶体管T8的第一极与第一电源端V1电连接，第八晶体管T8的第二极与第一节点N1电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第一电源端V1电连接，第九晶体管T9的第二极与级联输出端COUT电连接；第十晶体管T10的控制极与第二节点N2电连接，第十晶体管T10的第一极与第二电源端V2电连接，第十晶体管T10的第二极与级联输出端COUT电连接；第十一晶体管T11的控制极与第二电源端V2电连接，第十一晶体管T11的第一极与第五节点N5电连接，第十一晶体管T11的第二极与第九节点N9电连接；第十二晶体管T12的控制极与第二电源端V2电连接，第十二晶体管T12的第一极与第四节点N4电连接，第十二晶体管T12的第二极与第二节点N2电连接；第十三晶体管T13的控制极与第三电源端V3电连接，第十三晶体管T13的第一极与第一电源端V1电连接，第十三晶体管T13的第二极与第四节点N4电连接；第十四晶体管T14的控制极与第一时钟信号端CK1电连接，第十四晶体管T14的第一极与信号输入端IN电连接，第十四晶体管T14的第二极与第十节点N10电连接；第十五晶体管T15的控制极与第二电源端V2电连接，第十五晶体管T15的第一极与第十节点N10电连接，第十五晶体管T15的第二极与第六节点N6电连接；第十六晶体管T16的控制极与第六节点N6电连接，第十六晶体管T16的第一极与第六节点N6电连接，第十六晶体管T16的第二极与第二节点N2电连接；第一电容C1的第一极板C11与第九节点N9电连接，第一电容C1的第二极板C12与第八节点N8电连接；第二电容C2的第一极板C21与第一节点N1电连接，第二电容C2的第二极板C22与第一电源端V1电连接；第三电容C3的第一极板C31与第六节点N6电连接，第三电容C3的第二极板C32与第七节点N7电连接；第四电容C4的第一极板C41与第二电源端V2电连接，第四电容C4的第二极板C42与级联输出端COUT电连接。
在示例性实施方式中，当级联输出子电路为10T3C的电路结构时，级联输出子电路包括：第一晶体管T1至第十晶体管T10以及第一电容C1至第三电容C3。
在示例性实施方式中，当级联输出子电路为10T4C的电路结构时，级联输出子电路包括：第一晶体管T1至第十晶体管T10以及第一电容C1至第四电容C4。
在示例性实施方式中，当级联输出子电路为12T3C的电路结构时，级联输出子电路包括：第一晶体管T1至第十二晶体管T12以及第一电容C1至第三电容C3。
在示例性实施方式中，当级联输出子电路为12T3C的电路结构时，级联输出子电路包括：第一晶体管T1至第十二晶体管T12以及第一电容C1至第四电容C4。
在示例性实施方式中，当级联输出子电路为13T3C的电路结构时，级联输出子电路包括：第一晶体管T1至第十三晶体管T13以及第一电容C1至第三电容C3。
在示例性实施方式中，当级联输出子电路为13T4C的电路结构时，级联输出子电路包括：第一晶体管T1至第十三晶体管T13以及第一电容C1至第四电容C4。
在示例性实施方式中，当级联输出子电路为16T3C的电路结构时，级联输出子电路包括：第一晶体管T1至第十六晶体管T16以及第一电容C1至第三电容C3。
图9为一种移位寄存器的等效电路图一，图10为一种移位寄存器的等效电路图二。如图9和图10所示，在示例性实施方式中，级联输出子电路可以包括：第一晶体管T1至第十六晶体管T16以及第一电容C1至第四电容C4，第一电容C1至第四电容C4中的任一电容包括：第一极板和第二极板，扫描输出子电路包括：第十七晶体管T17至第十九晶体管T19，或者，包括：十七晶体管至第十九晶体管T19和第五电容C5。图9是以扫描输出子电路包括：第十七晶体管T17至第十九晶体管T19为例进行说明的，图10是以扫描输出子电路包括：十七晶体管T17至第十九晶体管T19和第五电容C5为例进行说明的。
如图9和图10所示，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第四节点N4电连接；第二晶体管T2的控制极与第四节点N4电连接，第二晶体管T2的第一极与第一时钟信号端CK1电连接，第二晶体管T2的第二极与第五节点N5电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2电连接，第三晶体管T3的第二极与第五节点N5电连接；第四晶体管T4的控制极与第六节点N6电连接，第四晶体管T4的第一极与第二时钟信号端CK2电连接，第四晶体管T4的第二极与第七节点N7电连接；第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一电源端V1电连接，第五晶体管T5的第二极与第七节点N7电连接；第六晶体管T6的控制极与第九节点N9电连接，第六晶体管T6的第一极与第二时钟信号端CK2电连接，第六晶体管T6的第二极与第八节点N8电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第一极与第八节点N8电连接，第七晶体管T7的第二极与第一节点N1电连接；第八晶体管T8的控制极与第四节点N4电连接，第八晶体管T8的第一极与第一电源端V1电连接，第八晶体管T8的第二极与第一节点N1电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第一电源端V1电连接，第九晶体管T9的第二极与级联输出端COUT电连接；第十晶体管T10的控制极与第二节点N2电连接，第十晶体管T10的第一极与第二电源端V2电连接，第十晶体管T10的第二极与级联输出端COUT电连接；第十一晶体管T11的控制极与第二电源端V2电连接，第十一晶体管T11的第一极与第五节点N5电连接，第十一晶体管T11的第二极与第九节点N9电连接；第十二晶体管T12的控制极与第二电源端V2电连接，第十二晶体管T12的第一极与第四节点N4电连接，第十二晶体管T12的第二极与第二节点N2电连接；第十三晶体管T13的控制极与第三电源端V3电连接，第十三晶体管T13的第一极与第一电源端V1电连接，第十三晶体管T13的第二极与第四节点N4电连接；第十四晶体管T14的控制极与第一时钟信号端CK1电连接，第十四晶体管T14的第一极与信号输入端IN电连接，第十四晶体管T14的第二极与第十节点N10电连接；第十五晶体管T15的控制极与第二电源端V2电连接，第十五晶体管T15的第一极与第十节点N10电连接，第十五晶体管T15的第二极与第六节点N6电连接；第十六晶体管T16的控制极与第六节点N6电连接，第十六晶体管T16的第一极与第六节点N6电连接，第十六晶体管T16的第二极与第二节点N2电连接；第一电容C1的第一极板C11与第九节点N9电连接；第十七晶体管T17的控制极与第二节点N2电连接，第十七晶体管T17的第一极与第二电源端V2电连接，第十七晶体管T17的第二极与扫描输出端NOUT电连接；第十八晶体管T18的控制极与第一节点N1电连接，第十八晶体管T18的第一极与第一电源端V1电连接，第十八晶体管T18的第二极与第三节点N3电连接；第十九晶体管T19的控制极与扫描控制信号端MS电连接，第十九晶体管T19的第一极与扫描输出端NOUT电连接，第十九晶体管T19的第二极与第三节点N3电连接；第一电容C1的第二极板C12与第八节点N8电连接；第二电容C2的第一极板C21与第一节点N1电连接，第二电容C2的第二极板C22与第一电源端V1电连接；第三电容C3的第一极板C31与第六节点N6电连接，第三电容C3的第二极板C32与第七节点N7电连接；第四电容C4的第一极板C41与第二电源端V2电连接，第四电容C4的第二极板C42与级联输出端COUT电连接；第五电容C5的第一极板C51与扫描输出端NOUT电连接，第五电容C5的第二极板C52与第一电源端V1电连接。
图11为一种移位寄存器的等效电路图三，图12为一种移位寄存器的等效电路图四。如图11和图12所示，在示例性实施方式中，级联输出子电路可以包括：第一晶体管T1至第十六晶体管T16以及第一电容C1至第四电容C4，第一电容C1至第四电容C4中的任一电容包括：第一极板和第二极板，扫描输出子电路包括：第十七晶体管T17至第十九晶体管T19，或者，包括：十七晶体管T17至第十九晶体管T19和第五电容C5。图11是以扫描输出子电路包括：第十七晶体管T17至第十九晶体管T19为例进行说明的，图12是以扫描输出子电路包括：十七晶体管至第十九晶体管T19和第五电容C5为例进行说明的。
如图11和图12所示，第一晶体管T1的控制极与第一时钟信号端CK1电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第四节点N4电连接；第二晶体管T2的控制极与第四节点N4电连接，第二晶体管T2的第一极与第一时钟信号端CK1电连接，第二晶体管T2的第二极与第五节点N5电连接；第三晶体管T3的控制极与第一时钟信号端CK1电连接，第三晶体管T3的第一极与第二电源端V2电连接，第三晶体管T3的第二极与第五节点N5电连接；第四晶体管T4的控制极与第六节点N6电连接，第四晶体管T4的第一极与第二时钟信号端CK2电连接，第四晶体管T4的第二极与第七节点N7电连接；第五晶体管T5的控制极与第五节点N5电连接，第五晶体管T5的第一极与第一电源端V1电连接，第五晶体管T5的第二极与第七节点N7电连接；第六晶体管T6的控制极与第九节点N9电连接，第六晶体管T6的第一极与第二时钟信号端CK2电连接，第六晶体管T6的第二极与第八节点N8电连接；第七晶体管T7的控制极与第二时钟信号端CK2电连接，第七晶体管T7的第一极与第八节点N8电连接，第七晶体管T7的第二极与第一节点N1电连接；第八晶体管T8的控制极与第四节点N4电连接，第八晶体管T8的第一极与第一电源端V1电连接，第八晶体管T8的第二极与第一节点N1电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第一电源端V1电连接，第九晶体管T9的第二极与级联输出端COUT电连接；第十晶体管T10的控制极与第二节点N2电连接，第十晶体管T10的第一极与第二电源端V2电连接，第十晶体管T10的第二极与级联输出端COUT电连接；第十一晶体管T11的控制极与第二电源端V2电连接，第十一晶体管T11的第一极与第五节点N5电连接，第十一晶体管T11的第二极与第九节点N9电连接；第十二晶体管T12的控制极与第二电源端V2电连接，第十二晶体管T12的第一极与第四节点N4电连接，第十二晶体管T12的第二极与第二节点N2电连接；第十三晶体管T13的控制极与第三电源端V3电连接，第十三晶体管T13的第一极与第一电源端V1电连接，第十三晶体管T13的第二极与第四节点N4电连接；第十四晶体管T14的控制极与第一时钟信号端CK1电连接，第十四晶体管T14的第一极与信号输入端IN电连接，第十四晶体管T14的第二极与第十节点N10电连接；第十五晶体管T15的控制极与第二电源端V2电连接，第十五晶体管T15的第一极与第十节点N10电连接，第十五晶体管T15的第二极与第六节点N6电连接；第十六晶体管T16的控制极与第六节点N6电连接，第十六晶体管T16的第一极与第六节点N6电连接，第十六晶体管T16的第二极与第二节点N2电连接；第一电容C1的第一极板C11与第九节点N9电连接；第十七晶体管T17的控制极与第二节点N2电连接，第十七晶体管T17的第一极与第二电源端V2电连接，第十七晶体管T17的第二极与扫描输出端NOUT电连接；第十八晶体管T18的控制极与第一节点N1电连接，第十八晶体管T18的第一极与扫描输出端NOUT电连接，第十八晶体管T18的第二极与第三节点N3电连接；第十九晶体管T19的控制极与扫描控制信号端MS电连接，第十九晶体管T19的第一极与第一电源端V1电连接，第十九晶体管T19的第二极与第三节点N3电连接；第一电容C1的第二极板C12与第八节点N8电连接；第二电容C2的第一极板C21与第一节点N1电连接，第二电容C2的第二极板C22与第一电源端V1电连接；第三电容C3的第一极板C31与第六节点N6电连接，第三电容C3的第二极板C32与第七节点N7电连接；第四电容C4的第一极板C41与第二电源端V2电连接，第四电容C4的第二极板C42与级联输出端COUT电连接；第五电容C5的第一极板C51与扫描输出端NOUT电连接，第五电容C5的第二极板C52与第一电源端V1电连接。
在示例性实施方式中，第一电容C1至第五电容C5中的任一电容可以是通过工艺制程制作的电容器件，例如，可以通过制作专门的电容电极来实现电容器件，电容的多个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。或者，第一电容C1至第五电容C5中的任一电容可以是多个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。第一电容C1至第五电容C5中的任一电容的连接方式包括但不局限于上面描述的方式，可以为其它适用的连接方式，可以存储相应节点的电平即可。这里，本公开示例性实施方式对此不做限定。
在示例性实施方式中，图9至图12是以级联输出子电路为16T4C的电路结构为例进行说明的。
在示例性实施方式中，按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，图9至图12提供移位寄存器中，第一晶体管T1至第十九晶体管T19可以为P型晶体管。第一晶体管T1至第十九晶体管T19可以为P型晶体管可以简化移位寄存器的制作工艺。
在示例性实施方式中，由于扫描控制信号端MS的存在，使得级联输出子电路和扫描输出子电路的输出独立，现将级联输出子电路和扫描输出子电路的工作过程分别描述。
在示例性实施方式中，第一电源端V1持续提供高电平信号，第二电源端V2持续提供低电平信号。由于第二电源端V2持续提供低电平信号，第十一晶体管T11、第十二晶体管T12和第十五晶体管T15持续导通。
在示例性实施方式中，第三电源端V3在开机初始化阶段为低电平信号，防止最后一级控制移位寄存器的第九晶体管T9和第十晶体管T10因输出信号的延迟同时导通，或者在异常关机阶段为低电平信号，防止第九晶体管T9和第十晶体管T10同时导通。第三电源端V3在正常显示阶段持续提供高电平信号，即在正常显示阶段，第十三晶体管T13断开。
图13为图9至图12提供的移位寄存器中的级联输出子电路的时序图。图13是以第一晶体管T1至第十六晶体管T16为P型晶体管为例，如图13所示，一种示例性实施方式提供的级联输出子电路的工作过程可以包括以下阶段：
第一阶段A1，信号输入端IN和第二时钟信号端CK2的信号为高电平信号，第一时钟信号端CK1的信号为低电平信号。第一时钟信号端CK1的信号为低电平信号，第一晶体管T1、第三晶体管T3和第十二晶体管T12导通，导通的第一晶体管T1将信号输入端IN的高电平信号传输至第四节点N4，第四节点N4的信号为高电平信号，导通的第十二晶体管T12将第四节点N4的高电平信号传输至第二节点N2，导通的第十四晶体管T14将信号输入端IN的高电平信号传输至第十节点N10，第十节点N10的信号为高电平信号，导通的第十五晶体管T15将第十节点N10的高电平信号传输至第六节点N6，第二晶体管T2、第四晶体管T4、第八晶体管T8、第十晶体管T10和第十六晶体管T16断开。另外，导通的第三晶体管T3将第二电源端V2的低电平信号传输至第五节点N5，第五节点N5的信号为低电平信号，导通的第十一晶体管T11将第五节点N5的低电平信号传输至第九节点N9，第九节点N9的信号为低电平信号，第五晶体管T5和第六晶体管T6导通。第二时钟信号端CK2的信号虽为高电平信号，但由于第七晶体管T7断开，第一节点N1的信号不会被拉高，保持为低电平信号，第九晶体管T9断开，级联输出端COUT的信号保持之前的低电平。在第一阶段A1中，第一节点N1为低电平信号，第二节点N2为高电平信号，级联输出端COUT的信号保持之前的低电平信号。
第二阶段A2，第二时钟信号端CK2的信号为低电平信号，信号输入端IN和第一时钟信号端CK1的信号为高电平信号。第二时钟信号端CK2的信号为低电平信号，第七晶体管T7导通。第一时钟信号端CK1的信号为高电平信号，第一晶体管T1和第三晶体管T3断开。在第三电容C3的作用下，第四节点N4、第二节点N2、第六节点N6和第十节点N10可以继续保持上一阶段的高电平信号，在第一电容C1作用下，所以第五节点N5和第九节点N9可以继续保持上一阶段的低电平信号，所以第五晶体管T5以及第六晶体管T6导通。第二晶体管T2、第四晶体管T4、第八晶体管T8以及第十晶体管T10断开。另外，第二时钟信号端CK2的低电平信号通过导通的第六晶体管T6和第七晶体管T7被传输至第一节点N1，第九晶体管T9导通，第一电源端V1的高电平信号通过导通的第九晶体管T9被传输至级联输出端COUT，因此，本阶段，第一节点N1为低电平信号，第二节点N2为高电平信号，级联输出端COUT的信号为高电平信号。
第三阶段A3，第一时钟信号端CK1的信号为低电平信号，信号输入端IN和第二时钟信号端CK2的信号为高电平信号。第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开，在第二电容C2的作用下，第一节点N1保持上一阶段的低电平信号，第九晶体管T持续导通，第一电源端V1的高电平信号通过导通的第九晶体管T9被传输至级联输出端COUT。第一时钟信号端CK1的信号为低电平信号，第一晶体管T1、第三晶体管T3和第十二晶体管T12导通，导通的第一晶体管T1将信号输入端IN的高电平信号传输至第四节点N4，第四节点N4的信号为高电平信号，导通的第十二晶体管T12将第四节点N4的高电平信号传输至第二节点N2，导通的第十四晶体管T14将信号输入端IN的高电平信号传输至第十节点N10，第十节点N10的信号为高电平信号，导通的第十五晶体管T15将第十节点N10的高电平信号传输至第六节点N6，第二晶体管T2、第四晶体管T4、第八晶体管T8、第十晶体管T10和第十六晶体管T16断开。另外，导通的第三晶体管T3将第二电源端V2的低电平信号传输至第五节点N5，第五节点N5的信号为低电平信号，导通的第十一晶体管T11将第五节点N5的低电平信号传输至第九节点N9，第九节点N9的信号为低电平信号，第五晶体管T5和第六晶体管T6导通。在本阶段，第一节点N1为低电平信号，第二节点N2为高电平信号，级联输出端COUT的信号为高电平信号。
在第四阶段A4，信号输入端IN和第二时钟信号端CK2的信号为低电平信号，第一时钟信号端CK1的信号为高电平信号。第一时钟信号端CK1的信号为高电平信号，第一晶体管T1以及第三晶体管T3断开。第二时钟信号端CK2的信号为低电平信号，第七晶体管T7导通。由于第三电容C3的存储作用，所以第四节点N4、第二节点N2、第六节点N6和第十节点N10的信号保持上一阶段的高电平信号，第二晶体管T2、第四晶体管T4、第八晶体管T8以及第十晶体管T10断开。由于第一电容C1的存储作用，第九节点N9继续保持上一阶段的低电平信号，第五晶体管T5以及第六晶体管T6导通。另外，第二时钟信号端CK2的低电平信号通过导通的第六晶体管T6以及第七晶体管T7被传输至第一节点N1，第一电源端V1的高电平信号通过导通的第九晶体管T9被传输至级联输出端COUT，级联输出端COUT的信号仍然为高电平信号。本阶段，第一节点N1为高电平信号，第二节点N2为低电平信号，级联输出端COUT为高电平信号。
在第五阶段A5，第二时钟信号端CK2的信号为高电平信号，信号输入端IN和第一时钟信号端CK1的信号为低电平信号。第一时钟信号端CK1的信号为低电平信号，第一晶体管T1、第三晶体管T3和第十四晶体管T14导通。第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开。导通的第一晶体管T1将信号输入端IN的低电平信号传输至第四节点N4，第四节点N4的信号为低电平信号，导通的第十二晶体管T12将第四节点N4的低电平信号传输至第一节点N1，第一节点N1的信号变为低电平信号，导通的第十四晶体管T14将信号输入端IN的低电平信号传输至第十节点N10，第十节点N10的信号为低电平信号，导通的第十五晶体管T15将第十节点N10的低电平信号传输至第六节点N6，第六节点N6的信号为低电平信号，第二晶体管T2、第四晶体管T4、第八晶体管T8以及第十晶体管T10导通。导通的第二晶体管T2将第一时钟信号端CK1低电平的信号传输至第五节点N5，使得第五节点N5为低电平信号，所以第五节点N5和第九节点N9继续保持上一阶段的低电平信号，第五晶体管T5以及第六晶体管T6导通。第二时钟信号端CK2的信号为高电平信号，第七晶体管T7断开。另外，第一电源端V1的高电平信号通过导通的第八晶体管T8传输至第一节点N1，第九晶体管T9断开。第二电源端V2的低电平信号通过导通的第十晶体管T10传输至级联输出端COUT，级联输出端COUT的信号变为低电平信号，本阶段，第一节点N1为高电平信号，第二节点N2为低电平信号，级联输出端COUT为低电平信号。
图14为图9至图12提供的移位寄存器中的扫描输出子电路的时序图一，图15为图9至图12提供的移位寄存器中的扫描输出子电路的时序图二，图16为图9至图12提供的移位寄存器中的扫描输出子电路的时序图三，图17为图9至图12提供的移位寄存器中的扫描输出子电路的时序图四。图14至图17是以第十七晶体管T17至第十九晶体管T19为P型晶体管为例进行说明的。
图14和图15是以显示产品显示正常显示画面时为例进行说明的，在任一显示帧，当级联输出端COUT的信号为高电平信号时，扫描控制信号端MS的至少部分时间段为低电平信号。
如图14所示，当级联输出端COUT的输出信号为高电平信号时，第一节点N1为低电平信号，第二节点N2为高电平信号。第二节点N2为高电平信号，第十七晶体管T17断开。第一节点N1为低电平信号，第十八晶体管T18导通，扫描控制信号端MS的至少部分时间段为低电平信号，第十九晶体管T19导通，第一电源端V1通过导通的第十八晶体管T18和第十九晶体管T19传输至扫描输出端NOUT，扫描输出端NOUT的信号为高电平信号。
如图15所示，当级联输出端COUT的输出信号为低电平信号时，第一节点N1为高电平信号，第二节点N2为低电平信号。第一节点N1为高电平信号，第十八晶体管T18断开，第一电源端V1的高电平信号无法传输至扫描输出端NOUT。第二节点N2为低电平信号，第十七晶体管T17导通，第二电源端V2的低电平信号传输至扫描输出端NOUT，扫描输出端NOUT的信号为低电平信号。
在显示产品显示正常画面时，级联输出端COUT的信号为高电平信号时，扫描输出端NOUT的信号为高电平信号，级联输出端COUT的信号为低电平信号时，扫描输出端NOUT的信号为低电平信号，即级联输出端COUT的信号和扫描输出端NOUT的信号保持一致，可以实现显示产品的正常显示。
图16和图17是以显示产品显示特殊画面为例进行说明的。在部分显示帧，扫描控制信号端MS的信号在级联输出端的信号为高电平信号时为高电平信号。
如图16所示，当级联输出端COUT的输出信号为高电平信号时，第一节点N1为低电平信号，第二节点N2为高电平信号。第二节点N2为高电平信号，第十七晶体管T17断开。第一节点N1为低电平信号，第十八晶体管T18导通，扫描控制信号端MS的信号为高电平信号，第十九晶体管T19断开，第一电源端V1无法写入扫描输出端NOUT，扫描输出端NOUT保持低电平信号。
如图17所示，当级联输出端COUT的输出信号为低电平信号时，第一节点N1为高电平信号，第二节点N2为低电平信号。第一节点N1为高电平信号，第十八晶体管T18断开，扫描控制信号端MS的信号为高电平信号，第十九晶体管T19断开，第一电源端V1的高电平信号无法传输至扫描输出端NOUT。第二节点N2为低电平信号，第十七晶体管T17导通，第二电源端V2的低电平信号传输至扫描输出端NOUT，扫描输出端NOUT的信号为低电平信号。
如图16和图17所示，在显示产品显示特殊画面时，无论级联输出端COUT的信号为高电平信号或者低电平信号时，扫描输出端NOUT的信号均为低电平信号，进而可以减少像素驱动电路的初始化和数据写入的次数，降低了显示产品的功耗。
本公开实施例还提供了一种移位寄存器的驱动方法，被配置为驱动移位寄存器，移位寄存器的驱动方法可以包括：
步骤100、级联输出子电路在信号输入端、第一时钟信号端和第二时钟信号端的信号的控制下，向第一节点和第二节点提供信号，在第一节点和第二节点的信号的控制下，向级联输出端提供第一电源端或第二电源端的信号。
步骤200、扫描输出子电路在第一节点、第二节点和扫描控制信号端的信号的控制下，向扫描输出端提供第一电源端或者第二电源端的信号。
图18为一种显示基板的结构示意图，图19为栅极驱动电路的级联示意图一，图20为栅极驱动电路的级联示意图二。如图18至图20所示，显示基板具有显示区AA和非显示区AA’，显示基板可以包括：位于非显示区AA’的栅极驱动电路和位于显示区AA的阵列排布的子像素和多条栅线GL，子像素包括：像素驱动电路P和发光器件。其中，栅线GL至少部分沿第一方向D1延伸，栅极驱动电路包括：多个级联的移位寄存器，像素驱动电路包括：多个晶体管。其中，至少一级移位寄存器的级联输出端与至少一级移位寄存器的信号输入端电连接，栅线与至少一个晶体管的栅电极电连接，任一移位寄存器与至少一条栅线电连接。图19和图20中的NScan(i)为第i级移位寄存器的级联输出子电路，NGate(i)为第i级移位寄存器的扫描输出子电路，NOUT(i)为第i级移位寄存器的扫描输出端。
移位寄存器可以为前述任一个实施例提供的移位寄存器，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，如图18所示，显示基板还可以包括位于非显示区AA’的时序控制器和数据驱动电路以及位于显示区AA的多条数据线DL，数据线DL沿第二方向D2延伸，第一方向D1和第二方向D2相交。像素驱动电路还与数据线DL电连接。时序控制器分别与数据驱动电路和栅极驱动电路连接，数据驱动电路分别与多个数据线DL连接，栅极驱动电路分别与多条栅线GL连接。显示基板还包括：位于显示区的阵列排布的发光器件，像素驱动电路被配置为驱动发光器件发光，像素驱动电路和像素驱动电路所驱动的发光器件构成子像素。
在示例性实施方式中，时序控制器可以将适合于数据驱动电路的规格的灰度值和控制信号提供到数据驱动电路，可以将适合于栅极驱动电路的规格的时钟信号、起始信号等提供到栅极驱动电路。数据驱动电路可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据DL的数据电压。例如，数据驱动电路可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线DL。栅极驱动电路可以通过从时序控制器接收时钟信号、起始信号等来产生将提供到栅线的扫描信号。例如，栅极驱动电路可以将具有导通电平脉冲的扫描信号顺序地提供到栅线GL。
在示例性实施方式中，显示基板可以包括以矩阵方式排布的多个像素单元，多个像素单元的至少一个包括出射第一颜色光线的第一子像素、出射第二颜色光线的第二子像素和出射第三颜色光线的第三子像素，第一子像素、第二子像素和第三子像素均包括像素驱动电路和发光器件。第一子像素、第二子像素和第三子像素中的像素驱动电路分别与数据线和栅线连接，像素驱动电路被配置为在栅线的控制下，接收数据线传输的数据电压，向所述发光器件输出相应的电流。第一子像素、第二子像素和第三子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素可以是出射红色光线的红色子像素(R)，第二子像素可以是出射蓝色光线的蓝色子像素(B)，第三子像素可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字方式等排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。
对于不同显示产品，栅极驱动电路中多个移位寄存器的级联关系可能有所不同。无论多个移位寄存器的级联关系如何，每个移位寄存器驱动几行子像素，只要是类似这种大面积的器件发生改变，以及这种改变产生额外空间以后，小器件可能的简单平移、拉伸都在本公开的保护范围内。
图21为一种像素驱动电路的等效电路示意图，图22为另一像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图21和图22所示，像素驱动电路可以包括7个晶体管(第一晶体管M1到第七晶体管M7)和1个电容C。
如图21和图22所示，第一晶体管M1的栅电极与复位信号线Reset电连接，第一晶体管M1的第一极与第一初始信号线INIT1电连接，第一晶体管M1的第二极与第一节点N1或者第三节点N3电连接；第二晶体管M2的栅电极与第二扫描信号线Gate2电连接，第二晶体管M2的第一极与第一节点N1电连接，第二晶体管M2的第二极与第三节点N3电连接；第三晶体管M3的栅电极与第一节点N1电连接，第三晶体管M3的第一极与第二节点N2电连接，第三晶体管M3的第二极与第三节点N3电连接；第四晶体管M4的栅电极与第一扫描信号线Gate1电连接，第四晶体管M4的第一极与数据信号线Data电连接，第四晶体管M4的第二极与第二节点N2电连接；第五晶体管M5的栅电极与发光信号线EM电连接，第五晶体管M5的第一极与高电平电源线VDD电连接，第五晶体管M5的第二极与第二节点N2电连接；第六晶体管M6的栅电极与发光信号线EM电连接，第六晶体管M6的第一极与第三节点N3电连接，第六晶体管M6的第二极与第四节点N4电连接；第七晶体管M7的栅电极与第一扫描信号线Gate1电连接，第七晶体管M7的第一极与第二初始信号线INIT2电连接，第七晶体管M7的第二极与第四节点N4电连接；电容C的第一极板与第一节点N1电连接，电容C的第二极板与高电平电源线VDD电连接。图21是以第一晶体管M1的第二极与第一节点N1电连接为例进行说明的，图22是以第一晶体管M1的第二极与第三节点N3为例进行说明的。
在示例性实施方式中，第一晶体管M1到第七晶体管M7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源图案采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源图案采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成LTPO显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第一晶体管M1和第二晶体管M2与第三晶体管M3至第七晶体管M7的晶体管类型相反。示例性地，第一晶体管M1和第二晶体管M2可以为N型晶体管，第三晶体管M3至第七晶体管M7可以为P型晶体管。
在示例性实施方式中，第一晶体管M1和第二晶体管M2可以为氧化物晶体管，第三晶体管M3至第七晶体管M7可以为低温多晶硅晶体管。
在示例性实施方式中，第一初始信号线INIT1的信号的电压值恒定，且为直流信号，第一初始信号线INIT1的信号的电压值可以为-3V。
在示例性实施方式中，第二初始信号线INIT2的信号的电压值恒定，且为直流信号，第二初始信号线INIT2的信号的电压值可以为0V。
在示例性实施方式中，发光器件L，可以分别与第四节点N4和低电平电源线VSS电连接。
在示例性实施方式中，高电平电源线VDD持续提供高电平信号，低电平电源线VSS持续提供低电平信号。
[根据细则91更正 09.10.2023]
图23为图21和图22提供的像素驱动电路的工作时序图。下面通过图21和图22示例的像素驱动电路在显示阶段的工作过程说明本公开示例性实施方式。图23是以第一晶体管M1和第二晶体管M2为N型晶体管，第三晶体管M3至第七晶体管M7为P型晶体管为例进行说明的，图21和图22中的像素驱动电路包括第一晶体管M1到第七晶体管M7、1个电容C和8个信号线(数据信号线Data、第一扫描信号线Gate1、第二扫描信号线Gate2、复位信号线Reset、第一初始信号线INIT1、第二初始信号线INIT2、发光信号线EM和高电平电源线VDD)。
结合图21、图22和图23所示，像素驱动电路的工作过程可以包括：
第一阶段P1，称为初始化阶段，复位信号线Reset的信号为高电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号通过导通的第一晶体管M1写入第一节点N1或者第三节点N3，对第一节点N1或者第三节点N3进行初始化(复位)，清空其内部的预存电压，完成初始化。
第二阶段P2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线Gate1的信号为低电平信号，第二扫描信号线Gate2的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于第一节点N1为低电平信号，因此第三晶体管M3导通。第一扫描信号线Gate1的信号为低电平信号，第四晶体管M4导通和第七晶体管M7导通，第二扫描信号线Gate2的信号为高电平信号，第二晶体管M2导通，数据信号线Data输出的数据电压经过导通的第四晶体管M4、第二节点N2、导通的第三晶体管M3、第三节点N3、导通的第二晶体管M2提供至第一节点N1，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入电容C，直至第一节点N1的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压，第七晶体管M7导通，第二初始信号线INIT2的信号通过导通的第七晶体管M7写入第四节点N4，对发光器件L的第一电极进行初始化(复位)，清空其内部的预存电压，完成初始化。
第三阶段P3，称为发光阶段，发光信号线EM的信号为低电平信号，第五晶体管M5和第六晶体管M6导通，高电平电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向发光器件L的第一极提供驱动电压，驱动发光器件L发光。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由栅电极和第一极之间的电压差决定。由于第一节点N1的电压为Vd-|Vth|，因而第三晶体管M3的驱动电流为：I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动发光器件L的驱动电流，K为常数，Vgs为第三晶体管M3的栅电极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为高电平电源线VDD输出的电源电压。
在示例性实施方式中，栅线可以包括：第一栅线和第二栅线，第一栅线可以包括：第一扫描信号线和发光信号线，第二栅线可以包括：复位信号线和第二扫描信号线。
在示例性实施方式中，发光器件可以包括：有机发光二极管OLED、量子点发光二极管和无机发光二极管中的任意一种。例如，发光器件可以采用微米级发光器件，例如微型发光二极管(Micro Light-Emitting Diode，Micro LED)、次毫米发光发光二极管(Mini Light-Emitting Diode，Mini LED)或者微型有机发光二极管(Micro OLED)等，本公开实施例对此不做限定。例如，以发光器件L为有机电致发光二极管(OLED)为例，发光器件可以包括：叠设的第一极(例如，作为阳极)、有机发光层和第二极(例如，作为阴极)。
在示例性实施方式中，本公开显示基板可以应用于具有栅极驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
在示例性实施方式中，本公开实施例提供的至少一个移位寄存器可以与第二栅线电连接。
如图19和图20所示，显示基板还可以包括：位于非显示区的至少一条扫描控制信号线，扫描控制信号线至少部分沿第二方向D2延伸。所有移位寄存器所连接的扫描控制信号端与至少一条扫描控制信号线电连接。图19是以一条扫描控制信号线MSL为例进行说明的，图20是以四条扫描控制信号线MSL1至MSL4为例进行说明的。
在示例性实施方式中，如图19所示，当扫描控制信号线的数量为一条时，所有移位寄存器所连接的扫描控制信号端与同一扫描控制信号线MSL电连接。
在示例性实施方式中，如图20所示，当扫描控制信号线的数量为至少两条时，第M*(k-1)+K*M(a-1)+1级移位寄存器至k*M+K*M(a-1)级移位寄存器中的任一移位寄存器所连接的扫描控制信号端与第k条扫描控制信号线电连接，1≤k≤K，1≤a≤N/M，M为一条扫描控制信号线所连接的移位寄存器的级数，N为移位寄存器的总级数，K为扫描控制信号线的数量，M≥1。
示例性地，以M＝7，K＝4为例，第一级移位寄存器至第七级移位寄存器所连接的扫描控制信号端与第一条扫描控制信号线MSL1电连接，第八级移位寄存器至第十四级移位寄存器所连接的扫描控制信号端与第二条扫描控制信号线MSL2电连接，第十五级移位寄存器至第二十一级移位寄存器所连接的扫描控制信号端与第三条扫描控制信号线MSL3电连接，第二十二级移位寄存器至第二十八级移位寄存器所连接的扫描控制信号端与第四条扫描控制信号线MSL4电连接，第二十九级移位寄存器至第三十五级移位寄存器所连接的扫描控制信号端与第一条扫描控制信号线MSL1电连接，第三十六级移位寄存器至第四十二级移位寄存器所连接的扫描控制信号端与第二条扫描控制信号线MSL2电连接，第四十三级移位寄存器至第四十九级移位寄存器所连接的扫描控制信号端与第三条扫描控制信号线MSL3电连接，第五十级移位寄存器至第五十六级移位寄存器所连接的扫描控制信号端与第四条扫描控制信号线MSL4电连接，依次类推。
在示例性实施方式中，显示基板所显示画面包括：多个显示帧，在任一显示帧，所述移位寄存器的扫描输出端的输出信号为脉冲信号，且脉冲信号的持续时间H满足如下关系式；H＝L*[M*K-(M-1)]*h
其中，L为任一级移位寄存器所连接的栅线的数量，h为单位时间，且等于相邻行子像素的刷新间隔时间。
在示例性实施方式中，显示区可以被划分为多个显示子区，至少一个显示子区包括：至少一条栅线。任一个显示子区的显示模式包括：第一显示模式和第二显示模式，第一显示模式的刷新频率大于第二显示模式的刷新频率。
在示例性实施方式中，在显示子区的显示模式为第一显示模式的状态下，对于与显示子区内的栅线所连接的移位寄存器，级联输出端的信号为第一电平信号时，扫描控制信号端的信号的至少部分时间段为有效电平信号，扫描输出端的信号为第一电平信号。在显示子区的显示模式为第二显示模式的状态下，对于与显示子区内的栅线所连接的移位寄存器，级联输出端的信号为第一电平信号时，扫描控制信号端的信号为无效电平信号，扫描输出端的信号为第二电平信号。其中，第一电平信号的电压值大于第二电平信号的电压值，第一电平信号为高电平信号，第二电平信号为低电平信号。
图24为图19提供的栅极驱动电路的多个扫描输出端的时序图。如图24所示，在时间段t内，由于扫描控制信号线MSL的信号为高电平信号，使得第二级移位寄存器的扫描输出端NOUT(2)至第N-1级移位寄存器的扫描输出端NOUT(N-1)的任一输出端的信号为低电平信号，即第二级移位寄存器的扫描输出端至第N-1级移位寄存器的扫描输出端所连接的栅线连接的像素驱动电路不会进行初始化和数据写入，实现显示产品的低频显示和低功耗显示。
图25为图20提供的栅极驱动电路的多个扫描输出端的时序图。如图25所示，在时间段t1和t3中，第一条扫描控制信号线MSL1至第四条扫描控制信号线MSL4的信号为低电平信号，此时，所有移位寄存器的扫描输出端依次输出高电平信号。
如图25所示，在时间段t2中，第一条扫描控制信号线MSL1在部分时间段为高电平信号，使得第一级移位寄存器和第七级移位寄存器的扫描输出端输出低电平信号，第一条扫描控制信号线MSL1为高电平信号的时间段为第一级移位寄存器级联输出端的信号为高电平信号的开始时间至第七移位寄存器级联输出端的信号为高电平信号的结束时间。
如图25所示，在时间段t2中，第二条扫描控制信号线MSL2在部分时间段为高电平信号，使得第八级移位寄存器和第十四级移位寄存器的扫描输出端输出低电平信号，第二条扫描控制信号线MSL2为高电平信号的时间段为第八级移位寄存器级联输出端的信号为高电平信号的开始时间至第十四移位寄存器级联输出端的信号为高电平信号的结束时间。
如图25所示，在时间段t2中，第三条扫描控制信号线MSL3在部分时间段为高电平信号，使得第四十三级移位寄存器和第四十九级移位寄存器的扫描输出端输出低电平信号，第三条扫描控制信号线MSL3为高电平信号的时间段为第四十三级移位寄存器级联输出端的信号为高电平信号的开始时间至第四十九移位寄存器级联输出端的信号为高电平信号的结束时间。
如图25所示，在时间段t2中，第四条扫描控制信号线MSL4为高电平信号的时间段为第五十级移位寄存器级联输出端的信号为高电平信号的开始时间至第五十六移位寄存器级联输出端的信号为高电平信号的结束时间，第四条扫描控制信号线MSL4为高电平信号的时间段为第五十级移位寄存器级联输出端的信号为高电平信号的开始时间至第五十六移位寄存器级联输出端的信号为高电平信号的结束时间。
图26为显示基板的非显示区的局部示意图。如图19、图20和图26所示，显示基板还可以包括：位于非显示区的第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第二电源线VGL和第三电源线VCX。图26中的移位寄存器为图11提供的移位寄存器，且图26是以扫描控制信号线为一条为例进行说明的。
在示例性实施方式中，第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第二电源线VGL和第三电源线VCX中的任一条至少部分沿第二方向D2延伸；
在示例性实施方式中，任一级移位寄存器所连接的第一时钟信号端与第一时钟信号线CLK1和第二时钟信号线CLK2的其中一条电连接，任一级移位寄存器所连接的第二时钟信号端与第一时钟信号线CLK1和第二时钟信号线CLK2的另一条电连接，相邻移位寄存器所连接的第一时钟信号端所连接的时钟信号线不同，相邻移位寄存器所连接的第二时钟信号端所连接的时钟信号线不同，所有移位寄存器所连接的第一电源端与第一电源线VGH电连接，所有移位寄存器所连接的第二电源端与第二电源线VGL电连接，所有移位寄存器所连接的第三电源端与第三电源线VCX电连接。
在示例性实施方式中，显示基板还可以包括：位于非显示区的初始信号线，至少一级移位寄存器的信号输入端与初始信号线电连接。初始信号线可以沿第二方向延伸，且可以位于第一时钟信号线远离显示区的一侧。
在示例性实施方式中，如图19、图20和图25所示，扫描控制信号线MSL可以位于第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、第二电源线VGL和第三电源线VCX中的任一条靠近显示区的一侧。
在示例性实施方式中，如图25所示，第二电源线VGL的数量为两条，第一时钟信号线CLK1、第二时钟信号线CLK2、第一条第二电源线VGL、第三电源线VCX、第二条第二电源线VGL和第一电源线VGH沿靠近显示区的方向依次排布。
在示例性实施方式中，如图25所示，移位寄存器可以包括：第十七晶体管T17至第十九晶体管T19；第十七晶体管T17至第十九晶体管T19可以沿第二方向D2排布。
在示例性实施方式中，如图25所示，第十七晶体管T17至第十九晶体管T19中的任一个晶体管的至少部分位于第一电源线VGH和扫描控制信号线MSL之间。
在示例性实施方式中，任一晶体管包括：有源图案，图27为第十七晶体管至第十九晶体管的有源图案的示意图。如图27所示，第十七晶体管的有源图案171沿第一方向D1的平均长度小于第十八晶体管的有源图案181和第十九晶体管的有源图案191中的任一个沿第一方向D1的平均长度。
在示例性实施方式中，如图25所示，第一电源线VGH和第二电源线VGL中的任一电源线的线宽可以大于扫描控制信号线MSL的线宽。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。图11至图18是以显示基板包括图8提供的移位寄存器，即移位寄存器包括：第一晶体管T1至第八晶体管T8以及第十晶体管T10为例进行说明的。
(1)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上沉积半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成半导体层图案。如图28所示，图28为图26形成半导体层图案后的示意图。
在示例性实施方式中，如图28所示，每个移位寄存器的半导体层图案可以至少包括：第一晶体管的有源图案11至第十九晶体管的有源图案191。
在示例性实施方式中，如图28所示，第五晶体管的有源图案51、第七晶体管的有源图案71、第八晶体管的有源图案81和第十三晶体管的有源图案131为一体结构，第十二晶体管的有源图案121和第十六晶体管的有源图案161为一体结构，第十七晶体管的有源图案171、第十八晶体管的有源图案181和第十九晶体管的有源图案191为一体结构，第一晶体管的有源图案11、第二晶体管的有源图案21、第三晶体管的有源图案31、第四晶体管的有源图案41、第六晶体管的有源图案61、第九晶体管的有源图案91、第十晶体管的有源图案101、第十一晶体管的有源图案111、第十四晶体管的有源图案141和第十五晶体管的有源图案151单独设置。
在示例性实施方式中，如图28所示，第一晶体管的有源图案11和十四晶体管的有源图案141沿第一方向D1排布，且第一晶体管的有源图案11位于十四晶体管的有源图案141靠近显示区的一侧，第二晶体管的有源图案21位于第一晶体管的有源图案11靠近显示区的一侧。第三晶体管的有源图案31与第一晶体管的有源图案11沿第二方向D2排布，且本级移位寄存器的第三晶体管的有源图案31位于第一晶体管的有源图案11靠近下一级移位寄存器的一侧，第十一晶体管的有源图案111和十五晶体管的有源图案151沿第一方向D1排布，第十一晶体管的有源图案111与第一晶体管的有源图案11沿第二方向D2排布，十五晶体管的有源图案151与十四晶体管的有源图案141沿第二方向D2排布，第十一晶体管的有源图案111位于十五晶体管的有源图案151靠近显示区的一侧，本级移位寄存器的第十一晶体管的有源图案111位于十五晶体管的有源图案151位于第三晶体管的有源图案31靠近下一级移位寄存器的一侧。本级移位寄存器的第四晶体管的有源图案41位于第十一晶体管的有源图案111靠近下一级移位寄存器的一侧。第六晶体管的有源图案61位于第二晶体管的有源图案21靠近显示区的一侧。第七晶体管的有源图案71位于第六晶体管的有源图案61靠近显示区的一侧，第八晶体管的有源图案81和第十三晶体管的有源图案131位于第二晶体管的有源图案21靠近显示区的一侧，且第十三晶体管的有源图案131位于第八晶体管的有源图案81远离显示区的一侧，第五晶体管的有源图案51位于第十一晶体管的有源图案111靠近显示区的一侧，第七晶体管的有源图案71、第八晶体管的有源图案81和第五晶体管的有源图案51沿第二方向D2排布，且本级移位寄存器的第七晶体管的有源图案71位于第八晶体管的有源图案81靠近上一级移位寄存器的一侧，本级移位寄存器的第五晶体管的有源图案51位于第八晶体管的有源图案81靠近下一级移位寄存器的一侧。第十六晶体管的有源图案161位于第四晶体管的有源图案41靠近显示区的一侧，第十二晶体管的有源图案121位于第十六晶体管的有源图案161靠近显示区的一侧，第五晶体管的有源图案51与第十二晶体管的有源图案121沿第二方向D2排布，且本级移位寄存器的第十二晶体管的有源图案121位于第五晶体管的有源图案51靠近下一级移位寄存器的一侧。第九晶体管的有源图案91位于第七晶体管的有源图案71靠近显示区的一侧，第十晶体管的有源图案101位于第十六晶体管的有源图案161靠近显示区的一侧，第九晶体管的有源图案91和第十晶体管的有源图案101沿第二方向D2排布，本级移位寄存器的第九晶体管的的有源图案91可以位于第十晶体管的有源图案101靠近上一级移位寄存器的一侧。第十七晶体管的有源图案171(也是第十八晶体管的有源图案181和第十九晶体管的有源图案191)位于第九晶体管的有源图案91和第十晶体管的有源图案101靠近显示区的一侧，且第十七晶体管的有源图案171至第九晶体管的有源图案191沿第二方向D2排布。本级移位寄存器的第十七晶体管的有源图案171位于第十八晶体管的有源图案181靠近下一级移位寄存器的一侧，本级移位寄存器的第十九晶体管的有源图案191位于第十八晶体管的有源图案181靠近上一级移位寄存器的一侧。
在示例性实施方式中，如图28所示，第一晶体管的有源图案11、第二晶体管的有源图案21、第三晶体管的有源图案31、第五晶体管的有源图案51、第七晶体管的有源图案71、第八晶体管的有源图案81、第九晶体管的有源图案91、第十一晶体管的有源图案111、第十二晶体管的有源图案121、第十四晶体管的有源图案141、第十五晶体管的有源图案151、第十七晶体管的有源图案171、第十八晶体管的有源图案181和第十九晶体管的有源图案191中的任一个有源图案的形状为条状，且沿第二方向D2延伸。
在示例性实施方式中，如图28所示，第四晶体管的有源图案41、第六晶体管的有源图案61、第十晶体管的有源图案101、第十三晶体管的有源图案131和第十六晶体管的有源图案161中的任一有源图案的形状为条状，且沿第一方向D1延伸。
在示例性实施方式中，如图28所示，第十二晶体管的有源图案121与第十六晶体管的有源图案161的一体结构呈倒“T”字型，第五晶体管的有源图案51、第七晶体管的有源图案71、第八晶体管的有源图案81和第十三晶体管的有源图案131的一体结构可以呈“┨”字型，第十七晶体管的有源图案171、第十八晶体管的有源图案181和第十九晶体管的有源图案191的一体结构呈条状，且沿第二方向D2延伸。
在示例性实施方式中，如图28所示，第十七晶体管的有源图案171的沿第一方向D1的平均长度小于第十八晶体管的有源图案181和第十九晶体管的有源图案191中的任一有源图案沿第一方向D1的平均长度。
在示例性实施方式中，如图28所示，每个晶体管的有源图案可以包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第五晶体管的有源图案51的第一区51-1可以作为第八晶体管的有源图案81的第一区81-1和第十三晶体管的有源图案131的第一区131-1，第七晶体管的有源图案71的第二区71-2可以作为第八晶体管的有源图案81的第二区81-2，第十二晶体管的有源图案121的第二区121-2可以作为第十六晶体管的有源图案161的第二区161-2，第十七晶体管的有源图案171的第二区171-2可以作为第十八晶体管的有源图案181的第一区181-1，第十八晶体管的有源图案181的第二区181-2可以作为第十九晶体管的有源图案191的第一区191-2。第一晶体管的有源图案11的第一区11-1和第二区11-2、第二晶体管的有源图案21的第一区21-1和第二区21-2、第三晶体管的有源图案31的第一区31-1和第二区31-2、第四晶体管的有源图案41的第一区41-1和第二区41-2、第五晶体管的有源图案51的第二区51-2、第六晶体管的有源图案61的第一区61-1和第二区61-2、第七晶体管的有源图案71的第一区71-1、第九晶体管的有源图案91的第一区91-1和第二区91-2、第十晶体管的有源图案101的第一区101-1和第二区101-2、第十一晶体管的有源图案111的第一区111-1和第二区111-2、第十二晶体管的有源图案121的第一区121-1、第十三晶体管的有源图案131的第二区131-2、第十四晶体管的有源图案141的第一区141-1和第二区141-2、第十五晶体管的有源图案151的第一区151-1和第二区151-2、第十六晶体管的有源图案161的第一区161-1、第十七晶体管的有源图案171的第一区171-1和第十九晶体管的有源图案191的第一区191-1单独设置。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成有前述图案的基底上沉积第一绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第一绝缘层，以及设置在第一绝缘层上的第一导电层图案，如图29和图30所示，图29为图26中第一导电层图案的示意图，图30为图26形成第一导电层图案后的示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，如图29和图30所示，每一个移位寄存器的第一导电层图案可以至少包括：第一晶体管的栅电极12至第十九晶体管的栅电极192、第一电容的第一极板C11至第四电容的第一极板C41以及第一连接部L1。
在示例性实施方式中，如图29和图30所示，第一晶体管的栅电极12和第十四晶体管的栅电极142为一体结构，第一晶体管的栅电极12和第十四晶体管的栅电极142的一体结构的形状为条状，且沿第一方向D1延伸。
在示例性实施方式中，如图29和图30所示，第二晶体管的栅电极22与第八晶体管的栅电极82为一体结构。第二晶体管的栅电极22的形状可以为开口朝向显示区的“n”字型，第八晶体管的栅电极82的形状可以为折线形，且至少部分沿第一方向D1延伸。
在示例性实施方式中，如图29和图30所示，第三晶体管的栅电极32单独设置，且形状可以为字型。
在示例性实施方式中，如图29和图30所示，第四晶体管的栅电极42、第十六晶体管的栅电极162和第三电容的C31为一体结构。第三电容的C31的形状为矩形状。本级移位寄存器的第四晶体管的栅电极42位于第三电容的C31靠近下一级移位寄存器的一侧，第四晶体管的栅电极42的形状为条状，且沿第二方向D2延伸。第十六晶体管的栅电极162位于第三电容的C31靠近显示区的一侧，第十六晶体管的栅电极162的形状呈字型。
在示例性实施方式中，如图29和图30所示，第五晶体管的栅电极52单独设置。第五晶体管的栅电极52的形状为折线状，且至少部分沿第一方向D1延伸。
在示例性实施方式中，如图29和图30所示，第六晶体管的栅电极62和第一电容的第一极板C11为一体结构。本级移位寄存器的第六晶体管的栅电极62位于第一电容的第一极板C11靠近下一级移位寄存器的一侧。第一电容的第一极板C11的形状可以为第六晶体管的栅电极62的形状为折线状，且至少部分沿第二方向D2延伸。
在示例性实施方式中，如图29和图30所示，第七晶体管的栅电极72单独设置。第七晶体管的栅电极72的形状为折线状，且至少部分沿第一方向D1延伸。
在示例性实施方式中，如图29和图30所示，第九晶体管的栅电极92、第十八晶体管的栅电极182和第二电容的第一极板C21为一体结构。第九晶体管的栅电极92和第十八晶体管的栅电极182均位于第二电容的第一极板C21靠近显示区一侧，第九晶体管的栅电极92与第二电容的第一极板C21靠近显示区的边界连接，本级移位寄存器的第十八晶体管的栅电极182与第二电容的第一极板C21靠近上一级移位寄存器的边界连接。第二电容的第一极板C21的形状可以为矩形状，矩形状的角部可设置倒角。第九晶体管的栅电极92的形状为条状，且沿第一方向D1延伸。第十八晶体管的栅电极182包括：第一连接段182A和至少一个第一分支段182B，第二电容的第一极板C21位于第一连接段182A远离显示区的一侧，第一分支段182B位于第一连接段182A靠近显示区的一侧，第一连接段182A分别与第二电容的第一极板C21和至少一个第一分支段182B电连接。第十八晶体管的栅电极182可以呈梳妆结构。第一连接段182A的形状可以呈字型，相当于“梳背”，第一分支段182B的形状可以为条状，且沿第一方向D1延伸，相当于“梳齿”，至少一个第一分支段182B沿第二方向D2排布。
在示例性实施方式中，如图29和图30所示，第十晶体管的栅电极102和第十七晶体管的栅电极172为一体结构。第十晶体管的栅电极102的形状可以呈向左旋转的“F”字型，第十七晶体管的栅电极172可以包括：第二连接段172A和至少一个第二分支段172B。第二分支段172B位于第二连接段172A靠近显示区的一侧。第十七晶体管的栅电极172的形状为梳状结构，第二连接段172A沿第二方向D2延伸，相当于“梳背”，第二分支段172B沿第一方向D1延伸，相当于“梳齿”，至少一个第二分支段172B沿第二方向D2排布。
在示例性实施方式中，如图29和图30所示，第十一晶体管的栅电极112和第十五晶体管的栅电极152为一体结构，第十一晶体管的栅电极112和第十五晶体管的栅电极152的一体结构的形状为条状，且沿第一方向D1延伸。
在示例性实施方式中，如图29和图30所示，第十二晶体管的栅电极122单独设置，且形状可以呈字型。
在示例性实施方式中，如图29和图30所示，第十三晶体管的栅电极132单独设置。第十三晶体管的栅电极132的形状为条状，且沿第二方向D2延伸。
在示例性实施方式中，如图29和图30所示，第十九晶体管的栅电极192单独设置。第十九晶体管的栅电极192包括：第三连接段192A和至少一个第三分支段192B。第三分支段192B位于第三连接段192A远离显示区的一侧。第十九晶体管的栅电极192可以呈梳状结构，第三连接段192A的形状可以呈字型，相当于“梳背”，第三分支段192B的形状为条状，且沿第一方向D1延伸，相当于“梳齿”，至少一个第三分支段192B沿第二方向D2排布。
在示例性实施方式中，如图29和图30所示，第四电容的第一极板C41单独设置，且位于第五晶体管的栅电极52和第十八晶体管的栅电极182之间。第四电容的第一极板C41包括：主体部和凸起部，主体部的形状可以为矩形状，凸起部位于主体部远离显示区的一侧。在示例性实施方式中，如图29和图30所示，第一连接部L1单独设置，且的形状为块状。第一连接部L1位于第四晶体管的栅电极42远离显示区的一侧，且位于本级移位寄存器的第三电容的第一极板C31靠近下一级移位寄存器的一侧。
在示例性实施方式中，如图29和图30所示，第一晶体管的栅电极12跨设在第一晶体管的有源图案上，第二晶体管的栅电极22跨设在第二晶体管的有源图案上，第三晶体管的栅电极32跨设在第三晶体管的有源图案上，第四晶体管的栅电极42跨设在第四晶体管的有源图案上，第五晶体管的栅电极52跨设在第五晶体管的有源图案上，第六晶体管的栅电极62跨设在第六晶体管的有源图案上，第七晶体管的栅电极72跨设在第七晶体管的有源图案上，第八晶体管的栅电极82跨设在第八晶体管的有源图案上，第九晶体管的栅电极92跨设在第九晶体管的有源图案上，第十晶体管的栅电极102跨设在第十晶体管的有源图案上，第十一晶体管的栅电极112跨设在第十一晶体管的有源图案上，第十二晶体管的栅电极122跨设在第十二晶体管的有源图案上，第十三晶体管的栅电极132跨设在第十三晶体管的有源图案上，第十四晶体管的栅电极142跨设在第十四晶体管的有源图案上，第十五晶体管的栅电极152跨设在第十五晶体管的有源图案上，第十六晶体管的栅电极162跨设在第十六晶体管的有源图案上，第十七晶体管的栅电极172的至少一个第二分支段172B跨设在第十七晶体管的有源图案上，第十八晶体管的栅电极182的至少一个第一分支段182B跨设在第十八晶体管的有源图案上，第十九晶体管的栅电极192的至少一个第三分支段192B跨设在第十九晶体管的有源图案上，也就是说，至少一个晶体管的控制极的延伸方向与有源图案的延伸方向相互垂直。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对半导体层进行导体化处理，被第一导电层遮挡区域的半导体层形成第一晶体管至第十九晶体管的沟道区域，未被第一导电层遮挡区域的半导体层被导体化，即第一晶体管至第十九晶体管的第一区和第二区均被导体化。如图30所示，本公开中的第一连接部L1被处理成导体化层，形成导体化的第一连接部L1。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成有前述图案的基底上，沉积第二绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层图案的第二绝缘层图案和位于第二绝缘层图案上的第二导电层图案，如图31和图32所示，图31为图26中的第二导电层图案的示意图，图32为图26形成第二导电层图案后的示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，如图31和图32所示，第二导电层图案可以至少包括：位于每个移位寄存器的第一电容的第二极板C12至第四电容的第二极板C42以及第二连接部L2。
在示例性实施方式中，如图31和图32所示，第一电容的第二极板C12在基底上的正投影与第一电容的第一极板在基底上的正投影至少部分交叠。第一电容的第二极板C12的面积小于第一电容的第一极板的面积。第一电容的第二极板C12的形状与第一电容的第一极板的形状相同。
在示例性实施方式中，如图31和图32所示，第二电容的第二极板C22在基底上的正投影与第二电容的第一极板在基底上的正投影至少部分交叠。第二电容的第二极板C22的面积小于第二电容的第一极板的面积。第二电容的第二极板C22的形状可以为矩形状，矩形状的角部可以设置倒角，且沿第二方向D2延伸。
在示例性实施方式中，如图31和图32所示，第三电容的第二极板C32在基底上的正投影与第三电容的第一极板在基底上的正投影至少部分交叠。第三电容的第二极板C32的面积小于第三电容的第一极板的面积。第三电容的第二极板C32的形状可以为矩形状。第三电容的第二极板C32靠近靠近第一电容的第二极板C32的边界设置有凹槽K，凹槽K在基底上的正投影与第三电容的第一极板在基底上的正投影至少部分交叠，且暴露出第三电容的第一极板。
在示例性实施方式中，如图31和图32所示，第四电容的第二极板C42在基底上的正投影位于第四电容的第一极板在基底上的正投影至少部分交叠。第四电容的第二极板C42的形状与第四电容的第一极板C41的形状相同，第四电容的第二极板C42的面积小于第四电容的第一极板的面积。
在示例性实施方式中，如图31和图32所示，第二连接部L2位于第三电容的第二极板C32和第二电容的第二极板C22之间，且位于本级移位寄存器的第一电容C12靠近下一级移位寄存器的一侧。第二连接部L2的形状为折线形，且至少部分沿第一方向D1延伸。
(4)形成第三绝缘层图案。在示例性实施方式中，形成第三绝缘层图案可以包括：在形成有前述图案的基底上，沉积第三绝缘薄膜，通过图案化工艺对第三绝缘薄膜进行构图，形成覆盖前述结构的第三绝缘层图案，第三绝缘层开设有多个过孔图案，如图33所示，图33为图26形成第三绝缘层图案后的示意图。
在示例性实施方式中，如图33所示，每个移位寄存器的第三绝缘层图案可以至少包括：第一过孔V1至第五十一过孔V51。
在示例性实施方式中，如图33所示，第一过孔V1在基底上的正投影位于第一晶体管的有源图案的第一区在基底上的正投影的范围之内，第一过孔V1内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第一晶体管的有源图案的第一区的表面，第一过孔V1被配置为使后续形成的第一晶体管的第一极(也是第十四晶体管的第一极)通过该过孔与第一晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第二过孔V2在基底上的正投影位于第一晶体管的有源图案的第二区在基底上的正投影的范围之内，第二过孔V2内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第一晶体管的有源图案的第二区的表面，第二过孔V2被配置为使后续形成的第一晶体管的第二极通过该过孔与第一晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第三过孔V3在基底上的正投影位于第二晶体管的有源图案的第一区在基底上的正投影的范围之内，第三过孔V3内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第二晶体管的有源图案的第一区的表面，第三过孔V3被配置为使后续形成的第二晶体管的第一极通过该过孔与第二晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第四过孔V4在基底上的正投影位于第二晶体管的有源图案的第二区在基底上的正投影的范围之内，第四过孔V4内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第二晶体管的有源图案的第二区的表面，第四过孔V4被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极和第十一晶体管的第一极)通过该过孔与第二晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第五过孔V5在基底上的正投影位于第三晶体管的有源图案的第一区在基底上的正投影的范围之内，第五过孔V5内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第三晶体管的有源图案的第一区的表面，第五过孔V5被配置为使后续形成的第三晶体管的第一极通过该过孔与第三晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第六过孔V6在基底上的正投影位于第三晶体管的有源图案的第二区在基底上的正投影的范围之内，第六过孔V6内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第三晶体管的有源图案的第二区的表面，第六过孔V6被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极和第十一晶体管的第一极)通过该过孔与第三晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第七过孔V7在基底上的正投影位于第四晶体管的有源图案的第一区在基底上的正投影的范围之内，第七过孔V7内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第四晶体管的有源图案的第一区的表面，第七过孔V7被配置为使后续形成的第四晶体管的第一极通过该过孔与第四晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第八过孔V8在基底上的正投影位于第四晶体管的有源图案的第二区在基底上的正投影的范围之内，第八过孔V8内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第四晶体管的有源图案的第二区的表面，第八过孔V8被配置为使后续形成的第四晶体管的第二极(也是第五晶体管的第二极)通过该过孔与第四晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第九过孔V9在基底上的正投影位于第五晶体管的有源图案的第一区(也是第八晶体管的有源图案的第一区和第十三晶体管的有源图案的第一区)在基底上的正投影的范围之内，第九过孔V9内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第四晶体管的有源图案的第二区的表面，第九过孔V9被配置为使后续形成的第五晶体管的第一极(也是第八晶体管的第一极、第九晶体管的第一极和第十三晶体管的第一极)通过该过孔与第五晶体管的有源图案的第一区(也是第八晶体管的有源图案的第一区和第十三晶体管的有源图案的第一区)连接。
在示例性实施方式中，如图33所示，第十过孔V10在基底上的正投影位于第五晶体管的有源图案的第二区在基底上的正投影的范围之内，第十过孔V10内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第五晶体管的有源图案的第二区的表面，第十过孔V10被配置为使后续形成的第四晶体管的第二极(也是第五晶体管的第二极)通过该过孔与第五晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第十一过孔V11在基底上的正投影位于第六晶体管的有源图案的第一区在基底上的正投影的范围之内，第十一过孔V11内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第六晶体管的有源图案的第一区的表面，第十一过孔V11被配置为使后续形成的第六晶体管的第一极通过该过孔与第六晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第十二过孔V12在基底上的正投影位于第六晶体管的有源图案的第二区在基底上的正投影的范围之内，第十二过孔V12内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第六晶体管的有源图案的第二区的表面，第十二过孔V12被配置为使后续形成的第六晶体管的第二极(也是第七晶体管的第一极)通过该过孔与第六晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第十三过孔V13在基底上的正投影位于第七晶体管的有源图案的第一区在基底上的正投影的范围之内，第十三过孔V13内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第七晶体管的有源图案的第一区的表面，第十三过孔V13被配置为使后续形成的第六晶体管的第二极(也是第七晶体管的第一极)通过该过孔与第七晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第十四过孔V14在基底上的正投影位于第七晶体管的有源图案的第二区(也是第八晶体管的有源图案的第二区)在基底上的正投影的范围之内，第十四过孔V14内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第七晶体管的有源图案的第二区(也是第八晶体管的有源图案的第二区)的表面，第十四过孔V14被配置为使后续形成的第七晶体管的第二极(也是第八晶体管的第二极)通过该过孔与第七晶体管的有源图案的第二区(也是第八晶体管的有源图案的第二区)连接。
在示例性实施方式中，如图33所示，第十五过孔V15在基底上的正投影位于第九晶体管的有源图案的第一区在基底上的正投影的范围之内，第十五过孔V15内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第九晶体管的有源图案的第一区的表面，第十五过孔V15被配置为使后续形成的第五晶体管的第一极(也是第八晶体管的第一极、第九晶体管的第一极和第十三晶体管的第一极)通过该过孔与第九晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第十六过孔V16在基底上的正投影位于第九晶体管的有源图案的第二区在基底上的正投影的范围之内，第十六过孔V16内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第九晶体管的有源图案的第二区的表面，第十六过孔V16被配置为使后续形成的第九晶体管的第二极(也是第十晶体管的第二极)通过该过孔与第九晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第十七过孔V17在基底上的正投影位于第十晶体管的有源图案的第一区在基底上的正投影的范围之内，第十七过孔V17内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十晶体管的有源图案的第一区的表面，第十七过孔V17被配置为使后续形成的第十晶体管的第一极通过该过孔与第十晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第十八过孔V18在基底上的正投影位于第十晶体管的有源图案的第二区在基底上的正投影的范围之内，第十八过孔V18内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十晶体管的有源图案的第二区的表面，第十八过孔V18被配置为使后续形成的第九晶体管的第二极(也是第十晶体管的第二极)通过该过孔与第十晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第十九过孔V19在基底上的正投影位于第十一晶体管的有源图案的第一区在基底上的正投影的范围之内，第十九过孔V19内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十一晶体管的有源图案的第一区的表面，第十九过孔V19被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极和第十一晶体管的第一极)通过该过孔与第十一晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第二十过孔V20在基底上的正投影位于第十一晶体管的有源图案的第二区在基底上的正投影的范围之内，第二十过孔V20内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十一晶体管的有源图案的第二区的表面，第二十过孔V20被配置为使后续形成的第十一晶体管的第二极通过该过孔与第十一晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第二十一过孔V21在基底上的正投影位于第十二晶体管的有源图案的第一区在基底上的正投影的范围之内，第二十一过孔V21内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十二晶体管的有源图案的第一区的表面，第二十一过孔V21被配置为使后续形成的第十二晶体管的第一极通过该过孔与第十二晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第二十二过孔V22在基底上的正投影位于第十二晶体管的有源图案的第二区(也是第十六晶体管的有源图案的第二区)在基底上的正投影的范围之内，第二十二过孔V22内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十二晶体管的有源图案的第二区(也是第十六晶体管的有源图案的第二区)的表面，第二十二过孔V22被配置为使后续形成的第十二晶体管的第二极(也是第十六晶体管的第二极)通过该过孔与第十二晶体管的有源图案的第二区(也是第十六晶体管的有源图案的第二区)连接。
在示例性实施方式中，如图33所示，第二十三过孔V23在基底上的正投影位于第十三晶体管的有源图案的第二区在基底上的正投影的范围之内，第二十三过孔V23内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十三晶体管的有源图案的第二区的表面，第二十三过孔V23被配置为使后续形成的第十三晶体管的第二极通过该过孔与第十三晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第二十四过孔V24在基底上的正投影位于第十四晶体管的有源图案的第一区在基底上的正投影的范围之内，第二十四过孔V24内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十四晶体管的有源图案的第一区的表面，第二十四过孔V24被配置为使后续形成的第一晶体管的第一极(也是第十四晶体管的第一极)通过该过孔与第十四晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第二十五过孔V25在基底上的正投影位于第十四晶体管的有源图案的第二区在基底上的正投影的范围之内，第二十五过孔V25内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十四晶体管的有源图案的第二区的表面，第二十五过孔V25被配置为使后续形成的第十四晶体管的第二极(也是第十五晶体管的第一极)通过该过孔与第十四晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第二十六过孔V26在基底上的正投影位于第十五晶体管的有源图案的第一区在基底上的正投影的范围之内，第二十六过孔V26内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十五晶体管的有源图案的第一区的表面，第二十六过孔V26被配置为使后续形成的第十四晶体管的第二极(也是第十五晶体管的第一极)通过该过孔与第十五晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第二十七过孔V27在基底上的正投影位于第十五晶体管的有源图案的第二区在基底上的正投影的范围之内，第二十七过孔V27内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十五晶体管的有源图案的第二区的表面，第二十七过孔V27被配置为使后续形成的第十五晶体管的第二极通过该过孔与第十五晶体管的有源图案的第二区连接。
在示例性实施方式中，如图33所示，第二十八过孔V28在基底上的正投影位于第十六晶体管的有源图案的第一区在基底上的正投影的范围之内，第二十八过孔V28内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十六晶体管的有源图案的第一区的表面，第二十八过孔V28被配置为使后续形成的第十六晶体管的第一极通过该过孔与第十六晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第二十九过孔V29在基底上的正投影位于第十七晶体管的有源图案的第一区在基底上的正投影的范围之内，第二十九过孔V29内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十七晶体管的有源图案的第一区的表面，第二十九过孔V29被配置为使后续形成的第十七晶体管的第一极通过该过孔与第十七晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第三十过孔V30在基底上的正投影位于第十七晶体管的有源图案的第二区(也是第十八晶体管的有源图案的第一区)在基底上的正投影的范围之内，第三十过孔V30内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十七晶体管的有源图案的第二区(也是第十八晶体管的有源图案的第一区)的表面，第三十过孔V30被配置为使后续形成的第十七晶体管的第二极(也是第十八晶体管的第一极)通过该过孔与第十七晶体管的有源图案的第二区(也是第十八晶体管的有源图案的第一区)连接。
在示例性实施方式中，如图33所示，第三十一过孔V31在基底上的正投影位于第十八晶体管的有源图案的第二区(也是第十九晶体管的有源图案的第二区)在基底上的正投影的范围之内，第三十一过孔V31内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十八晶体管的有源图案的第二区(也是第十九晶体管的有源图案的第二区)的表面，第三十一过孔V31被配置为使后续形成的第十八晶体管的第二极(也是第十九晶体管的第二极)通过该过孔与第十八晶体管的有源图案的第二区(也是第十九晶体管的有源图案的第二区)连接。
在示例性实施方式中，如图33所示，第三十二过孔V32在基底上的正投影位于第十九晶体管的有源图案的第一区在基底上的正投影的范围之内，第三十二过孔V32内的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十九晶体管的有源图案的第一区的表面，第三十二过孔V32被配置为使后续形成的第十九晶体管的第一极通过该过孔与第十九晶体管的有源图案的第一区连接。
在示例性实施方式中，如图33所示，第三十三过孔V33在基底上的正投影位于第一晶体管的栅电极(也是第十四晶体管的栅电极)在基底上的正投影的范围之内，第三十三过孔V33内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第一晶体管的栅电极(也是第十四晶体管的栅电极)的表面，第三十三过孔V33被配置为使后续形成的第三连接部和第二晶体管的第一极通过该过孔与第一晶体管的栅电极(也是第十四晶体管的栅电极)连接。
在示例性实施方式中，如图33所示，第三十四过孔V34在基底上的正投影位于第二晶体管的栅电极(也是第八晶体管的栅电极)在基底上的正投影的范围之内，第三十四过孔V34内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第二晶体管的栅电极(也是第八晶体管的栅电极)的表面，第三十四过孔V34被配置为使后续形成的第一晶体管的第二极和第十三晶体管的第二极通过该过孔与第二晶体管的栅电极(也是第八晶体管的栅电极)连接。
在示例性实施方式中，如图33所示，第三十五过孔V35在基底上的正投影位于第三晶体管的栅电极在基底上的正投影的范围之内，第三十五过孔V35内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第三晶体管的栅电极的表面，第三十五过孔V35被配置为使后续形成的第五连接部通过该过孔与第三晶体管的栅电极连接。
在示例性实施方式中，如图33所示，第三十六过孔V36在基底上的正投影位于第四晶体管的栅电极(也是第十六晶体管的栅电极和第三电容的第一极板)在基底上的正投影的范围之内，第三十六过孔V36内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第四晶体管的栅电极(也是第十六晶体管的栅电极和第三电容的第一极板)的表面，第三十六过孔V36被配置为使后续形成的第十五晶体管的第二极和第十六晶体管的第一极通过该过孔与第四晶体管的栅电极(也是第十六晶体管的栅电极和第三电容的第一极板)连接。
在示例性实施方式中，如图33所示，第三十七过孔V37在基底上的正投影位于第五晶体管的栅电极在基底上的正投影的范围之内，第三十七过孔V37内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第五晶体管的栅电极的表面，第三十七过孔V37被配置为使后续形成的第二晶体管的第二极(也是第三晶体管的第二极和第十一晶体管的第一极)通过该过孔与第五晶体管的栅电极连接。
在示例性实施方式中，如图33所示，第三十八过孔V38在基底上的正投影位于第六晶体管的栅电极(第一电容的第一极板)在基底上的正投影的范围之内，第三十八过孔V38内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第六晶体管的栅电极(第一电容的第一极板)的表面，第三十八过孔V38被配置为使后续形成的第十一晶体管的第二极通过该过孔与第六晶体管的栅电极(第一电容的第一极板)连接。
在示例性实施方式中，如图33所示，第三十九过孔V39在基底上的正投影位于第七晶体管的栅电极在基底上的正投影的范围之内，第三十九过孔V39内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第七晶体管的栅电极的表面，第三十九过孔V39被配置为使后续形成的第四连接部和第六晶体管的第一极通过该过孔与第七晶体管的栅电极连接。
在示例性实施方式中，如图33所示，第四十过孔V40在基底上的正投影位于第九晶体管的栅电极(也是第十八晶体管的栅电极和第二电容的第一极板)在基底上的正投影的范围之内，第四十过孔V40内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第九晶体管的栅电极(也是第十八晶体管的栅电极和第二电容的第一极板)的表面，第四十过孔V40被配置为使后续形成的第七晶体管的第二极和第八晶体管的第二极通过该过孔与第九晶体管的栅电极(也是第十八晶体管的栅电极和第二电容的第一极板)连接。
在示例性实施方式中，如图33所示，第四十一过孔V41在基底上的正投影位于第十晶体管的栅电极(也是第十七晶体管的栅电极)在基底上的正投影的范围之内，第四十一过孔V41内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十晶体管的栅电极(也是第十七晶体管的栅电极)的表面，第四十一过孔V41被配置为使后续形成的第十二晶体管的第二极和第十六晶体管的第二极通过该过孔与第十晶体管的栅电极(也是第十七晶体管的栅电极)连接。
在示例性实施方式中，如图33所示，第四十二过孔V42在基底上的正投影位于第十一晶体管的栅电极(也是第十五晶体管的栅电极)在基底上的正投影的范围之内，第四十二过孔V42内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十一晶体管的栅电极(也是第十五晶体管的栅电极)的表面，第四十二过孔V42被配置为使后续形成的第三晶体管的第一极通过该过孔与第十一晶体管的栅电极(也是第十五晶体管的栅电极)连接。
在示例性实施方式中，如图33所示，第四十三过孔V43在基底上的正投影位于第十二晶体管的栅电极在基底上的正投影的范围之内，第四十三过孔V43内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十二晶体管的栅电极的表面，第四十三过孔V43被配置为使后续形成的第十晶体管的第一极通过该过孔与第十二晶体管的栅电极连接。
在示例性实施方式中，如图33所示，第四十四过孔V44在基底上的正投影位于第十三晶体管的栅电极在基底上的正投影的范围之内，第四十四过孔V44内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十三晶体管的栅电极的表面，第四十四过孔V44被配置为使后续形成的第七连接部通过该过孔与第十三晶体管的栅电极连接。
在示例性实施方式中，如图33所示，第四十五过孔V45在基底上的正投影位于第十九晶体管的栅电极在基底上的正投影的范围之内，第四十五过孔V45内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第十九晶体管的栅电极的表面，第四十五过孔V45被配置为使后续形成的第八连接部通过该过孔与第十九晶体管的栅电极连接。
在示例性实施方式中，如图33所示，第四十六过孔V46在基底上的正投影位于第四电容的第一极板在基底上的正投影的范围之内，第四十六过孔V46内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第四电容的第一极板的表面，第四十六过孔V46被配置为使后续形成的第十晶体管的第一极通过该过孔与第四电容的第一极板连接。
在示例性实施方式中，如图33所示，第四十七过孔V47在基底上的正投影位于第一连接部在基底上的正投影的范围之内，第四十七过孔V47内的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第一连接部的表面，第四十七过孔V47被配置为使后续形成的第四晶体管的第一极通过该过孔与第一连接部连接。
在示例性实施方式中，如图33所示，第四十八过孔V48在基底上的正投影位于第一电容的第二极板在基底上的正投影的范围之内，第四十八过孔V48暴露出第一电容的第二极板的表面，第四十八过孔V48被配置为使后续形成的第六晶体管的第二极(也是第七晶体管的第一极)通过该过孔与第一电容的第二极板连接。
在示例性实施方式中，如图33所示，第四十九过孔V49在基底上的正投影位于第二电容的第二极板在基底上的正投影的范围之内，第四十九过孔V49暴露出第二电容的第二极板的表面，第四十九过孔V49被配置为使后续形成的第五晶体管的第一极(也是第八晶体管的第一极、第九晶体管的第一极和第十三晶体管的第一极)通过该过孔与第二电容的第二极板连接。
在示例性实施方式中，如图33所示，第五十过孔V50在基底上的正投影位于第三电容的第二极板在基底上的正投影的范围之内，第五十过孔V50暴露出第三电容的第二极板的表面，第五十过孔V50被配置为使后续形成的第四晶体管的第二极(也是第五晶体管的第二极)通过该过孔与第三电容的第二极板连接。
在示例性实施方式中，如图33所示，第五十一过孔V51在基底上的正投影位于第四电容的第二极板在基底上的正投影的范围之内，第五十一过孔V51暴露出第四电容的第二极板的表面，第五十一过孔V51被配置为使后续形成的第九晶体管的第二极(也是第十晶体管的第二极)通过该过孔与第四电容的第二极板连接。
在示例性实施方式中，如图33所示，第五十二过孔V52在基底上的正投影位于第二连接部在基底上的正投影的范围之内，第五十二过孔V52暴露出第二连接部的表面，第五十二过孔V52被配置为使后续形成的第十二晶体管的第一极通过该过孔与第二连接部连接。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第三绝缘层上的第四导电层，如图34和图35所示，图34为图26中的第三导电层图案的示意图，图35为图26形成第三导电层图案后的示意图。示例性实施方式中，第三导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，如图34和图35所示，第三导电层图案可以至少包括：第一晶体管的第一极13和第二极14至第十九晶体管的第一极193和第二极194、第三连接部L3至第八连接部L8。
在示例性实施方式中，如图34和图35所示，第一晶体管的第一极13和第十四晶体管的第一极143为一体结构。第一晶体管的第一极13(也是第十四晶体管的第一极143)的形状为呈“┘”。第一晶体管的第一极13(也是第十四晶体管的第一极143)通过第一过孔与第一晶体管的有源图案的第一区连接，且通过第二十四过孔与第十四晶体管的有源图案的第一区连接。
在示例性实施方式中，如图34和图35所示，第一晶体管的第二极14单独设置。第一晶体管的第二极14的形状为条状，且沿第二方向D2延伸。第一晶体管的第二极14通过第二过孔与第一晶体管的有源图案的第二区连接，且通过第三十四过孔与第二晶体管的栅电极(也是第八晶体管的栅电极)连接。
在示例性实施方式中，如图34和图35所示，第二晶体管的第一极23单独设置。第二晶体管的第一极23的形状为条状，且沿第二方向D2延伸。第二晶体管的第一极23通过第三过孔与第二晶体管的有源图案的第一区连接，且通过第三十三过孔与第一晶体管的栅电极(也是第十四晶体管的栅电极)连接。
在示例性实施方式中，如图34和图35所示，第二晶体管的第二极24、第三晶体管的第二极34和第十一晶体管的第一极113为一体结构。第二晶体管的第二极24、第三晶体管的第二极34和第十一晶体管的第一极113的一体结构为折线状，且至少部分沿第二方向D2延伸。第二晶体管的第二极24(也是第三晶体管的第二极34和第十一晶体管的第一极113)通过第四过孔与与第二晶体管的有源图案的第二区连接，通过第六过孔与第三晶体管的有源图案的第二区连接，通过第十九过孔与第十一晶体管的有源图案的第一区连接，且通过第三十七过孔与第五晶体管的栅电极连接。
在示例性实施方式中，如图34和图35所示，第三晶体管的第一极33单独设置。第三晶体管的第一极33的形状为条状，且沿第二方向D2延伸。第三晶体管的第一极33通过第五过孔与第三晶体管的有源图案的第一区连接，且通过第四十二过孔与第十一晶体管的栅电极(也是第十五晶体管的栅电极)连接。
在示例性实施方式中，如图34和图35所示，第四晶体管的第一极43单独设置。第四晶体管的第一极43的形状为条状，且至少部分沿第二方向D2延伸。第四晶体管的第一极43通过第七过孔与第四晶体管的有源图案的第一区连接，且通过第四十七过孔与第一连接部连接。
在示例性实施方式中，如图34和图35所示，第四晶体管的第二极44和第五晶体管的第二极54为一体结构单独设置。第四晶体管的第二极44和第五晶体管的第二极54一体结构的形状为折线状，且至少部分沿第二方向D2延伸。第四晶体管的第二极44(也是第五晶体管的第二极54)通过第八过孔与第四晶体管的有源图案的第二区连接，通过第十过孔与第五晶体管的有源图案的第二区连接，且通过第五十过孔与第三电容的第二极板连接。
在示例性实施方式中，如图34和图35所示，第五晶体管的第一极53、第八晶体管的第一极83、第九晶体管的第一极93和第十三晶体管的第一极133为一体结构，第五晶体管的第一极53、第八晶体管的第一极83、第九晶体管的第一极93和第十三晶体管的第一极133的一体结构为折线形，且至少部分沿第二方向D2延伸。第五晶体管的第一极53(也是第八晶体管的第一极83、第九晶体管的第一极83和第十三晶体管的第一极133)通过第九过孔与第五晶体管的有源图案的第一区(也是第八晶体管的有源图案的第一区和第十三晶体管的有源图案的第一区)连接，通过第十五过孔与第九晶体管的有源图案的第一区连接，且通过第四十九过孔与第二电容的第二极板连接。
在示例性实施方式中，如图34和图35所示，第六晶体管的第一极63单独设置。第六晶体管的第一极63的形状呈“I”字型。第六晶体管的第一极63通过第十一过孔与第六晶体管的有源图案的第一区连接，且通过第三十九过孔与第七晶体管的栅电极连接。
在示例性实施方式中，如图34和图35所示，第六晶体管的第二极64和第七晶体管的第一极73为一体结构。第六晶体管的第二极64和第七晶体管的第一极73的一体结构的形状呈字型。第六晶体管的第二极64(也是第七晶体管的第一极73)通过第十二过孔与第六晶体管的有源图案的第二区连接，通过第十三过孔与第七晶体管的有源图案的第一区连接，且通过第四十八过孔与第一电容的第二极板连接。
在示例性实施方式中，如图34和图35所示，第七晶体管的第二极74和第八晶体管的第一极84为一体结构。第七晶体管的第二极74和第八晶体管的第一极84的一体结构的形状为条状，且沿第一方向D1延伸。第七晶体管的第二极74(也是第八晶体管的第一极84)通过第十四过孔与第七晶体管的有源图案的第二区(也是第八晶体管的有源图案的第二区)连接，且通过第四十过孔与第九晶体管的栅电极(也是第十八晶体管的栅电极和第二电容的第一极板)连接。
在示例性实施方式中，如图34和图35所示，第九晶体管的第二极94和第十晶体管的第一极104为一体结构。第九晶体管的第二极94和第十晶体管的第一极104的一体结构的形状为“┘”字型。第九晶体管的第二极94(也是第十晶体管的第一极104)通过第十六过孔与第九晶体管的有源图案的第二区连接，通过第十八过孔与第十晶体管的有源图案的第二区连接，且通过第五十一过孔与第四电容的第二极板连接。
在示例性实施方式中，如图34和图35所示，第十晶体管的第一极103可以单独设置。第十晶体管的第一极103的形状折线状，且至少部分沿第二方向D2延伸。第十晶体管的第一极103通过第十七过孔与第十晶体管的有源图案的第一区连接，通过第四十三过孔与第十二晶体管的栅电极连接，且通过第四十六过孔与第四电容的第一极板连接。
在示例性实施方式中，如图34和图35所示，第十一晶体管的第二极114可以单独设置。第十一晶体管的第二极114的形状为折线状，且至少部分沿第二方向D2延伸。第十一晶体管的第二极114通过第二十过孔与第十一晶体管的有源图案的第二区连接，且通过第三十八过孔与第六晶体管的栅电极(第一电容的第一极板)连接。
在示例性实施方式中，如图34和图35所示，第十二晶体管的第一极123可以单独设置。第十二晶体管的第一极123的形状为条状，且沿第一方向D1延伸。第十二晶体管的第一极123通过第二十一过孔与第十二晶体管的有源图案的第一区连接，且通过第五十二过孔与第二连接部连接。
在示例性实施方式中，如图34和图35所示，第十二晶体管的第二极124和第十六晶体管的第一极164为一体结构。第十二晶体管的第二极124和第十六晶体管的第一极164的一体结构的形状为条状，且沿第一方向D1延伸。第十二晶体管的第二极124(也是第十六晶体管的第一极164)通过第二十二过孔与第十二晶体管的有源图案的第二区(也是第十六晶体管的有源图案的第二区)连接，且通过第四十一过孔与第十晶体管的栅电极(也是第十七晶体管的栅电极)连接。
在示例性实施方式中，如图34和图35所示，第十三晶体管的第二极134可以单独设置。第十三晶体管的第二极134的形状为条状，且沿第一方向D1延伸。第十三晶体管的第二极134通过第二十三过孔与第十三晶体管的有源图案的第二区连接，通过第三十四过孔与第二晶体管的栅电极(也是第八晶体管的栅电极)连接，且通过第五十二过孔与第二连接部连接。
在示例性实施方式中，如图34和图35所示，第十四晶体管的第二极144和第十五晶体管的第一极153为一体结构。第十四晶体管的第二极144和第十五晶体管的第一极153的一体结构的形状呈向右旋转的“几”字型。第十四晶体管的第二极144(也是第十五晶体管的第一极153)通过第二十五过孔与第十四晶体管的有源图案的第二区连接，且通过第二十六过孔与第十五晶体管的有源图案的第一区连接。
在示例性实施方式中，如图34和图35所示，第十五晶体管的第二极154可以单独设置。第十五晶体管的第二极154的形状为条状，且沿第二方向D2延伸。第十五晶体管的第二极154通过第二十七过孔与第十五晶体管的有源图案的第二区连接，且通过第三十六过孔与第四晶体管的栅电极(也是第十六晶体管的栅电极和第三电容的第一极板)连接。
在示例性实施方式中，如图34和图35所示，第十六晶体管的第一极163可以单独设置。第十六晶体管的第一极163的形状为条状，且沿第一方向D1延伸。第十六晶体管的第一极163通过第二十八过孔与第十六晶体管的有源图案的第一区连接，且通过第三十六过孔与第四晶体管的栅电极(也是第十六晶体管的栅电极和第三电容的第一极板)连接。
在示例性实施方式中，如图34和图35所示，第十七晶体管的第一极173可以单独设置。第十七晶体管的第一极173包括：第四连接段173A和至少一个第四分支段173B，至少一个第四分支段173B位于第四连接段173A靠近显示区的一侧，且与第四连接段173A连接。第十七晶体管的第一极173呈梳状结构，第四连接段173A的形状为“┘”字型，相当于“梳背”，第四分支段173B沿第一方向D1延伸，至少一个第四分支段173B沿第二方向D2排布，相当于“梳齿”。第十七晶体管的第一极173通过第二十九过孔与第十七晶体管的有源图案的第一区连接。
在示例性实施方式中，如图34和图35所示，第十七晶体管的第二极174和第十八晶体管的第一极183为一体结构。第十七晶体管的第二极174和第十八晶体管的第一极183的一体结构的形状呈梳状结构。第十七晶体管的第二极174和第十八晶体管的第一极183的一体结构包括：第五连接段174A和至少一个第五分支段174B，至少一个第五分支段174B与第五连接段174A连接，且位于第五连接段174A远离显示区的一侧，第五连接段174A的形状为条状，且沿第二方向D2延伸，相当于“梳背”，至少一个第五分支段174B的形状为条状，且沿第一方向D1延伸，至少一个第五分支段174B沿第二方向D2排布，相当于“梳齿”。第十七晶体管的第二极174(也是第十八晶体管的第一极183)通过第三十过孔与第十七晶体管的有源图案的第二区(也是第十八晶体管的有源图案的第一区)连接。
在示例性实施方式中，如图34和图35所示，第十八晶体管的第二极184和第十九晶体管的第二极194为一体结构。第十八晶体管的第二极184和第十九晶体管的第二极194的一体结构的形状呈梳状结构。第十八晶体管的第二极184和第十九晶体管的第二极194的一体结构包括：第六连接段184A和至少一个第六分支段184B，至少一个第六分支段184B与第六连接段184A连接，且位于第六连接段184A靠近显示区的一侧，第六连接段184A的形状为条状，且沿第二方向D2延伸，相当于“梳背”，至少一个第六分支段184B的形状为条状，且沿第一方向D1延伸，至少一个第六分支段184B沿第二方向D2排布，相当于“梳齿”。第十八晶体管的第二极184(也是第十九晶体管的第二极194)通过第三十一过孔与第十八晶体管的有源图案的第二区(也是第十九晶体管的有源图案的第二区)连接。
在示例性实施方式中，如图34和图35所示，第十九晶体管的第一极193可以单独设置。第十九晶体管的第一极193的形状为向左旋转的“n”字型，其开口背离显示区。第十九晶体管的第一极193通过第三十二过孔与第十九晶体管的有源图案的第一区连接。
在示例性实施方式中，如图34和图35所示，第三连接部L3单独设置。第三连接部L3的形状为条状，且沿第二方向D2延伸。第三连接部L3通过第三十三过孔与第一晶体管的栅电极(也是第十四晶体管的栅电极)连接。
在示例性实施方式中，如图34和图35所示，第四连接部L4单独设置。第四连接部L4的形状为条状，且沿第二方向D2延伸。第四连接部L4通过第三十九过孔与第七晶体管的栅电极连接。
在示例性实施方式中，如图34和图35所示，第五连接部L5单独设置。第五连接部L5的形状为条状，且沿第二方向D2延伸。第五连接部L5通过第三十五过孔与第三晶体管的栅电极连接。
在示例性实施方式中，如图34和图35所示，第六连接部L6单独设置。第六连接部L6的形状为条状，且沿第二方向D2延伸。第六连接部L6通过第三十九过孔与第七晶体管的栅电极连接。
在示例性实施方式中，如图34和图35所示，第七连接部L7单独设置。第七连接部L的形状为条状，且沿第一方向D1延伸。第七连接部L7通过第四十四过孔与第十三晶体管的栅电极连接。
在示例性实施方式中，如图34和图35所示，第八连接部L8单独设置。第八连接部L8的形状为条状，且沿第二方向D2延伸。第八连接部L8通过第四十五过孔与第十九晶体管的栅电极连接。
(6)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：
在形成有前述图案的基底上，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行构图，形成覆盖前述结构的第四绝缘层图案，第四绝缘层开设有多个过孔图案，如图36所示，图36为图26形成第四绝缘层图案后的示意图。
在示例性实施方式中，如图36所示，每个移位寄存器的第四绝缘层图案可以至少包括：第五十二过孔V52至第六十四过孔V64。
在示例性实施方式中，如图36所示，第五十二过孔V52在基底上的正投影位于第三连接部在基底上的正投影的范围之内，第五十二过孔V52暴露出第三连接部的表面，第五十二过孔V52被配置为使后续形成的第一时钟信号线和第二时钟信号线的其中一条信号线通过该过孔与第三连接部连接。图36是以第五十二过孔V52被配置为使后续形成的第一时钟信号线通过该过孔与第三连接部连接为例进行说明的。
在示例性实施方式中，如图36所示，第五十三过孔V53在基底上的正投影位于第位于连接部在基底上的正投影的范围之内，第五十三过孔V53暴露出第五连接部的表面，第五十三过孔V53被配置为使后续形成的第一时钟信号线和第二时钟信号线的其中一条信号线通过该过孔与第五连接部连接。图36是以第五十三过孔V53被配置为使后续形成的第一时钟信号线通过该过孔与第五连接部连接为例进行说明的。
在示例性实施方式中，如图36所示，第五十四过孔V54在基底上的正投影位于第四晶体管的第一极在基底上的正投影的范围之内，第五十四过孔V54暴露出第四晶体管的第一极的表面，第五十四过孔V54被配置为使后续形成的第一时钟信号线和第二时钟信号线的另一条信号线通过该过孔与第四晶体管的第一极连接。图36是以第五十四过孔V54被配置为使后续形成的第二时钟信号线通过该过孔与第四晶体管的第一极连接为例进行说明的。
在示例性实施方式中，如图36所示，第五十五过孔V55在基底上的正投影位于第四连接部在基底上的正投影的范围之内，第五十五过孔V55暴露出第四连接部的表面，第五十五过孔V55被配置为使后续形成的第一时钟信号线和第二时钟信号线的另一条信号线通过该过孔与第四连接部连接。图36是以第五十五过孔V55被配置为使后续形成的第二时钟信号线通过该过孔与第四连接部连接为例进行说明的。
在示例性实施方式中，如图36所示，第五十六过孔V56在基底上的正投影位于第三晶体管的第一极在基底上的正投影的范围之内，第五十六过孔V56暴露出第三晶体管的第一极的表面，第五十六过孔V56被配置为使后续形成的第一条第二电源线通过该过孔与第三晶体管的第一极连接。
在示例性实施方式中，如图36所示，第五十七过孔V57在基底上的正投影位于第四晶体管的第二极(也是第五晶体管的第二极)在基底上的正投影的范围之内，第五十七过孔V57暴露出第四晶体管的第二极(也是第五晶体管的第二极)的表面，第五十七过孔V57被配置为使后续形成的第九连接部通过该过孔与第四晶体管的第二极(也是第五晶体管的第二极)连接。
在示例性实施方式中，如图36所示，第五十八过孔V58在基底上的正投影位于第六连接部在基底上的正投影的范围之内，第五十八过孔V58暴露出第六连接部的表面，第五十八过孔V58被配置为使后续形成的第三电源线通过该过孔与第六连接部连接。
在示例性实施方式中，如图36所示，第五十九过孔V59在基底上的正投影位于第七连接部在基底上的正投影的范围之内，第五十九过孔V59暴露出第七连接部的表面，第五十九过孔V59被配置为使后续形成的第三电源线通过该过孔与第七连接部连接。
在示例性实施方式中，如图36所示，第六十过孔V60在基底上的正投影位于第十晶体管的第一极在基底上的正投影的范围之内，第六十过孔V60暴露出第十晶体管的第一极的表面，第六十过孔V60被配置为使后续形成的第二条第二电源线通过该过孔与第十晶体管的第一极连接。
在示例性实施方式中，如图36所示，第六十一过孔V61在基底上的正投影位于第十七晶体管的第一极在基底上的正投影的范围之内，第六十一过孔V61暴露出第十七晶体管的第一极的表面，第六十一过孔V61被配置为使后续形成的第二条第二电源线通过该过孔与第十七晶体管的第一极连接。
在示例性实施方式中，如图36所示，第六十二过孔V62在基底上的正投影位于第五晶体管的第一极(也是第八晶体管的第一极、第九晶体管的第一极和第十三晶体管的第一极)在基底上的正投影的范围之内，第六十二过孔V62暴露出第五晶体管的第一极(也是第八晶体管的第一极、第九晶体管的第一极和第十三晶体管的第一极)的表面，第六十二过孔V62被配置为使后续形成的第一电源线通过该过孔与第五晶体管的第一极(也是第八晶体管的第一极、第九晶体管的第一极和第十三晶体管的第一极)连接。
在示例性实施方式中，如图36所示，第六十三过孔V63在基底上的正投影位于第十九晶体管的第一极在基底上的正投影的范围之内，第六十三过孔V63暴露出第十九晶体管的第一极的表面，第六十三过孔V63被配置为使后续形成的第一电源线通过该过孔与第十九晶体管的第一极连接。
在示例性实施方式中，如图36所示，第六十四过孔V64在基底上的正投影位于第八连接部在基底上的正投影的范围之内，第六十四过孔V64暴露出第八连接部的表面，第六十四过孔V64被配置为使后续形成的扫描控制信号线通过该过孔与第八连接部连接。
(7)形成第四导电层图案。在示例性实施方式中，形成第四导电层图案可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第四绝缘层上的第四导电层，如图37和图38所示，图37为图26中的第四导电层图案的示意图，图38为图26形成第四导电层图案后的示意图。示例性实施方式中，第四导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，如图37和图38所示，位于每个移位寄存器的第四导电层图案可以至少包括：第一时钟信号线CLK1、第二时钟信号线CLK2、第一电源线VGH、两条第二电源线VGL、第三电源线VCX、扫描控制信号线MSL和第九连接部L9。
在示例性实施方式中，如图37和图38所示，第一时钟信号线CLK1、第二时钟信号线CLK2、第一条第二电源线VGL、第三电源线VCX、第二条第二电源线VGL、第一电源线VGH和扫描控制信号线MSL沿靠近显示区的方向依次排布。第九连接部L9位于第一条第二电源线VGL和第三电源线VCX之间。
在示例性实施方式中，如图37和图38所示，第一时钟信号线CLK1的形状可以为主体部分沿着第二方向D2延伸的线形状。第一时钟信号线CLK1通过第五十二过孔与第三连接部连接，且通过第五十三过孔与与第五连接部连接。
在示例性实施方式中，如图37和图38所示，第二时钟信号线CLK2的形状可以为主体部分沿着第二方向D2延伸的线形状。第二时钟信号线CLK2通过第五十四过孔与第四晶体管的第一极连接，且通过第五十五过孔与第四连接部连接。
在示例性实施方式中，如图37和图38所示，第一条第二电源线VGL的形状可以为主体部分沿着第二方向D2延伸的线形状。第一条第二电源线VGL通过第五十六过孔与第四晶体管的第一极连接，且通过第五十五过孔与第三晶体管的第一极连接。
在示例性实施方式中，如图37和图38所示，第三电源线VCX的形状可以为主体部分沿着第二方向D2延伸的线形状。第三电源线VCX通过第五十八过孔与第六连接部连接，且通过第五十九过孔与第七连接部连接。
在示例性实施方式中，如图37和图38所示，第二条第二电源线VGL的形状可以为主体部分沿着第二方向D2延伸的线形状。第二条第二电源线VGL通过第六十过孔与第十晶体管的第一极连接，且通过第六十一过孔与第十七晶体管的第一极连接。
在示例性实施方式中，如图37和图38所示，第一电源线VGH的形状可以为主体部分沿着第二方向D2延伸的线形状。第一电源线VGH通过第六十二过孔与第五晶体管的第一极(也是第八晶体管的第一极、第九晶体管的第一极和第十三晶体管的第一极)连接，且通过第六十三过孔与第十九晶体管的第一极连接。
在示例性实施方式中，如图37和图38所示，扫描控制信号线MSL的形状可以为主体部分沿着第二方向D2延伸的线形状。扫描控制信号线MSL通过第六十四过孔与第八连接部连接。
在示例性实施方式中，扫描控制信号线MSL的线宽小于第一电源线VGH和第二电源线VGL中任一信号线的线宽。
在示例性实施方式中，第三电源线VCX的线宽小于第一电源线VGH和第二电源线VGL中任一信号线的线宽。
在示例性实施方式中，第一时钟信号线CLK1和第二时钟信号线CLK2的线宽小于第一电源线VGH和第二电源线VGL中任一信号线的线宽。
(8)形成平坦层。在示例性实施方式中，形成平坦层图案可以包括：在形成有前述图案的基底上，沉积第五绝缘薄膜，涂覆平坦薄膜，通过图案化工艺对第五绝缘薄膜和平坦薄膜进行构图，形成覆盖前述结构的第五绝缘层图案和覆盖第五绝缘层图案的平坦层图案。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个移位寄存器，移位寄存器与第一时钟信号线、第二时钟信号线、第一电源线、第二电源线、第三电源线和扫描控制信号线电连接。在垂直于显示基板的平面内，驱动电路层可以设置在基底上，基底可以包括叠设的第一柔性层、阻挡层、基底导电层和第二柔性层。驱动电路层可以包括在基底上依次设置的半导体层、第一绝缘层、第一导电层、第二绝缘层、第三导电层、第四绝缘层、第四导电层、第五绝缘层和平坦层。半导体层可以至少包括第一晶体管至第十九晶体管的有源图案，第一导电层可以至少包括第一晶体管至第十九晶体管的栅电极以及第一电容的第一极板至第四电容的第一极板，第二导电层可以至少包括第一电容的第二极板至第四电容的第二极板，第三导电层可以至少包括第一晶体管至第十九晶体管中任一晶体管的第一极和第二极，第四导电层可以至少包括：第一时钟信号线、第二时钟信号线、第一电源线、第二电源线、第三电源线和扫描控制信号线。
在示例性实施方式中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属萡片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成基底的制备。
在示例性实施方式中，半导体层可以为非晶硅层或者多晶硅层，或者可以为金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层和第二绝缘层可以称为栅绝缘(GI)层，第三绝缘层可以称为层间绝缘(ILD)层，第四绝缘层可以称为钝化(PVX)层。
在示例性实施方式中，平坦层和平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，制备完成驱动电路层后，在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层图案，在形成前述图案的基底上，沉积像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成暴露出阳极导电层图案的像素定义层图案，在形成有像素定义层图案的基底上，涂覆有机发光材料，通过图案化工艺对有机发光材料进行图案化，形成有机结构层图案，在形成有机材料层图案的基底上，沉积阴极导电薄膜，通过图案化工艺对阴极导电薄膜进行图案化，形成阴极导电层。
至此，在基底上制备完成发光结构层。
在示例性实施方式中，阳极导电层至少包括多个阳极图案。其中，多个阳极图案可以包括第一发光器件的阳极、第二发光器件的阳极、第三发光器件的阳极和第四发光器件的阳极，第一发光器件的阳极位于出射红色光线的红色子像素，第二发光器件的阳极可以位于出射蓝色光线的蓝色子像素，第三发光器件的阳极可以位于出射绿色光线的第一绿色子像素，第四发光器件的阳极可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一发光器件的阳极和第二发光器件的阳极可以沿着第一方向D1交替设置，第三发光器件的阳极和第四发光器件的阳极可以沿着第一方向D1交替设置。或者，第一发光器件的阳极和第二发光器件的阳极可以沿着第二方向D2交替设置，第三发光器件的阳极和第四发光器件的阳极可以沿着第二方向D2交替设置。
在示例性实施方式中，一个像素单元中四个子像素的阳极形状和面积可以相同，或者可以不同。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，有机结构层至少可以包括：发光器件的有机发光层。
在示例性实施方式中，阴极导电层至少可以包括：多个发光器件的阴极。
在示例性实施方式中，阴极层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述导电的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。示例性地，第四导电层可以为钛、铝和钛形成的三层堆叠结构。
本公开实施例通过的显示基板可以适用于任何分辨率的显示产品中。
在示例性实施方式中，后续制备流程可以包括：在阴极导电层上形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
本公开实施例还提供了一种显示装置，该显示装置可以包括：显示基板。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在示例性实施方式中，显示装置可以为可穿戴设备、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (24)

  1. 一种移位寄存器，包括：级联输出子电路和扫描输出子电路；
    所述级联输出子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一电源端、第二电源端、级联输出端、第一节点和第二节点电连接，被配置为在信号输入端、第一时钟信号端和第二时钟信号端的信号的控制下，向第一节点和第二节点提供信号，在第一节点和第二节点的信号的控制下，向级联输出端提供第一电源端或第二电源端的信号；
    所述扫描输出子电路，分别与扫描控制信号端、第一电源端、第二电源端、扫描输出端、第一节点和第二节点电连接，被配置为在第一节点、第二节点和扫描控制信号端的信号的控制下，向扫描输出端提供第一电源端或者第二电源端的信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述扫描输出子电路包括：第一输出控制子电路和第二输出控制子电路；
    所述第一输出控制子电路，分别与第二电源端、扫描输出端和第二节点电连接，被配置为在第二节点的信号的控制下，向扫描输出端提供第二电源端的信号；
    所述第二输出控制子电路，分别与扫描控制信号端、第一电源端、扫描输出端和第一节点电连接，被配置为在扫描控制信号端和第一节点的信号的控制下，向扫描输出端提供第一电源端的信号。
  3. 根据权利要求2所述的移位寄存器，其中，所述扫描输出子电路还包括：存储子电路；
    存储子电路，分别与扫描输出端和第一电源端电连接，被配置为存储扫描输出端和第一电源端的信号之间的电压差。
  4. 根据权利要求2所述的移位寄存器，其中，所述第一输出控制子电路包括：第十七晶体管；
    第十七晶体管的控制极与第二节点电连接，第十七晶体管的第一极与第二电源端电连接，第十七晶体管的第二极与扫描输出端电连接。
  5. 根据权利要求2所述的移位寄存器，其中，所述第二输出控制子电路包括：第十八晶体管和第十九晶体管；
    第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与第一电源端电连接，第十八晶体管的第二极与第三节点电连接；
    第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与扫描输出端电连接，第十九晶体管的第二极与第三节点电连接。
  6. 根据权利要求2所述的移位寄存器，其中，所述第二输出控制子电路包括：第十八晶体管和第十九晶体管；
    第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与扫描输出端电连接，第十八晶体管的第二极与第三节点电连接；
    第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与第一电源端电连接，第十九晶体管的第二极与第三节点电连接。
  7. 根据权利要求3所述的移位寄存器，其中，所述存储子电路包括：第五电容；
    第五电容的第一极板与扫描输出端电连接，第五电容的第二极板与第一电源端电连接。
  8. 根据权利要求1所述的移位寄存器，其中，所述级联输出子电路包括：第一晶体管至第十六晶体管以及第一电容至第四电容，第一电容至第四电容中的任一电容包括：第一极板和第二极板；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第四节点电连接；
    第二晶体管的控制极与第四节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第五节点电连接；
    第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第五节点电连接；
    第四晶体管的控制极与第六节点电连接，第四晶体管的第一极与第二时钟信号端电连接，第四晶体管的第二极与第七节点电连接；
    第五晶体管的控制极与第五节点电连接，第五晶体管的第一极与第一电源端电连接，第五晶体管的第二极与第七节点电连接；
    第六晶体管的控制极与第九节点电连接，第六晶体管的第一极与第二时钟信号端电连接，第六晶体管的第二极与第八节点电连接；
    第七晶体管的控制极与第二时钟信号端电连接，第七晶体管的第一极与第八节点电连接，第七晶体管的第二极与第一节点电连接；
    第八晶体管的控制极与第四节点电连接，第八晶体管的第一极与第一电源端电连接，第八晶体管的第二极与第一节点电连接；
    第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第一电源端电连接，第九晶体管的第二极与级联输出端电连接；
    第十晶体管的控制极与第二节点电连接，第十晶体管的第一极与第二电源端电连接，第十晶体管的第二极与级联输出端电连接；
    第十一晶体管的控制极与第二电源端电连接，第十一晶体管的第一极与第五节点电连接，第十一晶体管的第二极与第九节点电连接；
    第十二晶体管的控制极与第二电源端电连接，第十二晶体管的第一极与第四节点电连接，第十二晶体管的第二极与第二节点电连接；
    第十三晶体管的控制极与第三电源端电连接，第十三晶体管的第一极与第一电源端电连接，第十三晶体管的第二极与第四节点电连接；
    第十四晶体管的控制极与第一时钟信号端电连接，第十四晶体管的第一极与信号输入端电连接，第十四晶体管的第二极与第十节点电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第十节点电连接，第十五晶体管的第二极与第六节点电连接；
    第十六晶体管的控制极与第六节点电连接，第十六晶体管的第一极与第六节点电连接，第十六晶体管的第二极与第二节点电连接；
    第一电容的第一极板与第九节点电连接，第一电容的第二极板与第八节点电连接；
    第二电容的第一极板与第一节点电连接，第二电容的第二极板与第一电源端电连接；
    第三电容的第一极板与第六节点电连接，第三电容的第二极板与第七节点电连接；
    第四电容的第一极板与第二电源端电连接，第四电容的第二极板与级联输出端电连接。
  9. 根据权利要求1或8所述的移位寄存器，其中，所述扫描输出子电路包括：第十七晶体管至第十九晶体管，或者，包括：十七晶体管至第十九晶体管和第五电容；
    第十七晶体管的控制极与第二节点电连接，第十七晶体管的第一极与第二电源端电连接，第十七晶体管的第二极与扫描输出端电连接；
    第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与第一电源端电连接，第十八晶体管的第二极与第三节点电连接；
    第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与扫描输出端电连接，第十九晶体管的第二极与第三节点电连接；
    第五电容的第一极板与扫描输出端电连接，第五电容的第二极板与第一电源端电连接。
  10. 根据权利要求1或8所述的移位寄存器，其中，所述扫描输出子电路包括：第十七晶体管至第十九晶体管，或者包括：十七晶体管至第十九晶体管和第五电容；
    第十七晶体管的控制极与第二节点电连接，第十七晶体管的第一极与第二电源端电连接，第十七晶体管的第二极与扫描输出端电连接；
    第十八晶体管的控制极与第一节点电连接，第十八晶体管的第一极与扫描输出端电连接，第十八晶体管的第二极与第三节点电连接；
    第十九晶体管的控制极与扫描控制信号端电连接，第十九晶体管的第一极与第一电源端电连接，第十九晶体管的第二极与第三节点电连接；
    第五电容的第一极板与扫描输出端电连接，第五电容的第二极板与第一电源端电连接。
  11. 一种显示基板，具有显示区和非显示区，其中，包括：位于所述非显示区的栅极驱动电路和位于所述显示区的阵列排布的子像素和多条栅线，所述子像素包括像素驱动电路和发光器件，所述栅线至少部分沿第一方向延伸，所述栅极驱动电路包括：多个级联的如权利要求1至10任一项所述的移位寄存器，所述像素驱动电路包括：多个晶体管；
    至少一级移位寄存器的级联输出端与至少一级移位寄存器的信号输入端电连接；
    所述栅线与所述至少一个晶体管的栅电极电连接，任一移位寄存器与至少一条栅线电连接。
  12. 根据权利要求11所述的显示基板，其中，所述显示区被划分为多个显示子区，至少一个显示子区包括：至少一条栅线；任一个显示子区的显示模式包括：第一显示模式和第二显示模式，第一显示模式的刷新频率大于第二显示模式的刷新频率；
    在显示子区的显示模式为第一显示模式的状态下，对于与显示子区内的栅线所连接的移位寄存器，级联输出端的信号为第一电平信号时，扫描控制信号端的信号的至少部分时间段为有效电平信号，扫描输出端的信号为第一电平信号；
    在显示子区的显示模式为第二显示模式的状态下，对于与显示子区内的栅线所连接的移位寄存器，级联输出端的信号为第一电平信号时，扫描控制信号端的信号为无效电平信号，扫描输出端的信号为第二电平信号；
    其中，所述第一电平信号的电压值大于所述第二电平信号的电压值。
  13. 根据权利要求11或12所述的显示基板，还包括：位于所述非显示区的至少一条扫描控制信号线，所述扫描控制信号线至少部分沿第二方向延伸，所述第一方向和所述第二方向相交；
    所有移位寄存器所连接的扫描控制信号端与所述至少一条扫描控制信号线电连接。
  14. 根据权利要求13所述的显示基板，其中，所述扫描控制信号线的数量为一条，
    所有移位寄存器所连接的扫描控制信号端与同一扫描控制信号线电连接。
  15. 根据权利要求13所述的显示基板，其中，所述扫描控制信号线的数量为至少两条；
    第M*(k-1)+K*M(a-1)+1级移位寄存器至k*M+K*M(a-1)级移位寄存器中的任一移位寄存器所连接的扫描控制信号端与第k条扫描控制信号线电连接，1≤k≤K，1≤a≤N/M，M为一条扫描控制信号线所连接的移位寄存器的级数，N为移位寄存器的总级数，K为扫描控制信号线的数量。
  16. 根据权利要求15所述的显示基板，其中，所述显示基板所显示画面包括：多个显示帧，在任一显示帧，所述移位寄存器的扫描输出端的输出信号为脉冲信号，且脉冲信号的持续时间H满足如下关系式；
    H＝L*[M*K-(M-1)]*h
    其中，L为任一级移位寄存器所连接的栅线的数量，h为单位时间，且等于相邻行子像素的刷新间隔时间。
  17. 根据权利要求13所述的显示基板，还包括：位于所述非显示区的第一时钟信号线、第二时钟信号线、第一电源线、第二电源线和第三电源线；所述第一时钟信号线、所述第二时钟信号线、所述第一电源线、所述第二电源线和所述第三电源线中的任一条至少部分沿所述第二方向延伸；
    任一级移位寄存器所连接的第一时钟信号端与第一时钟信号线和第二时钟信号线的其中一条电连接，任一级移位寄存器所连接的第二时钟信号端与第一时钟信号线和第二时钟信号线的另一条电连接，相邻移位寄存器所连接的第一时钟信号端所连接的时钟信号线不同，相邻移位寄存器所连接的第二时钟信号端所连接的时钟信号线不同，所有移位寄存器所连接的第一电源端与所述第一电源线电连接，所有移位寄存器所连接的第二电源端与所述第二电源线电连接，所有移位寄存器所连接的第三电源端与所述第三电源线电连接。
  18. 根据权利要求17所述的显示基板，其中，所述扫描控制信号线位于所述第一时钟信号线、所述第二时钟信号线、所述第一电源线、所述第二电源线和所述第三电源线中的任一条靠近所述显示区的一侧。
  19. 根据权利要求17或18所述的显示基板，其中，所述第二电源线的数量为两条，所述第一时钟信号线、所述第二时钟信号线、第一条第二电源线、所述第三电源线、第二条第二电源线和所述第一电源线沿靠近所述显示区的方向依次排布。
  20. 根据权利要求19所述的显示基板，其中，所述移位寄存器包括：第十七晶体管至第十九晶体管；第十七晶体管至第十九晶体管沿所述第二方向排布；
    所述第十七晶体管至第十九晶体管中的任一个晶体管的至少部分位于所述第一电源线和所述扫描控制信号线之间。
  21. 根据权利要求20所述的显示基板，其中，任一晶体管包括：有源图案，所述第十七晶体管的有源图案沿第一方向的平均长度小于所述第十八晶体管和所述第十九晶体管的任一晶体管的有源图案沿第一方向的平均长度。
  22. 根据权利要求17所述的显示基板，其中，所述第一电源线和所述第二电源线中的任一电源线的线宽大于所述扫描控制信号线的线宽。
  23. 一种显示装置，包括：如权利要求11至22任一项所述的显示基板。
  24. 一种移位寄存器的驱动方法，被配置为驱动如权利要求1至10任一项所述的移位寄存器，所述方法包括：
    级联输出子电路在信号输入端、第一时钟信号端和第二时钟信号端的信号的控制下，向第一节点和第二节点提供信号，在第一节点和第二节点的信号的控制下，向级联输出端提供第一电源端或第二电源端的信号；
    扫描输出子电路在第一节点、第二节点和扫描控制信号端的信号的控制下，向扫描输出端提供第一电源端或者第二电源端的信号。
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