WO2025035260A1 - 一种显示基板和显示装置 - Google Patents

一种显示基板和显示装置 Download PDF

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Publication number
WO2025035260A1
WO2025035260A1 PCT/CN2023/112539 CN2023112539W WO2025035260A1 WO 2025035260 A1 WO2025035260 A1 WO 2025035260A1 CN 2023112539 W CN2023112539 W CN 2023112539W WO 2025035260 A1 WO2025035260 A1 WO 2025035260A1
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WIPO (PCT)
Prior art keywords
transistor
contact portion
electrode
layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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PCT/CN2023/112539
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English (en)
French (fr)
Inventor
邹志翔
林亮
王章涛
张然
黄中浩
徐中
陈川
袁帅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380010100.XA priority Critical patent/CN119923968A/zh
Priority to PCT/CN2023/112539 priority patent/WO2025035260A1/zh
Publication of WO2025035260A1 publication Critical patent/WO2025035260A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display device.
  • Transistors as switch control elements or integrated components of peripheral drive circuits, are core devices in display technology.
  • mobility refers to the speed at which electrons move in semiconductor materials.
  • mobility means the display quality and service life that can be achieved with the same device size.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.
  • a technical solution adopted to solve the technical problem of the present disclosure is a display substrate, which includes a base substrate, and gate lines and data lines located on the base substrate, the gate lines and the data lines intersecting to define a plurality of pixel units; the gate lines extend along a first direction, the data lines extend along a second direction, and the first direction and the second direction intersect; the pixel unit includes a first transistor and a second transistor; the active layer of the first transistor includes a first contact portion and a second contact portion, the active layer of the second transistor includes a third contact portion and a fourth contact portion, the first contact portion is electrically connected to the data line, the second contact portion is electrically connected to the third contact portion, and the fourth contact portion is electrically connected to the first electrode of the pixel unit; along the second direction, the maximum spacing between the first contact portion and the gate line is not less than the maximum spacing between the fourth contact portion and the same gate line.
  • a width of the first contact portion is smaller than a width of the fourth contact portion.
  • the orthographic projection of the first contact portion on the substrate overlaps with the orthographic projection of the data line on the substrate, and the first contact portion includes a first portion connected to each other. and a second portion, the first portion is electrically connected to the data line, and along the first direction, a width of the first portion is greater than a width of the second portion.
  • the fourth contact portion overlaps with the orthographic projection of the gate line on the substrate, the fourth contact portion includes a third portion and a fourth portion connected to each other, the fourth portion is electrically connected to the first electrode, and along the second direction, the minimum width of the fourth portion is greater than the minimum width of the third portion.
  • the first contact portion is electrically connected to the data line through a first via hole
  • the fourth contact portion is electrically connected to the first electrode through a second via hole; along the second direction, the minimum spacing between the first via hole and the gate line is greater than the minimum spacing between the second via hole and the same gate line.
  • the first contact portion is electrically connected to the data line through a first via
  • the fourth contact portion is electrically connected to the first electrode through a second via and a third via; along the second direction, the minimum spacing between the first via and the gate line is greater than the minimum spacing between the second via and the same gate line; the minimum spacing between the third via and the gate line is less than the minimum spacing between the second via and the same gate line.
  • the pixel unit further includes an auxiliary component;
  • the auxiliary component includes a fifth portion and a sixth portion connected to each other, the fifth portion is electrically connected to the fourth contact portion through the second via hole; the sixth portion is electrically connected to the first electrode through the third via hole.
  • the auxiliary component is disposed in the same layer as the data line, and in the first direction, the auxiliary component is disposed between two adjacent data lines at positions where they are connected to the first contact portion.
  • the first contact portion, the second contact portion, the third contact portion, and the fourth contact portion are disposed in the same layer.
  • the active layer of the first transistor and/or the active layer of the second transistor includes a metal oxide semiconductor material.
  • the active layers of the first transistor and the second transistor include multiple sub-layers stacked in layers, and the mobility of the sub-layers away from the substrate is smaller than that of the sub-layers close to the substrate. The mobility of the layer.
  • the gate of the first transistor is located on a side of the active layer of the first transistor away from the substrate; the gate of the second transistor is located on a side of the active layer of the second transistor away from the substrate; the active layer of the first transistor and the active layer of the second transistor are arranged on the same layer;
  • the data line is multiplexed as the first electrode of the first transistor; the second contact portion is multiplexed as the second electrode of the first transistor, the third contact portion is multiplexed as the first electrode of the second transistor, and the second contact portion and the third contact portion are connected as an integrated structure.
  • the first electrode is a pixel electrode; the orthographic projections of the second contact portion and the third contact portion connected as one on the base substrate partially overlap with the orthographic projection of at least one pixel electrode on the base substrate.
  • the orthographic projection of the second contact portion and the third contact portion connected as one in one of the pixel units on the substrate partially overlaps with the orthographic projection of the other pixel unit on the substrate.
  • the active layer of the first transistor also includes a first channel portion arranged between the first contact portion and the second contact portion
  • the active layer of the second transistor also includes a second channel portion arranged between the third contact portion and the fourth contact portion; the first channel portion, the second contact portion and the third contact portion connected as a whole, and the second channel portion
  • the contour shape of the positive projection on the substrate is U-shaped.
  • the gate of the first transistor and the gate of the second transistor are arranged in the same layer; the active layer of the first transistor and the active layer of the second transistor are arranged in the same layer; the first electrode and the second electrode of the first transistor are arranged in the same layer as the first electrode and the second electrode of the second transistor;
  • the gate of the first transistor is located on a side of the active layer away from the substrate; the first electrode and the second electrode of the first transistor are located on a side of the gate away from the active layer;
  • the data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integral structure, and the second electrode of the first transistor is connected to the The first electrode of the second transistor is electrically connected to the second contact portion through a fourth via hole, and the first electrode of the second transistor is electrically connected to the third contact portion through a fifth via hole.
  • the display substrate further comprises a light shielding layer disposed near the base substrate at the pixel unit;
  • the active layer of the first transistor further includes a first channel portion disposed between the first contact portion and the second contact portion, and the active layer of the second transistor further includes a second channel portion disposed between the third contact portion and the fourth contact portion;
  • the orthographic projection of the light shielding layer on the base substrate at least covers the orthographic projections of the first channel portion and the second channel portion on the base substrate.
  • a first distance exists between a contour edge of an orthographic projection of the light shielding layer on the substrate and a contour edge of an orthographic projection of the first channel portion on the substrate;
  • the first spacing and/or the second spacing ranges from 4 ⁇ m to 6 ⁇ m.
  • the third spacing and/or the fourth spacing ranges from 0 to 4 ⁇ m.
  • the pixel units in the same row are electrically connected to the same gate line; the gate line serves as a gate of the first transistor and a gate of the second transistor.
  • a gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; and a thickness of the gate insulating layer is between 10 nm and 30 nm.
  • the gate of the first transistor and the gate of the second transistor are in the same layer. Setting; the active layer of the first transistor and the active layer of the second transistor are set in the same layer; the first electrode and the second electrode of the first transistor are set in the same layer as the first electrode and the second electrode of the second transistor;
  • the gate of the first transistor is located on a side of the active layer close to the substrate; the first electrode and the second electrode of the first transistor are located on a side of the active layer away from the gate;
  • the data line is multiplexed as the first electrode of the first transistor; the second electrode of the first transistor and the first electrode of the second transistor are connected as an integrated structure, and the second electrode of the first transistor is electrically connected to the second contact portion of the first transistor; the first electrode of the second transistor is electrically connected to the third contact portion of the second transistor.
  • the pixel units in the same row are electrically connected to the same gate line; the gate line is used as the gate of the first transistor and the gate of the second transistor;
  • the gate line is a composite film layer, comprising a buffer layer and a main conductive layer which are sequentially arranged on the base substrate.
  • a gate insulating layer is disposed on a side of the gate of the first transistor close to the active layer; and a thickness of the gate insulating layer is between 30 nm and 50 nm.
  • an embodiment of the present disclosure further provides a display device, comprising a display substrate as described in any one of the first aspects.
  • FIG. 1a is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure
  • FIG1b is a schematic diagram showing the positional relationship between the contact portion of the active layer and the gate line according to an embodiment of the present disclosure
  • FIG2 is a schematic diagram showing the specific distribution of the first contact portion and the second contact portion provided in an embodiment of the present disclosure
  • FIG3a is a plan view showing electrical connections between a transistor and a data line provided by an embodiment of the present disclosure
  • FIG3 b is a plan view showing electrical connections between a transistor, a data line and a first electrode provided in an embodiment of the present disclosure
  • FIG4 is a schematic diagram of an active layer using a composite film layer provided in an embodiment of the present disclosure.
  • FIG5 a is a top plan view of a transistor with a top-gate structure provided by an embodiment of the present disclosure
  • FIG5b is a cross-sectional view of the structure shown in FIG5a along the AA direction;
  • FIG6a is a schematic diagram of the plane where the active layer shown in FIG5b is located;
  • FIG6b is a schematic diagram of the plane where the first conductive layer shown in FIG5b is located;
  • FIG6c is a schematic diagram of a plane where the first via hole and the second via hole shown in FIG5b are located;
  • FIG6d is a schematic diagram of the plane where the second conductive layer shown in FIG5b is located;
  • FIG7 is a top plan view of a plurality of pixel units in a pixel unit provided by an embodiment of the present disclosure
  • FIG8a is a schematic diagram of the plane where the first sub-hole is located
  • FIG8b is a schematic diagram of the plane where the second electrode is located
  • FIG8c is a schematic diagram of the plane where the second sub-hole is located.
  • FIG8d is a schematic diagram of the plane where the first electrode is located
  • FIG9a is a schematic diagram of the structure of another top-gate transistor provided in an embodiment of the present disclosure.
  • FIG9b is a cross-sectional view of the structure shown in FIG9a along the BB direction;
  • FIG10 is a top view of the plane where the light shielding layer is located
  • FIG11 is a top view of an exemplary light shielding layer provided in an embodiment of the present disclosure.
  • FIG12a is a transistor device performance test result of the dual NMOS in normal working state (-1.5V) shown in FIG9b;
  • FIG12 b is a transistor device performance test result of the dual NMOS in a negative bias state (-8V) shown in FIG9 b ;
  • FIG13a is a schematic diagram of a bottom-gate transistor provided in an embodiment of the present disclosure.
  • FIG13b is a cross-sectional view of the structure shown in FIG13a along the CC direction;
  • FIG14a is a schematic diagram of the structure of another bottom-gate transistor provided in an embodiment of the present disclosure.
  • FIG14b is a cross-sectional view of the structure shown in FIG14a along the DD direction;
  • 15a to 15j are schematic diagrams of a preparation process of the display substrate shown in FIG. 5b provided in an embodiment of the present disclosure
  • 16a to 16j are schematic diagrams of a preparation process of the display substrate shown in FIG. 9b provided in an embodiment of the present disclosure
  • 17a to 17i are schematic diagrams of a preparation process of the display substrate shown in FIG. 13b provided in an embodiment of the present disclosure
  • 18a to 18i are schematic diagrams of the preparation process of the display substrate shown in FIG. 10 provided in an embodiment of the present disclosure.
  • the reference numerals are as follows: 1, substrate; 2, pixel unit; 21, pixel circuit; 22, first electrode; 23, second electrode; T1, first transistor; T2, second transistor; T11, first electrode of first transistor; T12, second electrode of first transistor; T13, active layer of first transistor; 13a, first contact portion; 13b, second contact portion; 13c, first channel portion; T14, gate of first transistor; T21, first electrode of second transistor; T22, second electrode of second transistor; T23, active layer of second transistor; 23a, third contact portion; 23b, fourth contact portion; 23c, second channel portion Channel portion; T24, the gate of the second transistor; Gate, gate line; Data, data line; ACT, semiconductor layer; ACT_1, sublayer; 31, first insulating layer; 32, second insulating layer; 33, third insulating layer; 34, fourth insulating layer; 35, fifth insulating layer; 41, first conductive layer; 42, second conductive layer; 43, third conductive layer; 50, light shielding layer; X, first direction; Y
  • amorphous silicon a-Si
  • metal oxide IGZO
  • LTPS low temperature polysilicon
  • Traditional technology maintains a high mobility level by developing different series of metal oxide materials, such as element ratio adjustment solutions including increasing the indium (In) content, removing zinc (Zn) components or adding tin (Sn) components, etc., so as to achieve a high mobility of about 20cm 2 / (V.s) to 50cm 2 / (V.s).
  • the optical band gap (Eg) of high mobility materials is small, which makes it easier to generate carriers, so that the electrons in the high mobility materials can absorb part of the visible light band to produce electronic transitions, which in turn leads to the device capability being manifested as the thin film transistor (TFT) being turned on prematurely, and the increase of new defects under light, and the serious degradation of the negative bias temperature illumination stability (NBTIS), resulting in a serious decline in service life.
  • TFT thin film transistor
  • NTIS negative bias temperature illumination stability
  • the development of high mobility materials is limited by the difficulty that mobility and Eg cannot achieve a win-win situation. At present, it has been slow to break through the mass production of high mobility materials of Mob 30 and above.
  • the relevant technology starts from the design direction of TFT devices and the design direction of dual-gate structures.
  • dual-gate TFTs and ultra-thin gate insulating layers (GI) thickness Through dual-gate TFTs and ultra-thin gate insulating layers (GI) thickness, device performance with ultra-high mobility indicators of approximately 20cm2 /(V.s) and above can be achieved.
  • this device design achieves high mobility, it also reduces the current value at low voltage, that is, the off-state current (Ioff), which will lead to a significant reduction in the device threshold voltage (Vth).
  • the reduction in GI thickness will also cause the device's breakdown voltage to decrease, thereby increasing the risk of device failure. Therefore, based on the above information, there are problems such as low threshold voltage and negative shift under light in the preparation of ultra-high mobility devices. Based on these problems, traditional technical solutions are often unable to break through ultra-high mobilities of 50cm2 /(V.s) and above, and there is no mass production performance on the market.
  • an embodiment of the present disclosure provides a display substrate, which improves the leakage problem caused by the negative bias of the threshold voltage (Vth) of the existing device by connecting two transistors electrically connected to the first electrode of the pixel unit in series, thereby improving the switching capability of the display substrate and the service life of the product.
  • Vth threshold voltage
  • FIG1a is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present disclosure
  • FIG1b is a schematic diagram of the positional relationship between a contact portion of an active layer and a gate line provided in an embodiment of the present disclosure.
  • a display substrate includes a base substrate 1 (not shown in FIG1a and FIG1b , see FIG4 for details), and a gate line Gate and a data line Data located on the base substrate 1, wherein the gate line Gate and the data line Data intersect to define a plurality of pixel units 2; the gate line Gate extends along a first direction X, and the data line Data extends along a second direction Y, and the first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are arranged perpendicularly.
  • the pixel unit 2 includes a pixel circuit 21 and a first electrode 22; the pixel circuit 21 includes at least a first transistor T1 and a second transistor T2; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, the first contact portion 13a is electrically connected to the data line Data, the second contact portion 13b is electrically connected to the third contact portion 23a, and the fourth contact portion 23b is electrically connected to the first electrode 22 of the pixel unit 2; along the second direction Y, the maximum spacing d1 between the first contact portion 13a and the gate line Gate is not less than the maximum spacing d2 between the fourth contact portion 23b and the same gate line.
  • the second electrode T12 of the first transistor T1 is electrically connected to the first electrode T21 of the second transistor T2, and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22.
  • the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both made of metal oxide semiconductor materials.
  • the metal oxide semiconductor material may be indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium It is made of one or more materials selected from zinc tin oxide (IGZTO), rare earth doped oxide (Ln-OS).
  • the material can be amorphous, partially crystalline, single crystal or polycrystalline, and the prepared active layer can be a single layer or multilayer structure. According to the actual characteristics of metal oxide semiconductor materials, this material can improve the mobility of transistors.
  • the transistor used in the embodiment of the present disclosure may be a field effect transistor (MOS transistor). Since the source and drain of the MOS transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode and the other electrode is called the second electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor.
  • the materials of the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 in the embodiment of the present disclosure are both metal oxide semiconductor materials. It should be noted that transistors made of metal oxide semiconductor materials can only prepare N-type transistors.
  • the transistor of the embodiment of the present disclosure is an N-type transistor.
  • the first electrode of the transistor is the drain of the N-type transistor
  • the second electrode of the transistor is the source of the N-type transistor.
  • the second transistor T2 electrically connected to the first electrode 22 the first transistor T1 is added and connected in series with the second transistor T2, the current value of one transistor will be suppressed by the other transistor, and in the extreme case, when one of the transistors has a negative bias in the conductive property, the other transistor is still in a normal working state, thereby significantly reducing the off-state current and reducing the risk of negative offset of the threshold voltage.
  • the active layers of the dual transistors electrically connected to the first electrode 22 are made of metal oxide semiconductor materials, thereby improving the mobility of the transistors; at the same time, the two transistors are connected in series, and the current value of one transistor will be suppressed by the other transistor.
  • the other transistor when one of the transistors has a negative bias in its conductive properties, the other transistor is still in a normal working state, which can significantly improve the threshold voltage of the entire device, thereby effectively improving the leakage problem of the entire device and the sand bright spot (Mura) problem of the display product caused by leakage.
  • Mura sand bright spot
  • the minimum width of the first contact portion 13 a is smaller than the minimum width of the fourth contact portion 23 b .
  • width may be understood as the maximum spacing or average spacing between boundaries of a specified film layer along a specified direction, and may be a lateral dimension or a longitudinal dimension.
  • Figure 2 is a schematic diagram of the specific distribution of the first contact portion and the second contact portion provided in the embodiment of the present disclosure.
  • the orthographic projection of the first contact portion 13a on the substrate substrate 1 overlaps with the orthographic projection of the data line Data on the substrate substrate 1, and the first contact portion 13a includes a first portion 13a1 and a second portion 13a2 connected to each other.
  • the first portion 13a1 is electrically connected to the data line Data, and along the first direction X, the width w1 of the first portion 13a1 is greater than the width w2 of the second portion 13a2.
  • the orthographic projection of the fourth contact portion 23b on the substrate 1 overlaps with the orthographic projection of the gate line Gate on the substrate 1, and the fourth contact portion 23b includes a third portion 23b1 and a fourth portion 23b2 connected to each other, the fourth portion 23b2 is electrically connected to the first electrode 22, and along the second direction Y, the minimum width w4 of the fourth portion 23b2 is greater than the minimum width w3 of the third portion 23b1.
  • FIG. 3a is a plan view of the electrical connection between the transistor and the data line provided in the embodiment of the present disclosure.
  • the first contact portion 13a is electrically connected to the data line Data through the first via hole Via1
  • the fourth contact portion 23b is electrically connected to the first electrode 22 through the second via hole Via2.
  • the minimum spacing d11 between the first via hole Via1 and the gate line Gate is greater than the minimum spacing d21 between the second via hole and the same gate line Gate.
  • FIG. 3b is a plan view of the transistor provided for the embodiment of the present disclosure, which is electrically connected to the data line and the first electrode.
  • the first contact portion 13a is electrically connected to the data line Data through the first via hole Via1
  • the fourth contact portion 23b is electrically connected to the first electrode 22 through the second via hole Via2 and the third via hole Via3.
  • the minimum spacing d11 between the first via hole Via1 and the gate line Gate is greater than the minimum spacing d21 between the second via hole and the same gate line Gate.
  • the minimum spacing d31 between the third via hole Via3 and Gate is less than the minimum spacing d21 between the second via hole Via2 and the same gate line Gate.
  • the pixel unit 2 also includes an auxiliary component 6;
  • the auxiliary component 6 includes a fifth part 61 and a sixth part 62 connected to each other, the fifth part 61 is electrically connected to the fourth contact portion 23b through the second via hole Via2; the sixth part 62 is electrically connected to the first electrode 22 through the third via hole Via3.
  • the position design of the third via hole Via3 and the auxiliary component 6 can reduce the via hole ratio to improve the opening ratio, and increase the overlap area and yield of the first electrode 22 (ie, the pixel electrode ITO) and other film layers.
  • the auxiliary component 6 is disposed in the same layer as the data line Data, and in the first direction X, an auxiliary component is disposed between the positions where two adjacent data lines Data are connected to the first contact portion 13 a .
  • the first contact portion 13 a , the second contact portion 13 b , the third contact portion 23 a , and the fourth contact portion 23 b are disposed in the same layer.
  • the active layer T13 of the first transistor T1 and/or the active layer T23 of the second transistor T2 includes multiple stacked sublayers, wherein the mobility of the sublayers away from the substrate 1 is smaller than the mobility of the sublayers close to the substrate 1 .
  • FIG4 is a schematic diagram of an active layer using a composite film layer provided in an embodiment of the present disclosure.
  • the active layer T13 of the first transistor T1 and/or the active layer T23 of the second transistor T2 include a multilayer stacked sublayer ACT_1, a sublayer ACT_2, and a sublayer ACT_3.
  • the mobility of the sublayer ACT_3 far away from the base substrate 1 is less than the mobility of the sublayer ACT_2 close to the base substrate 1; the mobility of the sublayer ACT_2 far away from the base substrate 1 is less than the mobility of the sublayer ACT_1 close to the base substrate 1.
  • the material of the sub-layers includes one of IGO, ITZO, and IGZTO; when the active layer T23 of the second transistor T2 includes a plurality of stacked sub-layers, the material of the sub-layers includes one of IGO, ITZO, and IGZTO.
  • the metal oxide materials IGO, ITZO, and IGZTO are all semiconductor materials with a mobility greater than or equal to 20 cm 2 /(V.s).
  • the material of the sublayer ACT_1 provided in the embodiment of the present disclosure is not limited to the above materials, and may also include other semiconductor materials with a mobility greater than or equal to 20 cm 2 /(V.s). For this, the embodiments of the present disclosure will not list them one by one.
  • the preparation process of sub-layers in a multi-layer stacked arrangement includes but is not limited to the preparation methods of oxide semiconductor devices such as ESL, BCE, and Top Gate.
  • the first transistor T1 and/or the second transistor T2 is an N-type metal oxide semiconductor transistor, hereinafter referred to as NMOS transistor.
  • the embodiment of the present disclosure takes the example that the first transistor T1 and the second transistor T2 are both NMOS transistors to illustrate the specific structures of the first transistor T1 and the second transistor T2.
  • FIG5a is a top plan view of a transistor of a top gate structure provided by an embodiment of the present disclosure
  • FIG5b is a cross-sectional view of the structure shown in FIG5a in the AA direction; as shown in FIG5a and FIG5b, the first transistor T1 and the second transistor T2 can be transistors of a top gate structure.
  • the gate T14 of the first transistor T1 is located on the side of the active layer T13 of the first transistor T1 away from the substrate 1; the gate T24 of the second transistor T2 is located on the side of the active layer T23 of the second transistor T2 away from the substrate 1; the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b; the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a and the fourth contact portion 23b.
  • the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are all conductive portions formed after the active layer is conductively converted, and the conductive performance of the conductive portion is higher than that of the first channel portion 13c (and also higher than that of the second channel portion 23c), and the conductive performance of the conductive portion is lower than that of the metal electrode.
  • a specific conductive process can be selected to use plasma of He, Ar, H2 , NH3 and other gases (including mixed gases) for processing, and conductive doping is performed to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b.
  • the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer.
  • the second contact portion 13b is multiplexed as the second electrode T12 of the first transistor T1
  • the third contact portion 23a is multiplexed as the first electrode T21 of the second transistor T2.
  • the second contact portion 13b and the third contact portion 23a are connected to form an integral structure.
  • the first electrode T11 of the first transistor T1 is electrically connected to the first contact portion 13a and the data line Data through the first via hole Via1.
  • the second transistor The second electrode T22 of the tube is electrically connected to the fourth contact portion 23b and the fifth portion 61 of the auxiliary component 6 through the second via hole Via2.
  • top-gate transistors Compared with bottom-gate transistors, top-gate transistors have a simpler manufacturing process, require fewer photomasks, and have lower costs.
  • Figure 6a is a schematic diagram of the plane where the active layer shown in Figure 5b is located
  • Figure 6b is a schematic diagram of the plane where the first conductive layer shown in Figure 5b is located
  • Figure 6c is a schematic diagram of the plane where the first via and the second via shown in Figure 5b are located
  • Figure 6d is a schematic diagram of the plane where the second conductive layer shown in Figure 5b is located.
  • the display substrate also includes a first insulating layer 31 disposed on the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the base substrate 1 (as shown in FIG6a); a second insulating layer 32 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; a first conductive layer 41 disposed on the side of the second insulating layer 32 away from the semiconductor layer ACT (as shown in FIG6b); a third insulating layer 33 disposed on the side of the first conductive layer 41 away from the second insulating layer 32; and a second conductive layer 42 disposed on the side of the third insulating layer 33 away from the first conductive layer 41 (as shown in FIGS.
  • the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 (including the second contact portion 13b multiplexed as the second electrode T12 of the first transistor T1) and the active layer T23 of the second transistor T2 (including the third contact portion 23a multiplexed as the first electrode T21 of the second transistor T2) are both located in the semiconductor layer ACT; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.
  • the contour shape of the orthographic projection of the pattern formed by the first channel portion 13 c , the second contact portion 13 b and the third contact portion 23 a connected as one, and the second channel portion 23 c on the base substrate 1 is U-shaped.
  • Figure 7 is a top plan view of multiple pixel units provided in an embodiment of the present disclosure.
  • the first electrode 22 is a pixel electrode ITO; the orthographic projection of the second contact portion 13b and the third contact portion 23a connected as a whole on the base substrate 1 partially overlaps with the orthographic projection of at least one pixel electrode ITO on the base substrate 1.
  • the active layer is a light-transmitting layer
  • the area corresponding to the orthographic projection of the pixel electrode ITO is a display light-transmitting layer.
  • the light area therefore, the orthographic projection between the contact portion of the active layer and the pixel electrode ITO overlaps, which does not affect the display luminescence.
  • the orthographic projection of the second contact portion 13b and the third contact portion 23a connected as one on the base substrate 1 overlaps with the orthographic projection of at least one pixel electrode ITO on the base substrate 1, thereby reducing the layout space of a single pixel unit 2, thereby improving the resolution.
  • two pixel units 2 are adjacently arranged along the column direction, wherein the orthographic projection of the second contact portion 13 b and the third contact portion 23 a connected as one in one pixel unit 2 on the base substrate 1 partially overlaps with the orthographic projection of another pixel electrode ITO on the base substrate 1 .
  • the display substrate further includes a data line Data.
  • the data line Data is electrically connected to the first electrode T11 of the first transistor T1.
  • the positive projection of the data line Data on the active layer T13 of the first transistor T1 runs through the active layer T13 of the first transistor T1 along the direction from the first contact portion 13a to the second contact portion 13b (i.e., the direction opposite to the Y direction), and the contour edge of the positive projection of the data line Data on the active layer T13 of the first transistor T1 is at a certain distance from the edge of the active layer T13 of the first transistor T1 in the width direction X of the data line Data.
  • the layout space of the single pixel unit 2 is reduced, thereby improving the resolution.
  • the orthographic projection of the pixel electrode ITO on the second contact portion 13b and the third contact portion 23a connected as one does not fall within the orthographic projection of the data line Data on the active layer, so as to further improve the pixel resolution.
  • FIG8a is a schematic diagram of the plane where the first sub-hole is located
  • FIG8b is a schematic diagram of the plane where the second electrode is located
  • FIG8c is a schematic diagram of the plane where the second sub-hole is located
  • FIG8d is a schematic diagram of the plane where the first electrode is located.
  • the pixel unit 2 further includes a second electrode 23, and the second electrode 23 is located on a side of the pixel electrode ITO close to the base substrate 1.
  • the second electrode 23 is a common electrode.
  • the pixel electrode ITO is a slit electrode; the common electrode is a plate electrode.
  • the pixel electrode ITO is electrically connected to the auxiliary component 6 through the third via hole via3, and the auxiliary component 6 is electrically connected to the fourth contact portion 23b through the second via hole via2.
  • the third via hole via3 includes a first sub-hole via31 penetrating the planarization layer 342, and a second sub-hole via32 penetrating the metal protection layer 341.
  • the pixel electrode ITO is electrically connected to the auxiliary component 6 through the first sub-hole via31 and the second sub-hole via32 in sequence.
  • FIG. 9a is a schematic diagram of the structure of another top-gate structure transistor provided in an embodiment of the present disclosure
  • FIG. 9b is a cross-sectional view of the structure shown in FIG. 9a in the BB direction. As shown in FIG. 9a and FIG.
  • the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer; the first electrode T11 and the second electrode of the first transistor T1 are arranged in the same layer as the first electrode T21 and the second electrode of the second transistor T2; the first transistor T1
  • the gate T14 is located on the side of the active layer away from the substrate 1; the first electrode T11 and the second electrode of the first transistor T1 are located on the side of the gate away from the active layer;
  • the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b;
  • the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23c located between the third contact portion 23a
  • the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are all conductive portions formed after the active layer is conductively converted, and the conductive performance of the conductive portion is higher than that of the first channel portion 13c (and also higher than that of the second channel portion 23c), and the conductive performance of the conductive portion is lower than that of the metal electrode.
  • a specific conductive process can be selected to use plasma of He, Ar, H2 , NH3 and other gases (including mixed gases) for processing, and conductive doping is performed to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b.
  • the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are connected as an integral structure, and the second electrode T12 of the first transistor T1 is electrically connected to the second contact portion 13b through the fourth via hole Via4, and the first electrode T21 of the second transistor T2 is electrically connected to the third contact portion 23a through the fifth via hole Via5.
  • the first electrode T11 of the first transistor T1 is electrically connected to the first contact portion 13a and the data line Data through the first via hole Via1.
  • the second electrode T22 of the second transistor is electrically connected to the first contact portion 13a and the data line Data through the second via hole Via4.
  • Via2 is electrically connected to the fourth contact portion 23 b and the fifth portion 61 of the auxiliary component 6 , respectively.
  • the transistor with the top gate structure shown in FIG9b is connected in series in a different manner from the transistor with the top gate structure shown in FIG5b.
  • the transistor with the top gate structure shown in FIG9b uses a metal electrode (the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 connected as an integral structure) to achieve series connection. Since the conductivity of the metal electrode is higher than that of the second contact portion 13b and the third contact portion 23a after being conductorized, the top gate structure shown in FIG9b has higher device stability.
  • the display substrate further includes a first insulating layer 31 disposed on the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the base substrate 1; a second insulating layer 32 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; a first conductive layer 41 disposed on the side of the second insulating layer 32 away from the semiconductor layer ACT; a third insulating layer 33 disposed on the side of the first conductive layer 41 away from the second insulating layer 32; and a second conductive layer 42 disposed on the side of the third insulating layer 33 away from the first conductive layer 41.
  • the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both located in the semiconductor layer ACT; the first electrode T11 and the second electrode T12 of the first transistor T1, and the first electrode T21 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.
  • the first insulating layer 31 may be a buffer insulating layer, which may be provided with a single-layer structure and may be made of SiOx (x>0) material; or, the buffer insulating layer may be provided with a composite film layer structure and may be made of a composite film layer SiN/SiOx (x>0) material.
  • the first insulating layer 31 can be a dielectric layer disposed between the light shielding layer 50 and the semiconductor layer ACT. In addition to its own light shielding effect, it will also produce other effects: on the one hand, electrical effects; the light shielding layer 50 is conductive, and for the device of the floating light shielding layer 50, it will induce charges to turn on the transistor in advance, and the threshold voltage Vth will be reduced. The thinner the first insulating layer 31, the greater the effect. For the light shielding layer device connected to the gate, the first insulating layer 31 needs to be thinned to provide a higher Ion capability. In general, the thickness of the first insulating layer 31 with moderate electrical requirements.
  • the first insulating layer 31 needs a certain thickness to ensure isolation, to prevent the active layer from breaking or short-circuiting at the edge of the light shielding layer 50, and the thickness of the first insulating layer 31 is set between 200nm and 500nm.
  • the second insulating layer 32 may be a gate insulating layer, and the material of the gate insulating layer may generally be SiOx (x>0) material.
  • the second insulating layer 32 exists between the first conductive layer 41 and the semiconductor layer ACT.
  • the thickness of the second insulating layer 32 is set between 100nm and 300nm to prevent the film layer from being too thin and causing electrical breakdown.
  • the first conductive layer 41 can be set to a single-layer structure, using materials such as Al or Cu.
  • the first conductive layer 41 can be set to a composite film layer structure, including a buffer layer and a main conductive layer, wherein the material of the buffer layer can be a Ti-based alloy material or a Mo-based alloy material, and the material of the main conductive layer can be a material such as Al or Cu.
  • the first conductive layer 41 can be set to a single-layer structure, using Al or Cu to add Ti-based alloy materials or Mo-based alloy materials.
  • the third insulating layer 33 is an intermediate dielectric layer, which can be provided with a single-layer structure and made of SiOx (x>0) material; alternatively, the intermediate dielectric layer can be provided with a composite film layer structure and made of a composite film layer SiN/SiOx (x>0) material.
  • the third insulating layer 33 serves to separate the gate and the source/drain in the longitudinal section of the device.
  • a certain thickness is required between the two to prevent short circuits and reduce the capacitance between metals to prevent pulling between electrical signals.
  • An excessively thick intermediate dielectric layer is not conducive to the stability of engineering contact, so the thickness of the third insulating layer 33 is set between 300nm and 600nm.
  • the material of the second conductive layer 42 is metal.
  • the top gate structure shown in Figure 9b is connected to the pixel electrode ITO structure, as shown in Figures 16j and 8a to 8d.
  • the pixel electrode ITO is electrically connected to the auxiliary component 6 through the third via hole via3, and the auxiliary component 6 is electrically connected to the fourth contact portion 23b through the second via hole via2.
  • the third via hole via3 includes a first sub-hole via31 that penetrates the planarization layer 342, and a second sub-hole via32 that penetrates the metal protection layer 341.
  • the pixel electrode ITO is electrically connected to the auxiliary component 6 through the first sub-hole via31 and the second sub-hole via32 in turn.
  • FIG10 is a top view of the plane where the light shielding layer is located. It is a top gate structure as shown in FIG9b, and includes a light shielding layer 50. In some embodiments, as shown in FIG5b, FIG9b and FIG10, the display substrate further includes a light shielding layer 50 disposed near the base substrate 1 in the pixel unit 2.
  • the light shielding layer 50 may be provided with a composite film layer structure, using a composite film layer of Mo-based alloy/Cu material, or a composite film layer of Mo-based alloy/Al material.
  • the orthographic projection of the light shielding layer 50 on the base substrate 1 at least covers the orthographic projections of the first channel portion 13 c of the active layer T13 of the first transistor T1 and the second channel portion 23 c of the active layer T23 of the second transistor T2 on the base substrate 1 .
  • a light-shielding layer 50 is provided to block the light emitted from the backlight source to the first channel portion 13c and the second channel portion 23c, so that the number of electron-hole pairs generated by the first contact portion 13a (or the third contact portion 23a) due to light excitation can be reduced, thereby reducing the number of electrons moving to the second contact portion 13b (or the fourth contact portion 23b) during the holding stage, thereby reducing the light leakage current and improving the flicker problem caused by the leakage current.
  • Figure 11 is a plan view of an exemplary light-shielding layer provided in an embodiment of the present disclosure.
  • first spacing L1 between the contour edge of the orthographic projection of the light shielding layer 50 on the substrate 1 and the contour edge of the orthographic projection of the first channel portion 13c on the substrate 1, and the range of the first spacing L1 is 4 ⁇ m to 6 ⁇ m.
  • the width of the light shielding layer 50 in the first direction X is set slightly larger to ensure that the first channel portion 13c is not affected by light in the first direction X, thereby ensuring the stability of the first transistor T1.
  • the contour of the orthographic projection of the light shielding layer 50 on the substrate 1 has a second spacing L2, and the second spacing L2 ranges from 4 ⁇ m to 6 ⁇ m. Since the direction in which the third contact portion 23a points to the fourth contact portion 23b is the current flow direction, that is, the second direction Y, in order to avoid forming a current path in the side portion of the second channel portion 23c opposite to the first direction X, the width of the light shielding layer 50 in the first direction X is set slightly larger, ensuring that the second channel portion 23c is not affected by light in the first direction X, thereby ensuring the stability of the second transistor T2.
  • the second direction there is a third spacing L3 between the contour edge of the orthographic projection of the light shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the first channel portion 13c on the substrate substrate 1, and the range of the third spacing L3 is 0 to 4 ⁇ m.
  • the second direction Y there is a fourth spacing L4 between the contour edge of the orthographic projection of the light shielding layer 50 on the substrate substrate 1 and the contour edge of the orthographic projection of the second channel portion 23c on the substrate substrate 1, and the range of the fourth spacing L4 is 0 to 4 ⁇ m.
  • the width of the light shielding layer 50 in the second direction Y is set slightly smaller here to improve the transmittance.
  • the pixel units 2 in the same row are electrically connected to the same gate line Gate; the gate line Gate is used as the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 .
  • the gate line Gate is reused as the transistor gate. This configuration method of using in-plane wiring is used to achieve a narrow frame.
  • FIG12a is a performance test result of the transistor device in the normal working state (-1.5V) of the dual NMOS shown in FIG9b
  • FIG12b is a performance test result of the transistor device in the negative bias state (-8V) of the dual NMOS shown in FIG9b
  • the horizontal axis Vg represents the gate T24 (i.e., gate line Gate) voltage of the first transistor T1 and the second transistor T2
  • the vertical axis Ids represents the first electrode T11 (i.e., drain) current of the first transistor T1
  • Vth represents the threshold voltage
  • 01 represents the curve of the dual NMOS structure shown in FIG9b
  • 02 represents the curve of the single NMOS structure.
  • the off-state current of the dual NMOS is relatively small and the threshold voltage is relatively large compared to the single NMOS, whether in the normal working state or the negative bias state. Therefore, compared with the prior art, the embodiment of the present disclosure can effectively improve the overall leakage of the device. Electrical problems, as well as the Mura problem of display products caused by leakage.
  • the first transistor T1 and the second transistor T2 may be bottom-gate transistors.
  • FIG13a is a schematic diagram of a bottom-gate transistor structure provided in an embodiment of the present disclosure
  • FIG13b is a cross-sectional view of the structure shown in FIG13a in the CC direction.
  • the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are arranged in the same layer; the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the gate T11 of the first transistor T1 and the gate T22 of the second transistor T2 are arranged in the same layer; the gate T14 of the first transistor T1 and the gate T24 ...
  • the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, wherein the second contact portion 13b is multiplexed as a first channel portion 13c of the first transistor T1;
  • the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, wherein the third contact portion 23a is multiplexed as a second channel portion 23c of the second transistor T2.
  • the first contact portion 13a and the fourth contact portion 23b are both conductive portions formed after the active layer is conductively converted, and the conductive properties of the conductive portions are higher than the conductive properties of the first channel portion 13c (and also higher than the conductive properties of the second channel portion 23c), and the conductive properties of the conductive portions are lower than the metal electrodes.
  • a specific conductive process may be selected to process with plasma of He, Ar, H2 , NH3 or other gases (including mixed gases), and perform conductive doping to form the first contact portion 13a and the fourth contact portion 23b.
  • the second contact portion 13 b and the third contact portion 23 a are connected to form an integral structure.
  • the data line Date is multiplexed as the first electrode T11 of the first transistor T1.
  • the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22 through the third via hole Via3.
  • the second contact portion 13b and the third contact portion 23a connected as one body can be used to realize the series connection of two transistors.
  • the bottom-gate transistor can reuse the gate electrode on the side of the active layer close to the substrate 1 as an optical protective film for the active layer, which can prevent the carriers generated by the light emitted by the backlight source from irradiating the active layer and destroying the electrical properties of the active layer.
  • the second contact portion 13b and the third contact portion 23a are connected as an integral structure, that is, the first channel portion 13c and the second channel portion 23c are connected as an integral structure, which increases the channel length of the transistor and reduces the occurrence of conductorization.
  • the display substrate further includes a first conductive layer 41 disposed on the base substrate 1; a first insulating layer 31 disposed on the side of the first conductive layer 41 away from the base substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the first conductive layer 41; a second conductive layer 42 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; and a second insulating layer 32 disposed on the side of the second conductive layer 42 away from the semiconductor layer ACT.
  • the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 (including the second contact portion 13b multiplexed as the second electrode T12 of the first transistor T1) and the active layer T23 of the second transistor T2 (including the third contact portion 23a multiplexed as the first electrode T21 of the second transistor T2) are both located in the semiconductor layer ACT; the first electrode T11 of the first transistor T1 and the second electrode T22 of the second transistor T2 are both located in the second conductive layer 42.
  • FIG. 14a is a schematic diagram of the structure of another bottom-gate transistor provided in an embodiment of the present disclosure
  • FIG. 14b is a cross-sectional view of the structure shown in FIG. 14a along the DD direction. As shown in FIG. 14a and FIG.
  • the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are arranged in the same layer; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are arranged in the same layer; the first electrode T11 and the second electrode T12 of the first transistor T1 are arranged in the same layer as the first electrode T21 and the second electrode T22 of the second transistor T2;
  • the gate T14 of the body transistor T1 is located on a side of the active layer close to the substrate 1; the first electrode T11 and the second electrode T12 of the first transistor T1 are located on a side of the active layer away from the gate;
  • the active layer T13 of the first transistor T1 includes a first contact portion 13a and a second contact portion 13b, and a first channel portion 13c located between the first contact portion 13a and the second contact portion 13b;
  • the active layer T23 of the second transistor T2 includes a third contact portion 23a and a fourth contact portion 23b, and a second channel portion 23
  • the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are all conductive portions formed by conducting the active layer, and the conductive performance of the conductive portion is higher than the conductive performance of the first channel portion 13c (also higher than the conductive performance of the second channel portion 23c), and the conductive performance of the conductive portion is lower than that of the metal electrode .
  • the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b are formed by plasma treatment of a gas such as NH3 (including a mixed gas) and conductive doping.
  • the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are connected as an integrated structure, and the second electrode T12 of the first transistor T1 is electrically connected to the second contact portion 13b of the first transistor T1; the first electrode T21 of the second transistor T2 is electrically connected to the third contact portion 23a of the second transistor T2.
  • the data line Date is multiplexed as the first electrode T11 of the first transistor T1.
  • the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22 through the third via hole Via3.
  • the transistor with the bottom gate structure shown in FIG14b is connected in series in a different manner from the transistor with the bottom gate structure shown in FIG13b.
  • the transistor with the bottom gate structure shown in FIG14b uses a metal electrode (the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 connected as an integral structure) to achieve series connection. Since the conductivity of the metal electrode is higher than the conductivity of the second contact portion 13b and the third contact portion 23a after being conductorized, the bottom gate structure shown in FIG14b is used, and the device stability is higher.
  • the two transistors are connected in series. If one of them is abnormally turned off after conductorization, the other can still ensure normal operation.
  • the display substrate further includes a first conductive layer 41 disposed on the substrate; a first insulating layer 31 disposed on the side of the first conductive layer 41 away from the substrate 1; a semiconductor layer ACT disposed on the side of the first insulating layer 31 away from the first conductive layer 41; a second conductive layer 42 disposed on the side of the semiconductor layer ACT away from the first insulating layer 31; and a second insulating layer 32 disposed on the side of the second conductive layer 42 away from the semiconductor layer ACT.
  • the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2 are both located in the first conductive layer 41; the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both located in the semiconductor layer ACT; the first electrode T11 and the second electrode of the first transistor T1, and the first electrode T21 and the second electrode of the second transistor T2 are both located in the second conductive layer 42.
  • the first conductive layer 41 can be provided with a single layer structure, using materials such as Al or Cu.
  • the first conductive layer 41 can be provided with a composite film structure, including a buffer layer and a main conductive layer, wherein the material of the buffer layer can be a Ti-based alloy material or a Mo-based alloy material, and the material of the main conductive layer can be a material such as Al or Cu.
  • the first conductive layer 41 can be provided with a single layer structure, using materials such as Al or Cu.
  • the layer structure adopts Al or Cu with Ti alloy material or Mo alloy material added thereto.
  • the first insulating layer 31 may be a gate insulating layer, and the material of the gate insulating layer may generally be SiOx (x>0) material.
  • the thickness of the first insulating layer 31 as the gate insulating layer is larger than that of the top gate structure.
  • the thinner the first insulating layer 31 as the gate insulating layer the higher the Ion.
  • the thickness of the first insulating layer 31 can be 300nm to 500nm.
  • the material of the second conductive layer 42 is metal.
  • the second insulating layer 32 is a channel protection layer
  • the material of the channel protection layer can generally be SiOx (x>0) material
  • the thickness of the second insulating layer 32 is not less than 100 nm.
  • the second insulating layer 32 is a channel protection layer, and the material of the channel protection layer can generally be a composite film layer of SiN and SiOx (x>0), and the overall thickness of the second insulating layer 32 is between 200nm and 400nm.
  • the selection of the thickness of the second insulating layer 32 is not only a requirement for the thickness coverage of the second conductive layer 42, but also a requirement for the protection of TFT characteristics, such as the thickness requirement of the SiOx (x>0) film layer to ensure that the device does not become conductive, and the use of the SiN film layer to block the influence of water vapor on the organic film layer (the water vapor barrier capability of the SiN film layer is better than that of the SiOx (x>0) film layer), etc.
  • the pixel units 2 in the same row are electrically connected to the same gate line Gate; the gate line Gate is used as the gate T14 of the first transistor T1 and the gate T24 of the second transistor T2; the gate line Gate is a composite film layer, including a buffer layer and a main conductive layer sequentially arranged on the base substrate 1.
  • the material of the buffer layer can be Ti-based alloy material or Mo-based alloy material, and the material of the main conductive layer can be Al or Cu and other materials.
  • the pixel unit 2 further includes a second electrode 23, and the second electrode 23 is located on a side of the pixel electrode ITO close to the substrate 1. It is a common electrode.
  • the pixel electrode ITO is a slit electrode; the common electrode is a plate electrode.
  • the pixel electrode ITO is electrically connected to the second electrode T22 of the second transistor T2 through the third via hole via3.
  • the third via hole via3 includes a first sub-hole via31 penetrating the planarization layer 342, and a second sub-hole via32 penetrating the metal protection layer 341.
  • the pixel electrode ITO is electrically connected to the second electrode T22 of the second transistor T2 through the first sub-hole via31 and the second sub-hole via32 in sequence.
  • the embodiment of the present disclosure further provides a display device, which includes the display substrate of any one of the above embodiments.
  • the display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.
  • an embodiment of the present disclosure further provides a method for preparing a display substrate, which is used for preparing the display substrate of any one of the above embodiments.
  • the method specifically includes: providing a base substrate 1; forming a plurality of pixel units 2 arranged in an array on the base substrate 1.
  • the step of forming the pixel unit 2 at least includes: sequentially forming a pixel circuit 21 and a first electrode 22 on the base substrate 1.
  • the pixel circuit 21 at least includes a first transistor T1 and a second transistor T2; the second electrode T12 of the first transistor T1 is electrically connected to the first electrode T21 of the second transistor T2, and the second electrode T22 of the second transistor T2 is electrically connected to the first electrode 22.
  • the materials of the active layer T13 of the first transistor T1 and the active layer T23 of the second transistor T2 are both metal oxide semiconductor materials.
  • FIG. 15a to FIG. 15j are schematic diagrams of a process for preparing a display substrate shown in FIG. 5b provided in an embodiment of the present disclosure, specifically including the following steps S11 to S111, wherein:
  • the base substrate 1 is a glass substrate.
  • a light shielding layer 50 is formed on the base substrate 1.
  • a first insulating layer is formed on the side of the light shielding layer 50 away from the substrate 1.
  • a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .
  • the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.
  • a second insulating layer 32 and a first conductive layer 41 are formed on a side of the semiconductor layer ACT away from the first insulating layer 31 .
  • the second insulating layer 32 is a gate insulating layer, and the first conductive layer 41 includes a gate, or a gate line Gate multiplexed as a gate.
  • the material of the gate insulating layer and the material of the first conductive layer 41 are deposited in sequence; then, gate photolithography and etching are performed, and the gate insulating layer is etched using the gate as a mask to expose the semiconductor layer ACT and then conduct it.
  • the conductorization process can be processed using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases).
  • the conductive second contact portion 13 b is directly connected to the conductive third contact portion 23 a .
  • a third insulating layer 33 is continuously formed on the basis of step S15.
  • the material of the second insulating layer 32 is deposited, and then the intermediate dielectric layer is photolithographically processed and etched to form a first via hole Via1 to the first contact portion 13 a of the active layer and a second via hole Via2 to the fourth contact portion 23 b.
  • a second conductive layer 42 is formed on a side of the third insulating layer 33 facing away from the substrate 1 .
  • the material of the second conductive layer 42 is a metal material, and the second conductive layer 42 is electrically connected to the first contact portion 13a and the fourth contact portion 23b respectively through the first via hole Via1 and the second via hole Via2 penetrating the third insulating layer 33.
  • the second contact portion 13b is multiplexed as the second electrode T12 of the first transistor T1
  • the third contact portion 23a is multiplexed as the first electrode T21 of the second transistor T2.
  • a second conductive layer 42 is formed on the side away from the third insulating layer 33 A fourth insulating layer 34 .
  • the fourth insulating layer 34 may be a metal protection layer 341 and a planarization layer 342 .
  • the materials of the metal protection layer 341 and the planarization layer 342 are deposited in sequence; then, the planarization layer 342 is subjected to organic material photolithography to form a first sub-hole Via31.
  • a second electrode 23 is formed on a side of the fourth insulating layer 34 away from the third insulating layer 33 .
  • the second electrode 23 is a common electrode.
  • the fifth insulating layer 35 is a passivation layer.
  • the material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.
  • a pixel electrode ITO is formed on a side of the fifth insulating layer 35 away from the second electrode 23 .
  • the pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is connected to the fourth contact portion 23b through the second via hole Via2.
  • FIG. 16a to FIG. 16j are schematic diagrams of a process for preparing a display substrate shown in FIG. 9b provided in an embodiment of the present disclosure, specifically including the following steps S21 to S211, wherein:
  • the base substrate 1 is a glass substrate.
  • a light shielding layer 50 is formed on the base substrate 1 .
  • a first insulating layer 31 is formed on the side of the light shielding layer 50 facing away from the base substrate 1 .
  • a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .
  • the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.
  • a second insulating layer 32 and a first conductive layer 41 are formed on a side of the semiconductor layer ACT away from the first insulating layer 31 .
  • the second insulating layer 32 is a gate insulating layer, and the first conductive layer 41 includes a gate, or a gate line Gate multiplexed as a gate.
  • the material of the gate insulating layer and the material of the first conductive layer 41 are deposited in sequence; then, gate photolithography and etching are performed, and the gate insulating layer is etched using the gate as a mask to expose the semiconductor layer ACT and then conduct it.
  • the conductorization process can be processed using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases).
  • a third insulating layer 33 is continuously formed on the basis of step S25.
  • the material of the second insulating layer 32 is deposited, and then the intermediate dielectric layer is photolithographically and etched to form a first via Via1 to the first contact portion 13a of the active layer, a fourth via Via4 to the second contact portion 13b, a fifth via Via5 to the third contact portion 23a, and a second via Via2 to the fourth contact portion 23b.
  • a second conductive layer 42 is formed on a side of the third insulating layer 33 facing away from the substrate 1 .
  • the material of the second conductive layer 42 is a source/drain metal, in which the drain of the first transistor T1 is electrically connected to the first contact portion 13a through a first via Via1 that penetrates the third insulating layer 33.
  • the source of the first transistor T1 is electrically connected to the drain of the second transistor T2, and is electrically connected to the second contact portion 13b and the third contact portion 23a through a fourth via Via4 and a fifth via Via5, respectively.
  • the source of the second transistor T2 is electrically connected to the fourth contact portion 23b through a second via Via2.
  • the auxiliary component 6 is reused as the source of the second transistor T2.
  • the auxiliary component 6 is connected to the third via Via4 through the third via Via5.
  • a fourth insulating layer 34 is formed on a side of the second conductive layer 42 away from the third insulating layer 33 .
  • the fourth insulating layer 34 is a planarization layer.
  • the material of the planarization layer is deposited, and then the organic material is photolithographically processed to form the first sub-hole Via31.
  • a second electrode 23 is formed on a side of the fourth insulating layer 34 away from the third insulating layer 33 .
  • the second electrode 23 is a common electrode.
  • the fifth insulating layer 35 is a passivation layer.
  • the material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.
  • a pixel electrode ITO is formed on a side of the fifth insulating layer 35 away from the second electrode 23 .
  • the pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is connected to the fourth contact portion 23b through the second via hole Via2.
  • FIG. 17a to FIG. 17i are schematic diagrams of a process for preparing a display substrate shown in FIG. 13b provided in an embodiment of the present disclosure, specifically including the following steps S31 to S310, wherein:
  • the base substrate 1 is a glass substrate.
  • the first conductive layer 41 is a composite film layer, including a buffer layer and a main conductive layer sequentially arranged on the base substrate 1.
  • the material of the buffer layer can be Ti alloy material or Mo alloy material, and the material of the main conductive layer can be Al or Cu.
  • the first conductive layer 41 includes a gate line Gate which is multiplexed as the gate of the first transistor T1 and the gate of the second transistor T2 .
  • a semiconductor layer is formed on the side of the first insulating layer 31 away from the light shielding layer 50.
  • Body layer ACT Body layer
  • the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.
  • the semiconductor layer ACT is conductively processed using a mask.
  • the conductive process may be processed using plasma of gases such as He, Ar, H2, NH3 (including mixed gases) to form the first contact portion 13a and the fourth contact portion 23b of the active layer.
  • the second conductive layer 42 includes a first electrode T11 of the first transistor T1 and a second electrode T22 of the second transistor T2.
  • the first electrode T11 of the first transistor T1 is directly connected to the first contact portion 13a
  • the second contact portion 13b is multiplexed as the first channel portion 13c of the first transistor T1
  • the third contact portion 23a is multiplexed as the second channel portion 23c of the second transistor T2.
  • the second contact portion 13b and the third contact portion 23a are connected as an integral structure
  • the second electrode T22 of the second transistor T2 is directly connected to the fourth contact portion 23b.
  • the active layer IGZO
  • a second insulating layer 32 is formed on a side of the second conductive layer 42 away from the first insulating layer 31 .
  • the second insulating layer 32 is a channel protection layer.
  • a third insulating layer 33 is formed on a side of the second insulating layer 32 away from the second conductive layer 42 .
  • the third insulating layer 33 is a planarization layer.
  • the material of the planarization layer is deposited, and then the organic material is photolithographically processed to form the first sub-hole Via31.
  • a second electrode 23 is formed on a side of the third insulating layer 33 that is away from the second insulating layer 32 .
  • the second electrode 23 is a common electrode.
  • a fourth insulating layer 34 is formed on a side of the second electrode 23 away from the third insulating layer.
  • the fourth insulating layer 34 is a passivation layer.
  • the material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.
  • a pixel electrode ITO is formed on a side of the fourth insulating layer 34 away from the second electrode 23 .
  • the pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is directly connected to the fourth contact portion 23b.
  • FIG. 18a to FIG. 18i are schematic diagrams of a process for preparing a display substrate shown in FIG. 10 provided in an embodiment of the present disclosure, specifically including the following steps S41 to S410, wherein:
  • the base substrate 1 is a glass substrate.
  • the first conductive layer 41 is a composite film layer, including a buffer layer and a main conductive layer sequentially arranged on the base substrate 1.
  • the material of the buffer layer can be Ti alloy material or Mo alloy material, and the material of the main conductive layer can be Al or Cu.
  • the first conductive layer 41 includes a gate line Gate which is multiplexed as the gate of the first transistor T1 and the gate of the second transistor T2 .
  • a semiconductor layer ACT is formed on a side of the first insulating layer 31 away from the light shielding layer 50 .
  • the material of the semiconductor layer ACT is deposited, and the material of the semiconductor layer ACT is selected from high-mobility oxide materials such as IGZTO, IGO, etc.; and then conventional annealing and patterning processes are performed.
  • the semiconductor layer ACT is conductorized using a mask.
  • the conductorization process can be processed using plasma (Plasma) of gases such as He, Ar, H2, NH3 (including mixed gases) to form the first contact portion 13a, the second contact portion 13b, the third contact portion 23a and the fourth contact portion 23b of the active layer.
  • plasma Pulsma
  • gases such as He, Ar, H2, NH3 (including mixed gases)
  • the second conductive layer 42 includes a first electrode T11 and a second electrode of the first transistor T1, and a first electrode T21 and a second electrode of the second transistor T2.
  • the second electrode T12 of the first transistor T1 and the first electrode T21 of the second transistor T2 are an integrated structure.
  • the first electrode T11 of the first transistor T1 is directly connected to the first contact portion 13a
  • the second electrode T12 of the first transistor T1 is directly connected to the second contact portion 13b
  • the first electrode T21 of the second transistor T2 is directly connected to the third contact portion 23a
  • the second electrode T22 of the second transistor T2 is directly connected to the fourth contact portion 23b.
  • the active layer IGZO
  • a second insulating layer 32 is formed on a side of the second conductive layer 42 away from the first insulating layer 31 .
  • the second insulating layer 32 is a channel protection layer.
  • a third insulating layer 33 is formed on a side of the second insulating layer 32 away from the second conductive layer 42 .
  • the third insulating layer 33 is a planarization layer.
  • the material of the planarization layer is deposited, and then the organic material is photolithographically processed to form the first sub-hole Via31.
  • a second electrode 23 is formed on a side of the third insulating layer 33 that is away from the second insulating layer 32 .
  • the second electrode 23 is a common electrode.
  • a fourth insulating layer 34 is formed on a side of the second electrode 23 away from the third insulating layer.
  • the fourth insulating layer 34 is a passivation layer.
  • the material of the passivation layer is deposited, and then the passivation layer is photolithographically and etched to form a second sub-hole Via32 leading to the second electrode T22 of the second transistor T2.
  • a pixel electrode ITO is formed on a side of the fourth insulating layer 34 away from the second electrode 23 .
  • the pixel electrode ITO is a slit electrode and has a connection portion, which is connected to the auxiliary component 6 (ie, the second electrode T22 of the second transistor T2) through the third via hole Via3; the auxiliary component 6 is directly connected to the fourth contact portion 23b.

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Abstract

本公开提供一种显示基板和显示装置，属于显示技术领域，其中，显示基板包括衬底基板、以及位于衬底基板上的栅线和数据线，栅线和数据线交叉限定出多个像素单元；栅线沿第一方向延伸，数据线沿第二方向延伸，第一方向和第二方向相交；像素单元包括第一晶体管和第二晶体管；第一晶体管的有源层包括第一接触部和第二接触部，第二晶体管的有源层包括第三接触部和第四接触部，第一接触部与数据线电连接，第二接触部与第三接触部电连接，第四接触部与像素单元的第一电极电连接；沿着第二方向，第一接触部与栅线的最大间距不小于第四接触部与同一栅线的最大间距。

Description

一种显示基板和显示装置 技术领域
本公开属于显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
晶体管作为开关控制元件或者周边驱动电路的集成元件，是显示技术中的核心器件。在半导体领域，迁移率指的是电子在半导体材料中的移动速度，对于半导体显示器件而言，迁移率就意味着同样器件大小下所能达成的显示画质及使用寿命能力。
然而，随着对器件半导体材料的优化设计，在提高迁移率的同时也带来了例如存在着阈值电压偏低，以及光照下的负向偏移等问题。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板和显示装置。
第一方面，解决本公开技术问题所采用的技术方案是一种显示基板，其包括衬底基板、以及位于所述衬底基板上的栅线和数据线，所述栅线和所述数据线交叉限定出多个像素单元；所述栅线沿第一方向延伸，所述数据线沿第二方向延伸，所述第一方向和所述第二方向相交；所述像素单元包括第一晶体管和第二晶体管；所述第一晶体管的有源层包括第一接触部和第二接触部，所述第二晶体管的有源层包括第三接触部和第四接触部，所述第一接触部与所述数据线电连接，所述第二接触部与所述第三接触部电连接，所述第四接触部与所述像素单元的第一电极电连接；沿着所述第二方向，所述第一接触部与所述栅线的最大间距不小于所述第四接触部与同一所述栅线的最大间距。
在一些实施例中，沿着所述第一方向，所述第一接触部的宽度小于所述第四接触部的宽度。
在一些实施例中，所述第一接触部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影交叠，所述第一接触部包括彼此连接的第一部分 和第二部分，所述第一部分与所述数据线电连接，沿着所述第一方向，所述第一部分的宽度大于所述第二部分的宽度。
在一些实施例中，所述第四接触部在所述衬底基板的正投影与所述栅线在所述衬底基板的正投影部分交叠，所述第四接触部包括彼此连接的第三部分和第四部分，所述第四部分与所述第一电极电连接，沿着所述第二方向，所述第四部分的最小宽度大于所述第三部分的最小宽度。
在一些实施例中，所述第一接触部与所述数据线通过第一过孔电连接，所述第四接触部与所述第一电极通过第二过孔电连接；沿着所述第二方向，所述第一过孔与所述栅线的最小间距大于所述第二过孔与同一栅线的最小间距。
在一些实施例中，所述第一接触部与所述数据线通过第一过孔电连接，所述第四接触部与所述第一电极通过第二过孔和第三过孔电连接；沿着所述第二方向，所述第一过孔与所述栅线的最小间距大于所述第二过孔与同一栅线的最小间距；所述第三过孔与所述栅线的最小间距小于所述第二过孔与同一栅线的最小间距。
在一些实施例中，所述像素单元还包括辅助部件；所述辅助部件包括彼此连接的第五部分和第六部分，所述第五部分与所述第四接触部通过所述第二过孔电连接；所述第六部分与所述第一电极通过所述第三过孔电连接。
在一些实施例中，所述辅助部件与所述数据线同层设置，且在所述第一方向上，相邻两条所述数据线在与所述第一接触部连接位置之间设置有所述辅助部件。
在一些实施例中，所述第一接触部、所述第二接触部、所述第三接触部和所述第四接触部同层设置。
在一些实施例中，所述第一晶体管的有源层和/或所述第二晶体管的有源层包括金属氧化物半导体材料。
在一些实施例中，所述第一晶体管和第二晶体管的有源层包括层叠设置的多层子层，远离所述衬底基板的子层的迁移率小于靠近所述衬底基板的子 层的迁移率。
在一些实施例中，所述第一晶体管的栅极位于所述第一晶体管的有源层背离所述衬底基板的一侧；所述第二晶体管的栅极位于所述第二晶体管的有源层背离所述衬底基板的一侧；所述第一晶体管的有源层和所述第二晶体管的有源层同层设置；
所述数据线复用为所述第一晶体管的第一极；所述第二接触部复用为所述第一晶体管的第二极，所述第三接触部复用为所述第二晶体管的第一极，所述第二接触部与所述第三接触部连接为一体结构。
在一些实施例中，所述第一电极为像素电极；连接为一体的所述第二接触部与所述第三接触部在所述衬底基板上的正投影，与至少一个所述像素电极在所述衬底基板上的正投影部分重叠。
在一些实施例中，对于相邻的两所述像素单元，其中一个所述像素单元中连接为一体的所述第二接触部与所述第三接触部在所述衬底基板上的正投影，与另一个所述像素单元在所述衬底基板上的正投影部分重叠。
在一些实施例中，所述第一晶体管的有源层还包括设置在所述第一接触部和所述第二接触部之间的第一沟道部，所述第二晶体管的有源层还包括设置在所述第三接触部和所述第四接触部之间的第二沟道部；所述第一沟道部、连接为一体的所述第二接触部与所述第三接触部，以及所述第二沟道部所构成的图案在所述衬底基板上的正投影的轮廓形状为U型。
在一些实施例中，所述第一晶体管的栅极和所述第二晶体管的栅极同层设置；所述第一晶体管的有源层和所述第二晶体管的有源层同层设置；所述第一晶体管的第一极和第二极，与所述第二晶体管的第一极和第二极同层设置；
所述第一晶体管的栅极位于所述有源层背离所述衬底基板的一侧；所述第一晶体管的第一极和第二极位于所述栅极背离所述有源层的一侧；
所述数据线复用为所述第一晶体管的第一极；所述第一晶体管的第二极和所述第二晶体管的第一极连接为一体结构，且所述第一晶体管的第二极通 过第四过孔与所述第二接触部电连接，所述第二晶体管的第一极通过第五过孔与所述第三接触部电连接。
在一些实施例中，所述显示基板还包括设置在所述像素单元靠近所述衬底基板的遮光层；
所述第一晶体管的有源层还包括设置在所述第一接触部和所述第二接触部之间的第一沟道部，所述第二晶体管的有源层还包括设置在所述第三接触部和所述第四接触部之间的第二沟道部；
所述遮光层在所述衬底基板上的正投影至少覆盖，所述第一沟道部和所述第二沟道部在所述衬底基板上的正投影。
在一些实施例中，在第一方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘，和所述第一沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第一间距；
在第一方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘和，所述第二沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第二间距；
所述第一间距和/或所述第二间距的范围在4μm～6μm。
在一些实施例中，在第二方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘，和所述第一沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第三间距；
在第二方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘和，所述第二沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第四间距；
所述第三间距和/或所述第四间距的范围在0～4μm。
在一些实施例中，位于同一行的所述像素单元电连接同一条栅线；所述栅线用作所述第一晶体管的栅极和所述第二晶体管的栅极。
在一些实施例中，所述第一晶体管的栅极在靠近所述有源层的一侧设置有栅极绝缘层；所述栅极绝缘层的厚度在10nm～30nm之间。
在一些实施例中，所述第一晶体管的栅极和所述第二晶体管的栅极同层 设置；所述第一晶体管的有源层和所述第二晶体管的有源层同层设置；所述第一晶体管的第一极和第二极，与所述第二晶体管的第一极和第二极同层设置；
所述第一晶体管的栅极位于所述有源层靠近所述衬底基板的一侧；所述第一晶体管的第一极和第二极位于所述有源层背离所述栅极的一侧；
所述数据线复用为所述第一晶体管的第一极；所述第一晶体管的第二极和所述第二晶体管的第一极连接为一体结构，且所述第一晶体管的第二极与所述第一晶体管的第二接触部电连接；所述第二晶体管的第一极与所述第二晶体管的第三接触部电连接。
在一些实施例中，位于同一行的所述像素单元电连接同一条栅线；所述栅线用作所述第一晶体管的栅极和所述第二晶体管的栅极；
所述栅线为复合膜层，包括依次设置在所述衬底基板上的缓冲层和主体导电层。
在一些实施例中，所述第一晶体管的栅极在靠近所述有源层的一侧设置有栅极绝缘层；所述栅极绝缘层的厚度在30nm～50nm之间。
第二方面，本公开实施例还提供了一种显示装置，其中，包括如第一方面中任一项所述的显示基板。
附图说明
图1a为本公开实施例提供的像素电路的结构示意图；
图1b为本公开实施例提供的有源层的接触部与栅线之间的位置关系示意图；
图2为本公开实施例提供的第一接触部和第二接触部的具体分布示意图；
图3a为本公开实施例提供的晶体管与数据线电连接的平面图；
图3b为为本公开实施例提供的晶体管与数据线和第一电极电连接的平面图；
图4为本公开实施例提供的采用复合膜层的有源层的示意图；
图5a为本公开实施例提供的一种顶栅型结构的晶体管的俯视平面图；
图5b为图5a所示结构AA方向的截面图；
图6a为图5b所示有源层所在平面的示意图；
图6b为图5b所示第一导电层所在平面的示意图；
图6c为图5b所示第一过孔和第二过孔所在平面的示意图；
图6d为图5b所示第二导电层所在平面的示意图；
图7为本公开实施例提供的像素单元中多个像素单元的俯视平面图；
图8a为第一子孔所在平面的示意图；
图8b为第二电极所在平面的示意图；
图8c为第二子孔所在平面的示意图；
图8d为第一电极所在平面的示意图；
图9a为本公开实施例提供的另一种顶栅型结构的晶体管的结构示意图；
图9b为图9a所示结构BB方向的截面图；
图10为遮光层所在平面的俯视图；
图11为本公开实施例提供的一种示例性的遮光层的平面俯视图；
图12a为图9b所示双NMOS正常工作状态(-1.5V)的晶体管器件性能测试结果；
图12b为图9b所示双NMOS负偏压状态(-8V)的晶体管器件性能测试结果；
图13a为本公开实施例提供的一种底栅型结构的晶体管的结构示意图；
图13b为图13a所示结构CC方向的截面图；
图14a为本公开实施例提供的另一种底栅型结构的晶体管的结构示意图；
图14b为图14a所示结构DD方向的截面图；
图15a～图15j为本公开实施例提供的图5b所示显示基板的制备流程示意图；
图16a～图16j为本公开实施例提供的图9b所示显示基板的制备流程示意图；
图17a～图17i为本公开实施例提供的图13b所示显示基板的制备流程示意图；
图18a～图18i为本公开实施例提供的图10所示显示基板的制备流程示意图。
其中附图标记为：1、衬底基板；2、像素单元；21、像素电路；22、第一电极；23、第二电极；T1、第一晶体管；T2、第二晶体管；T11、第一晶体管的第一极；T12、第一晶体管的第二极；T13、第一晶体管的有源层；13a、第一接触部；13b、第二接触部；13c、第一沟道部；T14、第一晶体管的栅极；T21、第二晶体管的第一极；T22、第二晶体管的第二极；T23、第二晶体管的有源层；23a、第三接触部；23b、第四接触部；23c、第二沟道部；T24、第二晶体管的栅极；Gate、栅线；Data、数据线；ACT、半导体层；ACT_1、子层；31、第一绝缘层；32、第二绝缘层；33、第三绝缘层；34、第四绝缘层；35、第五绝缘层；41、第一导电层；42、第二导电层；43、第三导电层；50、遮光层；X、第一方向；Y、第二方向；6、辅助部件；61、第五部分；62、第六部分；Via1、第一过孔；Via2、第二过孔；Via3、第三过孔；Via31、第一子孔；Via32、第二子孔。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。 基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在相关技术中，目前业内使用的非晶硅(a-Si)，金属氧化物(IGZO)，低温多晶硅(LTPS)而言，其有效迁移率实际约为1cm2/(V﹒s)，10cm2/(V﹒s)，80cm2/(V﹒s)，可以看出，材料性能上低温多晶硅(LTPS)遥遥领先。传统技术通过开发金属氧化物材料的不同系列，以保持高迁移率水平，例如包含铟(In)含量提升的元素比例调整方案、去除锌(Zn)成分或新加入锡(Sn)成分等元素变更方案，不一而足，从而可以实现约20cm2/(V﹒s)～50cm2/(V﹒s)的较高迁移率。但是，在提高迁移率的同时也带来了如下的一系列问题：一方面、高迁移材料的光学带隙(Eg)较小，更容易产生载流子，从而使得高迁材料中的电子可以吸收部分可见光波段的光产生电子跃迁，进而导致器件能力上表现为见光薄膜晶体管(Thin Film Transistor，TFT)提前开启，且光照下新增缺陷增加，负偏压温度光照稳定性(Negative Bias Temperature Illumination Stability，NBTIS)劣化严重，导致使用寿命严重衰退。另一方面、高迁材料的开发受限于迁移率与Eg不能双赢的难点，目前迟迟未能突破Mob 30及以上高迁材料的量产。而相关技术从TFT器件设计方向，以及双栅结构设计方向入手，通过双栅TFT及超薄栅绝缘层(GI)厚度，能够实现近似20cm2/(V﹒s)及以上超高迁移率指标的器件性能。然而， 这种器件设计尽管实现了高迁移率，但同时也降低了低电压下的电流值，也即关态电流(Ioff)，因此会导致器件阈值电压(Vth)的显著降低。同时，GI厚度的降低，也会造成器件的耐击穿电压下降，从而提高器件失效风险。因此，综合上述信息，对于超高迁移率器件的制备，存在着阈值电压偏低，以及光照下的负向偏移等问题。基于这些问题，传统技术方案往往无法突破50cm2/(V﹒s)及以上的超高迁移率，市面上无量产实绩。
鉴于此，本公开实施例提供了一种显示基板，通过将与像素单元的第一电极电连接的双晶体管串联，改善现有器件阈值电压(Vth)负偏带来的漏电问题，提升显示基板的开关能力以及产品的使用寿命。
图1a为本公开实施例提供的像素电路的结构示意图，图1b为本公开实施例提供的有源层的接触部与栅线之间的位置关系示意图，如图1a和图1b所示，显示基板包括衬底基板1(图1a和图1b中未示出，具体参见图4)、以及位于衬底基板1上的栅线Gate和数据线Data，栅线Gate和数据线Data交叉限定出多个像素单元2；栅线Gate沿第一方向X延伸，数据线Data沿第二方向Y延伸，第一方向X和第二方向Y相交，例如，第一方向X和第二方向Y垂直设置。像素单元2包括像素电路21和第一电极22；像素电路21至少包括第一晶体管T1和第二晶体管T2；第一晶体管T1的有源层T13包括第一接触部13a和第二接触部13b，第二晶体管T2的有源层T23包括第三接触部23a和第四接触部23b，第一接触部13a与数据线Data电连接，第二接触部13b与第三接触部23a电连接，第四接触部23b与像素单元2的第一电极22电连接；沿着第二方向Y，第一接触部13a与栅线Gate的最大间距d1不小于第四接触部23b与同一栅线的最大间距d2。
如图1a所示，第一晶体管T1的第二极T12和第二晶体管T2的第一极T21电连接，第二晶体管T2的第二极T22与第一电极22电连接。第一晶体管T1的有源层T13和第二晶体管T2的有源层T23的材料均为金属氧化物半导体材料。
示例性的，金属氧化物半导体材料可以采用铟镓锌氧化物(IGZO)，铟镓锡氧化物(IGTO)以及铟锡锌氧化物(ITZO)，铟镓氧化物(IGO)，铟镓 锌锡氧化物(IGZTO)，稀土掺杂氧化物(Ln-OS)中的一种或多种材料制成。材料可为非晶、部分结晶、单晶或多晶状态，制备的有源层可为单层或多层结构。根据金属氧化物半导体材料实际特性可知，这种材料能够提高晶体管的迁移率。
需要说明的是，本公开实施例中所采用的晶体管可以为场效应管(MOS管)，由于采用的MOS管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例及之后的描述中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，本公开实施例中第一晶体管T1的有源层T13和第二晶体管T2的有源层T23的材料均为金属氧化物半导体材料。要知道，金属氧化物半导体材料的晶体管只能制备N型晶体管，因此，本公开实施例的晶体管为N型晶体管。其中，晶体管的第一极为N型晶体管的漏极，晶体管的第二极为N型晶体管的源极，栅极输入高电平信号时，源漏极导通。
像素单元2在实际应用中，不是像素单元2中的任意晶体管所采用上述结构均会达到类似效果。因此，需要说明的是，对于任意像素单元2，是与第一电极22电连接的第二晶体管T2，增加第一晶体管T1并与第二晶体管T2串联，其中一个晶体管的电流值会被另一个晶体管所抑制，在极限情况下，当其中一个晶体管出现导体化性质的负偏时，另外一个晶体管仍处于正常工作状态，从而显著降低关态电流，并降低阈值电压负偏移的风险。
本公开实施例提供的显示基板，与第一电极22电连接的双晶体管的有源层的材料均采用金属氧化物半导体材料，因此能够提高晶体管的迁移率；同时，两个晶体管串联，其中一个晶体管的电流值会被另一个晶体管所抑制，在极限情况下，当其中一个晶体管出现导体化性质的负偏时，另外一个晶体管仍处于正常工作状态，能够显著提高器件整体的阈值电压，从而有效改善器件整体的漏电问题，以及漏电所造成的显示产品沙粒亮点(Mura)问题。
在一些实施例中，如图1b所示，沿着第一方向X，第一接触部13a的最小宽度小于第四接触部23b的最小宽度。
这里，“宽度”可以理解为沿指定方向，指定膜层的边界之间的最大间距或平均间距，可以为横向尺寸，也可以为纵向尺寸。
在一些实施例中，图2为本公开实施例提供的第一接触部和第二接触部的具体分布示意图，如图2所示，第一接触部13a在衬底基板1的正投影与数据线Data在衬底基板1的正投影交叠，第一接触部13a包括彼此连接的第一部分13a1和第二部分13a2，第一部分13a1与数据线Data电连接，沿着第一方向X，第一部分13a1的宽度w1大于第二部分13a2的宽度w2。
在一些实施例中，如图2所示，第四接触部23b在衬底基板1的正投影与栅线Gate在述衬底基板1的正投影部分交叠，第四接触部23b包括彼此连接的第三部分23b1和第四部分23b2，第四部分23b2与第一电极22电连接，沿着第二方向Y，第四部分23b2的最小宽度w4大于第三部分23b1的最小宽度w3。
在一些实施例中，图3a为本公开实施例提供的晶体管与数据线电连接的平面图，如图3a所示，第一接触部13a与数据线Data通过第一过孔Via1电连接，第四接触部23b与第一电极22通过第二过孔Via2电连接。沿着第二方向Y，第一过孔Via1与栅线Gate的最小间距d11大于第二过孔与同一栅线Gate的最小间距d21。
在一些实施例中，图3b为为本公开实施例提供的晶体管与数据线和第一电极电连接的平面图，如图3b所示，第一接触部13a与数据线Data通过第一过孔Via1电连接，第四接触部23b与第一电极22通过第二过孔Via2和第三过孔Via3电连接。沿着第二方向Y，第一过孔Via1与栅线Gate的最小间距d11大于第二过孔与同一栅线Gate的最小间距d21。第三过孔Via3与Gate的最小间距d31小于第二过孔Via2与同一栅线Gate的最小间距d21。
在一些实施例中，如图3b所示，像素单元2还包括辅助部件6；辅助部件6包括彼此连接的第五部分61和第六部分62，第五部分61与第四接触部23b通过第二过孔Via2电连接；第六部分62与第一电极22通过第三过孔Via3电连接。
本实施例中，第三过孔Via3和辅助部件6的位置设计，可缩小过孔占比从而提高开口率，以及增加第一电极22(也即像素电极ITO)与其他膜层的搭接面积和良率。
在一些实施例中，如图6d所示，辅助部件6与数据线Data同层设置，且在第一方向X上，相邻两条数据线Data在与第一接触部13a连接位置之间设置有辅助部件。
在一些实施例中，如图6a所示，第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b同层设置。
在一些实施例中，第一晶体管T1的有源层T13和/或第二晶体管T2的有源层T23包括层叠设置的多层子层，其中，远离衬底基板1的子层的迁移率小于靠近衬底基板1的子层的迁移率。
图4为本公开实施例提供的采用复合膜层的有源层的示意图，如图4所示，第一晶体管T1的有源层T13和/或第二晶体管T2的有源层T23包括多层层叠设置的子层ACT_1、子层ACT_2和子层ACT_3。其中，远离衬底基板1的子层ACT_3的迁移率小于靠近衬底基板1的子层ACT_2的迁移率；远离衬底基板1的子层ACT_2的迁移率小于靠近衬底基板1的子层ACT_1的迁移率。
需要说明的是，迁移率越高，对应器件的稳定性越低。因此，本实施例通过依次沉积迁移率较小的子层ACT_1，在确保器件具有较高迁移率的同时，提升器件的稳定性。
在一些实施例中，当第一晶体管T1的有源层T13包括多层层叠设置的子时，子层的材料包括IGO、ITZO、IGZTO中的一种；当第二晶体管T2的有源层T23包括多层层叠设置的子层时，子层的材料包括IGO、ITZO、IGZTO中的一种。
上述金属氧化物材料IGO、ITZO、IGZTO均为具备迁移率大于或等于20cm2/(V﹒s)的半导体材料。当然，本公开实施例提供的子层ACT_1的材料也不限于上述几种，还可以包括其他迁移率大于或等于20cm2/(V﹒s)的半导 体材料，对此，本公开实施例不再一一列举。
对于多层层叠设置的子层的制备工艺，包括但不仅限于ESL，BCE，Top Gate等氧化物半导体器件的制备方式。
在一些实施例中，第一晶体管T1和/或第二晶体管T2为N型金属氧化物半导体晶体管，以下简称NMOS管。
本公开实施例以第一晶体管T1和第二晶体管T2均为NMOS管为例，对第一晶体管T1和第二晶体管T2的具体结构进行说明。
在一些实施例中，图5a为本公开实施例提供的一种顶栅型结构的晶体管的俯视平面图，图5b为图5a所示结构AA方向的截面图；如图5a和图5b所示，第一晶体管T1和第二晶体管T2可以采用顶栅型结构的晶体管。第一晶体管T1的栅极T14位于第一晶体管T1的有源层T13背离衬底基板1的一侧；第二晶体管T2的栅极T24位于第二晶体管T2的有源层T23背离衬底基板1的一侧；第一晶体管T1的有源层T13包括第一接触部13a和第二接触部13b，以及位于第一接触部13a和第二接触部13b之间的第一沟道部13c；第二晶体管T2的有源层T23包括第三接触部23a和第四接触部23b，以及位于第三接触部23a和第四接触部23b之间的第二沟道部23c。
其中，第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b均是对有源层进行导体化后形成的导电部，该导电部的导电性能高于第一沟道部13c的导电性能(也高于第二沟道部23c的导电性能)，导电部的导电性能低于金属电极。具体导体化工艺，例如可以选用He、Ar、H2、NH3等气体(包含混合气体)的等离子体进行处理，进行导体化掺杂，形成第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b。
示例性的，如图5a和图5b所示，第一晶体管T1的有源层T13和第二晶体管T2的有源层T23同层设置。第二接触部13b复用为第一晶体管T1的第二极T12，第三接触部23a复用为第二晶体管T2的第一极T21，第二接触部13b与第三接触部23a连接为一体结构。第一晶体管T1的第一极T11通过第一过孔Via1，分别第一接触部13a和数据线Data电连接。第二晶体 管的第二极T22，通过第二过孔Via2分别与第四接触部23b和辅助部件6的第五部分61电连接。
顶栅型结构的晶体管相比于底栅型结构的晶体管的制造工艺简单，所需光刻版数量少，成本低。
图6a为图5b所示有源层所在平面的示意图，图6b为图5b所示第一导电层所在平面的示意图，图6c为图5b所示第一过孔和第二过孔所在平面的示意图，图6d为图5b所示第二导电层所在平面的示意图。
示例性的，如图5b所示，显示基板还包括在衬底基板1上设置的第一绝缘层31；设置在第一绝缘层31背离衬底基板1一侧的半导体层ACT(如图6a所示)；设置在半导体层ACT背离第一绝缘层31一侧的第二绝缘层32；设置在第二绝缘层32背离半导体层ACT一侧的第一导电层41(如图6b所示)；设置在第一导电层41背离第二绝缘层32一侧的第三绝缘层33；设置在第三绝缘层33背离第一导电层41一侧的第二导电层42(如图6c和图6d所示)。第一晶体管T1的栅极T14和第二晶体管T2的栅极T24均位于第一导电层41；第一晶体管T1的有源层T13(包括复用为第一晶体管T1的第二极T12的第二接触部13b)和第二晶体管T2的有源层T23(包括复用为第二晶体管T2的第一极T21的第三接触部23a)均位于半导体层ACT；第一晶体管T1的第一极T11和第二晶体管T2的第二极T22均位于第二导电层42。
在一些实施例中，如图5a所示，第一沟道部13c、连接为一体的第二接触部13b与第三接触部23a，以及第二沟道部23c所构成的图案在衬底基板1上的正投影的轮廓形状为U型。
在一些实施例中，图7为本公开实施例提供的多个像素单元的俯视平面图，如图7所示，第一电极22为像素电极ITO；连接为一体的第二接触部13b与第三接触部23a在衬底基板1上的正投影，与至少一个像素电极ITO在衬底基板1上的正投影部分重叠。
示例性的，有源层的为透光层，像素电极ITO正投影对应区域为显示透 光区，因此有源层的接触部与像素电极ITO之间的正投影存在交叠，不影响显示发光。通过连接为一体的第二接触部13b与第三接触部23a在衬底基板1上的正投影，与至少一个像素电极ITO在衬底基板1上的正投影部分重叠，减小了单个像素单元2的布局空间，从而提高分辨率。
在一些实施例中，如图7所示，其示出了沿列方向相邻设置的两像素单元2，其中一个像素单元2中连接为一体的第二接触部13b与第三接触部23a在衬底基板1上的正投影，与另一个像素电极ITO在衬底基板1上的正投影部分重叠。
当然，还可以沿行方向相邻设置的两像素单元2，其中一个像素单元2中连接为一体的第二接触部13b与第三接触部23a在衬底基板1上的正投影，与另一个像素电极ITO在衬底基板1上的正投影部分重叠。
在一些实施例中，如图7所示，显示基板还包括数据线Data。数据线Data与第一晶体管T1的第一极T11电连接。数据线Data在第一晶体管T1的有源层T13上的正投影，沿第一接触部13a指向第二接触部13b的方向(也即与Y方向相反的方向)，贯穿第一晶体管T1的有源层T13，且数据线Data在第一晶体管T1的有源层T13上的正投影的轮廓边缘与第一晶体管T1的有源层T13边缘在数据线Data的宽度方向X上存在一定距离。通过本实施例的结构设置，减小了单个像素单元2的布局空间，从而提高分辨率。
在此基础上，结合像素电极ITO的布局结构，像素电极ITO在连接为一体的第二接触部13b与第三接触部23a上的正投影不落入数据线Data在有源层上的正投影，以进一步提高像素分辨率。
图8a为第一子孔所在平面的示意图，图8b为第二电极所在平面的示意图，图8c为第二子孔所在平面的示意图，图8d为第一电极所在平面的示意图。
在一些实施例中，如图15j和8b所示，像素单元2还包括第二电极23，第二电极23位于像素电极ITO靠近衬底基板1的一侧。第二电极23为公共电极。
在一些实施例中，如图8d所示，像素电极ITO为狭缝电极；公共电极为板状电极。像素电极ITO通过第三过孔via3与辅助部件6电连接，辅助部件6通过和第二过孔via2与第四接触部23b电连接。如图8a和图8c所示，第三过孔via3包括贯穿平坦化层342的第一子孔via31，以及贯穿金属保护层341的第二子孔via32。像素电极ITO依次通过第一子孔via31和第二子孔via32与辅助部件6电连接。
在一些实施例中，图9a为本公开实施例提供的另一种顶栅型结构的晶体管的结构示意图，图9b为图9a所示结构BB方向的截面图，如图9a和图9b所示，第一晶体管T1的栅极T14和第二晶体管T2的栅极T24同层设置；第一晶体管T1的有源层T13和第二晶体管T2的有源层T23同层设置；第一晶体管T1的第一极T11和第二极，与第二晶体管T2的第一极T21和第二极同层设置；第一晶体管T1的栅极T14位于有源层背离衬底基板1的一侧；第一晶体管T1的第一极T11和第二极位于栅极背离有源层的一侧；第一晶体管T1的有源层T13包括第一接触部13a和第二接触部13b，以及位于第一接触部13a和第二接触部13b之间的第一沟道部13c；第二晶体管T2的有源层T23包括第三接触部23a和第四接触部23b，以及位于第三接触部23a和第四接触部23b之间的第二沟道部23c。
其中，第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b均是对有源层进行导体化后形成的导电部，该导电部的导电性能高于第一沟道部13c的导电性能(也高于第二沟道部23c的导电性能)，导电部的导电性能低于金属电极。具体导体化工艺，例如可以选用He、Ar、H2、NH3等气体(包含混合气体)的等离子体进行处理，进行导体化掺杂，形成第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b。
第一晶体管T1的第二极T12和第二晶体管T2的第一极T21连接为一体结构，且第一晶体管T1的第二极T12通过第四过孔Via4与第二接触部13b电连接，第二晶体管T2的第一极T21通过第五过孔Via5与第三接触部23a电连接。第一晶体管T1的第一极T11通过第一过孔Via1，分别第一接触部13a和数据线Data电连接。第二晶体管的第二极T22，通过第二过孔 Via2分别与第四接触部23b和辅助部件6的第五部分61电连接。
图9b所示顶栅结构的晶体管与图5b所示顶栅结构的晶体管的串联方式不同，图9b所示顶栅结构的晶体管，相比图5b所示顶栅结构的晶体管，采用金属电极(连接为一体结构的第一晶体管T1的第二极T12和第二晶体管T2的第一极T21)实现串联，由于金属电极的导电性能高于第二接触部13b和第三接触部23a导体化后的导电性能，因此采用图9b所示的顶栅结构，器件稳定性更高。
示例性的，如图9b所示，显示基板还包括在衬底基板1上设置的第一绝缘层31；设置在第一绝缘层31背离衬底基板1一侧的半导体层ACT；设置在半导体层ACT背离第一绝缘层31一侧的第二绝缘层32；设置在第二绝缘层32背离半导体层ACT一侧的第一导电层41；设置在第一导电层41背离第二绝缘层32一侧的第三绝缘层33；设置在第三绝缘层33背离第一导电层41一侧的第二导电层42。第一晶体管T1的栅极T14和第二晶体管T2的栅极T24均位于第一导电层41；第一晶体管T1的有源层T13和第二晶体管T2的有源层T23均位于半导体层ACT；第一晶体管T1的第一极T11和第二极T12，以及第二晶体管T2的第一极T21和第二极T22均位于第二导电层42。
示例性的，如图9b所示，第一绝缘层31可以是缓冲绝缘层，缓冲绝缘层可以设置单层结构，采用SiOx(x>0)材料；又或者，缓冲绝缘层可以设置为复合膜层结构，采用复合膜层SiN/SiOx(x>0)材料。
示例性的，如图9b所示，第一绝缘层31可以是设置在遮光层50和半导体层ACT之间的介质层，除去本身的遮光作用外，还会产生其他影响：一方面是电性影响；遮光层50是导电的，对于Floating遮光层50的器件会感生电荷使晶体管提前开启，阈值电压Vth减小，第一绝缘层31越薄影响越大，对于连接栅极的遮光层器件，需要减薄第一绝缘层31提供较高的Ion能力，综合来说电性需求适中的第一绝缘层31厚度。另一方面是制程覆盖性影响；第一绝缘层31需要一定的厚度确保隔绝性，防止有源层在遮光层50边缘发生断裂或短路，设定第一绝缘层31的厚度在200nm～500nm之间。
示例性的，如图9b所示，第二绝缘层32可以是栅极绝缘层，栅极绝缘层的材料一般可以采用SiOx(x>0)材料。
示例性的，如图9b所示，与第一绝缘层31不同的是，第二绝缘层32存在于第一导电层41和半导体层ACT之间，对于电性来说第二绝缘层32越薄Ion越高；另外，由于顶栅型结构的制程上不需要第二绝缘层32做覆盖保护，且考虑工艺能力，防止膜层过薄发生电性击穿，设定第二绝缘层32的厚度在100nm～300nm之间。示例性的，如图9b所示，第一导电层41可以设置单层结构，采用Al或Cu等材料。又或者，第一导电层41可以设置为复合膜层结构，包括缓冲层和主体导电层，其中缓冲层的材料可以采用Ti系合金材料或Mo系合金材料，主体导电层的材料可以采用Al或Cu等材料。又或者，第一导电层41可以设置单层结构，采用Al或Cu中添加Ti系合金材料或Mo系合金材料等。
示例性的，如图9b所示，第三绝缘层33是中间介电层，中间介电层可以设置单层结构，采用SiOx(x>0)材料；又或者，中间介电层也可以设置为复合膜层结构，采用复合膜层SiN/SiOx(x>0)材料。
示例性的，如图9b所示，第三绝缘层33在器件纵向剖面上起隔断栅极和源/漏极的作用，二者之间需要一定的厚度来防止出现短路不良以及降低金属之间的电容大小，防止电信号之间的拉载；过厚的中间介质层厚度不利于工程接触的稳定性，因此设定第三绝缘层33的厚度在300nm～600nm之间。
示例性的，如图9b所示，第二导电层42的材料为金属。
示例性的，如图16j和8a～8d所示，图9b所示的顶栅型结构与像素电极ITO连接结构，如图16j和8a～8d所示。像素电极ITO通过第三过孔via3与辅助部件6电连接，辅助部件6通过和第二过孔via2与第四接触部23b电连接。如图8a和图8c所示，第三过孔via3包括贯穿平坦化层342的第一子孔via31，以及贯穿金属保护层341的第二子孔via32。像素电极ITO依次通过第一子孔via31和第二子孔via32与辅助部件6电连接。
图10为遮光层所在平面的俯视图。无论是图5b所示的顶栅型结构，还 是图9b所示的顶栅型结构，均包括遮光层50。在一些实施例中，如图5b、图9b和图10所示，显示基板还包括设置在像素单元2靠近衬底基板1的遮光层50。
示例性的，遮光层50可以设置复合膜层结构，采用复合膜层Mo系合金/Cu材料，或者复合膜层Mo系合金/Al材料。
如图5a或9a所示，遮光层50在衬底基板1上的正投影至少覆盖，第一晶体管T1的有源层T13的第一沟道部13c和第二晶体管T2的有源层T23的第二沟道部23c在衬底基板1上的正投影。
本实施例通过设置遮光层50遮挡背光源射向第一沟道部13c和第二沟道部23c的光线，这样可以减少第一接触部13a(或第三接触部23a)因光照激发产生的电子空穴对数量，从而减少在保持阶段向第二接触部13b(或第四接触部23b)移动的电子数量，进而降低了光照漏电流，改善了因漏电流导致的闪烁问题。
在一些实施例中，图11为本公开实施例提供的一种示例性的遮光层的平面俯视图，如图11所示，遮光层50在衬底基板1上的正投影的轮廓边缘，和第一沟道部13c在衬底基板1上的正投影的轮廓边缘之间具有最大第一间距；遮光层50在衬底基板1上的正投影的轮廓边缘和，第二沟道部23c在衬底基板1上的正投影的轮廓边缘之间具有最大第二间距；最大第一间距和/或最大第二间距的范围在4μm～6μm。
示例性的，如图11所示，在第一方向X上，遮光层50在衬底基板1上的正投影的轮廓边缘，和第一沟道部13c在衬底基板1上的正投影的轮廓边缘之间具有第一间距L1，第一间距L1的范围在4μm～6μm。由于第一接触部13a指向第二接触部13b的方向上为电流流动方向(也即与Y方向相反的方向)，因此，为了避免在第一沟道部13c沿第一方向X相对的侧面部分形成电流通路此处遮光层50在第一方向X上的宽度设置稍大一些，确保在第一方向X上第一沟道部13c不被光照影响，从而确保第一晶体管T1的稳定性。同理，在第一方向X上，遮光层50在衬底基板1上的正投影的轮廓 边缘，和第二沟道部23c在衬底基板1上的正投影的轮廓边缘之间具有第二间距L2，第二间距L2的范围在4μm～6μm。由于第三接触部23a指向第四接触部23b的方向上为电流流动方向，也即第二方向Y，因此，为了避免在第二沟道部23c沿第一方向X相对的侧面部分形成电流通路，此处遮光层50在第一方向X上的宽度设置稍大一些，确保在第一方向X上第二沟道部23c不被光照影响，从而确保第二晶体管T2的稳定性。
示例性的，如图11所示，在第二方向上，遮光层50在衬底基板1上的正投影的轮廓边缘，和第一沟道部13c在衬底基板1上的正投影的轮廓边缘之间具有第三间距L3，第三间距L3的范围在0～4μm。在第二方向Y上，遮光层50在衬底基板1上的正投影的轮廓边缘，和第二沟道部23c在衬底基板1上的正投影的轮廓边缘之间具有第四间距L4，第四间距L4的范围在0～4μm。由于遮光层50不透光，因此，遮光层50覆盖面积越小越好；然而，为了确保器件的稳定性，遮光层50覆盖面积越大越好。基于此，充分考虑到像素规格和器件稳定性的影响，此处遮光层50在第二方向Y上的宽度设置稍小一些，以提高透光率。
在一些实施例中，如图5a或图9a所示，位于同一行的像素单元2电连接同一条栅线Gate；栅线Gate用作第一晶体管T1的栅极T14和第二晶体管T2的栅极T24。
本实施例栅线Gate复用为晶体管栅极，这种采用面内走线的设置方式，用以实现窄边框。
图12a为图9b所示双NMOS正常工作状态(-1.5V)的晶体管器件性能测试结果，图12b为图9b所示双NMOS负偏压状态(-8V)的晶体管器件性能测试结果，其中横坐标Vg表示第一晶体管T1和第二晶体管T2的栅极T24(也即栅线Gate)电压，纵坐标Ids表示第一晶体管T1的第一极T11(也即漏极)电流，Vth表示阈值电压，01表示图9b所示双NMOS结构的曲线，02表示单NMOS结构的曲线，如图9a和9b可知，双NMOS相比单NMOS无论是在正常工作状态，还是负偏压状态下，关态电流都相对较小，阈值电压相对较大，因此，本公开实施例相比现有技术能够有效改善器件整体的漏 电问题，以及漏电所造成的显示产品沙粒亮点(Mura)问题。
在一些实施例中，第一晶体管T1和第二晶体管T2可以采用底栅型结构的晶体管。图13a为本公开实施例提供的一种底栅型结构的晶体管的结构示意图，图13b为图13a所示结构CC方向的截面图，如图13a和图13b所示，第一晶体管T1的栅极T14和第二晶体管T2的栅极T24同层设置；第一晶体管T1的有源层T13和第二晶体管T2的有源层T23同层设置；第一晶体管T1的第一极T11，与第二晶体管T2的第二极T22同层设置；第一晶体管T1的栅极T14位于有源层靠近衬底基板1的一侧；第一晶体管T1的第一极T11位于有源层T13背离栅极T14的一侧；第一晶体管T1的有源层T13包括第一接触部13a和第二接触部13b，其中，第二接触部13b复用为第一晶体管T1的第一沟道部13c；第二晶体管T2的有源层T23包括第三接触部23a和第四接触部23b，其中，第三接触部23a复用为第二晶体管T2的第二沟道部23c。
其中，第一接触部13a和第四接触部23b均是对有源层进行导体化后形成的导电部，该导电部的导电性能高于第一沟道部13c的导电性能(也高于第二沟道部23c的导电性能)，导电部的导电性能低于金属电极。具体导体化工艺，例如可以选用He、Ar、H2、NH3等气体(包含混合气体)的等离子体进行处理，进行导体化掺杂，形成第一接触部13a和第四接触部23b。
如图13a所示，第二接触部13b与第三接触部23a连接为一体结构。
如图13a所示，数据线Date复用为第一晶体管T1的第一极T11。第二晶体管T2的第二极T22通过第三过孔Via3与第一电极22电连接。
本公开实施例无论是底栅型结构的晶体管，还是顶栅型结构的晶体管，均可以采用连接为一体的第二接触部13b与第三接触部23a，实现双晶体管串联。
底栅型结构的晶体管相比于顶栅型结构的晶体管，能够将有源层靠近衬底基板1一侧的栅极复用为有源层的光学保护膜，能够防止背光源发出的光照射到有源层所产生载流子破坏有源层的电学特性，因此底栅型结构的晶体 管相比顶栅型结构的晶体管的器件性能更稳定。另外，本实施例第二接触部13b与第三接触部23a连接为一体结构，也即第一沟道部13c和第二沟道部23c连接为一体结构，增加了晶体管的沟道长度，降低出现导体化情况发生。
示例性的，如图13b所示，显示基板还包括在衬底基板1上设置的第一导电层41；设置在第一导电层41背离衬底基板1一侧的第一绝缘层31；设置在第一绝缘层31背离第一导电层41一侧的半导体层ACT；设置在半导体层ACT背离第一绝缘层31一侧的第二导电层42；设置在第二导电层42背离半导体层ACT一侧的第二绝缘层32。第一晶体管T1的栅极T14和第二晶体管T2的栅极T24均位于第一导电层41；第一晶体管T1的有源层T13(包括复用为第一晶体管T1的第二极T12的第二接触部13b)和第二晶体管T2的有源层T23(包括复用为第二晶体管T2的第一极T21的第三接触部23a)均位于半导体层ACT；第一晶体管T1的第一极T11和第二晶体管T2的第二极T22均位于第二导电层42。
在一些实施例中，图14a为本公开实施例提供的另一种底栅型结构的晶体管的结构示意图，图14b为图14a所示结构DD方向的截面图，如图14a和图14b所示，第一晶体管T1的栅极T14和第二晶体管T2的栅极T24同层设置；第一晶体管T1的有源层T13和第二晶体管T2的有源层T23同层设置；第一晶体管T1的第一极T11和第二极T12，与第二晶体管T2的第一极T21和第二极T22同层设置；第一晶体管T1的栅极T14位于有源层靠近衬底基板1的一侧；第一晶体管T1的第一极T11和第二极T12位于有源层背离栅极的一侧；第一晶体管T1的有源层T13包括第一接触部13a和第二接触部13b，以及位于第一接触部13a和第二接触部13b之间的第一沟道部13c；第二晶体管T2的有源层T23包括第三接触部23a和第四接触部23b，以及位于第三接触部23a和第四接触部23b之间的第二沟道部23c。
其中，第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b均是对有源层进行导体化后形成的导电部，该导电部的导电性能高于第一沟道部13c的导电性能(也高于第二沟道部23c的导电性能)，导电部的导电性能低于金属电极。具体导体化工艺，例如可以选用He、Ar、H2、 NH3等气体(包含混合气体)的等离子体进行处理，进行导体化掺杂，形成第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b。
如图14a所示，第一晶体管T1的第二极T12和第二晶体管T2的第一极T21连接为一体结构，且第一晶体管T1的第二极T12与第一晶体管T1的第二接触部13b电连接；第二晶体管T2的第一极T21与第二晶体管T2的第三接触部23a电连接。
如图14a所示，数据线Date复用为第一晶体管T1的第一极T11。第二晶体管T2的第二极T22通过第三过孔Via3与第一电极22电连接。
图14b所示底栅结构的晶体管与图13b所示底栅结构的晶体管的串联方式不同，图14b所示底栅结构的晶体管，相比图13b所示底栅结构的晶体管，采用金属电极(连接为一体结构的第一晶体管T1的第二极T12和第二晶体管T2的第一极T21)实现串联，由于金属电极的导电性能高于第二接触部13b和第三接触部23a导体化后的导电性能，因此采用图14b所示的底栅结构，器件稳定性更高。另外，本实施例将两晶体管串联，若其中一个发生导体化关断异常，另一个还可以确保正常工作。
示例性的，如图14b所示，显示基板还包括在衬底上设置的第一导电层41；设置在第一导电层41背离衬底基板1一侧的第一绝缘层31；设置在第一绝缘层31背离第一导电层41一侧的半导体层ACT；设置在半导体层ACT背离第一绝缘层31一侧的第二导电层42；设置在第二导电层42背离半导体层ACT一侧的第二绝缘层32。第一晶体管T1的栅极T14和第二晶体管T2的栅极T24均位于第一导电层41；第一晶体管T1的有源层T13和第二晶体管T2的有源层T23均位于半导体层ACT；第一晶体管T1的第一极T11和第二极，以及第二晶体管T2的第一极T21和第二极均位于第二导电层42。
示例性的，第一导电层41可以设置单层结构，采用Al或Cu等材料。又或者，第一导电层41可以设置为复合膜层结构，包括缓冲层和主体导电层，其中缓冲层的材料可以采用Ti系合金材料或Mo系合金材料，主体导电层的材料可以采用Al或Cu等材料。又或者，第一导电层41可以设置单 层结构，采用Al或Cu中添加Ti系合金材料或Mo系合金材料等。
示例性的，如图13b或图14b所示，第一绝缘层31可以是栅极绝缘层，栅极绝缘层的材料一般可以采用SiOx(x>0)材料。
示例性的，如图13b或图14b所示，在对栅极的覆盖性及电容减小这一需求上，由于底栅型结构的制程上需要作为栅极绝缘层的第一绝缘层31做覆盖保护，且作为栅极绝缘层的第一绝缘层31的厚度影响电容，因此相比顶栅型结构，作为栅极绝缘层的第一绝缘层31的厚度较大。另外，在对Ion这一需求上，作为栅极绝缘层的第一绝缘层31越薄Ion越高，结合上述两种需求，第一绝缘层31的厚度可以在300nm～500nm。示例性的，如图13b或图14b所示，第二导电层42的材料为金属。
示例性的，如图13b或图14b所示，第二绝缘层32是沟道保护层，该沟道保护层的材料一般可以采用SiOx(x>0)材料，第二绝缘层32的厚度不低于100nm。
示例性的，如图13b或图14b所示，第二绝缘层32是沟道保护层，该沟道保护层的材料一般可以采用SiN和SiOx(x>0)的复合膜层，第二绝缘层32的整体厚度在200nm～400nm之间。另外，对于第二绝缘层32的厚度的选择，非仅是对第二导电层42的厚度覆盖需求，还有对TFT特性的防护需求，例如SiOx(x>0)膜层的厚度需求确保器件不发生导体化，以及采用SiN膜层阻隔有机膜层水汽的影响(SiN膜层的水汽阻隔能力优于SiOx(x>0)膜层)等等。
在一些实施例中，如图13b或图14b所示，位于同一行的像素单元2电连接同一条栅线Gate；栅线Gate用作第一晶体管T1的栅极T14和第二晶体管T2的栅极T24；栅线Gate为复合膜层，包括依次设置在衬底基板1上的缓冲层和主体导电层。其中，缓冲层的材料可以采用Ti系合金材料或Mo系合金材料，主体导电层的材料可以采用Al或Cu等材料。
在一些实施例中，如图17i、18i和8b所示，像素单元2还包括第二电极23，第二电极23位于像素电极ITO靠近衬底基板1的一侧。第二电极23 为公共电极。
在一些实施例中，如图8d所示，像素电极ITO为狭缝电极；公共电极为板状电极。像素电极ITO通过第三过孔via3与第二晶体管T2的第二极T22电连接。如图8a和图8c所示，第三过孔via3包括贯穿平坦化层342的第一子孔via31，以及贯穿金属保护层341的第二子孔via32。像素电极ITO依次通过第一子孔via31和第二子孔via32与第二晶体管T2的第二极T22电连接。
另外，本公开实施例还提供了一种显示装置，其包括上述实施例中任一项的显示基板。该显示装置例如可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、车载设备等任何具有显示功能的产品。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
另外，本公开实施例还提供了一种显示基板的制备方法，用于上述各实施例中任一项的显示基板的制备。
该方法具体包括：提供一衬底基板1；在衬底基板1上形成呈阵列排布的多个像素单元2。其中，形成像素单元2的步骤至少包括：依次在衬底基板1上形成像素电路21和第一电极22。像素电路21至少包括第一晶体管T1和第二晶体管T2；第一晶体管T1的第二极T12和第二晶体管T2的第一极T21电连接，第二晶体管T2的第二极T22与第一电极22电连接。第一晶体管T1的有源层T13和第二晶体管T2的有源层T23的材料均为金属氧化物半导体材料。
在一些实施例中，图15a～图15j为本公开实施例提供的图5b所示显示基板的制备流程示意图，具体包括如下步骤S11～S111，其中：
S11、提供一衬底基板1。
本步骤中，衬底基板1为玻璃基板。
S12、如图15a所示，在衬底基板1上形成遮光层50。
S13、如图15b所示，在遮光层50背离衬底基板1的一侧形成第一绝缘 层31。
S14、如图15c所示，在第一绝缘层31背离遮光层50的一侧形成半导体层ACT。
具体地，沉积半导体层ACT的材料，半导体层ACT的材料选自高迁移率氧化物材料如IGZTO、IGO等；然后进行常规退火及图形化工艺。
S15、如图15d所示，在半导体层ACT背离第一绝缘层31的一侧形成第二绝缘层32和第一导电层41。
第二绝缘层32为栅极绝缘层，第一导电层41包括栅极，或者复用为栅极的栅线Gate。
依次沉积栅极绝缘层的材料和第一导电层41的材料；之后，进行栅极光刻及刻蚀，并以栅极为掩膜对栅极绝缘层进行刻蚀，裸露出半导体层ACT后进行导体化，导体化工艺可选用He、Ar、H2、NH3等气体(包含混合气体)的等离子体(Plasma)进行处理。
需要说明的是，这里导体化后的第二接触部13b与导体化后的第三接触部23a直接连接。
S16、如图15e所示，在步骤S15的基础上继续形成第三绝缘层33。
沉积第二绝缘层32的材料，之后进行中间介电层光刻以及刻蚀，形成到有源层的第一接触部13a的第一过孔Via1和第四接触部23b的第二过孔Via2。
S17、如图15f所示，在第三绝缘层33背离衬底基板1的一侧形成第二导电层42。
第二导电层42的材料为金属材料，该第二导电层42通过贯穿第三绝缘层33的第一过孔Via1和第二过孔Via2分别与第一接触部13a和第四接触部23b电连接。第二接触部13b复用为第一晶体管T1的第二极T12，第三接触部23a复用为第二晶体管T2的第一极T21。
S18、如图15g所示，在第二导电层42背离第三绝缘层33的一侧形成 第四绝缘层34。
第四绝缘层34可以是金属保护层341和平坦化层342。
依次沉积金属保护层341和平坦化层342的材料；之后对平坦化层342进行有机材料光刻，形成第一子孔Via31。
S19、如图15h所示，在第四绝缘层34背离第三绝缘层33的一侧形成第二电极23。
第二电极23为公共电极。
S110、如图15i所示，在第二电极23背离第四绝缘层34的一侧形成第五绝缘层35。
第五绝缘层35为钝化层。
沉积钝化层的材料，之后进行钝化层光刻以及刻蚀，形成到第二晶体管T2的第二极T22的第二子孔Via32。
S111、如图15j所示，在第五绝缘层35背离第二电极23的一侧形成像素电极ITO。
像素电极ITO为狭缝电极。像素电极ITO具有连接部，该连接部通过贯穿第三过孔Via3连接至辅助部件6(也即第二晶体管T2的第二极T22)；辅助部件6通过贯穿第二过孔Via2连接至第四接触部23b。
在一些实施例中，图16a～图16j为本公开实施例提供的图9b所示显示基板的制备流程示意图，具体包括如下步骤S21～S211，其中：
S21、提供一衬底基板1。
本步骤中，衬底基板1为玻璃基板。
S22、如图16a所示，在衬底基板1上形成遮光层50。
S23、如图16b所示，在遮光层50背离衬底基板1的一侧形成第一绝缘层31。
S24、如图16c所示，在第一绝缘层31背离遮光层50的一侧形成半导体层ACT。
具体地，沉积半导体层ACT的材料，半导体层ACT的材料选自高迁移率氧化物材料如IGZTO、IGO等；然后进行常规退火及图形化工艺。
S25、如图16d所示，在半导体层ACT背离第一绝缘层31的一侧形成第二绝缘层32和第一导电层41。
第二绝缘层32为栅极绝缘层，第一导电层41包括栅极，或者复用为栅极的栅线Gate。
依次沉积栅极绝缘层的材料和第一导电层41的材料；之后，进行栅极光刻及刻蚀，并以栅极为掩膜对栅极绝缘层进行刻蚀，裸露出半导体层ACT后进行导体化，导体化工艺可选用He、Ar、H2、NH3等气体(包含混合气体)的等离子体(Plasma)进行处理。
S26、如图16e所示，在步骤S25的基础上继续形成第三绝缘层33。
沉积第二绝缘层32的材料，之后进行中间介电层光刻以及刻蚀，形成到有源层的第一接触部13a的第一过孔Via1、到第二接触部13b的第四过孔Via4、到第三接触部23a的第五过孔Via5和到第四接触部23b的第二过Via2。
S27、如图16f所示，在第三绝缘层33背离衬底基板1的一侧形成第二导电层42。
第二导电层42的材料为源/漏金属，该源/漏金属中的第一晶体管T1的漏极与通过贯穿第三绝缘层33的第一过孔Via1与第一接触部13a电连接。第一晶体管T1的源极与第二晶体管T2的漏极电连接，且分别通过第四过孔Via4和第五过Via5，各自与第二接触部13b和第三接触部23a电连接。第二晶体管T2的源极通过一个第二过孔Via2与第四接触部23b电连接。辅助部件6复用为第二晶体管T2的源极。辅助部件6通过第三过孔
S28、如图16g所示，在第二导电层42背离第三绝缘层33的一侧形成第四绝缘层34。
第四绝缘层34是平坦化层。
沉积平坦化层的材料，之后进行有机材料光刻，形成第一子孔Via31。
S29、如图16h所示，在第四绝缘层34背离第三绝缘层33的一侧形成第二电极23。
第二电极23为公共电极。
S210、如图16i所示，在第二电极23背离第四绝缘层34的一侧形成第五绝缘层35。
第五绝缘层35为钝化层。
沉积钝化层的材料，之后进行钝化层光刻以及刻蚀，形成到第二晶体管T2的第二极T22的第二子孔Via32。
S211、如图16j所示，在第五绝缘层35背离第二电极23的一侧形成像素电极ITO。
像素电极ITO为狭缝电极。像素电极ITO具有连接部，该连接部通过贯穿第三过孔Via3连接至辅助部件6(也即第二晶体管T2的第二极T22)；辅助部件6通过贯穿第二过孔Via2连接至第四接触部23b。
在一些实施例中，图17a～图17i为本公开实施例提供的图13b所示显示基板的制备流程示意图，具体包括如下步骤S31～S310，其中：
S31、提供一衬底基板1。
本步骤中，衬底基板1为玻璃基板。
S32、如图17a所示，在衬底基板1上形成第一导电层41。
第一导电层41为复合膜层，包括依次设置在衬底基板1上的缓冲层和主体导电层。其中，缓冲层的材料可以采用Ti系合金材料或Mo系合金材料，主体导电层的材料可以采用Al或Cu等材料。
第一导电层41包括复用为第一晶体管T1栅极和第二晶体管T2栅极的栅线Gate。
S33、如图17b所示，在第一导电层41背离衬底基板1的一侧形成第一绝缘层31。
S34、如图17c所示，在第一绝缘层31背离遮光层50的一侧形成半导 体层ACT。
具体地，沉积半导体层ACT的材料，半导体层ACT的材料选自高迁移率氧化物材料如IGZTO、IGO等；然后进行常规退火及图形化工艺。
采用掩膜版对半导体层ACT进行导体化，导体化工艺可选用He、Ar、H2、NH3等气体(包含混合气体)的等离子体(Plasma)进行处理，形成有源层的第一接触部13a和第四接触部23b。
S35、如图17d所示，在半导体层ACT背离第一绝缘层31的一侧形成第二导电层42。
第二导电层42包括第一晶体管T1的第一极T11，以及第二晶体管T2的第二极T22。第一晶体管T1的第一极T11与第一接触部13a直接连接，第二接触部13b复用为第一晶体管T1的第一沟道部13c，第三接触部23a复用为第二晶体管T2的第二沟道部23c。第二接触部13b与第三接触部23a为连接为一体结构，第二晶体管T2的第二极T22与第四接触部23b直接连接。
为防止有源层(IGZO)被刻蚀液过多损伤，优选可以采用Cu叠层及双氧水系刻蚀药液完成第二导电层42的制程。
S36、如图17e所示，在第二导电层42背离第一绝缘层31的一侧形成第二绝缘层32。
该第二绝缘层32是沟道保护层。
S37、如图17f所示，在第二绝缘层32背离第二导电层42的一侧形成第三绝缘层33。
第三绝缘层33为平坦化层。
沉积平坦化层的材料，之后进行有机材料光刻，形成第一子孔Via31。
S38、如图17g所示，在第三绝缘层33背离第二绝缘层32的一侧形成第二电极23。
第二电极23为公共电极。
S39、如图17h所示，在第二电极23背离第san绝缘层的一侧形成第四绝缘层34。
第四绝缘层34为钝化层。
沉积钝化层的材料，之后进行钝化层光刻以及刻蚀，形成到第二晶体管T2的第二极T22的第二子孔Via32。
S310、如图17i所示，在第四绝缘层34背离第二电极23的一侧形成像素电极ITO。
像素电极ITO为狭缝电极。像素电极ITO具有连接部，该连接部通过贯穿第三过孔Via3连接至辅助部件6(也即第二晶体管T2的第二极T22)；辅助部件6直接连接至第四接触部23b。
在一些实施例中，图18a～图18i为本公开实施例提供的图10所示显示基板的制备流程示意图，具体包括如下步骤S41～S410，其中：
S41、提供一衬底基板1。
本步骤中，衬底基板1为玻璃基板。
S42、如图18a所示，在衬底基板1上形成第一导电层41。
第一导电层41为复合膜层，包括依次设置在衬底基板1上的缓冲层和主体导电层。其中，缓冲层的材料可以采用Ti系合金材料或Mo系合金材料，主体导电层的材料可以采用Al或Cu等材料。
第一导电层41包括复用为第一晶体管T1栅极和第二晶体管T2栅极的栅线Gate。
S43、如图18b所示，在第一导电层41背离衬底基板1的一侧形成第一绝缘层31。
S44、如图18c所示，在第一绝缘层31背离遮光层50的一侧形成半导体层ACT。
具体地，沉积半导体层ACT的材料，半导体层ACT的材料选自高迁移率氧化物材料如IGZTO、IGO等；然后进行常规退火及图形化工艺。
采用掩膜版对半导体层ACT进行导体化，导体化工艺可选用He、Ar、H2、NH3等气体(包含混合气体)的等离子体(Plasma)进行处理，形成有源层的第一接触部13a、第二接触部13b、第三接触部23a和第四接触部23b。
S45、如图18d所示，在半导体层ACT背离第一绝缘层31的一侧形成第二导电层42。
第二导电层42包括第一晶体管T1的第一极T11和第二极，以及第二晶体管T2的第一极T21和第二极。第一晶体管T1的第二极T12和第二晶体管T2的第一极T21为一体结构。第一晶体管T1的第一极T11与第一接触部13a直接连接，第一晶体管T1的第二极T12与第二接触部13b直接连接，第二晶体管T2的第一极T21与第三接触部23a直接连接，第二晶体管T2的第二极T22与第四接触部23b直接连接。
为防止有源层(IGZO)被刻蚀液过多损伤，优选可以采用Cu叠层及双氧水系刻蚀药液完成第二导电层42的制程。
S46、如图18e所示，在第二导电层42背离第一绝缘层31的一侧形成第二绝缘层32。
该第二绝缘层32是沟道保护层。
S47、如图18f所示，在第二绝缘层32背离第二导电层42的一侧形成第三绝缘层33。
第三绝缘层33为平坦化层。
沉积平坦化层的材料，之后进行有机材料光刻，形成第一子孔Via31。
S48、如图18g所示，在第三绝缘层33背离第二绝缘层32的一侧形成第二电极23。
第二电极23为公共电极。
S49、如图18h所示，在第二电极23背离第san绝缘层的一侧形成第四绝缘层34。
第四绝缘层34为钝化层。
沉积钝化层的材料，之后进行钝化层光刻以及刻蚀，形成到第二晶体管T2的第二极T22的第二子孔Via32。
S410、如图18i所示，在第四绝缘层34背离第二电极23的一侧形成像素电极ITO。
像素电极ITO为狭缝电极。像素电极ITO具有连接部，该连接部通过贯穿第三过孔Via3连接至辅助部件6(也即第二晶体管T2的第二极T22)；辅助部件6直接连接至第四接触部23b。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (25)

  1. 一种显示基板，其包括衬底基板、以及位于所述衬底基板上的栅线和数据线，所述栅线和所述数据线交叉限定出多个像素单元；所述栅线沿第一方向延伸，所述数据线沿第二方向延伸，所述第一方向和所述第二方向相交；所述像素单元包括第一晶体管和第二晶体管；所述第一晶体管的有源层包括第一接触部和第二接触部，所述第二晶体管的有源层包括第三接触部和第四接触部，所述第一接触部与所述数据线电连接，所述第二接触部与所述第三接触部电连接，所述第四接触部与所述像素单元的第一电极电连接；沿着所述第二方向，所述第一接触部与所述栅线的最大间距不小于所述第四接触部与同一所述栅线的最大间距。
  2. 根据权利要求1所述的显示基板，其中，沿着所述第一方向，所述第一接触部的宽度小于所述第四接触部的宽度。
  3. 根据权利要求1所述的显示基板，其中，所述第一接触部在所述衬底基板的正投影与所述数据线在所述衬底基板的正投影交叠，所述第一接触部包括彼此连接的第一部分和第二部分，所述第一部分与所述数据线电连接，沿着所述第一方向，所述第一部分的宽度大于所述第二部分的宽度。
  4. 根据权利要求3所述的显示基板，其中，所述第四接触部在所述衬底基板的正投影与所述栅线在所述衬底基板的正投影部分交叠，所述第四接触部包括彼此连接的第三部分和第四部分，所述第四部分与所述第一电极电连接，沿着所述第二方向，所述第四部分的最小宽度大于所述第三部分的最小宽度。
  5. 根据权利要求1所述的显示基板，其中，所述第一接触部与所述数据线通过第一过孔电连接，所述第四接触部与所述第一电极通过第二过孔电连接；沿着所述第二方向，所述第一过孔与所述栅线的最小间距大于所述第二过孔与同一栅线的最小间距。
  6. 根据权利要求1所述的显示基板，其中，所述第一接触部与所述数据线通过第一过孔电连接，所述第四接触部与所述第一电极通过第二过孔和 第三过孔电连接；沿着所述第二方向，所述第一过孔与所述栅线的最小间距大于所述第二过孔与同一栅线的最小间距；所述第三过孔与所述栅线的最小间距小于所述第二过孔与同一栅线的最小间距。
  7. 根据权利要求6所述的显示基板，其中，所述像素单元还包括辅助部件；所述辅助部件包括彼此连接的第五部分和第六部分，所述第五部分与所述第四接触部通过所述第二过孔电连接；所述第六部分与所述第一电极通过所述第三过孔电连接。
  8. 根据权利要求7所述的显示基板，其中，所述辅助部件与所述数据线同层设置，且在所述第一方向上，相邻两条所述数据线在与所述第一接触部连接位置之间设置有所述辅助部件。
  9. 根据权利要求1所述的显示基板，其中，所述第一接触部、所述第二接触部、所述第三接触部和所述第四接触部同层设置。
  10. 根据权利要求1所述的显示基板，其中，所述第一晶体管的有源层和/或所述第二晶体管的有源层包括金属氧化物半导体材料。
  11. 根据权利要求10所述的显示基板，其中，所述第一晶体管和第二晶体管的有源层包括层叠设置的多层子层，远离所述衬底基板的子层的迁移率小于靠近所述衬底基板的子层的迁移率。
  12. 根据权利要求1所述的显示基板，其中，所述第一晶体管的栅极位于所述第一晶体管的有源层背离所述衬底基板的一侧；所述第二晶体管的栅极位于所述第二晶体管的有源层背离所述衬底基板的一侧；所述第一晶体管的有源层和所述第二晶体管的有源层同层设置；
    所述数据线复用为所述第一晶体管的第一极；所述第二接触部复用为所述第一晶体管的第二极，所述第三接触部复用为所述第二晶体管的第一极，所述第二接触部与所述第三接触部连接为一体结构。
  13. 根据权利要求12所述的显示基板，其中，所述第一电极为像素电极；连接为一体的所述第二接触部与所述第三接触部在所述衬底基板上的正投影，与至少一个所述像素电极在所述衬底基板上的正投影部分重叠。
  14. 根据权利要求13所述的显示基板，其中，对于相邻的两所述像素单元，其中一个所述像素单元中连接为一体的所述第二接触部与所述第三接触部在所述衬底基板上的正投影，与另一个所述像素单元在所述衬底基板上的正投影部分重叠。
  15. 根据权利要求12所述的显示基板，其中，所述第一晶体管的有源层还包括设置在所述第一接触部和所述第二接触部之间的第一沟道部，所述第二晶体管的有源层还包括设置在所述第三接触部和所述第四接触部之间的第二沟道部；所述第一沟道部、连接为一体的所述第二接触部与所述第三接触部，以及所述第二沟道部所构成的图案在所述衬底基板上的正投影的轮廓形状为U型。
  16. 根据权利要求1所述的显示基板，其中，所述第一晶体管的栅极和所述第二晶体管的栅极同层设置；所述第一晶体管的有源层和所述第二晶体管的有源层同层设置；所述第一晶体管的第一极和第二极，与所述第二晶体管的第一极和第二极同层设置；
    所述第一晶体管的栅极位于所述有源层背离所述衬底基板的一侧；所述第一晶体管的第一极和第二极位于所述栅极背离所述有源层的一侧；
    所述数据线复用为所述第一晶体管的第一极；所述第一晶体管的第二极和所述第二晶体管的第一极连接为一体结构，且所述第一晶体管的第二极通过第四过孔与所述第二接触部电连接，所述第二晶体管的第一极通过第五过孔与所述第三接触部电连接。
  17. 根据权利要求12～16中任一项所述的显示基板，其中，所述显示基板还包括设置在所述像素单元靠近所述衬底基板的遮光层；
    所述第一晶体管的有源层还包括设置在所述第一接触部和所述第二接触部之间的第一沟道部，所述第二晶体管的有源层还包括设置在所述第三接触部和所述第四接触部之间的第二沟道部；
    所述遮光层在所述衬底基板上的正投影至少覆盖，所述第一沟道部和所述第二沟道部在所述衬底基板上的正投影。
  18. 根据权利要求17所述的显示基板，其中，在第一方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘，和所述第一沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第一间距；
    在第一方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘和，所述第二沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第二间距；
    所述第一间距和/或所述第二间距的范围在4μm～6μm。
  19. 根据权利要求17所述的显示基板，其中，在第二方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘，和所述第一沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第三间距；
    在第二方向上，所述遮光层在所述衬底基板上的正投影的轮廓边缘和，所述第二沟道部在所述衬底基板上的正投影的轮廓边缘之间具有第四间距；
    所述第三间距和/或所述第四间距的范围在0～4μm。
  20. 根据权利要求1～16中任一项所述的显示基板，其中，位于同一行的所述像素单元电连接同一条栅线；所述栅线用作所述第一晶体管的栅极和所述第二晶体管的栅极。
  21. 根据权利要求1～16中任一项所述的显示基板，其中，所述第一晶体管的栅极在靠近所述有源层的一侧设置有栅极绝缘层；所述栅极绝缘层的厚度在10nm～30nm之间。
  22. 根据权利要求1所述的显示基板，其中，所述第一晶体管的栅极和所述第二晶体管的栅极同层设置；所述第一晶体管的有源层和所述第二晶体管的有源层同层设置；所述第一晶体管的第一极和第二极，与所述第二晶体管的第一极和第二极同层设置；
    所述第一晶体管的栅极位于所述有源层靠近所述衬底基板的一侧；所述第一晶体管的第一极和第二极位于所述有源层背离所述栅极的一侧；
    所述数据线复用为所述第一晶体管的第一极；所述第一晶体管的第二极和所述第二晶体管的第一极连接为一体结构，且所述第一晶体管的第二极与所述第一晶体管的第二接触部电连接；所述第二晶体管的第一极与所述第二 晶体管的第三接触部电连接。
  23. 根据权利要求22所述的显示基板，其中，位于同一行的所述像素单元电连接同一条栅线；所述栅线用作所述第一晶体管的栅极和所述第二晶体管的栅极；
    所述栅线为复合膜层，包括依次设置在所述衬底基板上的缓冲层和主体导电层。
  24. 根据权利要求22所述的显示基板，其中，所述第一晶体管的栅极在靠近所述有源层的一侧设置有栅极绝缘层；所述栅极绝缘层的厚度在30nm～50nm之间。
  25. 一种显示装置，其中，包括如权利要求1～24中任一项所述的显示基板。
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CN106252363A (zh) * 2016-09-29 2016-12-21 上海中航光电子有限公司 阵列基板、显示面板及显示装置
CN114203738A (zh) * 2021-12-13 2022-03-18 武汉华星光电技术有限公司 一种阵列基板及显示终端
CN115951527A (zh) * 2022-12-29 2023-04-11 苏州清越光电科技股份有限公司 一种显示面板和显示装置

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