WO2025030786A1 - 一种存储器及其读写方法、电子设备 - Google Patents

一种存储器及其读写方法、电子设备 Download PDF

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Publication number
WO2025030786A1
WO2025030786A1 PCT/CN2024/073718 CN2024073718W WO2025030786A1 WO 2025030786 A1 WO2025030786 A1 WO 2025030786A1 CN 2024073718 W CN2024073718 W CN 2024073718W WO 2025030786 A1 WO2025030786 A1 WO 2025030786A1
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line
selection
storage array
transistor
lines
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French (fr)
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戴瑾
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Definitions

  • the present application relates to the field of semiconductor technology, and more specifically, to a memory and a reading and writing method thereof, and an electronic device.
  • Memory is the main medium for data storage.
  • Common memory devices are mostly two-dimensional (2D) memory devices with planar structures.
  • 2D two-dimensional
  • 3D three-dimensional
  • Three-dimensional storage devices can realize the storage and transmission of data in three-dimensional space, which can greatly improve the storage capacity of storage devices, reduce storage costs, improve the integration and storage density of storage devices, and help to achieve the miniaturization of storage devices.
  • the embodiment of the present application provides a memory and a read/write method thereof, and an electronic device, and provides a method for selecting a horizontal word line during a read/write operation.
  • the technical solution provided by the embodiment of the present application is as follows:
  • an embodiment of the present application provides a memory, including:
  • a three-dimensional memory array is located on one side of the substrate, comprising a plurality of memory array layers stacked in a direction perpendicular to the substrate, wherein the memory array layers include memory cells arranged in a two-dimensional array, a plurality of bit lines perpendicular to the substrate, and a plurality of word lines parallel to the substrate, wherein each layer In the storage array layer, a row of storage cells is connected to one word line;
  • Each storage array layer further includes: a selection circuit, a first selection line, a second selection line, a plurality of third selection lines and a plurality of low-level potential terminals;
  • the first selection line and the second selection line are parallel to the substrate, the third selection line is perpendicular to the substrate, and the third selection line is arranged in one-to-one correspondence with the word line;
  • the selection circuit is respectively connected to the word lines, the first selection line, the second selection line, the third selection lines and the low level potential ends;
  • the plurality of selection circuits are used to determine the selected storage array layer based on the level states of the first selection line and the second selection line of the corresponding storage array layer, and to determine the selected word line during read and write operations based on the level state of the third selection line of the selected storage array layer.
  • the plurality of low-level potential ends are a plurality of power lines perpendicular to the substrate;
  • the power lines are arranged in one-to-one correspondence with the word lines;
  • a plurality of word lines stacked and arranged along a direction perpendicular to the substrate correspond to one power line.
  • the low-level potential ends included in all the storage array layers are conductive walls
  • the selection circuit in each storage array layer includes a first sub-selection circuit and a second sub-selection circuit
  • the first sub-selection circuit For each layer of the storage array layer, the first sub-selection circuit is respectively connected to a plurality of the word lines, the first selection line and the third selection line of the same layer of the storage array layer; for the three-dimensional storage array, the first sub-selection circuit of each layer is used to determine the storage array layer in which the word line is connected to the third selection line based on the level state of the first selection line of the corresponding storage array layer, and to determine the selected word line based on the level state of the third selection line of the storage array layer in which the word line is connected to the third selection line;
  • the second sub-selection circuit For each layer of the storage array layer, the second sub-selection circuit is respectively connected to a plurality of the word lines, the second selection line and the low level potential end of the same layer of the storage array layer; For the three-dimensional memory array, the second sub-selection circuit of each layer is used to determine the memory array layer to which the word line is connected to the low-level potential end based on the level state of the second selection line of the corresponding memory array layer;
  • the memory array layer in which the word line is connected to the third selection line is a selected memory array layer, and the memory array layer in which the word line is connected to the low level potential end is an unselected memory array layer.
  • the first sub-selection circuit is located on one side of the word line, and the second sub-selection circuit is located on the same side of the word line;
  • the first sub-selection circuit is located at a first side of the word line
  • the second sub-selection circuit is located at a second side of the word line
  • the first side and the second side are arranged opposite to each other.
  • the first sub-selection circuit includes a plurality of first transistors, and the first transistors are arranged in a one-to-one correspondence with the word lines;
  • a gate of the first transistor is connected to the first selection line, a first electrode of the first transistor is connected to the word line, and a second electrode of the first transistor is connected to the third selection line.
  • the second sub-selection circuit includes a plurality of second transistors, and the second transistors are arranged in a one-to-one correspondence with the word lines;
  • a gate of the second transistor is connected to the second selection line, a first electrode of the second transistor is connected to the word line, and a second electrode of the second transistor is connected to the low level potential end.
  • the first transistor is an N-type transistor
  • the second transistor is an N-type transistor
  • a level state of the first selection line is opposite to a level state of the second selection line
  • the first transistor is a P-type transistor
  • the second transistor is a P-type transistor
  • the level state of the first selection line is opposite to the level state of the second selection line
  • the first transistor is an N-type transistor
  • the second transistor is a P-type transistor
  • the level state of the first selection line is the same as the level state of the second selection line
  • the first transistor is a P-type transistor
  • the second transistor is an N-type transistor
  • a level state of the first selection line is the same as a level state of the second selection line.
  • the storage unit includes a transistor and a capacitor
  • the gate of the transistor is connected to the word line, and the first electrode of the transistor is connected to the bit line.
  • the second electrode of the transistor is connected to one end of the capacitor, and the other end of the capacitor is grounded.
  • the memory includes at least one of the following:
  • the memory cells located in the same column along the extending direction of the bit line share one bit line;
  • a plurality of the word lines stacked and arranged in a direction perpendicular to the substrate correspond to one third selection line;
  • the first electrodes of the transistors are connected to the bit lines in a one-to-one correspondence; or, the first electrodes of two adjacent transistors in a direction perpendicular to the word line are connected to the same bit line.
  • the memory includes a read/write circuit, a number of bit line selection units, and a number of control lines;
  • bit lines are connected to the bit line selection units in a one-to-one correspondence, and the control lines are connected to the bit line selection units in a one-to-one correspondence;
  • the bit line selection unit is used to select the bit line based on the control of the control line, so as to connect the selected bit line to the read/write circuit.
  • the memory includes a plurality of first connection lines and/or a plurality of second connection lines;
  • Each of the first selection lines is connected to a peripheral circuit via one of the first connection lines, the first connection lines are perpendicular to the substrate, and a plurality of the first connection lines are arranged in a staircase manner along a direction perpendicular to the substrate;
  • Each of the second selection lines is connected to the peripheral circuit via a second connection line.
  • the second connection line is perpendicular to the substrate, and a plurality of the second connection lines are arranged in a staircase manner along a direction perpendicular to the substrate.
  • an embodiment of the present application provides an electronic device, comprising a memory as described in any one of the first aspects.
  • an embodiment of the present application provides a method for reading and writing a memory, comprising:
  • Writing operation stage applying a first electrical signal to a first selection line corresponding to the storage array layer to which data is to be written, and applying a second electrical signal to a second selection line corresponding to the storage array layer to which data is to be written, so that the word line of the storage array layer to which data is to be written is connected to the third selection line in a one-to-one correspondence, so as to select the storage array layer to which data is to be written;
  • the write operation stage also includes: applying a second electrical signal to a first selection line corresponding to a storage array layer that does not require data to be written, and applying a first electrical signal to a second selection line that does not require data to be written, so that the word line of the storage array layer that does not require data to be written is connected to the low-level potential end.
  • each storage array layer includes a selection circuit, a first selection line, a second selection line, a third selection line and a low-level potential end
  • the selection circuit is respectively connected to the word line, the first selection line, the second selection line, the third selection line and the low-level potential end
  • the multiple selection circuits are used to determine the selected storage array layer based on the level state of the first selection line and the second selection line of the corresponding storage array layer, and determine the word line selected during the read and write operations based on the level state of the third selection line of the selected storage array layer; therefore, the embodiment of the present application can provide a method for selecting the word line parallel to the substrate direction that needs to be selected during the read and write operations by designing a new peripheral circuit.
  • FIG1 is a schematic diagram of the structure of a k-th storage array layer included in a memory provided in an embodiment of the present application;
  • FIG2 is a schematic diagram of a specific structure of a k-th storage array layer included in a memory provided in an embodiment of the present application;
  • FIG3 is a schematic diagram of the structure of a transistor included in a memory provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of a three-dimensional structure of a memory provided in an embodiment of the present application.
  • FIG5 is a flow chart of a method for reading and writing a memory provided in an embodiment of the present application.
  • 11-storage array layer 12storage unit; 13-selection circuit; 131-first sub-selection circuit; 132-second sub-selection circuit; 14-source electrode; 15-drain electrode; 16-semiconductor layer; 17-gate insulating layer; 18-gate electrode.
  • planar 1T1C one transistor and one capacitor
  • 2D memory devices are restricted in terms of obtaining higher capacitance, lower leakage, and higher integration.
  • the transistors in the integrated circuit can be placed close to each other and can be stacked in multiple layers, saving area in the plane.
  • 3D-DRAM technologies and most 3D memory structures are 2D memory cells placed horizontally and then stacked in multiple layers.
  • some designs use a vertical word line design (i.e., the word line extends in a direction perpendicular to the substrate), and some designs use a horizontal word line design (i.e., the word line extends in a direction parallel to the substrate).
  • the horizontal word line design has the advantage of low bit line parasitic capacitance and can provide a more economical design.
  • the memory in the embodiment of the present application is a 3D memory including 1T1C.
  • the word lines included in the 3D memory are designed in a horizontal word line manner.
  • the present application designs a new peripheral circuit of the memory, which can accurately select the word lines that need to be selected during read and write operations, thereby improving the performance of the memory.
  • An embodiment of the present application provides a memory, including: a substrate and a three-dimensional storage array located on one side of the substrate, the three-dimensional storage array includes a plurality of storage array layers stacked in a direction perpendicular to the substrate, and the substrate may be a semiconductor substrate such as a silicon substrate.
  • FIG. 1 only shows a storage array layer 11 (e.g., the kth storage array layer) located on one side of the substrate.
  • the storage array layer 11 includes a plurality of storage cells 12 arranged in an array, a plurality of word lines parallel to the substrate (such as WL-k,1, WL-k,2, WL-k,3 in FIG. 1 ), a plurality of bit lines perpendicular to the substrate (such as BL_1,1, BL_1,2, BL_1,M-1, BL_1,M, etc. in FIG.
  • a selection circuit 13 a first selection line WL_layer_k, a second selection line WL_N_layer_k, a plurality of third selection lines (such as WL-row1, WL-row2, WL-row3 in FIG. 1 ), and a plurality of low level Potential end (position such as the positions of multiple V_low in FIG. 1 ).
  • a row of storage cells 12 is connected to a word line.
  • a selection circuit 13 For each storage array layer, a selection circuit 13, a first selection line WL_layer_k, a second selection line WL_N_layer_k and a plurality of low-level potential ends correspond to all storage cells.
  • the first selection line WL_layer_k and the second selection line WL_N_layer_k are parallel to the substrate, the third selection line is perpendicular to the substrate, and the third selection line is arranged in one-to-one correspondence with the word line.
  • the selection circuit 13 is respectively connected to a plurality of word lines, the first selection line WL_layer_k, the second selection line WL_N_layer_k, a plurality of third selection lines and a plurality of low-level potential ends.
  • a plurality of selection circuits 13 are used to determine a selected storage array layer based on the level state of the first selection line WL_layer_k and the second selection line WL_N_layer_k of the corresponding storage array layer, and to determine a word line selected during a read or write operation based on the level state of the third selection line of the selected storage array layer.
  • the substrate in the embodiment of the present application extends along the first direction and the second direction in Figure 1, and multiple word lines extend parallel to the substrate.
  • the third direction in Figure 1 refers to the direction perpendicular to the paper surface, that is, the direction perpendicular to the substrate.
  • the selection circuit 13 in the embodiment of the present application can be located on one side of the word line or on two opposite sides of the word line.
  • FIG. 1 only shows the case where the selection circuit 13 is located on two opposite sides of the word line.
  • a plurality of word lines extend along the second direction, a first selection line WL_layer_k and a second selection line WL_N_layer_k both extend along the first direction, and a third selection line extends along the third direction; each low-level potential end can be connected to a signal line, and these signal lines can extend along the third direction, and each signal line is connected to a low-level potential, for example, each signal line is grounded.
  • the low-level potential in the embodiment of the present application refers to a zero potential or a negative potential.
  • each memory array layer includes a selection circuit, a first selection line, a second selection line, a third selection line and a low level potential end, the selection circuit is respectively connected to the word line, the first selection line, the second selection line, the third selection line and the low level potential end, and the plurality of selection circuits are used to determine the selected memory array layer based on the level state of the first selection line and the second selection line of the corresponding memory array layer, and the third selection line of the selected memory array layer based on the level state of the third selection line of the selected memory array layer.
  • the level state of the selection line determines the word line selected during the read and write operations; therefore, the embodiment of the present application can provide a method for selecting the word line parallel to the substrate direction that needs to be selected during the read and write operations by designing a new peripheral circuit.
  • a plurality of word lines stacked in a direction perpendicular to the substrate correspond to a common third selection line
  • the third selection lines (such as WL-row1, WL-row2, and WL-row3 in FIG. 1 ) are perpendicular to the substrate.
  • a third selection line (such as WL-row1)
  • all storage array layers share the third selection line;
  • the third selection line is connected to a peripheral circuit to receive a high-level signal or a low-level signal output by the peripheral circuit, and the setting method of the third selection line can save costs; of course, in actual design, the third selection lines included in different layers of storage array layers may not be shared.
  • This design method has more wiring and is not conducive to the integration of the device.
  • the several low-level potential terminals (such as the multiple V_lows in Figure 1) in the embodiment of the present application are several power lines perpendicular to the substrate.
  • the power lines and word lines are arranged one by one, and multiple word lines stacked in a direction perpendicular to the substrate correspond to one power line.
  • the power line can be grounded or connected to a negative potential signal terminal; the setting method of the power line can save costs.
  • the several low-level potential ends included in all the storage array layers in the embodiment of the present application are conductive walls.
  • all the storage array layers share the conductive wall, and the conductive wall can be grounded or connected to the negative potential signal end.
  • this implementation only requires one conductive wall to achieve grounding of the low-level potential ends included in all the storage array layers, which can minimize production costs.
  • the selection circuit in each storage array layer in the embodiment of the present application includes a first sub-selection circuit 131 and a second sub-selection circuit 132; for each storage array layer, the first sub-selection circuit 131 is respectively connected to the word line (such as WL-k,1, WL-k,2, WL-k,3 in FIG. 2 ), the first selection line WL_layer_k and the third selection line (such as WL-row1, WL-row2, WL-row3 in FIG.
  • each first sub-selection circuit 131 is used to determine the storage array layer whose word line is connected to the third selection line based on the level state of the first selection line WL_layer_k of the corresponding storage array layer, and determine the selected word line based on the level state of the third selection line of the storage array layer whose word line is connected to the third selection line;
  • the second sub-selection circuit 132 is respectively connected to the word line, the second selection line WL_N_layer_k and the low-level potential end (such as the multiple V_lows in FIG.
  • each layer of the second sub-selection circuit 132 is used to determine the storage array layer where the word line is connected to the low-level potential end based on the level state of the second selection line WL_N_layer_k of the corresponding storage array layer; wherein: the storage array layer where the word line is connected to the third selection line is the selected storage array layer, and the storage array layer where the word line is connected to the low-level potential end is the unselected storage array layer.
  • the first sub-selection circuit 131 and the first selection line WL_layer_k are located on one side of the word line, and the second sub-selection circuit 132 and the second selection line WL_N_layer_k are located on the same side of the word line; in another optional embodiment, the first sub-selection circuit 131 and the first selection line WL_layer_k are located on a first side of the word line, and the second sub-selection circuit 132 and the second selection line WL_N_layer_k are located on a second side of the word line, and the first side and the second side are arranged opposite to each other, the first sub-selection circuit 131 and the second sub-selection circuit 132 are arranged opposite to each other, and the first selection line WL_layer_k and the second selection line WL_N_layer _k are relatively arranged; since the first sub-selection circuit 131, the second sub-selection circuit 132, the first selection line WL_layer_k and the
  • the first sub-selection circuit 131 includes a plurality of first transistors T1, and the first transistors T1 are arranged in a one-to-one correspondence with the word lines; the gate of the first transistor T1 is connected to the first selection line WL_layer_k, the first electrode of the first transistor T1 is connected to the word line (such as the first electrode of the first first transistor T1 is connected to one end of the word line WL-k,1, the first electrode of the second first transistor T1 is connected to one end of the word line WL-k,2, and the first electrode of the third first transistor T1 is connected to one end of the word line WL-k,3), and the second electrode of the first transistor is connected to the third selection line (such as the second electrode of the first first transistor T1 is connected to the third selection line WL-row1, the second electrode of the second first transistor T1 is connected to the third selection line WL-row2, and the second electrode of the third first transistor T1 is connected to the third selection line WL
  • the second sub-selection circuit 132 includes a plurality of second transistors T2, and the second transistors T2 are arranged in a one-to-one correspondence with the word lines; the gate of the second transistor T2 is connected to the second selection line WL_N_layer_k, the first electrode of the second transistor T2 is connected to the word line (such as the first electrode of the first second transistor T2 is connected to the other end of the word line WL-k, 1, the first electrode of the second second transistor T2 is connected to the other end of the word line WL-k, 2, and the first electrode of the third second transistor T2 is connected to the other end of the word line WL-k, 3), and the second electrode of the second transistor T2 is connected to the low level potential end (such as V_low in Figure 2).
  • the first transistor T1 and the second transistor T2 are of the same type. In another optional embodiment, the first transistor T1 and the second transistor T2 are of different types. Since the manufacturing cost is higher and the yield is easily reduced when the first transistor T1 and the second transistor T2 are of different types, this is not a preferred design method in actual design, but only a design method that can be implemented.
  • the first transistor T1 is an N-type transistor
  • the second transistor T2 is an N-type transistor
  • the first transistor T1 is a P-type transistor
  • the second transistor T2 is a P-type transistor
  • the level state of the first selection line WL_layer_k is opposite to the level state of the second selection line WL_N_layer_k; that is, in the embodiment of the present application, if the first transistor T1 and the second transistor T2 are of the same type, the level state of the first selection line WL_layer_k is opposite to the level state of the second selection line WL_N_layer_k.
  • the level state of the first selection line WL_layer_k and the level state of the second selection line WL_N_layer_k are opposite at any time.
  • the level state of the first selection line WL_layer_k is a high level (i.e., the logic level is 1)
  • the level state of the second selection line WL_N_layer_k is a low level (i.e., the logic level is 0)
  • the level state of the third selection line in the embodiment of the present application can be a high level or a low level, and the level state of the low level potential end is always a low level.
  • the first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor; or, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor; the level state of the first selection line WL_layer_k is the same as the level state of the second selection line WL_N_layer_k; that is, in the embodiment of the present application, if the first transistor T1 If the type of the second transistor T2 is different, the level state of the first selection line WL_layer_k is the same as the level state of the second selection line WL_N_layer_k.
  • the level state of the first selection line WL_layer_k and the level state of the second selection line WL_N_layer_k are the same at any time. For example, if the level state of the first selection line WL_layer_k is a high level (that is, the logic level is 1), then the level state of the second selection line WL_N_layer_k is also a high level; if the level state of the first selection line WL_layer_k is a low level (that is, the logic level is 0), then the level state of the second selection line WL_N_layer_k is also a low level.
  • the embodiment of the present application is described by taking the first transistor T1 and the second transistor T2 as the same type, and the first transistor T1 is an N-type transistor and the second transistor T2 is an N-type transistor as an example.
  • the first selection line WL_layer_k and the second selection line WL_N_layer_k serve as storage array layer selection lines, that is, which storage array layer is selected is determined by the level state of the first selection line WL_layer_k and the level state of the second selection line WL_N_layer_k; specifically, if the k-th storage array layer needs to be selected, the level state of the first selection line WL_layer_k included in the k-th storage array layer is a high level (that is, the peripheral circuit outputs a high level signal for the first selection line WL_layer_k), and the level state of the second selection line WL_N_layer_k included in the k-th storage array layer is a low level (that is, the peripheral circuit outputs a low level signal for the second selection line WL_N_layer_k); for all storage array layers that do not need to be selected, the level state of the first selection line WL_layer_k included in each storage array layer is a low level, and
  • the storage unit in the embodiment of the present application includes a transistor T and a capacitor C, wherein the transistor T and the capacitor C can be designed in a horizontal two-dimensional arrangement; the gate of the transistor T is connected to the word line, the first electrode of the transistor T is connected to the bit line, the second electrode of the transistor T is connected to one end of the capacitor C, and the other end of the capacitor C is grounded.
  • the transistor T in the embodiment of the present application is an N-type transistor. Of course, in actual design, the transistor T can also be a P-type transistor.
  • the first electrode of the transistor in the embodiment of the present application refers to the source electrode of the transistor, and the second electrode of the transistor refers to the crystal electrode.
  • the drain of the transistor, or the first pole of the transistor refers to the drain of the transistor, the second pole of the transistor refers to the source of the transistor, the first pole and the second pole of the transistor can be interchangeable and are not limited here.
  • the channels of the transistor T, the first transistor T1 and the second transistor T2 in the embodiment of the present application are all horizontal channels.
  • the transistor T includes a source 14, a drain 15, a semiconductor layer 16, a gate insulating layer 17 and a gate 18, wherein the semiconductor layer 16 is arranged around the gate 18, and the first transistor T1 and the second transistor T2 can also adopt the arrangement shown in FIG3.
  • the semiconductor layer is preferably a metal oxide semiconductor, such as IGZO (Indium Gallium Zinc Oxide).
  • IGZO Indium Gallium Zinc Oxide
  • the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO and other materials, as long as the leakage current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.
  • a plurality of word lines stacked and arranged in a direction perpendicular to the substrate correspond to a third selection line
  • the third selection line serves as a word line selection line, that is, which word line in the selected storage array layer is selected is determined by the level state of the third selection line; specifically, if the k-th storage array layer is selected, the plurality of third selection lines of the k-th storage array layer are connected to the plurality of word lines in a one-to-one correspondence, and when the level state of the third selection line is high, the word line connected to the third selection line with the high level is selected, and when the level state of the third selection line is low, the word line connected to the third selection line with the low level is selected.
  • the line is not selected. For example, if the word line WL-k,1 needs to be selected, the level state of the third selection line WL-row1 connected to the word line WL-k,1 is high (that is, the peripheral circuit outputs a high level signal for the third selection line WL-row1), and the level state of the third selection line connected to other word lines is low (that is, the peripheral circuit outputs a low level signal for the third selection line connected to other word lines).
  • the transistor T connected to the word line WL-k,1 is turned on, and the data of the bit lines BL_1,1, BL_1,2, BL_1,M-1, BL_1,M can be written into the capacitor C, or through the bit line BL_1,1, BL_1,2, BL_1,M-1, and BL_1,M read the data stored in the capacitor C.
  • word lines when other word lines are selected, data writing and data reading of the storage cells in the corresponding rows can be achieved.
  • the memory cells located in the same column along the extension direction of the bit line share a bit line, that is, for a bit line (for example, bit line BL_1,1), all memory array layers stacked along the extension direction of the bit line share the bit line; for each memory array layer, the first electrode of the transistor T included in the memory cell is connected to the bit line one by one.
  • bit line for example, bit line BL_1,1
  • the first electrodes of two adjacent transistors T (for example, two adjacent transistors in the first column in FIG. 2 ) in a direction perpendicular to the word line are connected to the same bit line. This design can save the number of bit lines, reduce the size of the memory, and thus improve the integration of the device.
  • the memory in the embodiment of the present application includes a read-write circuit, a plurality of bit line selection units and a plurality of control lines.
  • the bit lines are connected to the bit line selection units in a one-to-one correspondence, and the control lines are connected to the bit line selection units in a one-to-one correspondence.
  • the bit line selection units are used to select the bit lines based on the control of the control lines to connect the selected bit lines to the read-write circuits.
  • the bit line selection units are located at the bottom or top of the three-dimensional storage array, and the bit line selection units form an array.
  • a row of bit line selection units corresponding to the word lines is opened through the control of the control lines, and this row of storage cells is connected to a row of read-write circuits. Specifically, when writing data, the read-write circuit transmits the data to the row of storage cells through the bit lines, and when reading data, the read-write circuit can receive the data transmitted by the row of storage cells through the bit lines to complete the reading of the row of storage cells.
  • the memory further includes a plurality of first connection lines and/or a plurality of second connection lines; each first selection line is connected to the peripheral circuit via a first connection line, the first connection line is perpendicular to the substrate, and the plurality of first connection lines are arranged in a step-by-step manner along a direction perpendicular to the substrate; each second selection line is connected to the peripheral circuit via a second connection line, the second connection line is perpendicular to the substrate, and the plurality of second connection lines are arranged in a step-by-step manner along a direction perpendicular to the substrate; through this arrangement, the first selection lines included in the storage array layers of different layers can be connected to the peripheral circuit within the minimum wiring space to receive the electrical signal output by the peripheral circuit; and the second selection lines included in the storage array layers of different layers can be connected to the peripheral circuit to receive the electrical signal output by the peripheral circuit.
  • the electrical signal output is used to complete the control of the selection circuit.
  • FIG. 4 shows three first selection lines included in three adjacent storage array layers, each of which is connected to the peripheral circuit through a corresponding first connection line, and the top ends of the plurality of first connection lines are flush, and the bottom ends are respectively located in different storage array layers. Since different storage array layers are stacked, the bottom ends of the first connection lines are located in different planes, thereby making the first connection lines arranged in a stepped manner, which can be achieved by the arrangement of stepped through holes during specific production.
  • an embodiment of the present application provides an electronic device, including a memory provided in any of the above embodiments.
  • the electronic device includes the above-mentioned memory, so the electronic device has the same beneficial effects as the above-mentioned memory, which will not be repeated here.
  • the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.
  • an embodiment of the present application provides a method for reading and writing the above-mentioned memory, as shown in FIG5 , the write operation phase of the memory includes:
  • a high-level signal is applied to the first selection line WL_layer_k corresponding to the storage array layer to which data is to be written, and a low-level signal is applied to the second selection line WL_N_layer_k, the first transistor T1 is turned on, the second transistor T2 is turned off, and each word line is connected to a third selection line in a one-to-one correspondence; then, a high-level signal is applied to the third selection line connected to the word line to which data is to be written, for example, if the word line to be written is WL-K,1, then after the word line WL-K,1 receives the high-level signal, the transistor T of the first row is controlled to be turned on, so that the data of the bit line connected to the transistor T of the first row can be written; in addition, a low-level signal is applied to other third selection lines (i.e., the third selection lines connected
  • the memory applies a high-level signal to the first selection line WL_layer_k corresponding to the storage array layer of the data to be read, and applies a low-level signal to the second selection line WL_N_layer_k in the reading operation stage, the first transistor T1 is turned on, the second transistor T2 is turned off, and each word line is connected to a third selection line one-to-one; then, a high-level signal is applied to the third selection line connected to the word line of the data to be read, for example, the word line of the data to be read is WL-K,1, then after the word line WL-K,1 receives the high-level signal, the transistor T of the first row is controlled to be turned on, so that the data stored in the first row of storage cells can be transferred to the corresponding bit line, and the stored data is read through the read-write circuit connected to the bit line; in addition, a low-level signal is applied to other
  • the read operation phase also includes: applying a low level signal to a first selection line WL_layer_k corresponding to a storage array layer that does not need to read data, and applying a high level signal to a second selection line WL_N_layer_k that does not need to read data.
  • the write operation stage also includes: applying a second electrical signal to a first selection line corresponding to a storage array layer that does not require data to be written, and applying a first electrical signal to a second selection line that does not require data to be written, so that the word line of the storage array layer that does not require data to be written is connected to the low-level potential end.
  • a low level signal is applied to the first selection line WL_layer_k corresponding to the storage array layer that does not need to write data, and a high level signal is applied to the second selection line WL_N_layer_k that does not need to write data.
  • each storage array layer includes a selection circuit, a first selection line, a second selection line, a third selection line and a low-level potential end
  • the selection circuit is respectively connected to the word line, the first selection line, the second selection line, the third selection line and the low-level potential end
  • the multiple selection circuits are used to determine the selected storage array layer based on the level state of the first selection line and the second selection line of the corresponding storage array layer, and determine the word line selected during the read and write operations based on the level state of the third selection line of the selected storage array layer; therefore, the embodiment of the present application can provide a method for selecting the word line parallel to the substrate direction that needs to be selected during the read and write operations by designing a new peripheral circuit.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, “plurality” means two or more.

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Abstract

本申请提供了一种存储器及其读写方法、电子设备。该存储器包括位于衬底一侧的三维存储阵列，三维存储阵列包括若干层存储阵列层，存储阵列层包括存储单元、垂直于衬底的位线和平行于衬底的字线；每一层存储阵列层还包括：选择电路、第一选择线、第二选择线、若干第三选择线和若干低电平电位端；第一选择线和第二选择线平行于衬底，第三选择线与字线一一对应设置；选择电路分别与字线、第一选择线、第二选择线、若干第三选择线和若干低电平电位端连接，多个选择电路用于基于相应存储阵列层的第一选择线和第二选择线的电平状态，确定出被选择的存储阵列层，以及基于被选择的存储阵列层的第三选择线的电平状态，确定读写操作时被选中的字线。

Description

一种存储器及其读写方法、电子设备
本申请要求于2023年08月10日提交至中国国家知识产权局、申请号为202311010849.2、发明名称为“一种存储器及其读写方法、电子设备”的专利申请的优先权。
技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种存储器及其读写方法、电子设备。
背景技术
存储器是用于数据存放的主要介质。常见的存储器件多为平面结构的二维(2D)存储器件，随着各类电子设备对集成度和存储容量等需求的不断提高，三维(3D)存储器件应运而生。
三维存储器件可实现数据在三维空间中的存储和传递，能够大幅度提高存储器件的存储能力，降低存储成本，提高存储器件的集成度和存储密度，有助于实现存储器件的小型化。
发明内容
本申请实施例提供一种存储器及其读写方法、电子设备，提供了一种读写操作时对水平字线的选择方式。为了实现上述目的，本申请实施例提供的技术方案如下：
第一方面，本申请实施例提供了一种存储器，包括：
衬底；
三维存储阵列，位于所述衬底的一侧，包括若干层沿垂直于所述衬底方向叠层设置的存储阵列层，所述存储阵列层包括二维阵列排布的存储单元、若干垂直于所述衬底的位线和若干平行于所述衬底的字线，每一层所 述存储阵列层中，一行所述存储单元连接一条所述字线；
每一层所述存储阵列层还包括：选择电路、第一选择线、第二选择线、若干第三选择线和若干低电平电位端；
所述第一选择线和所述第二选择线平行于所述衬底，所述第三选择线垂直于所述衬底，且所述第三选择线与所述字线一一对应设置；
所述选择电路，分别与若干所述字线、所述第一选择线、所述第二选择线、若干所述第三选择线和若干所述低电平电位端连接；
针对所述三维存储阵列，多个所述选择电路用于基于相应所述存储阵列层的所述第一选择线和所述第二选择线的电平状态，确定出被选择的存储阵列层，以及基于被选择的存储阵列层的所述第三选择线的电平状态，确定读写操作时被选中的字线。
可选地，若干所述低电平电位端为若干垂直于所述衬底的电源线；
每一所述存储阵列层，所述电源线与所述字线一一对应设置；
沿垂直于所述衬底的方向且堆叠设置的多条所述字线共同对应一条所述电源线。
可选地，所有的所述存储阵列层包括的若干所述低电平电位端为导电墙；
沿垂直于所述衬底的方向，所有的所述存储阵列层共用所述导电墙。
可选地，每一层所述存储阵列层中的所述选择电路包括第一子选择电路和第二子选择电路；
针对每一层所述存储阵列层，所述第一子选择电路，分别与同一层所述存储阵列层的若干所述字线、所述第一选择线和所述第三选择线连接；针对所述三维存储阵列，每一层所述第一子选择电路用于基于相应所述存储阵列层的所述第一选择线的电平状态，确定出所述字线与所述第三选择线连接的存储阵列层，以及基于字线与所述第三选择线连接的存储阵列层的所述第三选择线的电平状态，确定被选中的所述字线；
针对每一层所述存储阵列层，所述第二子选择电路，分别与同一层所述存储阵列层的若干所述字线、所述第二选择线和所述低电平电位端连接； 针对所述三维存储阵列，每一层所述第二子选择电路用于基于相应所述存储阵列层的所述第二选择线的电平状态，确定所述字线与所述低电平电位端连接的存储阵列层；其中：
所述字线与所述第三选择线连接的存储阵列层为被选择的存储阵列层，所述字线与所述低电平电位端连接的存储阵列层为未被选择的存储阵列层。
可选地，所述第一子选择电路位于所述字线的一侧，所述第二子选择电路位于所述字线的相同侧；
或者，所述第一子选择电路位于所述字线的第一侧，所述第二子选择电路位于所述字线的第二侧，所述第一侧和所述第二侧相对设置。
可选地，所述第一子选择电路包括若干第一晶体管，所述第一晶体管与所述字线一一对应设置；
所述第一晶体管的栅极与所述第一选择线连接，所述第一晶体管的第一极与所述字线连接，所述第一晶体管的第二极与所述第三选择线连接。
可选地，所述第二子选择电路包括若干第二晶体管，所述第二晶体管与所述字线一一对应设置；
所述第二晶体管的栅极与所述第二选择线连接，所述第二晶体管的第一极与所述字线连接，所述第二晶体管的第二极与所述低电平电位端连接。
可选地，所述第一晶体管为N型晶体管，所述第二晶体管为N型晶体管，所述第一选择线的电平状态与所述第二选择线的电平状态相反；
或者，所述第一晶体管为P型晶体管，所述第二晶体管为P型晶体管，所述第一选择线的电平状态与所述第二选择线的电平状态相反；
或者，所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管，所述第一选择线的电平状态与所述第二选择线的电平状态相同；
或者，所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管，所述第一选择线的电平状态与所述第二选择线的电平状态相同。
可选地，所述存储单元包括一个晶体管和一个电容；
所述晶体管的栅极与所述字线连接，所述晶体管的第一极与所述位线 连接，所述晶体管的第二极与所述电容的一端连接，所述电容的另一端接地。
可选地，所述存储器包括如下至少一项；
沿所述位线的延伸方向位于同一列的存储单元共用一条所述位线；
沿垂直于所述衬底的方向且堆叠设置的多条所述字线共同对应一条所述第三选择线；
针对每一层所述存储阵列层，所述晶体管的第一极与所述位线一一对应连接；或者，沿垂直于所述字线方向上相邻的两个所述晶体管的第一极连接同一条位线。
可选地，存储器包括读写电路、若干位线选择单元和若干控制线；
所述位线与所述位线选择单元一一对应连接，所述控制线与所述位线选择单元一一对应连接；
所述位线选择单元用于基于所述控制线的控制选择所述位线，以将选中的所述位线与所述读写电路连接。
可选地，存储器包括若干第一连接线和/或若干第二连接线；
每一所述第一选择线通过一条所述第一连接线与外围电路连接，所述第一连接线垂直于所述衬底，且沿垂直于所述衬底方向，多条所述第一连接线呈阶梯排布；
每一所述第二选择线通过一条所述第二连接线与外围电路连接，所述第二连接线垂直于所述衬底，且沿垂直于所述衬底方向，多条所述第二连接线呈阶梯排布。
第二方面，本申请实施例提供了一种电子设备，包括如第一方面任一的存储器。
第三方面，本申请实施例提供了一种存储器的读写方法，包括：
写入操作阶段：向待要写入数据的存储阵列层对应的第一选择线施加第一电信号，以及向待要写入数据的存储阵列层对应的第二选择线施加第二电信号，使得待要写入数据的存储阵列层的所述字线与所述第三选择线一一对应连接，以选中待要写入数据的存储阵列层；
基于选中的待要写入数据的存储阵列层，向与待要写入数据的存储单元行连接的字线对应的第三选择线施加第三电信号，使得与所述字线连接的存储单元行导通，以选中待要写入数据的存储单元行；
基于选中的待要写入数据的存储单元行，将与所述存储单元行中存储单元连接的位线的数据写入所述存储单元。
可选地，所述写入操作阶段还包括：向不需要写入数据的存储阵列层对应的第一选择线施加第二电信号，以及向不需要写入数据的第二选择线施加第一电信号，使得不需要写入数据的存储阵列层的所述字线与所述低电平电位端连接。
本申请实施例提供的技术方案，至少具有如下有益效果：
本申请实施例提供的存储器，由于每一存储阵列层均包括选择电路、第一选择线、第二选择线、第三选择线和低电平电位端，选择电路分别与字线、第一选择线、第二选择线、第三选择线和低电平电位端连接，多个选择电路用于基于相应存储阵列层的第一选择线和第二选择线的电平状态，确定出被选择的存储阵列层，以及基于被选择的存储阵列层的第三选择线的电平状态，确定读写操作时被选中的字线；因此，本申请实施例通过设计新的外围电路，能够提供一种在读写操作时选定需要被选择的平行于衬底方向的字线的方式。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种存储器包括的第k层存储阵列层的结构示意图；
图2为本申请实施例提供的一种存储器包括的第k层存储阵列层的具体结构示意图；
图3为本申请实施例提供的存储器包括的晶体管的结构示意图；
图4为本申请实施例提供的存储器的立体结构示意图；
图5为本申请实施例提供的一种存储器的读写方法流程图。
附图标记：
11-存储阵列层；12-存储单元；13-选择电路；131-第一子选择电路；
132-第二子选择电路；
14-源极；15-漏极；16-半导体层；17-栅极绝缘层；18-栅极。
具体实施方式
下面详细描述本申请，本申请实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外，如果已知技术的详细描述对于示出的本申请的特征是不必要的，则将其省略。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。应该理解，当我们称元件被“连接”或“耦接”到另一元件时，它可以直接连接或耦接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
随着DRAM(Dynamic Random Access Memory，动态随机存取存储器)技术的发展，平面的1T1C(一个晶体管和一个电容)存储器结构已经趋于极限，在获取更高电容，更低漏电，更高集成度方面，目前的2D存储器件发展受到了限制。
对于DRAM而言，通过将存储阵列晶体管布置在3D而不是2D的情况下，集成电路(IC)中的晶体管可彼此靠近放置，且可实现多层堆栈，节省平面内的面积。目前有多种3D-DRAM技术，大部分的3D存储器结构都是将2D的存储单元水平放置再多层堆叠。
目前3D存储器结构的字线设计方式中，部分设计采用垂直字线(即字线的延伸方向垂直于衬底)的设计方式，部分设计采用水平字线(即字线的延伸方向平行于衬底)的设计方式，其中水平字线的设计方式具有低位线寄生电容的优势，可以提供更经济的设计。
本申请实施例中的存储器为包括1T1C的3D存储器，该3D存储器包括的字线采用水平字线的设计方式，本申请通过设计新的存储器的外围电路，能够在读写操作时精确的选定需要被选择的字线，提升存储器的性能。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本申请的实施例进行描述。
本申请实施例提供了一种存储器，包括：衬底和位于衬底一侧的三维存储阵列，三维存储阵列包括若干层沿垂直于衬底方向叠层设置的存储阵列层，衬底可以为硅衬底等半导体衬底。
如图1所示，图1仅示出了位于衬底一侧的一层存储阵列层11(例如第k层存储阵列层)，存储阵列层11包括若干阵列排布的存储单元12、若干平行于衬底的字线(如图1中的WL-k,1、WL-k,2、WL-k,3)、若干垂直于衬底的位线(如图1中的BL_1,1、BL_1,2、BL_1,M-1、BL_1,M等)、选择电路13、第一选择线WL_layer_k、第二选择线WL_N_layer_k、若干第三选择线(如图1中的WL-row1、WL-row2、WL-row3)和若干低电平 电位端(位置如图1中的多个V_low的位置)。
如图1所示，一行存储单元12连接一条字线，针对每一层存储阵列层，选择电路13、第一选择线WL_layer_k、第二选择线WL_N_layer_k和若干低电平电位端均对应所有的存储单元，第一选择线WL_layer_k和第二选择线WL_N_layer_k平行于衬底，第三选择线垂直于衬底，且第三选择线与字线一一对应设置；选择电路13分别与若干字线、第一选择线WL_layer_k、第二选择线WL_N_layer_k、若干第三选择线和若干低电平电位端连接；针对三维存储阵列，多个选择电路13用于基于相应存储阵列层的第一选择线WL_layer_k和第二选择线WL_N_layer_k的电平状态，确定出被选择的存储阵列层，以及基于被选择的存储阵列层的第三选择线的电平状态，确定读写操作时被选中的字线。
需要说明的是，本申请实施例中的衬底沿图1中的第一方向和第二方向延伸，多条字线平行于衬底延伸，图1中的第三方向指垂直于纸面的方向，即垂直于衬底的方向。
需要说明的是，本申请实施例中的选择电路13可以位于字线的一侧，也可以位于字线的相对两侧，图1中仅示出了选择电路13位于字线相对两侧的情况。
具体地，如图1所示，多条字线沿第二方向延伸，第一选择线WL_layer_k和第二选择线WL_N_layer_k均沿第一方向延伸，第三选择线沿第三方向延伸；每一低电平电位端均可以连接一条信号线，这些信号线可以沿第三方向延伸，每条信号线均连接低电平电位，例如每条信号线均接地，当然，实际设计时，所有的信号线可以先连接到一起，然后再接地连接。本申请实施例中的低电平电位指零电位或者负电位。
本申请实施例提供的存储器，由于每一存储阵列层均包括选择电路、第一选择线、第二选择线、第三选择线和低电平电位端，选择电路分别与字线、第一选择线、第二选择线、第三选择线和低电平电位端连接，多个选择电路用于基于相应存储阵列层的第一选择线和第二选择线的电平状态，确定出被选择的存储阵列层，以及基于被选择的存储阵列层的第三选 择线的电平状态，确定读写操作时被选中的字线；因此，本申请实施例通过设计新的外围电路，能够提供一种在读写操作时选定需要被选择的平行于衬底方向的字线的方式。
在一种具体的实施例中，沿垂直于衬底的方向且堆叠设置的多条字线共同对应一条第三选择线，第三选择线(如图1中的WL-row1、WL-row2、WL-row3)垂直于衬底，针对一条第三选择线(例如WL-row1)，所有的存储阵列层共用该条第三选择线；第三选择线连接外围电路，用于接收外围电路输出的高电平信号或低电平信号，第三选择线的设置方式能够节省成本；当然，实际设计时，也可以是不同层存储阵列层包括的第三选择线不共用，这种设计方式布线较多，不利于器件的集成度。
在一种可选的实施例中，本申请实施例中的若干低电平电位端(如图1中的多个V_low)为若干垂直于衬底的电源线，如图1所示，每一存储阵列层，电源线与字线一一对应设置，沿垂直于衬底的方向且堆叠设置的多条字线共同对应一条电源线，该电源线可以接地，也可以接负电位信号端；电源线的设置方式能够节省成本。
在另一种可选的实施例中，本申请实施例中的所有的存储阵列层包括的若干低电平电位端为导电墙，沿垂直于衬底的方向，所有的存储阵列层共用该导电墙，该导电墙可以接地，也可以接负电位信号端；这种实施方式在实际制作时，可以仅制作一导电墙，即可实现所有存储阵列层包括的低电平电位端接地，能够最大程度的降低生产成本。
在一种具体的实施例中，如图2所示，本申请实施例中每一层存储阵列层中的选择电路包括第一子选择电路131和第二子选择电路132；针对每一层存储阵列层，第一子选择电路131，分别与字线(如图2中的WL-k,1、WL-k,2、WL-k,3)、第一选择线WL_layer_k和第三选择线(如图2中的WL-row1、WL-row2、WL-row3)连接；针对三维存储阵列，每一层第一子选择电路131用于基于相应存储阵列层的第一选择线WL_layer_k的电平状态，确定出字线与第三选择线连接的存储阵列层，以及基于字线与第三选择线连接的存储阵列层的第三选择线的电平状态，确定被选中的字线； 针对每一层存储阵列层，第二子选择电路132，分别与字线、第二选择线WL_N_layer_k和低电平电位端(如图2中的多个V_low)连接；针对三维存储阵列，每一层第二子选择电路132用于基于相应存储阵列层的第二选择线WL_N_layer_k的电平状态，确定字线与低电平电位端连接的存储阵列层；其中：字线与第三选择线连接的存储阵列层为被选择的存储阵列层，字线与低电平电位端连接的存储阵列层为未被选择的存储阵列层。
在一种可选的实施例中，第一子选择电路131和第一选择线WL_layer_k位于字线的一侧，第二子选择电路132和第二选择线WL_N_layer_k位于字线的相同侧；在另一种可选的实施例中，第一子选择电路131和第一选择线WL_layer_k位于字线的第一侧，第二子选择电路132和第二选择线WL_N_layer_k位于字线的第二侧，第一侧和第二侧相对设置，第一子选择电路131和第二子选择电路132相对设置，第一选择线WL_layer_k和第二选择线WL_N_layer_k相对设置；由于第一子选择电路131、第二子选择电路132、第一选择线WL_layer_k和第二选择线WL_N_layer_k均位于存储阵列层的边缘，因此第一子选择电路131、第二子选择电路132、第一选择线WL_layer_k和第二选择线WL_N_layer_k的设计不会影响存储器的整体设计，且由于第一子选择电路131和第二子选择电路132相对设置，第一选择线WL_layer_k和第二选择线WL_N_layer_k相对设置，能够使得存储器的外围电路的布线更均匀。
在一种具体的实施例中，如图2所示，第一子选择电路131包括若干第一晶体管T1，第一晶体管T1与字线一一对应设置；第一晶体管T1的栅极与第一选择线WL_layer_k连接，第一晶体管T1的第一极与字线连接(如第一个第一晶体管T1的第一极与字线WL-k,1的一端连接，第二个第一晶体管T1的第一极与字线WL-k,2的一端连接，第三个第一晶体管T1的第一极与字线WL-k,3的一端连接)，第一晶体管的第二极与第三选择线连接(如第一个第一晶体管T1的第二极与第三选择线WL-row1连接，第二个第一晶体管T1的第二极与第三选择线WL-row2连接，第三个第一晶体管T1的第二极与第三选择线WL-row3连接)。
在一种具体的实施例中，如图2所示，第二子选择电路132包括若干第二晶体管T2，第二晶体管T2与字线一一对应设置；第二晶体管T2的栅极与第二选择线WL_N_layer_k连接，第二晶体管T2的第一极与字线连接(如第一个第二晶体管T2的第一极与字线WL-k,1的另一端连接，第二个第二晶体管T2的第一极与字线WL-k,2的另一端连接，第三个第二晶体管T2的第一极与字线WL-k,3的另一端连接)，第二晶体管T2的第二极与低电平电位端(如图2中的V_low)连接。
在一种可选的实施例中，第一晶体管T1和第二晶体管T2的类型相同，在另一种可选的实施例中，第一晶体管T1和第二晶体管T2的类型不同，由于第一晶体管T1和第二晶体管T2的类型不同时，制作成本较高，且容易导致良率下降，因此实际设计时不作为优选的设计方式，仅作为一种可以实施的设计方式。
在一种具体实施例中，第一晶体管T1为N型晶体管，第二晶体管T2为N型晶体管；或者，第一晶体管T1为P型晶体管，第二晶体管T2为P型晶体管；第一选择线WL_layer_k的电平状态与第二选择线WL_N_layer_k的电平状态相反；即本申请实施例中，若第一晶体管T1和第二晶体管T2的类型相同，则第一选择线WL_layer_k的电平状态与第二选择线WL_N_layer_k的电平状态相反。
具体地，本申请实施例中，针对同一层的存储阵列层，在任何时刻第一选择线WL_layer_k的电平状态与第二选择线WL_N_layer_k的电平状态均相反，例如：第一择线WL_layer_k的电平状态为高电平(即逻辑电平为1)，则第二选择线WL_N_layer_k的电平状态为低电平(即逻辑电平为0)；本申请实施例中的第三选择线的电平状态可以为高电平，也可以为低电平，低电平电位端的电平状态始终为低电平。
在另一种具体实施例中，第一晶体管T1为N型晶体管，第二晶体管T2为P型晶体管；或者，第一晶体管T1为P型晶体管，第二晶体管T2为N型晶体管；第一选择线WL_layer_k的电平状态与第二选择线WL_N_layer_k的电平状态相同；即本申请实施例中，若第一晶体管T1 和第二晶体管T2的类型不同，则第一选择线WL_layer_k的电平状态与第二选择线WL_N_layer_k的电平状态相同。
具体地，本申请实施例中，针对同一层的存储阵列层，在任何时刻第一选择线WL_layer_k的电平状态与第二选择线WL_N_layer_k的电平状态均相同，例如：第一择线WL_layer_k的电平状态为高电平(即逻辑电平为1)，则第二选择线WL_N_layer_k的电平状态也为高电平；第一择线WL_layer_k的电平状态为低电平(即逻辑电平为0)，则第二选择线WL_N_layer_k的电平状态也为低电平。
如图2所示，本申请实施例以第一晶体管T1和第二晶体管T2的类型相同，且第一晶体管T1为N型晶体管，第二晶体管T2为N型晶体管为例进行说明。
本申请实施例中的第一选择线WL_layer_k和第二选择线WL_N_layer_k作为存储阵列层选择线，即通过第一选择线WL_layer_k的电平状态和第二选择线WL_N_layer_k的电平状态，确定哪一层存储阵列层被选择；具体地，若需要选择第k层存储阵列层，则第k层存储阵列层包括的第一选择线WL_layer_k的电平状态为高电平(即外围电路为第一选择线WL_layer_k输出高电平信号)，第k层存储阵列层包括的第二选择线WL_N_layer_k的电平状态为低电平(即外围电路为第二选择线WL_N_layer_k输出低电平信号)；针对不需要被选择的所有存储阵列层，每一层存储阵列层包括的第一选择线WL_layer_k的电平状态为低电平，每一层存储阵列层包括的第二选择线WL_N_layer_k的电平状态为高电平。
如图2所示，本申请实施例中的存储单元包括一个晶体管T和一个电容C，其中晶体管T和电容C可以按照水平二维布置的方式设计；晶体管T的栅极与字线连接，晶体管T的第一极与位线连接，晶体管T的第二极与电容C的一端连接，电容C的另一端接地。本申请实施例中的晶体管T为N型晶体管，当然，实际设计时，晶体管T也可以为P型晶体管。
需要说明的是，本申请实施例中的晶体管(晶体管T、第一晶体管T1和第二晶体管T2)的第一极指晶体管的源极，晶体管的第二极指晶体 管的漏极，或者，晶体管的第一极指晶体管的漏极，晶体管的第二极指晶体管的源极，晶体管的第一极和第二极可以互换，在此不做限定。
在一种具体实施例中，本申请实施例中的晶体管T、第一晶体管T1和第二晶体管T2的沟道均采用水平沟道，如图3所示，晶体管T包括源极14、漏极15、半导体层16、栅极绝缘层17和栅极18，其中，半导体层16环绕栅极18设置，第一晶体管T1和第二晶体管T2也可以采用图3所示的设置方式。具体地，半导体层优选金属氧化物半导体，如IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)，当金属氧化物材料为IGZO时，晶体管的漏电流较小(漏电流小于或者等于10-15A)，由此保证了动态存储器的低刷新率。
需要说明的是，金属氧化物的材料也可以是ITO，IWO、ZnOx、InOx、In2O3、InWO、SnO2、TiOx、InSnOx、ZnxOyNz、MgxZnyOz、InxZnyOz、InxGayZnzOa、ZrxInyZnzOa、HfxInyZnzOa、SnxInyZnzOa、AlxSnyInzZnaOd、SixInyZnzOa、ZnxSnyOz、AlxZnySnzOa、GaxZnySnzOa、ZrxZnySnzOa、InGaSiO、IAZO等材料，只要保证晶体管的漏电流能满足要求即可，具体可根据实际情况进行调整。
如图2所示，本申请实施例中沿垂直于衬底的方向且堆叠设置的多条字线共同对应一条第三选择线，第三选择线作为字线选择线，即通过第三选择线的电平状态，确定被选择的存储阵列层中哪一条字线被选中；具体地，若第k层存储阵列层被选择，则第k层存储阵列层的多条第三选择线与多条字线一一对应连接，第三选择线的电平状态为高电平时，与高电平的第三选择线连接的字线被选中，第三选择线的电平状态为低电平时，与低电平的第三选择线连接的字线未被选中，例如：若需要选中字线WL-k,1，则与字线WL-k,1连接的第三选择线WL-row1的电平状态为高电平(即外围电路为第三选择线WL-row1输出高电平信号)，与其它字线连接的第三选择线的电平状态为低电平(即外围电路为与其它字线连接的第三选择线输出低电平信号)，与字线WL-k,1连接的晶体管T导通，可以将位线BL_1,1、BL_1,2、BL_1,M-1、BL_1,M的数据写入电容C，或者通过位线 BL_1,1、BL_1,2、BL_1,M-1、BL_1,M读取电容C存储的数据，同样地，当其它字线被选中时，可实现对应行的存储单元的数据写入和数据读取。
具体地，如图2所示，沿位线的延伸方向位于同一列的存储单元共用一条位线，即针对一条位线(例如位线BL_1,1)，沿该位线延伸方向堆叠的所有的存储阵列层共用该条位线；针对每一层存储阵列层，存储单元包括的晶体管T的第一极与位线一一对应连接，这种设计方式简单易于制作。
在一种可选的实施例中，针对每一层存储阵列层，沿垂直于字线方向上相邻的两个晶体管T(例如图2中位于第一列的相邻的两个晶体管)的第一极连接同一条位线，这种设计方式能够节省位线的数量，减小存储器的尺寸，进而可以提升器件的集成度。
如图2所示，本申请实施例中的存储器包括读写电路、若干位线选择单元和若干控制线，位线与位线选择单元一一对应连接，控制线与位线选择单元一一对应连接；位线选择单元用于基于控制线的控制选择位线，以将选中的位线与读写电路连接；具体地，位线选择单元位于三维存储阵列的底部或顶部，位线选择单元组成一个阵列，通过控制线的控制打开和字线对应的一行位线选择单元，把这一行存储单元连接到一行读写电路，具体地，当写入数据时，读写电路将数据通过位线传输到该行存储单元，当读取数据时，读写电路可以接收该行存储单元通过位线传输的数据，以完成对该行存储单元的读取。
在一种具体的实施例中，存储器还包括若干第一连接线和/或若干第二连接线；每一第一选择线通过一条第一连接线与外围电路连接，第一连接线垂直于衬底，且沿垂直于衬底方向，多条第一连接线呈阶梯排布；每一第二选择线通过一条第二连接线与外围电路连接，第二连接线垂直于衬底，且沿垂直于衬底方向，多条第二连接线呈阶梯排布；通过这种设置方式，能够在最小的布线空间内，使得不同层的存储阵列层包括的第一选择线均与外围电路连接，以接收外围电路输出的电信号；以及能够使得不同层的存储阵列层包括的第二选择线均与外围电路连接，以接收外围电路输 出的电信号，以完成对选择电路的控制。
具体地，如图4所示，图中仅示出了第一选择线和第一连接线的设置方式，第二选择线和第二连接线的设置方式类似，这里不再赘述；图4中示出了位于相邻三层存储阵列层包括的三条第一选择线，每一条第一选择线均通过对应连接的第一连接线与外围电路连接，多条第一连接线的顶端平齐，底端分别位于不同的存储阵列层，由于不同的存储阵列层叠层设置，因此第一连接线的底端位于不同的平面，进而使得第一连接线呈阶梯排布，具体制作时，可以通过阶梯通孔的设置方式实现。
基于同一发明构思，本申请实施例提供了一种电子设备，包括如上述任一实施例提供的存储器。
该电子设备包括上述的存储器，因此该电子设备具有与上述存储器相同的有益效果，这里不再赘述。
具体地，电子设备包括存储装置、智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
基于同一发明构思，本申请实施例提供了一种上述存储器的读写方法，如图5所示，该存储器的写入操作阶段包括：
S101、向待要写入数据的存储阵列层对应的第一选择线施加第一电信号，以及向待要写入数据的存储阵列层对应的第二选择线施加第二电信号，使得待要写入数据的存储阵列层的字线与第三选择线一一对应连接，以选中待要写入数据的存储阵列层；
S102、基于选中的待要写入数据的存储阵列层，向与待要写入数据的存储单元行连接的字线对应的第三选择线施加第三电信号，使得与字线连接的存储单元行包括的晶体管导通，以选中待要写入数据的存储单元行；
S103、基于选中的待要写入数据的存储单元行，将与存储单元行中存储单元连接的位线的数据写入存储单元。
具体地，存储器包括的存储阵列层的设置方式以图2为例进行说明， 在写入操作阶段，向待要写入数据的存储阵列层对应的第一选择线WL_layer_k施加高电平信号，以及向第二选择线WL_N_layer_k施加低电平信号，第一晶体管T1导通，第二晶体管T2关断，每一条字线均与一条第三选择线一一对应连接；之后，向与待要写入数据的字线连接的第三选择线施加高电平信号，例如待要写入的字线为WL-K,1，则字线WL-K,1接收到高电平信号后，控制第一行的晶体管T导通，进而能够将与第一行晶体管T连接的位线的数据写入；另外，向其它的第三选择线(即与不需要写入的字线连接的第三选择线)施加低电平信号，使得存储单元包括的其它晶体管均处于关断状态，此时位线上即便有数据也无法写入存储单元。
在一种可选的实施例中，若本申请实施例中的存储单元包括一个晶体管和一个电容，该存储器在读取操作阶段，向待要读取数据的存储阵列层对应的第一选择线WL_layer_k施加高电平信号，以及向第二选择线WL_N_layer_k施加低电平信号，第一晶体管T1导通，第二晶体管T2关断，每一条字线均与一条第三选择线一一对应连接；之后，向与待要读取数据的字线连接的第三选择线施加高电平信号，例如待要读取数据的字线为WL-K,1，则字线WL-K,1接收到高电平信号后，控制第一行的晶体管T导通，进而能够将第一行存储单元存储的数据传输到对应的位线，通过位线连接的读写电路实现对存储数据的读取；另外，向其它的第三选择线(即与不需要读取的字线连接的第三选择线)施加低电平信号，使得存储单元包括的其它晶体管均处于关断状态。另外，在该读取操作阶段，还包括：向不需要读取数据的存储阵列层对应的第一选择线WL_layer_k施加低电平信号，以及向不需要读取数据的第二选择线WL_N_layer_k施加高电平信号。
在一种具体的实施例中，写入操作阶段还包括：向不需要写入数据的存储阵列层对应的第一选择线施加第二电信号，以及向不需要写入数据的第二选择线施加第一电信号，使得不需要写入数据的存储阵列层的字线与低电平电位端连接。
具体地，存储器包括的存储阵列层的设置方式以图2为例进行说明， 在写入操作阶段，向不需要写入数据的存储阵列层对应的第一选择线WL_layer_k施加低电平信号，以及向不需要写入数据的第二选择线WL_N_layer_k施加高电平信号。
综上所述，应用本申请实施例，至少能够实现如下有益效果：
本申请实施例提供的存储器，由于每一存储阵列层均包括选择电路、第一选择线、第二选择线、第三选择线和低电平电位端，选择电路分别与字线、第一选择线、第二选择线、第三选择线和低电平电位端连接，多个选择电路用于基于相应存储阵列层的第一选择线和第二选择线的电平状态，确定出被选择的存储阵列层，以及基于被选择的存储阵列层的第三选择线的电平状态，确定读写操作时被选中的字线；因此，本申请实施例通过设计新的外围电路，能够提供一种在读写操作时选定需要被选择的平行于衬底方向的字线的方式。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发 明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种存储器，包括：
    衬底；
    三维存储阵列，位于所述衬底的一侧，包括若干层沿垂直于所述衬底方向叠层设置的存储阵列层，所述存储阵列层包括二维阵列排布的存储单元、若干垂直于所述衬底的位线和若干平行于所述衬底的字线，每一层所述存储阵列层中，一行所述存储单元连接一条所述字线；
    其特征在于，每一层所述存储阵列层还包括：选择电路、第一选择线、第二选择线、若干第三选择线和若干低电平电位端；
    所述第一选择线和所述第二选择线平行于所述衬底，所述第三选择线垂直于所述衬底，且所述第三选择线与所述字线一一对应设置；
    所述选择电路，分别与若干所述字线、所述第一选择线、所述第二选择线、若干所述第三选择线和若干所述低电平电位端连接；
    针对所述三维存储阵列，多个所述选择电路用于基于相应所述存储阵列层的所述第一选择线和所述第二选择线的电平状态，确定出被选择的存储阵列层，以及基于被选择的存储阵列层的所述第三选择线的电平状态，确定读写操作时被选中的字线。
  2. 根据权利要求1所述的存储器，其特征在于，若干所述低电平电位端为若干垂直于所述衬底的电源线；
    每一所述存储阵列层，所述电源线与所述字线一一对应设置；
    沿垂直于所述衬底的方向且堆叠设置的多条所述字线共同对应一条所述电源线。
  3. 根据权利要求1所述的存储器，其特征在于，所有的所述存储阵列层包括的若干所述低电平电位端为导电墙；
    沿垂直于所述衬底的方向，所有的所述存储阵列层共用所述导电墙。
  4. 根据权利要求1-3任一项所述的存储器，其特征在于，每一层所述存储阵列层中的所述选择电路包括第一子选择电路和第二子选择电路；
    针对每一层所述存储阵列层，所述第一子选择电路，分别与同一层所述存储阵列层的若干所述字线、所述第一选择线和所述第三选择线连接；针对所述三维存储阵列，每一层所述第一子选择电路用于基于相应所述存储阵列层的所述第一选择线的电平状态，确定出所述字线与所述第三选择线连接的存储阵列层，以及基于字线与所述第三选择线连接的存储阵列层的所述第三选择线的电平状态，确定被选中的所述字线；
    针对每一层所述存储阵列层，所述第二子选择电路，分别与同一层所述存储阵列层的若干所述字线、所述第二选择线和所述低电平电位端连接；针对所述三维存储阵列，每一层所述第二子选择电路用于基于相应所述存储阵列层的所述第二选择线的电平状态，确定所述字线与所述低电平电位端连接的存储阵列层；其中：
    所述字线与所述第三选择线连接的存储阵列层为被选择的存储阵列层，所述字线与所述低电平电位端连接的存储阵列层为未被选择的存储阵列层。
  5. 根据权利要求4所述的存储器，其特征在于，所述第一子选择电路位于所述字线的一侧，所述第二子选择电路位于所述字线的相同侧；
    或者，所述第一子选择电路位于所述字线的第一侧，所述第二子选择电路位于所述字线的第二侧，所述第一侧和所述第二侧相对设置。
  6. 根据权利要求4所述的存储器，其特征在于，所述第一子选择电路包括若干第一晶体管，所述第一晶体管与所述字线一一对应设置；
    所述第一晶体管的栅极与所述第一选择线连接，所述第一晶体管的第一极与所述字线连接，所述第一晶体管的第二极与所述第三选择线连接。
  7. 根据权利要求6所述的存储器，其特征在于，所述第二子选择电路包括若干第二晶体管，所述第二晶体管与所述字线一一对应设置；
    所述第二晶体管的栅极与所述第二选择线连接，所述第二晶体管的第一极与所述字线连接，所述第二晶体管的第二极与所述低电平电位端连接。
  8. 根据权利要求7所述的存储器，其特征在于，所述第一晶体管为N型晶体管，所述第二晶体管为N型晶体管，所述第一选择线的电平状态与 所述第二选择线的电平状态相反；
    或者，所述第一晶体管为P型晶体管，所述第二晶体管为P型晶体管，所述第一选择线的电平状态与所述第二选择线的电平状态相反；
    或者，所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管，所述第一选择线的电平状态与所述第二选择线的电平状态相同；
    或者，所述第一晶体管为P型晶体管，所述第二晶体管为N型晶体管，所述第一选择线的电平状态与所述第二选择线的电平状态相同。
  9. 根据权利要求1所述的存储器，其特征在于，所述存储单元包括一个晶体管和一个电容；
    所述晶体管的栅极与所述字线连接，所述晶体管的第一极与所述位线连接，所述晶体管的第二极与所述电容的一端连接，所述电容的另一端接地。
  10. 根据权利要求9所述的存储器，其特征在于，所述存储器包括如下至少一项；
    沿所述位线的延伸方向位于同一列的存储单元共用一条所述位线；
    沿垂直于所述衬底的方向且堆叠设置的多条所述字线共同对应一条所述第三选择线；
    针对每一层所述存储阵列层，所述晶体管的第一极与所述位线一一对应连接；或者，沿垂直于所述字线方向上相邻的两个所述晶体管的第一极连接同一条位线。
  11. 根据权利要求9所述的存储器，其特征在于，包括读写电路、若干位线选择单元和若干控制线；
    所述位线与所述位线选择单元一一对应连接，所述控制线与所述位线选择单元一一对应连接；
    所述位线选择单元用于基于所述控制线的控制选择所述位线，以将选中的所述位线与所述读写电路连接。
  12. 根据权利要求1-11任一项所述的存储器，其特征在于，包括若干第一连接线和/或若干第二连接线；
    每一所述第一选择线通过一条所述第一连接线与外围电路连接，所述第一连接线垂直于所述衬底，且沿垂直于所述衬底方向，多条所述第一连接线呈阶梯排布；
    每一所述第二选择线通过一条所述第二连接线与外围电路连接，所述第二连接线垂直于所述衬底，且沿垂直于所述衬底方向，多条所述第二连接线呈阶梯排布。
  13. 一种电子设备，其特征在于，包括如权利要求1至12任一所述的存储器。
  14. 一种如权利要求1至12任一所述的存储器的读写方法，其特征在于，包括：
    写入操作阶段：向待要写入数据的存储阵列层对应的第一选择线施加第一电信号，以及向待要写入数据的存储阵列层对应的第二选择线施加第二电信号，使得待要写入数据的存储阵列层的所述字线与所述第三选择线一一对应连接，以选中待要写入数据的存储阵列层；
    基于选中的待要写入数据的存储阵列层，向与待要写入数据的存储单元行连接的字线对应的第三选择线施加第三电信号，使得与所述字线连接的存储单元行导通，以选中待要写入数据的存储单元行；
    基于选中的待要写入数据的存储单元行，将与所述存储单元行中存储单元连接的位线的数据写入所述存储单元。
  15. 根据权利要求14所述的读写方法，其特征在于，所述写入操作阶段还包括：向不需要写入数据的存储阵列层对应的第一选择线施加第二电信号，以及向不需要写入数据的第二选择线施加第一电信号，使得不需要写入数据的存储阵列层的所述字线与所述低电平电位端连接。
PCT/CN2024/073718 2023-08-10 2024-01-23 一种存储器及其读写方法、电子设备 Pending WO2025030786A1 (zh)

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